./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1 --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 1d054f79132e175b09d8c50472a4c24ca52f401c76e1d0704dd5609a369827e2 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-12-02 06:03:12,172 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-12-02 06:03:12,227 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Default.epf [2024-12-02 06:03:12,232 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-12-02 06:03:12,232 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-12-02 06:03:12,254 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-12-02 06:03:12,254 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-12-02 06:03:12,254 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-12-02 06:03:12,255 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-12-02 06:03:12,255 INFO L153 SettingsManager]: * Use memory slicer=true [2024-12-02 06:03:12,255 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-12-02 06:03:12,255 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-12-02 06:03:12,255 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-12-02 06:03:12,255 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-12-02 06:03:12,256 INFO L153 SettingsManager]: * Use SBE=true [2024-12-02 06:03:12,256 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-12-02 06:03:12,256 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-12-02 06:03:12,256 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-12-02 06:03:12,256 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-12-02 06:03:12,256 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-12-02 06:03:12,256 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-12-02 06:03:12,256 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-12-02 06:03:12,256 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-12-02 06:03:12,256 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-12-02 06:03:12,256 INFO L153 SettingsManager]: * Use constant arrays=true [2024-12-02 06:03:12,257 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-12-02 06:03:12,257 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 06:03:12,257 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 06:03:12,257 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 06:03:12,257 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:03:12,257 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-12-02 06:03:12,257 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 06:03:12,257 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 06:03:12,257 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 06:03:12,257 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:03:12,257 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-12-02 06:03:12,257 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-12-02 06:03:12,258 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-12-02 06:03:12,258 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-12-02 06:03:12,258 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-12-02 06:03:12,258 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-12-02 06:03:12,258 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-12-02 06:03:12,258 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-12-02 06:03:12,258 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-12-02 06:03:12,258 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-12-02 06:03:12,258 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1d054f79132e175b09d8c50472a4c24ca52f401c76e1d0704dd5609a369827e2 [2024-12-02 06:03:12,493 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-12-02 06:03:12,500 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-12-02 06:03:12,502 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-12-02 06:03:12,503 INFO L270 PluginConnector]: Initializing CDTParser... [2024-12-02 06:03:12,503 INFO L274 PluginConnector]: CDTParser initialized [2024-12-02 06:03:12,504 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-12-02 06:03:15,108 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/data/4b7801461/736a6900ff9e4bc089c47f830cd45af2/FLAGd2708a964 [2024-12-02 06:03:15,363 INFO L384 CDTParser]: Found 1 translation units. [2024-12-02 06:03:15,364 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-12-02 06:03:15,374 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/data/4b7801461/736a6900ff9e4bc089c47f830cd45af2/FLAGd2708a964 [2024-12-02 06:03:15,686 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/data/4b7801461/736a6900ff9e4bc089c47f830cd45af2 [2024-12-02 06:03:15,687 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-12-02 06:03:15,688 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-12-02 06:03:15,689 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-12-02 06:03:15,689 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-12-02 06:03:15,692 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-12-02 06:03:15,693 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:03:15" (1/1) ... [2024-12-02 06:03:15,693 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@53ee55cd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:15, skipping insertion in model container [2024-12-02 06:03:15,693 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:03:15" (1/1) ... [2024-12-02 06:03:15,721 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-12-02 06:03:15,862 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c[1268,1281] [2024-12-02 06:03:16,056 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 06:03:16,065 INFO L200 MainTranslator]: Completed pre-run [2024-12-02 06:03:16,072 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c[1268,1281] [2024-12-02 06:03:16,176 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 06:03:16,190 INFO L204 MainTranslator]: Completed translation [2024-12-02 06:03:16,190 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16 WrapperNode [2024-12-02 06:03:16,191 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-12-02 06:03:16,191 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-12-02 06:03:16,192 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-12-02 06:03:16,192 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-12-02 06:03:16,198 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16" (1/1) ... [2024-12-02 06:03:16,223 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16" (1/1) ... [2024-12-02 06:03:16,439 INFO L138 Inliner]: procedures = 18, calls = 41, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 2370 [2024-12-02 06:03:16,439 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-12-02 06:03:16,440 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-12-02 06:03:16,440 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-12-02 06:03:16,440 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-12-02 06:03:16,449 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16" (1/1) ... [2024-12-02 06:03:16,449 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16" (1/1) ... [2024-12-02 06:03:16,487 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16" (1/1) ... [2024-12-02 06:03:16,592 INFO L175 MemorySlicer]: Split 20 memory accesses to 3 slices as follows [2, 9, 9]. 45 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0, 0]. The 8 writes are split as follows [0, 4, 4]. [2024-12-02 06:03:16,592 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16" (1/1) ... [2024-12-02 06:03:16,592 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16" (1/1) ... [2024-12-02 06:03:16,647 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16" (1/1) ... [2024-12-02 06:03:16,654 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16" (1/1) ... [2024-12-02 06:03:16,666 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16" (1/1) ... [2024-12-02 06:03:16,698 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16" (1/1) ... [2024-12-02 06:03:16,708 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16" (1/1) ... [2024-12-02 06:03:16,739 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-12-02 06:03:16,739 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-12-02 06:03:16,740 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-12-02 06:03:16,740 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-12-02 06:03:16,741 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16" (1/1) ... [2024-12-02 06:03:16,746 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:03:16,757 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:03:16,768 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-12-02 06:03:16,771 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-12-02 06:03:16,794 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-12-02 06:03:16,794 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-12-02 06:03:16,794 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-12-02 06:03:16,794 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-12-02 06:03:16,794 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2024-12-02 06:03:16,794 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#2 [2024-12-02 06:03:16,795 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-12-02 06:03:16,795 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2024-12-02 06:03:16,795 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2024-12-02 06:03:16,795 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#2 [2024-12-02 06:03:16,795 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-12-02 06:03:16,795 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-12-02 06:03:16,795 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2024-12-02 06:03:16,795 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2024-12-02 06:03:16,795 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#2 [2024-12-02 06:03:16,795 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-12-02 06:03:17,015 INFO L234 CfgBuilder]: Building ICFG [2024-12-02 06:03:17,017 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-12-02 06:03:19,582 INFO L? ?]: Removed 1283 outVars from TransFormulas that were not future-live. [2024-12-02 06:03:19,582 INFO L283 CfgBuilder]: Performing block encoding [2024-12-02 06:03:19,607 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-12-02 06:03:19,607 INFO L312 CfgBuilder]: Removed 7 assume(true) statements. [2024-12-02 06:03:19,607 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:03:19 BoogieIcfgContainer [2024-12-02 06:03:19,607 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-12-02 06:03:19,610 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-12-02 06:03:19,610 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-12-02 06:03:19,616 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-12-02 06:03:19,616 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 06:03:15" (1/3) ... [2024-12-02 06:03:19,616 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6f6d829 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 06:03:19, skipping insertion in model container [2024-12-02 06:03:19,617 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:03:16" (2/3) ... [2024-12-02 06:03:19,617 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6f6d829 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 06:03:19, skipping insertion in model container [2024-12-02 06:03:19,617 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:03:19" (3/3) ... [2024-12-02 06:03:19,618 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-12-02 06:03:19,633 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-12-02 06:03:19,635 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c that has 2 procedures, 752 locations, 1 initial locations, 7 loop locations, and 1 error locations. [2024-12-02 06:03:19,716 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-12-02 06:03:19,726 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@63c30431, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-12-02 06:03:19,726 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-12-02 06:03:19,731 INFO L276 IsEmpty]: Start isEmpty. Operand has 752 states, 744 states have (on average 1.4973118279569892) internal successors, (1114), 745 states have internal predecessors, (1114), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:03:19,745 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 242 [2024-12-02 06:03:19,745 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:19,746 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:19,747 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:19,751 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:19,751 INFO L85 PathProgramCache]: Analyzing trace with hash -1021292254, now seen corresponding path program 1 times [2024-12-02 06:03:19,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:19,757 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [183494443] [2024-12-02 06:03:19,757 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:19,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:19,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:20,154 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-12-02 06:03:20,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:20,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [183494443] [2024-12-02 06:03:20,155 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [183494443] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:03:20,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1580588706] [2024-12-02 06:03:20,156 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:20,156 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:20,156 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:03:20,159 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:03:20,162 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-12-02 06:03:20,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:20,643 INFO L256 TraceCheckSpWp]: Trace formula consists of 1101 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-12-02 06:03:20,651 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:03:20,674 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-12-02 06:03:20,674 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:03:20,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1580588706] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:20,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:03:20,675 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 2 [2024-12-02 06:03:20,677 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [191452265] [2024-12-02 06:03:20,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:20,680 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-12-02 06:03:20,681 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:20,695 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-12-02 06:03:20,696 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 06:03:20,698 INFO L87 Difference]: Start difference. First operand has 752 states, 744 states have (on average 1.4973118279569892) internal successors, (1114), 745 states have internal predecessors, (1114), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) Second operand has 2 states, 2 states have (on average 110.5) internal successors, (221), 2 states have internal predecessors, (221), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:20,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:20,759 INFO L93 Difference]: Finished difference Result 1493 states and 2239 transitions. [2024-12-02 06:03:20,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-12-02 06:03:20,761 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 110.5) internal successors, (221), 2 states have internal predecessors, (221), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) Word has length 241 [2024-12-02 06:03:20,761 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:20,772 INFO L225 Difference]: With dead ends: 1493 [2024-12-02 06:03:20,772 INFO L226 Difference]: Without dead ends: 749 [2024-12-02 06:03:20,777 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 242 GetRequests, 242 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 06:03:20,780 INFO L435 NwaCegarLoop]: 1113 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1113 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:20,780 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1113 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:03:20,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 749 states. [2024-12-02 06:03:20,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 749 to 749. [2024-12-02 06:03:20,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 749 states, 742 states have (on average 1.486522911051213) internal successors, (1103), 742 states have internal predecessors, (1103), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:03:20,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 749 states to 749 states and 1113 transitions. [2024-12-02 06:03:20,838 INFO L78 Accepts]: Start accepts. Automaton has 749 states and 1113 transitions. Word has length 241 [2024-12-02 06:03:20,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:20,838 INFO L471 AbstractCegarLoop]: Abstraction has 749 states and 1113 transitions. [2024-12-02 06:03:20,839 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 110.5) internal successors, (221), 2 states have internal predecessors, (221), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:20,839 INFO L276 IsEmpty]: Start isEmpty. Operand 749 states and 1113 transitions. [2024-12-02 06:03:20,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 242 [2024-12-02 06:03:20,843 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:20,843 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:20,851 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-12-02 06:03:21,044 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable0 [2024-12-02 06:03:21,044 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:21,045 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:21,045 INFO L85 PathProgramCache]: Analyzing trace with hash 526745560, now seen corresponding path program 1 times [2024-12-02 06:03:21,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:21,045 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117625360] [2024-12-02 06:03:21,045 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:21,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:21,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:21,673 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:03:21,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:21,673 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1117625360] [2024-12-02 06:03:21,673 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1117625360] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:21,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:21,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:03:21,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1949465731] [2024-12-02 06:03:21,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:21,675 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:03:21,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:21,676 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:03:21,676 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:03:21,676 INFO L87 Difference]: Start difference. First operand 749 states and 1113 transitions. Second operand has 3 states, 3 states have (on average 73.0) internal successors, (219), 3 states have internal predecessors, (219), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:21,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:21,712 INFO L93 Difference]: Finished difference Result 1496 states and 2224 transitions. [2024-12-02 06:03:21,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:03:21,713 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 73.0) internal successors, (219), 3 states have internal predecessors, (219), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 241 [2024-12-02 06:03:21,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:21,716 INFO L225 Difference]: With dead ends: 1496 [2024-12-02 06:03:21,716 INFO L226 Difference]: Without dead ends: 755 [2024-12-02 06:03:21,717 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:03:21,718 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 7 mSDsluCounter, 1108 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 2219 SdHoareTripleChecker+Invalid, 6 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:21,718 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 2219 Invalid, 6 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:03:21,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 755 states. [2024-12-02 06:03:21,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 755 to 750. [2024-12-02 06:03:21,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 750 states, 743 states have (on average 1.4858681022880216) internal successors, (1104), 743 states have internal predecessors, (1104), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:03:21,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 750 states to 750 states and 1114 transitions. [2024-12-02 06:03:21,740 INFO L78 Accepts]: Start accepts. Automaton has 750 states and 1114 transitions. Word has length 241 [2024-12-02 06:03:21,740 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:21,740 INFO L471 AbstractCegarLoop]: Abstraction has 750 states and 1114 transitions. [2024-12-02 06:03:21,741 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 73.0) internal successors, (219), 3 states have internal predecessors, (219), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:21,741 INFO L276 IsEmpty]: Start isEmpty. Operand 750 states and 1114 transitions. [2024-12-02 06:03:21,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 246 [2024-12-02 06:03:21,744 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:21,744 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:21,744 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-12-02 06:03:21,745 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:21,745 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:21,745 INFO L85 PathProgramCache]: Analyzing trace with hash -1295801430, now seen corresponding path program 1 times [2024-12-02 06:03:21,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:21,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023150734] [2024-12-02 06:03:21,746 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:21,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:21,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:22,347 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:03:22,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:22,347 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1023150734] [2024-12-02 06:03:22,348 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1023150734] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:03:22,348 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1355622720] [2024-12-02 06:03:22,348 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:22,348 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:22,348 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:03:22,350 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:03:22,352 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-12-02 06:03:22,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:22,813 INFO L256 TraceCheckSpWp]: Trace formula consists of 1112 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:03:22,820 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:03:22,846 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:03:22,846 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:03:22,896 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:03:22,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1355622720] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:03:22,896 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:03:22,896 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 6 [2024-12-02 06:03:22,896 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1128530644] [2024-12-02 06:03:22,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:22,897 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:03:22,897 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:22,898 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:03:22,898 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:03:22,898 INFO L87 Difference]: Start difference. First operand 750 states and 1114 transitions. Second operand has 3 states, 3 states have (on average 74.33333333333333) internal successors, (223), 3 states have internal predecessors, (223), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:22,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:22,936 INFO L93 Difference]: Finished difference Result 1469 states and 2184 transitions. [2024-12-02 06:03:22,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:03:22,937 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 74.33333333333333) internal successors, (223), 3 states have internal predecessors, (223), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 245 [2024-12-02 06:03:22,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:22,940 INFO L225 Difference]: With dead ends: 1469 [2024-12-02 06:03:22,940 INFO L226 Difference]: Without dead ends: 751 [2024-12-02 06:03:22,941 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 492 GetRequests, 488 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:03:22,941 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 7 mSDsluCounter, 1101 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 2212 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:22,942 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 2212 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:03:22,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 751 states. [2024-12-02 06:03:22,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 751 to 751. [2024-12-02 06:03:22,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 751 states, 744 states have (on average 1.4852150537634408) internal successors, (1105), 744 states have internal predecessors, (1105), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:03:22,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 751 states to 751 states and 1115 transitions. [2024-12-02 06:03:22,961 INFO L78 Accepts]: Start accepts. Automaton has 751 states and 1115 transitions. Word has length 245 [2024-12-02 06:03:22,962 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:22,962 INFO L471 AbstractCegarLoop]: Abstraction has 751 states and 1115 transitions. [2024-12-02 06:03:22,962 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 74.33333333333333) internal successors, (223), 3 states have internal predecessors, (223), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:22,962 INFO L276 IsEmpty]: Start isEmpty. Operand 751 states and 1115 transitions. [2024-12-02 06:03:22,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 250 [2024-12-02 06:03:22,965 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:22,965 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:22,976 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-12-02 06:03:23,166 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:23,166 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:23,166 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:23,166 INFO L85 PathProgramCache]: Analyzing trace with hash -1377415492, now seen corresponding path program 1 times [2024-12-02 06:03:23,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:23,166 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309823732] [2024-12-02 06:03:23,166 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:23,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:23,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:23,769 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:03:23,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:23,769 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [309823732] [2024-12-02 06:03:23,769 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [309823732] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:03:23,769 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1831868032] [2024-12-02 06:03:23,770 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:23,770 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:23,770 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:03:23,773 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:03:23,775 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-12-02 06:03:24,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:24,303 INFO L256 TraceCheckSpWp]: Trace formula consists of 1123 conjuncts, 16 conjuncts are in the unsatisfiable core [2024-12-02 06:03:24,311 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:03:24,355 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:03:24,355 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:03:25,196 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:03:25,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1831868032] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:03:25,196 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:03:25,196 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 8] total 12 [2024-12-02 06:03:25,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278577992] [2024-12-02 06:03:25,197 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:03:25,198 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2024-12-02 06:03:25,198 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:25,199 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2024-12-02 06:03:25,199 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:03:25,199 INFO L87 Difference]: Start difference. First operand 751 states and 1115 transitions. Second operand has 12 states, 12 states have (on average 30.666666666666668) internal successors, (368), 12 states have internal predecessors, (368), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:03:26,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:26,930 INFO L93 Difference]: Finished difference Result 2117 states and 3148 transitions. [2024-12-02 06:03:26,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:03:26,931 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 30.666666666666668) internal successors, (368), 12 states have internal predecessors, (368), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 249 [2024-12-02 06:03:26,931 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:26,935 INFO L225 Difference]: With dead ends: 2117 [2024-12-02 06:03:26,935 INFO L226 Difference]: Without dead ends: 1375 [2024-12-02 06:03:26,936 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 501 GetRequests, 490 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=53, Invalid=103, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:03:26,937 INFO L435 NwaCegarLoop]: 1385 mSDtfsCounter, 2019 mSDsluCounter, 6303 mSDsCounter, 0 mSdLazyCounter, 2637 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2024 SdHoareTripleChecker+Valid, 7688 SdHoareTripleChecker+Invalid, 2638 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 2637 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.6s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:26,937 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2024 Valid, 7688 Invalid, 2638 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 2637 Invalid, 0 Unknown, 0 Unchecked, 1.6s Time] [2024-12-02 06:03:26,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1375 states. [2024-12-02 06:03:26,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1375 to 986. [2024-12-02 06:03:26,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 986 states, 974 states have (on average 1.482546201232033) internal successors, (1444), 974 states have internal predecessors, (1444), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:26,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 986 states to 986 states and 1464 transitions. [2024-12-02 06:03:26,965 INFO L78 Accepts]: Start accepts. Automaton has 986 states and 1464 transitions. Word has length 249 [2024-12-02 06:03:26,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:26,965 INFO L471 AbstractCegarLoop]: Abstraction has 986 states and 1464 transitions. [2024-12-02 06:03:26,965 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 30.666666666666668) internal successors, (368), 12 states have internal predecessors, (368), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:03:26,965 INFO L276 IsEmpty]: Start isEmpty. Operand 986 states and 1464 transitions. [2024-12-02 06:03:26,968 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2024-12-02 06:03:26,968 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:26,968 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:26,976 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2024-12-02 06:03:27,168 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:27,169 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:27,169 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:27,169 INFO L85 PathProgramCache]: Analyzing trace with hash 1657948098, now seen corresponding path program 1 times [2024-12-02 06:03:27,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:27,169 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510701332] [2024-12-02 06:03:27,169 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:27,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:27,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:27,500 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:03:27,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:27,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [510701332] [2024-12-02 06:03:27,501 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [510701332] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:03:27,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [469435638] [2024-12-02 06:03:27,501 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:27,501 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:27,502 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:03:27,504 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:03:27,509 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-12-02 06:03:27,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:27,983 INFO L256 TraceCheckSpWp]: Trace formula consists of 1137 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:03:27,988 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:03:28,021 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:03:28,021 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:03:28,073 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2024-12-02 06:03:28,073 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [469435638] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:03:28,073 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:03:28,073 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 6, 4] total 9 [2024-12-02 06:03:28,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [335372874] [2024-12-02 06:03:28,073 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:03:28,074 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:03:28,074 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:28,075 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:03:28,075 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:03:28,075 INFO L87 Difference]: Start difference. First operand 986 states and 1464 transitions. Second operand has 9 states, 9 states have (on average 29.22222222222222) internal successors, (263), 9 states have internal predecessors, (263), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:03:28,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:28,168 INFO L93 Difference]: Finished difference Result 2004 states and 2978 transitions. [2024-12-02 06:03:28,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:03:28,168 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 29.22222222222222) internal successors, (263), 9 states have internal predecessors, (263), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 254 [2024-12-02 06:03:28,169 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:28,170 INFO L225 Difference]: With dead ends: 2004 [2024-12-02 06:03:28,170 INFO L226 Difference]: Without dead ends: 1033 [2024-12-02 06:03:28,171 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 512 GetRequests, 504 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:03:28,172 INFO L435 NwaCegarLoop]: 1121 mSDtfsCounter, 52 mSDsluCounter, 5563 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 52 SdHoareTripleChecker+Valid, 6684 SdHoareTripleChecker+Invalid, 60 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:28,172 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [52 Valid, 6684 Invalid, 60 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:03:28,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1033 states. [2024-12-02 06:03:28,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1033 to 1028. [2024-12-02 06:03:28,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1028 states, 1016 states have (on average 1.4763779527559056) internal successors, (1500), 1016 states have internal predecessors, (1500), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:28,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1028 states to 1028 states and 1520 transitions. [2024-12-02 06:03:28,194 INFO L78 Accepts]: Start accepts. Automaton has 1028 states and 1520 transitions. Word has length 254 [2024-12-02 06:03:28,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:28,194 INFO L471 AbstractCegarLoop]: Abstraction has 1028 states and 1520 transitions. [2024-12-02 06:03:28,194 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 29.22222222222222) internal successors, (263), 9 states have internal predecessors, (263), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:03:28,194 INFO L276 IsEmpty]: Start isEmpty. Operand 1028 states and 1520 transitions. [2024-12-02 06:03:28,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 271 [2024-12-02 06:03:28,197 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:28,197 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:28,205 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-12-02 06:03:28,397 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:28,397 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:28,398 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:28,398 INFO L85 PathProgramCache]: Analyzing trace with hash 1935099494, now seen corresponding path program 2 times [2024-12-02 06:03:28,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:28,398 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989449024] [2024-12-02 06:03:28,398 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:03:28,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:28,471 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:03:28,471 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:03:28,727 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2024-12-02 06:03:28,727 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:28,727 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [989449024] [2024-12-02 06:03:28,727 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [989449024] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:28,727 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:28,727 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:03:28,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1570529706] [2024-12-02 06:03:28,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:28,728 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:03:28,728 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:28,729 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:03:28,729 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:03:28,729 INFO L87 Difference]: Start difference. First operand 1028 states and 1520 transitions. Second operand has 4 states, 4 states have (on average 57.0) internal successors, (228), 4 states have internal predecessors, (228), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:28,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:28,765 INFO L93 Difference]: Finished difference Result 1032 states and 1524 transitions. [2024-12-02 06:03:28,765 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:03:28,765 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 57.0) internal successors, (228), 4 states have internal predecessors, (228), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 270 [2024-12-02 06:03:28,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:28,769 INFO L225 Difference]: With dead ends: 1032 [2024-12-02 06:03:28,769 INFO L226 Difference]: Without dead ends: 1030 [2024-12-02 06:03:28,769 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:03:28,770 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 0 mSDsluCounter, 2216 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3327 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:28,770 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3327 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:03:28,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1030 states. [2024-12-02 06:03:28,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1030 to 1030. [2024-12-02 06:03:28,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1030 states, 1018 states have (on average 1.475442043222004) internal successors, (1502), 1018 states have internal predecessors, (1502), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:28,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1030 states to 1030 states and 1522 transitions. [2024-12-02 06:03:28,787 INFO L78 Accepts]: Start accepts. Automaton has 1030 states and 1522 transitions. Word has length 270 [2024-12-02 06:03:28,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:28,788 INFO L471 AbstractCegarLoop]: Abstraction has 1030 states and 1522 transitions. [2024-12-02 06:03:28,788 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 57.0) internal successors, (228), 4 states have internal predecessors, (228), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:28,788 INFO L276 IsEmpty]: Start isEmpty. Operand 1030 states and 1522 transitions. [2024-12-02 06:03:28,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 272 [2024-12-02 06:03:28,791 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:28,791 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:28,791 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2024-12-02 06:03:28,791 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:28,792 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:28,792 INFO L85 PathProgramCache]: Analyzing trace with hash -139761292, now seen corresponding path program 1 times [2024-12-02 06:03:28,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:28,792 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220553557] [2024-12-02 06:03:28,792 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:28,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:28,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:29,099 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 68 trivial. 0 not checked. [2024-12-02 06:03:29,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:29,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1220553557] [2024-12-02 06:03:29,100 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1220553557] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:03:29,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1303739253] [2024-12-02 06:03:29,100 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:29,100 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:29,100 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:03:29,102 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:03:29,103 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-12-02 06:03:29,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:29,608 INFO L256 TraceCheckSpWp]: Trace formula consists of 1184 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-12-02 06:03:29,612 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:03:29,643 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 68 trivial. 0 not checked. [2024-12-02 06:03:29,644 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:03:29,806 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 13 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:03:29,807 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1303739253] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:03:29,807 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:03:29,807 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 10] total 15 [2024-12-02 06:03:29,807 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [955993095] [2024-12-02 06:03:29,807 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:03:29,808 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2024-12-02 06:03:29,808 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:29,809 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2024-12-02 06:03:29,809 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2024-12-02 06:03:29,809 INFO L87 Difference]: Start difference. First operand 1030 states and 1522 transitions. Second operand has 15 states, 15 states have (on average 18.0) internal successors, (270), 15 states have internal predecessors, (270), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:03:29,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:29,965 INFO L93 Difference]: Finished difference Result 2069 states and 3061 transitions. [2024-12-02 06:03:29,966 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:03:29,966 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 18.0) internal successors, (270), 15 states have internal predecessors, (270), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 271 [2024-12-02 06:03:29,966 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:29,969 INFO L225 Difference]: With dead ends: 2069 [2024-12-02 06:03:29,969 INFO L226 Difference]: Without dead ends: 1060 [2024-12-02 06:03:29,971 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 549 GetRequests, 533 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=84, Invalid=222, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:03:29,971 INFO L435 NwaCegarLoop]: 1129 mSDtfsCounter, 86 mSDsluCounter, 11200 mSDsCounter, 0 mSdLazyCounter, 110 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 86 SdHoareTripleChecker+Valid, 12329 SdHoareTripleChecker+Invalid, 112 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 110 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:29,972 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [86 Valid, 12329 Invalid, 112 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 110 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:03:29,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1060 states. [2024-12-02 06:03:29,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1060 to 1060. [2024-12-02 06:03:29,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1060 states, 1048 states have (on average 1.4713740458015268) internal successors, (1542), 1048 states have internal predecessors, (1542), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:29,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1060 states to 1060 states and 1562 transitions. [2024-12-02 06:03:29,998 INFO L78 Accepts]: Start accepts. Automaton has 1060 states and 1562 transitions. Word has length 271 [2024-12-02 06:03:29,998 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:29,998 INFO L471 AbstractCegarLoop]: Abstraction has 1060 states and 1562 transitions. [2024-12-02 06:03:29,998 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 18.0) internal successors, (270), 15 states have internal predecessors, (270), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:03:29,998 INFO L276 IsEmpty]: Start isEmpty. Operand 1060 states and 1562 transitions. [2024-12-02 06:03:30,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 292 [2024-12-02 06:03:30,002 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:30,003 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:30,015 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-12-02 06:03:30,203 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:30,203 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:30,203 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:30,204 INFO L85 PathProgramCache]: Analyzing trace with hash 439580942, now seen corresponding path program 2 times [2024-12-02 06:03:30,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:30,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729663465] [2024-12-02 06:03:30,204 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:03:30,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:30,277 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:03:30,277 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:03:30,512 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 188 trivial. 0 not checked. [2024-12-02 06:03:30,512 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:30,512 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [729663465] [2024-12-02 06:03:30,512 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [729663465] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:30,512 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:30,512 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:03:30,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [284459305] [2024-12-02 06:03:30,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:30,513 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:03:30,513 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:30,513 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:03:30,513 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:03:30,514 INFO L87 Difference]: Start difference. First operand 1060 states and 1562 transitions. Second operand has 4 states, 4 states have (on average 57.25) internal successors, (229), 4 states have internal predecessors, (229), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:30,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:30,550 INFO L93 Difference]: Finished difference Result 1717 states and 2538 transitions. [2024-12-02 06:03:30,550 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:03:30,550 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 57.25) internal successors, (229), 4 states have internal predecessors, (229), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 291 [2024-12-02 06:03:30,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:30,554 INFO L225 Difference]: With dead ends: 1717 [2024-12-02 06:03:30,554 INFO L226 Difference]: Without dead ends: 1062 [2024-12-02 06:03:30,555 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:03:30,555 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 0 mSDsluCounter, 2212 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3323 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:30,555 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3323 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:03:30,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1062 states. [2024-12-02 06:03:30,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1062 to 1062. [2024-12-02 06:03:30,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1062 states, 1050 states have (on average 1.4704761904761905) internal successors, (1544), 1050 states have internal predecessors, (1544), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:30,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1062 states to 1062 states and 1564 transitions. [2024-12-02 06:03:30,577 INFO L78 Accepts]: Start accepts. Automaton has 1062 states and 1564 transitions. Word has length 291 [2024-12-02 06:03:30,577 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:30,577 INFO L471 AbstractCegarLoop]: Abstraction has 1062 states and 1564 transitions. [2024-12-02 06:03:30,577 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 57.25) internal successors, (229), 4 states have internal predecessors, (229), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:30,577 INFO L276 IsEmpty]: Start isEmpty. Operand 1062 states and 1564 transitions. [2024-12-02 06:03:30,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 293 [2024-12-02 06:03:30,580 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:30,580 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:30,580 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2024-12-02 06:03:30,581 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:30,581 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:30,581 INFO L85 PathProgramCache]: Analyzing trace with hash -355857243, now seen corresponding path program 1 times [2024-12-02 06:03:30,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:30,581 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1501183291] [2024-12-02 06:03:30,581 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:30,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:30,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:30,950 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2024-12-02 06:03:30,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:30,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1501183291] [2024-12-02 06:03:30,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1501183291] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:03:30,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [258587087] [2024-12-02 06:03:30,951 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:30,951 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:30,951 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:03:30,952 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:03:30,954 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-12-02 06:03:31,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:31,477 INFO L256 TraceCheckSpWp]: Trace formula consists of 1242 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-12-02 06:03:31,482 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:03:31,559 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 124 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2024-12-02 06:03:31,560 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:03:31,671 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2024-12-02 06:03:31,671 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [258587087] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:03:31,672 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:03:31,672 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-12-02 06:03:31,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1544288726] [2024-12-02 06:03:31,672 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:03:31,673 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-12-02 06:03:31,673 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:31,673 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-12-02 06:03:31,673 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:03:31,674 INFO L87 Difference]: Start difference. First operand 1062 states and 1564 transitions. Second operand has 18 states, 18 states have (on average 15.722222222222221) internal successors, (283), 18 states have internal predecessors, (283), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:03:31,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:31,856 INFO L93 Difference]: Finished difference Result 2053 states and 3038 transitions. [2024-12-02 06:03:31,856 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-12-02 06:03:31,857 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 15.722222222222221) internal successors, (283), 18 states have internal predecessors, (283), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 292 [2024-12-02 06:03:31,857 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:31,859 INFO L225 Difference]: With dead ends: 2053 [2024-12-02 06:03:31,859 INFO L226 Difference]: Without dead ends: 1110 [2024-12-02 06:03:31,860 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 591 GetRequests, 573 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:03:31,860 INFO L435 NwaCegarLoop]: 1157 mSDtfsCounter, 135 mSDsluCounter, 11475 mSDsCounter, 0 mSdLazyCounter, 232 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 135 SdHoareTripleChecker+Valid, 12632 SdHoareTripleChecker+Invalid, 233 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 232 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:31,861 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [135 Valid, 12632 Invalid, 233 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 232 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:03:31,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-12-02 06:03:31,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-12-02 06:03:31,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.46448087431694) internal successors, (1608), 1098 states have internal predecessors, (1608), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:31,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1628 transitions. [2024-12-02 06:03:31,878 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1628 transitions. Word has length 292 [2024-12-02 06:03:31,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:31,878 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1628 transitions. [2024-12-02 06:03:31,878 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 15.722222222222221) internal successors, (283), 18 states have internal predecessors, (283), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:03:31,878 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1628 transitions. [2024-12-02 06:03:31,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 309 [2024-12-02 06:03:31,880 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:31,880 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:31,888 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-12-02 06:03:32,080 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:32,080 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:32,081 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:32,081 INFO L85 PathProgramCache]: Analyzing trace with hash 1595157741, now seen corresponding path program 2 times [2024-12-02 06:03:32,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:32,081 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1424730291] [2024-12-02 06:03:32,081 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:03:32,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:32,155 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:03:32,156 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:03:32,474 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:03:32,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:32,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1424730291] [2024-12-02 06:03:32,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1424730291] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:32,474 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:32,474 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:03:32,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [734365615] [2024-12-02 06:03:32,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:32,475 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:03:32,475 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:32,475 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:03:32,475 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:03:32,476 INFO L87 Difference]: Start difference. First operand 1110 states and 1628 transitions. Second operand has 4 states, 4 states have (on average 57.5) internal successors, (230), 4 states have internal predecessors, (230), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:32,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:32,670 INFO L93 Difference]: Finished difference Result 1767 states and 2603 transitions. [2024-12-02 06:03:32,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:03:32,670 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 57.5) internal successors, (230), 4 states have internal predecessors, (230), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 308 [2024-12-02 06:03:32,671 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:32,674 INFO L225 Difference]: With dead ends: 1767 [2024-12-02 06:03:32,674 INFO L226 Difference]: Without dead ends: 1110 [2024-12-02 06:03:32,675 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:03:32,675 INFO L435 NwaCegarLoop]: 1012 mSDtfsCounter, 955 mSDsluCounter, 1014 mSDsCounter, 0 mSdLazyCounter, 204 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 955 SdHoareTripleChecker+Valid, 2026 SdHoareTripleChecker+Invalid, 204 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 204 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:32,675 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [955 Valid, 2026 Invalid, 204 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 204 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:03:32,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-12-02 06:03:32,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-12-02 06:03:32,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.4635701275045538) internal successors, (1607), 1098 states have internal predecessors, (1607), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:32,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1627 transitions. [2024-12-02 06:03:32,701 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1627 transitions. Word has length 308 [2024-12-02 06:03:32,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:32,701 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1627 transitions. [2024-12-02 06:03:32,701 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 57.5) internal successors, (230), 4 states have internal predecessors, (230), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:32,702 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1627 transitions. [2024-12-02 06:03:32,704 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 310 [2024-12-02 06:03:32,704 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:32,704 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:32,704 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2024-12-02 06:03:32,704 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:32,705 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:32,705 INFO L85 PathProgramCache]: Analyzing trace with hash -663449310, now seen corresponding path program 1 times [2024-12-02 06:03:32,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:32,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240263334] [2024-12-02 06:03:32,705 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:32,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:32,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:33,168 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:03:33,168 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:33,168 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1240263334] [2024-12-02 06:03:33,168 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1240263334] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:33,168 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:33,168 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:03:33,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1135216456] [2024-12-02 06:03:33,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:33,168 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:03:33,168 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:33,169 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:03:33,169 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:03:33,169 INFO L87 Difference]: Start difference. First operand 1110 states and 1627 transitions. Second operand has 5 states, 5 states have (on average 46.2) internal successors, (231), 5 states have internal predecessors, (231), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:33,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:33,300 INFO L93 Difference]: Finished difference Result 1805 states and 2656 transitions. [2024-12-02 06:03:33,300 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:03:33,300 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 46.2) internal successors, (231), 5 states have internal predecessors, (231), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 309 [2024-12-02 06:03:33,300 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:33,302 INFO L225 Difference]: With dead ends: 1805 [2024-12-02 06:03:33,302 INFO L226 Difference]: Without dead ends: 1110 [2024-12-02 06:03:33,303 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:03:33,303 INFO L435 NwaCegarLoop]: 1100 mSDtfsCounter, 1046 mSDsluCounter, 2118 mSDsCounter, 0 mSdLazyCounter, 123 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1046 SdHoareTripleChecker+Valid, 3218 SdHoareTripleChecker+Invalid, 124 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 123 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:33,304 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1046 Valid, 3218 Invalid, 124 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 123 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:03:33,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-12-02 06:03:33,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-12-02 06:03:33,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.4617486338797814) internal successors, (1605), 1098 states have internal predecessors, (1605), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:33,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1625 transitions. [2024-12-02 06:03:33,329 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1625 transitions. Word has length 309 [2024-12-02 06:03:33,330 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:33,330 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1625 transitions. [2024-12-02 06:03:33,330 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 46.2) internal successors, (231), 5 states have internal predecessors, (231), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:33,330 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1625 transitions. [2024-12-02 06:03:33,332 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 311 [2024-12-02 06:03:33,332 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:33,333 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:33,333 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2024-12-02 06:03:33,333 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:33,333 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:33,333 INFO L85 PathProgramCache]: Analyzing trace with hash -280266578, now seen corresponding path program 1 times [2024-12-02 06:03:33,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:33,333 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1663612527] [2024-12-02 06:03:33,333 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:33,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:33,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:34,044 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:03:34,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:34,044 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1663612527] [2024-12-02 06:03:34,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1663612527] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:34,044 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:34,044 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:03:34,045 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [418669387] [2024-12-02 06:03:34,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:34,045 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:03:34,045 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:34,046 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:03:34,046 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:03:34,046 INFO L87 Difference]: Start difference. First operand 1110 states and 1625 transitions. Second operand has 5 states, 5 states have (on average 46.4) internal successors, (232), 5 states have internal predecessors, (232), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:34,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:34,320 INFO L93 Difference]: Finished difference Result 1773 states and 2606 transitions. [2024-12-02 06:03:34,321 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:03:34,321 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 46.4) internal successors, (232), 5 states have internal predecessors, (232), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 310 [2024-12-02 06:03:34,322 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:34,325 INFO L225 Difference]: With dead ends: 1773 [2024-12-02 06:03:34,325 INFO L226 Difference]: Without dead ends: 1110 [2024-12-02 06:03:34,326 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:03:34,327 INFO L435 NwaCegarLoop]: 1012 mSDtfsCounter, 1090 mSDsluCounter, 1023 mSDsCounter, 0 mSdLazyCounter, 200 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1095 SdHoareTripleChecker+Valid, 2035 SdHoareTripleChecker+Invalid, 200 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 200 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:34,327 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1095 Valid, 2035 Invalid, 200 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 200 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:03:34,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-12-02 06:03:34,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-12-02 06:03:34,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.4599271402550091) internal successors, (1603), 1098 states have internal predecessors, (1603), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:34,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1623 transitions. [2024-12-02 06:03:34,360 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1623 transitions. Word has length 310 [2024-12-02 06:03:34,361 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:34,361 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1623 transitions. [2024-12-02 06:03:34,361 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 46.4) internal successors, (232), 5 states have internal predecessors, (232), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:34,361 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1623 transitions. [2024-12-02 06:03:34,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 312 [2024-12-02 06:03:34,363 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:34,363 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:34,364 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2024-12-02 06:03:34,364 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:34,364 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:34,364 INFO L85 PathProgramCache]: Analyzing trace with hash 260057573, now seen corresponding path program 1 times [2024-12-02 06:03:34,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:34,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774045689] [2024-12-02 06:03:34,364 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:34,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:34,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:35,006 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:03:35,006 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:35,006 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1774045689] [2024-12-02 06:03:35,006 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1774045689] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:35,006 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:35,006 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:03:35,006 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96325581] [2024-12-02 06:03:35,006 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:35,007 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:03:35,007 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:35,007 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:03:35,007 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:03:35,007 INFO L87 Difference]: Start difference. First operand 1110 states and 1623 transitions. Second operand has 4 states, 4 states have (on average 58.25) internal successors, (233), 4 states have internal predecessors, (233), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:35,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:35,182 INFO L93 Difference]: Finished difference Result 1767 states and 2595 transitions. [2024-12-02 06:03:35,183 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:03:35,183 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 58.25) internal successors, (233), 4 states have internal predecessors, (233), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 311 [2024-12-02 06:03:35,183 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:35,185 INFO L225 Difference]: With dead ends: 1767 [2024-12-02 06:03:35,185 INFO L226 Difference]: Without dead ends: 1110 [2024-12-02 06:03:35,186 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:03:35,186 INFO L435 NwaCegarLoop]: 1012 mSDtfsCounter, 949 mSDsluCounter, 1014 mSDsCounter, 0 mSdLazyCounter, 198 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 949 SdHoareTripleChecker+Valid, 2026 SdHoareTripleChecker+Invalid, 198 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 198 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:35,186 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [949 Valid, 2026 Invalid, 198 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 198 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:03:35,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-12-02 06:03:35,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-12-02 06:03:35,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.459016393442623) internal successors, (1602), 1098 states have internal predecessors, (1602), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:35,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1622 transitions. [2024-12-02 06:03:35,210 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1622 transitions. Word has length 311 [2024-12-02 06:03:35,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:35,210 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1622 transitions. [2024-12-02 06:03:35,210 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 58.25) internal successors, (233), 4 states have internal predecessors, (233), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:35,210 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1622 transitions. [2024-12-02 06:03:35,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 313 [2024-12-02 06:03:35,212 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:35,213 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:35,213 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2024-12-02 06:03:35,213 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:35,213 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:35,213 INFO L85 PathProgramCache]: Analyzing trace with hash -815635257, now seen corresponding path program 1 times [2024-12-02 06:03:35,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:35,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [952184366] [2024-12-02 06:03:35,214 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:35,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:35,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:36,741 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:03:36,741 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:36,741 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [952184366] [2024-12-02 06:03:36,741 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [952184366] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:36,741 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:36,741 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:03:36,741 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [589070882] [2024-12-02 06:03:36,741 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:36,742 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:03:36,742 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:36,742 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:03:36,743 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:03:36,743 INFO L87 Difference]: Start difference. First operand 1110 states and 1622 transitions. Second operand has 8 states, 8 states have (on average 29.25) internal successors, (234), 8 states have internal predecessors, (234), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:36,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:36,884 INFO L93 Difference]: Finished difference Result 1879 states and 2758 transitions. [2024-12-02 06:03:36,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:03:36,885 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 29.25) internal successors, (234), 8 states have internal predecessors, (234), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 312 [2024-12-02 06:03:36,885 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:36,888 INFO L225 Difference]: With dead ends: 1879 [2024-12-02 06:03:36,888 INFO L226 Difference]: Without dead ends: 1134 [2024-12-02 06:03:36,889 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:03:36,889 INFO L435 NwaCegarLoop]: 1088 mSDtfsCounter, 1034 mSDsluCounter, 5381 mSDsCounter, 0 mSdLazyCounter, 157 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1037 SdHoareTripleChecker+Valid, 6469 SdHoareTripleChecker+Invalid, 158 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 157 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:36,889 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1037 Valid, 6469 Invalid, 158 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 157 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:03:36,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1134 states. [2024-12-02 06:03:36,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1134 to 1128. [2024-12-02 06:03:36,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1128 states, 1116 states have (on average 1.4587813620071686) internal successors, (1628), 1116 states have internal predecessors, (1628), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:36,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1128 states to 1128 states and 1648 transitions. [2024-12-02 06:03:36,912 INFO L78 Accepts]: Start accepts. Automaton has 1128 states and 1648 transitions. Word has length 312 [2024-12-02 06:03:36,913 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:36,913 INFO L471 AbstractCegarLoop]: Abstraction has 1128 states and 1648 transitions. [2024-12-02 06:03:36,913 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 29.25) internal successors, (234), 8 states have internal predecessors, (234), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:36,913 INFO L276 IsEmpty]: Start isEmpty. Operand 1128 states and 1648 transitions. [2024-12-02 06:03:36,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 314 [2024-12-02 06:03:36,915 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:36,915 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:36,916 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2024-12-02 06:03:36,916 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:36,916 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:36,916 INFO L85 PathProgramCache]: Analyzing trace with hash -395838274, now seen corresponding path program 1 times [2024-12-02 06:03:36,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:36,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556286891] [2024-12-02 06:03:36,916 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:36,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:37,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:37,330 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:03:37,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:37,330 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1556286891] [2024-12-02 06:03:37,330 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1556286891] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:37,330 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:37,330 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:03:37,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1076809485] [2024-12-02 06:03:37,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:37,331 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:03:37,331 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:37,331 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:03:37,332 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:03:37,332 INFO L87 Difference]: Start difference. First operand 1128 states and 1648 transitions. Second operand has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:38,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:38,029 INFO L93 Difference]: Finished difference Result 1886 states and 2767 transitions. [2024-12-02 06:03:38,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:03:38,030 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 313 [2024-12-02 06:03:38,030 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:38,032 INFO L225 Difference]: With dead ends: 1886 [2024-12-02 06:03:38,032 INFO L226 Difference]: Without dead ends: 1136 [2024-12-02 06:03:38,032 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:03:38,033 INFO L435 NwaCegarLoop]: 816 mSDtfsCounter, 1024 mSDsluCounter, 2423 mSDsCounter, 0 mSdLazyCounter, 1194 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1027 SdHoareTripleChecker+Valid, 3239 SdHoareTripleChecker+Invalid, 1195 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1194 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:38,033 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1027 Valid, 3239 Invalid, 1195 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1194 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-12-02 06:03:38,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1136 states. [2024-12-02 06:03:38,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1136 to 1132. [2024-12-02 06:03:38,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1132 states, 1120 states have (on average 1.457142857142857) internal successors, (1632), 1120 states have internal predecessors, (1632), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:38,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1132 states to 1132 states and 1652 transitions. [2024-12-02 06:03:38,052 INFO L78 Accepts]: Start accepts. Automaton has 1132 states and 1652 transitions. Word has length 313 [2024-12-02 06:03:38,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:38,053 INFO L471 AbstractCegarLoop]: Abstraction has 1132 states and 1652 transitions. [2024-12-02 06:03:38,053 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:38,053 INFO L276 IsEmpty]: Start isEmpty. Operand 1132 states and 1652 transitions. [2024-12-02 06:03:38,055 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 314 [2024-12-02 06:03:38,055 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:38,055 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:38,055 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2024-12-02 06:03:38,055 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:38,056 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:38,056 INFO L85 PathProgramCache]: Analyzing trace with hash -257926317, now seen corresponding path program 1 times [2024-12-02 06:03:38,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:38,056 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705691643] [2024-12-02 06:03:38,056 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:38,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:38,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:38,468 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:03:38,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:38,468 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1705691643] [2024-12-02 06:03:38,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1705691643] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:38,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:38,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:03:38,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1721128861] [2024-12-02 06:03:38,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:38,469 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:03:38,469 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:38,469 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:03:38,469 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:03:38,470 INFO L87 Difference]: Start difference. First operand 1132 states and 1652 transitions. Second operand has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:39,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:39,058 INFO L93 Difference]: Finished difference Result 1908 states and 2796 transitions. [2024-12-02 06:03:39,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:03:39,058 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 313 [2024-12-02 06:03:39,059 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:39,060 INFO L225 Difference]: With dead ends: 1908 [2024-12-02 06:03:39,060 INFO L226 Difference]: Without dead ends: 1136 [2024-12-02 06:03:39,061 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:03:39,061 INFO L435 NwaCegarLoop]: 818 mSDtfsCounter, 1030 mSDsluCounter, 2426 mSDsCounter, 0 mSdLazyCounter, 1180 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1033 SdHoareTripleChecker+Valid, 3244 SdHoareTripleChecker+Invalid, 1182 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 1180 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:39,061 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1033 Valid, 3244 Invalid, 1182 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 1180 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-12-02 06:03:39,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1136 states. [2024-12-02 06:03:39,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1136 to 1136. [2024-12-02 06:03:39,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1136 states, 1124 states have (on average 1.4555160142348755) internal successors, (1636), 1124 states have internal predecessors, (1636), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:39,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1136 states to 1136 states and 1656 transitions. [2024-12-02 06:03:39,085 INFO L78 Accepts]: Start accepts. Automaton has 1136 states and 1656 transitions. Word has length 313 [2024-12-02 06:03:39,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:39,086 INFO L471 AbstractCegarLoop]: Abstraction has 1136 states and 1656 transitions. [2024-12-02 06:03:39,086 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:39,086 INFO L276 IsEmpty]: Start isEmpty. Operand 1136 states and 1656 transitions. [2024-12-02 06:03:39,088 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 315 [2024-12-02 06:03:39,088 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:39,088 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:39,088 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2024-12-02 06:03:39,088 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:39,089 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:39,089 INFO L85 PathProgramCache]: Analyzing trace with hash 1921876768, now seen corresponding path program 1 times [2024-12-02 06:03:39,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:39,089 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077730984] [2024-12-02 06:03:39,089 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:39,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:39,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:39,980 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:03:39,980 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:39,980 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077730984] [2024-12-02 06:03:39,980 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077730984] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:39,980 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:39,981 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:03:39,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [718308432] [2024-12-02 06:03:39,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:39,981 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:03:39,981 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:39,982 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:03:39,982 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:03:39,982 INFO L87 Difference]: Start difference. First operand 1136 states and 1656 transitions. Second operand has 6 states, 6 states have (on average 39.333333333333336) internal successors, (236), 6 states have internal predecessors, (236), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:40,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:40,814 INFO L93 Difference]: Finished difference Result 2363 states and 3467 transitions. [2024-12-02 06:03:40,815 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:03:40,815 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.333333333333336) internal successors, (236), 6 states have internal predecessors, (236), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 314 [2024-12-02 06:03:40,815 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:40,820 INFO L225 Difference]: With dead ends: 2363 [2024-12-02 06:03:40,820 INFO L226 Difference]: Without dead ends: 1693 [2024-12-02 06:03:40,821 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:03:40,821 INFO L435 NwaCegarLoop]: 809 mSDtfsCounter, 2525 mSDsluCounter, 2343 mSDsCounter, 0 mSdLazyCounter, 1165 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2530 SdHoareTripleChecker+Valid, 3152 SdHoareTripleChecker+Invalid, 1168 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1165 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:40,821 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2530 Valid, 3152 Invalid, 1168 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1165 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2024-12-02 06:03:40,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1693 states. [2024-12-02 06:03:40,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1693 to 1022. [2024-12-02 06:03:40,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1022 states, 1010 states have (on average 1.4584158415841584) internal successors, (1473), 1010 states have internal predecessors, (1473), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:40,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1022 states to 1022 states and 1493 transitions. [2024-12-02 06:03:40,858 INFO L78 Accepts]: Start accepts. Automaton has 1022 states and 1493 transitions. Word has length 314 [2024-12-02 06:03:40,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:40,858 INFO L471 AbstractCegarLoop]: Abstraction has 1022 states and 1493 transitions. [2024-12-02 06:03:40,858 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.333333333333336) internal successors, (236), 6 states have internal predecessors, (236), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:40,858 INFO L276 IsEmpty]: Start isEmpty. Operand 1022 states and 1493 transitions. [2024-12-02 06:03:40,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 316 [2024-12-02 06:03:40,860 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:40,860 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:40,860 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2024-12-02 06:03:40,860 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:40,861 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:40,861 INFO L85 PathProgramCache]: Analyzing trace with hash 1323386401, now seen corresponding path program 1 times [2024-12-02 06:03:40,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:40,861 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1755926380] [2024-12-02 06:03:40,861 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:40,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:41,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:41,998 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:03:41,999 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:41,999 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1755926380] [2024-12-02 06:03:41,999 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1755926380] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:41,999 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:41,999 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:03:41,999 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1451051789] [2024-12-02 06:03:41,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:42,000 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:03:42,000 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:42,000 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:03:42,000 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:03:42,001 INFO L87 Difference]: Start difference. First operand 1022 states and 1493 transitions. Second operand has 8 states, 8 states have (on average 29.625) internal successors, (237), 8 states have internal predecessors, (237), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:42,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:42,137 INFO L93 Difference]: Finished difference Result 1767 states and 2590 transitions. [2024-12-02 06:03:42,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:03:42,138 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 29.625) internal successors, (237), 8 states have internal predecessors, (237), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 315 [2024-12-02 06:03:42,138 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:42,140 INFO L225 Difference]: With dead ends: 1767 [2024-12-02 06:03:42,140 INFO L226 Difference]: Without dead ends: 1046 [2024-12-02 06:03:42,140 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:03:42,141 INFO L435 NwaCegarLoop]: 1088 mSDtfsCounter, 1010 mSDsluCounter, 5390 mSDsCounter, 0 mSdLazyCounter, 157 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1012 SdHoareTripleChecker+Valid, 6478 SdHoareTripleChecker+Invalid, 158 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 157 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:42,141 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1012 Valid, 6478 Invalid, 158 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 157 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:03:42,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1046 states. [2024-12-02 06:03:42,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1046 to 1040. [2024-12-02 06:03:42,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1040 states, 1028 states have (on average 1.4581712062256809) internal successors, (1499), 1028 states have internal predecessors, (1499), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:42,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1040 states to 1040 states and 1519 transitions. [2024-12-02 06:03:42,155 INFO L78 Accepts]: Start accepts. Automaton has 1040 states and 1519 transitions. Word has length 315 [2024-12-02 06:03:42,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:42,155 INFO L471 AbstractCegarLoop]: Abstraction has 1040 states and 1519 transitions. [2024-12-02 06:03:42,155 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 29.625) internal successors, (237), 8 states have internal predecessors, (237), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:42,155 INFO L276 IsEmpty]: Start isEmpty. Operand 1040 states and 1519 transitions. [2024-12-02 06:03:42,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 317 [2024-12-02 06:03:42,156 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:42,156 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:42,157 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2024-12-02 06:03:42,157 INFO L396 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:42,157 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:42,157 INFO L85 PathProgramCache]: Analyzing trace with hash 1658628649, now seen corresponding path program 1 times [2024-12-02 06:03:42,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:42,157 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [183820526] [2024-12-02 06:03:42,157 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:42,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:42,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:42,663 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:03:42,663 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:42,663 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [183820526] [2024-12-02 06:03:42,663 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [183820526] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:42,663 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:42,663 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:03:42,663 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1812348767] [2024-12-02 06:03:42,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:42,664 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:03:42,664 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:42,664 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:03:42,664 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:03:42,664 INFO L87 Difference]: Start difference. First operand 1040 states and 1519 transitions. Second operand has 6 states, 6 states have (on average 39.666666666666664) internal successors, (238), 6 states have internal predecessors, (238), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:03:43,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:43,173 INFO L93 Difference]: Finished difference Result 1774 states and 2599 transitions. [2024-12-02 06:03:43,173 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:03:43,173 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.666666666666664) internal successors, (238), 6 states have internal predecessors, (238), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 316 [2024-12-02 06:03:43,173 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:43,179 INFO L225 Difference]: With dead ends: 1774 [2024-12-02 06:03:43,179 INFO L226 Difference]: Without dead ends: 1048 [2024-12-02 06:03:43,180 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:03:43,180 INFO L435 NwaCegarLoop]: 816 mSDtfsCounter, 1071 mSDsluCounter, 2414 mSDsCounter, 0 mSdLazyCounter, 1194 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1075 SdHoareTripleChecker+Valid, 3230 SdHoareTripleChecker+Invalid, 1195 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1194 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:43,180 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1075 Valid, 3230 Invalid, 1195 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1194 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-12-02 06:03:43,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1048 states. [2024-12-02 06:03:43,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1048 to 1044. [2024-12-02 06:03:43,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1044 states, 1032 states have (on average 1.4563953488372092) internal successors, (1503), 1032 states have internal predecessors, (1503), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:43,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1044 states to 1044 states and 1523 transitions. [2024-12-02 06:03:43,194 INFO L78 Accepts]: Start accepts. Automaton has 1044 states and 1523 transitions. Word has length 316 [2024-12-02 06:03:43,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:43,194 INFO L471 AbstractCegarLoop]: Abstraction has 1044 states and 1523 transitions. [2024-12-02 06:03:43,194 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.666666666666664) internal successors, (238), 6 states have internal predecessors, (238), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:03:43,194 INFO L276 IsEmpty]: Start isEmpty. Operand 1044 states and 1523 transitions. [2024-12-02 06:03:43,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 317 [2024-12-02 06:03:43,195 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:43,196 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:43,196 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2024-12-02 06:03:43,196 INFO L396 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:43,196 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:43,196 INFO L85 PathProgramCache]: Analyzing trace with hash 874653310, now seen corresponding path program 1 times [2024-12-02 06:03:43,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:43,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [300036502] [2024-12-02 06:03:43,196 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:43,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:43,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:44,227 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:03:44,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:44,228 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [300036502] [2024-12-02 06:03:44,228 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [300036502] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:44,228 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:44,228 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:03:44,228 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790115820] [2024-12-02 06:03:44,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:44,229 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:03:44,229 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:44,229 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:03:44,229 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:03:44,230 INFO L87 Difference]: Start difference. First operand 1044 states and 1523 transitions. Second operand has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:44,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:44,344 INFO L93 Difference]: Finished difference Result 1859 states and 2719 transitions. [2024-12-02 06:03:44,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:03:44,344 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 316 [2024-12-02 06:03:44,344 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:44,347 INFO L225 Difference]: With dead ends: 1859 [2024-12-02 06:03:44,347 INFO L226 Difference]: Without dead ends: 1070 [2024-12-02 06:03:44,348 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:03:44,348 INFO L435 NwaCegarLoop]: 1089 mSDtfsCounter, 1022 mSDsluCounter, 4311 mSDsCounter, 0 mSdLazyCounter, 126 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1025 SdHoareTripleChecker+Valid, 5400 SdHoareTripleChecker+Invalid, 127 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 126 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:44,348 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1025 Valid, 5400 Invalid, 127 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 126 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:03:44,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1070 states. [2024-12-02 06:03:44,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1070 to 1050. [2024-12-02 06:03:44,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1050 states, 1038 states have (on average 1.4556840077071291) internal successors, (1511), 1038 states have internal predecessors, (1511), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:44,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1050 states to 1050 states and 1531 transitions. [2024-12-02 06:03:44,374 INFO L78 Accepts]: Start accepts. Automaton has 1050 states and 1531 transitions. Word has length 316 [2024-12-02 06:03:44,374 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:44,374 INFO L471 AbstractCegarLoop]: Abstraction has 1050 states and 1531 transitions. [2024-12-02 06:03:44,375 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:44,375 INFO L276 IsEmpty]: Start isEmpty. Operand 1050 states and 1531 transitions. [2024-12-02 06:03:44,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 317 [2024-12-02 06:03:44,376 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:44,376 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:44,376 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2024-12-02 06:03:44,376 INFO L396 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:44,377 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:44,377 INFO L85 PathProgramCache]: Analyzing trace with hash 2027061502, now seen corresponding path program 1 times [2024-12-02 06:03:44,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:44,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722550427] [2024-12-02 06:03:44,377 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:44,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:44,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:44,810 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:03:44,810 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:44,810 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1722550427] [2024-12-02 06:03:44,810 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1722550427] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:44,810 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:44,811 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:03:44,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [871947604] [2024-12-02 06:03:44,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:44,811 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:03:44,811 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:44,812 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:03:44,812 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:03:44,812 INFO L87 Difference]: Start difference. First operand 1050 states and 1531 transitions. Second operand has 4 states, 4 states have (on average 59.5) internal successors, (238), 4 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:44,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:44,849 INFO L93 Difference]: Finished difference Result 1830 states and 2678 transitions. [2024-12-02 06:03:44,850 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:03:44,850 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 59.5) internal successors, (238), 4 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 316 [2024-12-02 06:03:44,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:44,852 INFO L225 Difference]: With dead ends: 1830 [2024-12-02 06:03:44,852 INFO L226 Difference]: Without dead ends: 1046 [2024-12-02 06:03:44,852 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:03:44,853 INFO L435 NwaCegarLoop]: 1093 mSDtfsCounter, 1010 mSDsluCounter, 1100 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1013 SdHoareTripleChecker+Valid, 2193 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:44,853 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1013 Valid, 2193 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:03:44,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1046 states. [2024-12-02 06:03:44,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1046 to 1046. [2024-12-02 06:03:44,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1046 states, 1034 states have (on average 1.4555125725338491) internal successors, (1505), 1034 states have internal predecessors, (1505), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:44,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1046 states to 1046 states and 1525 transitions. [2024-12-02 06:03:44,867 INFO L78 Accepts]: Start accepts. Automaton has 1046 states and 1525 transitions. Word has length 316 [2024-12-02 06:03:44,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:44,867 INFO L471 AbstractCegarLoop]: Abstraction has 1046 states and 1525 transitions. [2024-12-02 06:03:44,867 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 59.5) internal successors, (238), 4 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:44,867 INFO L276 IsEmpty]: Start isEmpty. Operand 1046 states and 1525 transitions. [2024-12-02 06:03:44,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 317 [2024-12-02 06:03:44,868 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:44,868 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:44,868 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2024-12-02 06:03:44,868 INFO L396 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:44,869 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:44,869 INFO L85 PathProgramCache]: Analyzing trace with hash -657479526, now seen corresponding path program 1 times [2024-12-02 06:03:44,869 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:44,869 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68497422] [2024-12-02 06:03:44,869 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:44,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:45,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:45,708 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:03:45,708 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:45,708 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [68497422] [2024-12-02 06:03:45,708 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [68497422] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:45,708 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:45,708 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:03:45,708 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [212022186] [2024-12-02 06:03:45,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:45,709 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:03:45,709 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:45,709 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:03:45,709 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:03:45,709 INFO L87 Difference]: Start difference. First operand 1046 states and 1525 transitions. Second operand has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:45,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:45,821 INFO L93 Difference]: Finished difference Result 1813 states and 2650 transitions. [2024-12-02 06:03:45,822 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:03:45,822 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 316 [2024-12-02 06:03:45,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:45,825 INFO L225 Difference]: With dead ends: 1813 [2024-12-02 06:03:45,825 INFO L226 Difference]: Without dead ends: 1072 [2024-12-02 06:03:45,826 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:03:45,828 INFO L435 NwaCegarLoop]: 1088 mSDtfsCounter, 1001 mSDsluCounter, 4316 mSDsCounter, 0 mSdLazyCounter, 126 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1003 SdHoareTripleChecker+Valid, 5404 SdHoareTripleChecker+Invalid, 127 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 126 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:45,828 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1003 Valid, 5404 Invalid, 127 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 126 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:03:45,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1072 states. [2024-12-02 06:03:45,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1072 to 1052. [2024-12-02 06:03:45,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1052 states, 1040 states have (on average 1.4548076923076922) internal successors, (1513), 1040 states have internal predecessors, (1513), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:45,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1052 states to 1052 states and 1533 transitions. [2024-12-02 06:03:45,842 INFO L78 Accepts]: Start accepts. Automaton has 1052 states and 1533 transitions. Word has length 316 [2024-12-02 06:03:45,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:45,842 INFO L471 AbstractCegarLoop]: Abstraction has 1052 states and 1533 transitions. [2024-12-02 06:03:45,842 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:03:45,842 INFO L276 IsEmpty]: Start isEmpty. Operand 1052 states and 1533 transitions. [2024-12-02 06:03:45,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 318 [2024-12-02 06:03:45,843 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:45,843 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:45,843 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2024-12-02 06:03:45,843 INFO L396 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:45,844 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:45,844 INFO L85 PathProgramCache]: Analyzing trace with hash 1689075490, now seen corresponding path program 1 times [2024-12-02 06:03:45,844 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:45,844 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280543737] [2024-12-02 06:03:45,844 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:45,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:46,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:46,659 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:03:46,659 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:46,660 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280543737] [2024-12-02 06:03:46,660 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1280543737] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:46,660 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:46,660 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:03:46,660 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [516994502] [2024-12-02 06:03:46,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:46,660 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:03:46,660 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:46,661 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:03:46,661 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:03:46,661 INFO L87 Difference]: Start difference. First operand 1052 states and 1533 transitions. Second operand has 6 states, 6 states have (on average 39.833333333333336) internal successors, (239), 6 states have internal predecessors, (239), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:46,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:46,793 INFO L93 Difference]: Finished difference Result 1908 states and 2795 transitions. [2024-12-02 06:03:46,793 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:03:46,793 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.833333333333336) internal successors, (239), 6 states have internal predecessors, (239), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 317 [2024-12-02 06:03:46,794 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:46,797 INFO L225 Difference]: With dead ends: 1908 [2024-12-02 06:03:46,797 INFO L226 Difference]: Without dead ends: 1223 [2024-12-02 06:03:46,798 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:03:46,798 INFO L435 NwaCegarLoop]: 1091 mSDtfsCounter, 1815 mSDsluCounter, 3267 mSDsCounter, 0 mSdLazyCounter, 82 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1820 SdHoareTripleChecker+Valid, 4358 SdHoareTripleChecker+Invalid, 87 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 82 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:46,799 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1820 Valid, 4358 Invalid, 87 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 82 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:03:46,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1223 states. [2024-12-02 06:03:46,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1223 to 1223. [2024-12-02 06:03:46,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1223 states, 1211 states have (on average 1.458298926507019) internal successors, (1766), 1211 states have internal predecessors, (1766), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:46,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1223 states to 1223 states and 1786 transitions. [2024-12-02 06:03:46,824 INFO L78 Accepts]: Start accepts. Automaton has 1223 states and 1786 transitions. Word has length 317 [2024-12-02 06:03:46,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:46,824 INFO L471 AbstractCegarLoop]: Abstraction has 1223 states and 1786 transitions. [2024-12-02 06:03:46,824 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.833333333333336) internal successors, (239), 6 states have internal predecessors, (239), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:03:46,825 INFO L276 IsEmpty]: Start isEmpty. Operand 1223 states and 1786 transitions. [2024-12-02 06:03:46,829 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 679 [2024-12-02 06:03:46,829 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:46,829 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:46,830 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2024-12-02 06:03:46,830 INFO L396 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:46,830 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:46,830 INFO L85 PathProgramCache]: Analyzing trace with hash -1448692047, now seen corresponding path program 1 times [2024-12-02 06:03:46,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:46,830 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1913794937] [2024-12-02 06:03:46,831 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:46,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:47,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:47,739 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:03:47,739 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:47,739 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1913794937] [2024-12-02 06:03:47,739 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1913794937] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:47,739 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:03:47,739 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:03:47,739 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [332382859] [2024-12-02 06:03:47,739 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:47,740 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:03:47,740 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:47,741 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:03:47,741 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:03:47,741 INFO L87 Difference]: Start difference. First operand 1223 states and 1786 transitions. Second operand has 3 states, 3 states have (on average 191.66666666666666) internal successors, (575), 3 states have internal predecessors, (575), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:03:47,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:47,780 INFO L93 Difference]: Finished difference Result 1910 states and 2797 transitions. [2024-12-02 06:03:47,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:03:47,781 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 191.66666666666666) internal successors, (575), 3 states have internal predecessors, (575), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 678 [2024-12-02 06:03:47,781 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:47,784 INFO L225 Difference]: With dead ends: 1910 [2024-12-02 06:03:47,784 INFO L226 Difference]: Without dead ends: 1225 [2024-12-02 06:03:47,784 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:03:47,785 INFO L435 NwaCegarLoop]: 1106 mSDtfsCounter, 1 mSDsluCounter, 1102 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2208 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:47,785 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2208 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:03:47,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1225 states. [2024-12-02 06:03:47,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1225 to 1224. [2024-12-02 06:03:47,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1224 states, 1212 states have (on average 1.4579207920792079) internal successors, (1767), 1212 states have internal predecessors, (1767), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:47,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1224 states to 1224 states and 1787 transitions. [2024-12-02 06:03:47,825 INFO L78 Accepts]: Start accepts. Automaton has 1224 states and 1787 transitions. Word has length 678 [2024-12-02 06:03:47,825 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:47,825 INFO L471 AbstractCegarLoop]: Abstraction has 1224 states and 1787 transitions. [2024-12-02 06:03:47,826 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 191.66666666666666) internal successors, (575), 3 states have internal predecessors, (575), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:03:47,826 INFO L276 IsEmpty]: Start isEmpty. Operand 1224 states and 1787 transitions. [2024-12-02 06:03:47,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 681 [2024-12-02 06:03:47,835 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:47,835 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:47,836 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23 [2024-12-02 06:03:47,836 INFO L396 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:47,836 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:47,836 INFO L85 PathProgramCache]: Analyzing trace with hash 1803025741, now seen corresponding path program 1 times [2024-12-02 06:03:47,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:47,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135194864] [2024-12-02 06:03:47,837 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:47,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:48,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:48,707 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:03:48,707 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:48,707 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135194864] [2024-12-02 06:03:48,707 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135194864] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:03:48,707 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1828195587] [2024-12-02 06:03:48,707 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:48,707 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:48,707 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:03:48,709 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:03:48,710 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-12-02 06:03:49,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:49,597 INFO L256 TraceCheckSpWp]: Trace formula consists of 3370 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-12-02 06:03:49,604 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:03:50,367 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 0 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2024-12-02 06:03:50,367 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:03:50,367 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1828195587] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:50,367 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:03:50,367 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2024-12-02 06:03:50,367 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1659403262] [2024-12-02 06:03:50,367 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:50,368 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:03:50,368 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:50,368 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:03:50,368 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:03:50,369 INFO L87 Difference]: Start difference. First operand 1224 states and 1787 transitions. Second operand has 4 states, 4 states have (on average 145.0) internal successors, (580), 4 states have internal predecessors, (580), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:03:50,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:50,756 INFO L93 Difference]: Finished difference Result 1909 states and 2795 transitions. [2024-12-02 06:03:50,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:03:50,756 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 145.0) internal successors, (580), 4 states have internal predecessors, (580), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 680 [2024-12-02 06:03:50,757 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:50,759 INFO L225 Difference]: With dead ends: 1909 [2024-12-02 06:03:50,759 INFO L226 Difference]: Without dead ends: 1223 [2024-12-02 06:03:50,760 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 684 GetRequests, 679 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:03:50,760 INFO L435 NwaCegarLoop]: 807 mSDtfsCounter, 830 mSDsluCounter, 809 mSDsCounter, 0 mSdLazyCounter, 601 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 830 SdHoareTripleChecker+Valid, 1616 SdHoareTripleChecker+Invalid, 602 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 601 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:50,760 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [830 Valid, 1616 Invalid, 602 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 601 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 06:03:50,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1223 states. [2024-12-02 06:03:50,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1223 to 1223. [2024-12-02 06:03:50,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1223 states, 1211 states have (on average 1.4566473988439306) internal successors, (1764), 1211 states have internal predecessors, (1764), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:50,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1223 states to 1223 states and 1784 transitions. [2024-12-02 06:03:50,776 INFO L78 Accepts]: Start accepts. Automaton has 1223 states and 1784 transitions. Word has length 680 [2024-12-02 06:03:50,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:50,777 INFO L471 AbstractCegarLoop]: Abstraction has 1223 states and 1784 transitions. [2024-12-02 06:03:50,777 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 145.0) internal successors, (580), 4 states have internal predecessors, (580), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:03:50,777 INFO L276 IsEmpty]: Start isEmpty. Operand 1223 states and 1784 transitions. [2024-12-02 06:03:50,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 682 [2024-12-02 06:03:50,780 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:50,780 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:50,795 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-12-02 06:03:50,981 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24,8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:50,981 INFO L396 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:50,981 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:50,981 INFO L85 PathProgramCache]: Analyzing trace with hash 1248578247, now seen corresponding path program 1 times [2024-12-02 06:03:50,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:50,982 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857799554] [2024-12-02 06:03:50,982 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:50,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:51,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:51,646 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:03:51,646 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:51,646 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857799554] [2024-12-02 06:03:51,646 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1857799554] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:03:51,646 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [809965809] [2024-12-02 06:03:51,646 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:51,646 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:51,646 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:03:51,648 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:03:51,648 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-12-02 06:03:52,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:52,628 INFO L256 TraceCheckSpWp]: Trace formula consists of 3373 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-12-02 06:03:52,636 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:03:53,407 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 0 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2024-12-02 06:03:53,408 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:03:53,408 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [809965809] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:53,408 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:03:53,408 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2024-12-02 06:03:53,408 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916467930] [2024-12-02 06:03:53,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:53,408 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:03:53,408 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:53,409 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:03:53,409 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:03:53,409 INFO L87 Difference]: Start difference. First operand 1223 states and 1784 transitions. Second operand has 4 states, 4 states have (on average 145.25) internal successors, (581), 4 states have internal predecessors, (581), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:03:53,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:53,800 INFO L93 Difference]: Finished difference Result 1907 states and 2789 transitions. [2024-12-02 06:03:53,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:03:53,801 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 145.25) internal successors, (581), 4 states have internal predecessors, (581), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 681 [2024-12-02 06:03:53,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:53,803 INFO L225 Difference]: With dead ends: 1907 [2024-12-02 06:03:53,803 INFO L226 Difference]: Without dead ends: 1222 [2024-12-02 06:03:53,803 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 685 GetRequests, 680 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:03:53,804 INFO L435 NwaCegarLoop]: 807 mSDtfsCounter, 822 mSDsluCounter, 809 mSDsCounter, 0 mSdLazyCounter, 595 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 822 SdHoareTripleChecker+Valid, 1616 SdHoareTripleChecker+Invalid, 596 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 595 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:53,804 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [822 Valid, 1616 Invalid, 596 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 595 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 06:03:53,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1222 states. [2024-12-02 06:03:53,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1222 to 1222. [2024-12-02 06:03:53,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1222 states, 1210 states have (on average 1.4553719008264463) internal successors, (1761), 1210 states have internal predecessors, (1761), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:53,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1222 states to 1222 states and 1781 transitions. [2024-12-02 06:03:53,819 INFO L78 Accepts]: Start accepts. Automaton has 1222 states and 1781 transitions. Word has length 681 [2024-12-02 06:03:53,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:53,819 INFO L471 AbstractCegarLoop]: Abstraction has 1222 states and 1781 transitions. [2024-12-02 06:03:53,819 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 145.25) internal successors, (581), 4 states have internal predecessors, (581), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:03:53,820 INFO L276 IsEmpty]: Start isEmpty. Operand 1222 states and 1781 transitions. [2024-12-02 06:03:53,822 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 683 [2024-12-02 06:03:53,822 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:53,822 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:53,833 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2024-12-02 06:03:54,023 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable25 [2024-12-02 06:03:54,023 INFO L396 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:54,023 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:54,023 INFO L85 PathProgramCache]: Analyzing trace with hash -454481253, now seen corresponding path program 1 times [2024-12-02 06:03:54,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:54,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [62761713] [2024-12-02 06:03:54,024 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:54,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:54,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:54,681 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:03:54,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:54,682 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [62761713] [2024-12-02 06:03:54,682 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [62761713] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:03:54,682 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [113428262] [2024-12-02 06:03:54,682 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:54,682 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:54,682 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:03:54,684 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:03:54,686 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-12-02 06:03:55,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:55,629 INFO L256 TraceCheckSpWp]: Trace formula consists of 3376 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-12-02 06:03:55,637 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:03:56,429 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 0 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2024-12-02 06:03:56,429 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:03:56,429 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [113428262] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:03:56,429 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:03:56,429 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2024-12-02 06:03:56,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [820605510] [2024-12-02 06:03:56,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:03:56,430 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:03:56,430 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:03:56,431 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:03:56,431 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:03:56,431 INFO L87 Difference]: Start difference. First operand 1222 states and 1781 transitions. Second operand has 4 states, 4 states have (on average 145.5) internal successors, (582), 4 states have internal predecessors, (582), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:03:56,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:03:56,771 INFO L93 Difference]: Finished difference Result 1905 states and 2783 transitions. [2024-12-02 06:03:56,771 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:03:56,772 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 145.5) internal successors, (582), 4 states have internal predecessors, (582), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 682 [2024-12-02 06:03:56,772 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:03:56,774 INFO L225 Difference]: With dead ends: 1905 [2024-12-02 06:03:56,774 INFO L226 Difference]: Without dead ends: 1221 [2024-12-02 06:03:56,775 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 686 GetRequests, 681 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:03:56,775 INFO L435 NwaCegarLoop]: 807 mSDtfsCounter, 808 mSDsluCounter, 809 mSDsCounter, 0 mSdLazyCounter, 589 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 808 SdHoareTripleChecker+Valid, 1616 SdHoareTripleChecker+Invalid, 590 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 589 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-12-02 06:03:56,776 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [808 Valid, 1616 Invalid, 590 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 589 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-12-02 06:03:56,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1221 states. [2024-12-02 06:03:56,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1221 to 1221. [2024-12-02 06:03:56,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1221 states, 1209 states have (on average 1.4540942928039702) internal successors, (1758), 1209 states have internal predecessors, (1758), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:03:56,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1221 states to 1221 states and 1778 transitions. [2024-12-02 06:03:56,802 INFO L78 Accepts]: Start accepts. Automaton has 1221 states and 1778 transitions. Word has length 682 [2024-12-02 06:03:56,802 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:03:56,802 INFO L471 AbstractCegarLoop]: Abstraction has 1221 states and 1778 transitions. [2024-12-02 06:03:56,802 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 145.5) internal successors, (582), 4 states have internal predecessors, (582), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:03:56,803 INFO L276 IsEmpty]: Start isEmpty. Operand 1221 states and 1778 transitions. [2024-12-02 06:03:56,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 684 [2024-12-02 06:03:56,807 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:03:56,808 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:03:56,818 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-12-02 06:03:57,008 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable26 [2024-12-02 06:03:57,008 INFO L396 AbstractCegarLoop]: === Iteration 28 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:03:57,009 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:03:57,009 INFO L85 PathProgramCache]: Analyzing trace with hash -725772091, now seen corresponding path program 1 times [2024-12-02 06:03:57,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:03:57,009 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896068161] [2024-12-02 06:03:57,009 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:57,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:03:57,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:57,814 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:03:57,815 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:03:57,815 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [896068161] [2024-12-02 06:03:57,815 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [896068161] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:03:57,815 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1470656762] [2024-12-02 06:03:57,815 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:03:57,815 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:03:57,815 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:03:57,816 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:03:57,817 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-12-02 06:03:58,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:03:58,816 INFO L256 TraceCheckSpWp]: Trace formula consists of 3379 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-12-02 06:03:58,824 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:03:59,629 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-12-02 06:03:59,629 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:00,324 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-12-02 06:04:00,324 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1470656762] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:00,324 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:04:00,324 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-12-02 06:04:00,324 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639357479] [2024-12-02 06:04:00,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:00,325 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:04:00,325 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:00,325 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:04:00,325 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-12-02 06:04:00,326 INFO L87 Difference]: Start difference. First operand 1221 states and 1778 transitions. Second operand has 5 states, 5 states have (on average 116.0) internal successors, (580), 5 states have internal predecessors, (580), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:00,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:00,504 INFO L93 Difference]: Finished difference Result 1904 states and 2778 transitions. [2024-12-02 06:04:00,504 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:04:00,504 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 116.0) internal successors, (580), 5 states have internal predecessors, (580), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 683 [2024-12-02 06:04:00,505 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:00,506 INFO L225 Difference]: With dead ends: 1904 [2024-12-02 06:04:00,506 INFO L226 Difference]: Without dead ends: 1221 [2024-12-02 06:04:00,507 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1369 GetRequests, 1351 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:04:00,507 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 915 mSDsluCounter, 1013 mSDsCounter, 0 mSdLazyCounter, 196 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 920 SdHoareTripleChecker+Valid, 2015 SdHoareTripleChecker+Invalid, 197 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 196 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:00,508 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [920 Valid, 2015 Invalid, 197 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 196 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:04:00,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1221 states. [2024-12-02 06:04:00,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1221 to 1221. [2024-12-02 06:04:00,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1221 states, 1209 states have (on average 1.4532671629445824) internal successors, (1757), 1209 states have internal predecessors, (1757), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:00,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1221 states to 1221 states and 1777 transitions. [2024-12-02 06:04:00,529 INFO L78 Accepts]: Start accepts. Automaton has 1221 states and 1777 transitions. Word has length 683 [2024-12-02 06:04:00,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:00,529 INFO L471 AbstractCegarLoop]: Abstraction has 1221 states and 1777 transitions. [2024-12-02 06:04:00,529 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 116.0) internal successors, (580), 5 states have internal predecessors, (580), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:00,530 INFO L276 IsEmpty]: Start isEmpty. Operand 1221 states and 1777 transitions. [2024-12-02 06:04:00,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 685 [2024-12-02 06:04:00,532 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:00,532 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:00,543 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-12-02 06:04:00,733 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable27 [2024-12-02 06:04:00,733 INFO L396 AbstractCegarLoop]: === Iteration 29 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:00,733 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:00,733 INFO L85 PathProgramCache]: Analyzing trace with hash -187341309, now seen corresponding path program 1 times [2024-12-02 06:04:00,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:00,733 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100422689] [2024-12-02 06:04:00,733 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:00,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:00,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:01,410 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:04:01,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:01,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100422689] [2024-12-02 06:04:01,410 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100422689] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:01,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [369504225] [2024-12-02 06:04:01,410 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:01,410 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:01,411 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:01,412 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:01,413 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-12-02 06:04:02,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:02,465 INFO L256 TraceCheckSpWp]: Trace formula consists of 3382 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-12-02 06:04:02,472 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:03,282 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-12-02 06:04:03,283 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:03,997 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-12-02 06:04:03,997 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [369504225] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:03,997 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:04:03,997 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-12-02 06:04:03,997 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1677296034] [2024-12-02 06:04:03,997 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:03,998 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:04:03,998 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:03,999 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:04:03,999 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-12-02 06:04:03,999 INFO L87 Difference]: Start difference. First operand 1221 states and 1777 transitions. Second operand has 5 states, 5 states have (on average 116.2) internal successors, (581), 5 states have internal predecessors, (581), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:04,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:04,178 INFO L93 Difference]: Finished difference Result 1904 states and 2776 transitions. [2024-12-02 06:04:04,179 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:04:04,179 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 116.2) internal successors, (581), 5 states have internal predecessors, (581), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 684 [2024-12-02 06:04:04,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:04,181 INFO L225 Difference]: With dead ends: 1904 [2024-12-02 06:04:04,181 INFO L226 Difference]: Without dead ends: 1221 [2024-12-02 06:04:04,181 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1371 GetRequests, 1353 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:04:04,182 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 1803 mSDsluCounter, 1004 mSDsCounter, 0 mSdLazyCounter, 194 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1808 SdHoareTripleChecker+Valid, 2006 SdHoareTripleChecker+Invalid, 201 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 194 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:04,182 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1808 Valid, 2006 Invalid, 201 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 194 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:04:04,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1221 states. [2024-12-02 06:04:04,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1221 to 1221. [2024-12-02 06:04:04,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1221 states, 1209 states have (on average 1.4524400330851943) internal successors, (1756), 1209 states have internal predecessors, (1756), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:04,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1221 states to 1221 states and 1776 transitions. [2024-12-02 06:04:04,200 INFO L78 Accepts]: Start accepts. Automaton has 1221 states and 1776 transitions. Word has length 684 [2024-12-02 06:04:04,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:04,200 INFO L471 AbstractCegarLoop]: Abstraction has 1221 states and 1776 transitions. [2024-12-02 06:04:04,201 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 116.2) internal successors, (581), 5 states have internal predecessors, (581), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:04,201 INFO L276 IsEmpty]: Start isEmpty. Operand 1221 states and 1776 transitions. [2024-12-02 06:04:04,205 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 686 [2024-12-02 06:04:04,205 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:04,206 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:04,217 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-12-02 06:04:04,406 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable28 [2024-12-02 06:04:04,406 INFO L396 AbstractCegarLoop]: === Iteration 30 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:04,407 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:04,407 INFO L85 PathProgramCache]: Analyzing trace with hash -1903378360, now seen corresponding path program 1 times [2024-12-02 06:04:04,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:04,407 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341791879] [2024-12-02 06:04:04,407 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:04,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:04,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:05,122 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:04:05,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:05,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341791879] [2024-12-02 06:04:05,123 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341791879] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:05,123 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1306050373] [2024-12-02 06:04:05,123 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:05,123 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:05,123 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:05,124 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:05,125 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-12-02 06:04:06,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:06,225 INFO L256 TraceCheckSpWp]: Trace formula consists of 3385 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-12-02 06:04:06,231 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:07,058 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-12-02 06:04:07,058 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:07,774 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-12-02 06:04:07,774 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1306050373] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:07,774 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:04:07,774 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-12-02 06:04:07,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103264831] [2024-12-02 06:04:07,774 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:07,775 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:04:07,775 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:07,776 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:04:07,776 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-12-02 06:04:07,776 INFO L87 Difference]: Start difference. First operand 1221 states and 1776 transitions. Second operand has 5 states, 5 states have (on average 116.4) internal successors, (582), 5 states have internal predecessors, (582), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:07,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:07,953 INFO L93 Difference]: Finished difference Result 1904 states and 2774 transitions. [2024-12-02 06:04:07,953 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:04:07,954 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 116.4) internal successors, (582), 5 states have internal predecessors, (582), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 685 [2024-12-02 06:04:07,954 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:07,956 INFO L225 Difference]: With dead ends: 1904 [2024-12-02 06:04:07,956 INFO L226 Difference]: Without dead ends: 1221 [2024-12-02 06:04:07,957 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1373 GetRequests, 1355 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:04:07,958 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 897 mSDsluCounter, 1013 mSDsCounter, 0 mSdLazyCounter, 192 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 902 SdHoareTripleChecker+Valid, 2015 SdHoareTripleChecker+Invalid, 193 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 192 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:07,958 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [902 Valid, 2015 Invalid, 193 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 192 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:04:07,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1221 states. [2024-12-02 06:04:07,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1221 to 1221. [2024-12-02 06:04:07,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1221 states, 1209 states have (on average 1.4516129032258065) internal successors, (1755), 1209 states have internal predecessors, (1755), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:07,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1221 states to 1221 states and 1775 transitions. [2024-12-02 06:04:07,983 INFO L78 Accepts]: Start accepts. Automaton has 1221 states and 1775 transitions. Word has length 685 [2024-12-02 06:04:07,983 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:07,983 INFO L471 AbstractCegarLoop]: Abstraction has 1221 states and 1775 transitions. [2024-12-02 06:04:07,983 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 116.4) internal successors, (582), 5 states have internal predecessors, (582), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:07,983 INFO L276 IsEmpty]: Start isEmpty. Operand 1221 states and 1775 transitions. [2024-12-02 06:04:07,986 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 687 [2024-12-02 06:04:07,986 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:07,986 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:07,997 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-12-02 06:04:08,186 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29,13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:08,187 INFO L396 AbstractCegarLoop]: === Iteration 31 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:08,187 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:08,187 INFO L85 PathProgramCache]: Analyzing trace with hash 2069984561, now seen corresponding path program 1 times [2024-12-02 06:04:08,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:08,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788949168] [2024-12-02 06:04:08,187 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:08,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:08,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:08,874 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:04:08,874 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:08,874 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [788949168] [2024-12-02 06:04:08,874 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [788949168] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:08,874 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [514530697] [2024-12-02 06:04:08,874 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:08,874 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:08,874 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:08,875 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:08,876 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-12-02 06:04:10,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:10,071 INFO L256 TraceCheckSpWp]: Trace formula consists of 3388 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-12-02 06:04:10,078 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:10,912 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-12-02 06:04:10,912 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:11,694 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-12-02 06:04:11,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [514530697] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:11,695 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:04:11,695 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-12-02 06:04:11,695 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319319628] [2024-12-02 06:04:11,695 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:11,696 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:04:11,696 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:11,697 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:04:11,697 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-12-02 06:04:11,697 INFO L87 Difference]: Start difference. First operand 1221 states and 1775 transitions. Second operand has 5 states, 5 states have (on average 116.6) internal successors, (583), 5 states have internal predecessors, (583), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:11,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:11,879 INFO L93 Difference]: Finished difference Result 1904 states and 2772 transitions. [2024-12-02 06:04:11,879 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:04:11,879 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 116.6) internal successors, (583), 5 states have internal predecessors, (583), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 686 [2024-12-02 06:04:11,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:11,882 INFO L225 Difference]: With dead ends: 1904 [2024-12-02 06:04:11,882 INFO L226 Difference]: Without dead ends: 1221 [2024-12-02 06:04:11,882 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1375 GetRequests, 1357 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:04:11,883 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 885 mSDsluCounter, 1013 mSDsCounter, 0 mSdLazyCounter, 190 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 890 SdHoareTripleChecker+Valid, 2015 SdHoareTripleChecker+Invalid, 191 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 190 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:11,883 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [890 Valid, 2015 Invalid, 191 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 190 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:04:11,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1221 states. [2024-12-02 06:04:11,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1221 to 1221. [2024-12-02 06:04:11,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1221 states, 1209 states have (on average 1.4507857733664185) internal successors, (1754), 1209 states have internal predecessors, (1754), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:11,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1221 states to 1221 states and 1774 transitions. [2024-12-02 06:04:11,912 INFO L78 Accepts]: Start accepts. Automaton has 1221 states and 1774 transitions. Word has length 686 [2024-12-02 06:04:11,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:11,912 INFO L471 AbstractCegarLoop]: Abstraction has 1221 states and 1774 transitions. [2024-12-02 06:04:11,912 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 116.6) internal successors, (583), 5 states have internal predecessors, (583), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:11,912 INFO L276 IsEmpty]: Start isEmpty. Operand 1221 states and 1774 transitions. [2024-12-02 06:04:11,919 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 688 [2024-12-02 06:04:11,919 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:11,919 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:11,930 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2024-12-02 06:04:12,119 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30,14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:12,119 INFO L396 AbstractCegarLoop]: === Iteration 32 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:12,120 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:12,120 INFO L85 PathProgramCache]: Analyzing trace with hash 918314603, now seen corresponding path program 1 times [2024-12-02 06:04:12,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:12,120 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92215115] [2024-12-02 06:04:12,120 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:12,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:12,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:12,868 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:04:12,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:12,868 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [92215115] [2024-12-02 06:04:12,868 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [92215115] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:12,868 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1268003579] [2024-12-02 06:04:12,868 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:12,868 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:12,868 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:12,870 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:12,870 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-12-02 06:04:14,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:14,095 INFO L256 TraceCheckSpWp]: Trace formula consists of 3391 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:04:14,100 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:14,120 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 8 refuted. 0 times theorem prover too weak. 313 trivial. 0 not checked. [2024-12-02 06:04:14,120 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:14,160 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-12-02 06:04:14,160 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1268003579] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:14,160 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:04:14,161 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:04:14,161 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1706499443] [2024-12-02 06:04:14,161 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:14,162 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:04:14,162 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:14,162 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:04:14,162 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:04:14,163 INFO L87 Difference]: Start difference. First operand 1221 states and 1774 transitions. Second operand has 3 states, 3 states have (on average 194.66666666666666) internal successors, (584), 3 states have internal predecessors, (584), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:14,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:14,183 INFO L93 Difference]: Finished difference Result 1905 states and 2772 transitions. [2024-12-02 06:04:14,183 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:04:14,183 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 194.66666666666666) internal successors, (584), 3 states have internal predecessors, (584), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 687 [2024-12-02 06:04:14,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:14,185 INFO L225 Difference]: With dead ends: 1905 [2024-12-02 06:04:14,185 INFO L226 Difference]: Without dead ends: 1222 [2024-12-02 06:04:14,186 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1376 GetRequests, 1371 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:04:14,186 INFO L435 NwaCegarLoop]: 1093 mSDtfsCounter, 1 mSDsluCounter, 1089 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2182 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:14,186 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2182 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:14,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1222 states. [2024-12-02 06:04:14,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1222 to 1222. [2024-12-02 06:04:14,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1222 states, 1210 states have (on average 1.4504132231404958) internal successors, (1755), 1210 states have internal predecessors, (1755), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:14,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1222 states to 1222 states and 1775 transitions. [2024-12-02 06:04:14,205 INFO L78 Accepts]: Start accepts. Automaton has 1222 states and 1775 transitions. Word has length 687 [2024-12-02 06:04:14,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:14,205 INFO L471 AbstractCegarLoop]: Abstraction has 1222 states and 1775 transitions. [2024-12-02 06:04:14,205 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 194.66666666666666) internal successors, (584), 3 states have internal predecessors, (584), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:14,205 INFO L276 IsEmpty]: Start isEmpty. Operand 1222 states and 1775 transitions. [2024-12-02 06:04:14,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 690 [2024-12-02 06:04:14,208 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:14,208 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:14,220 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2024-12-02 06:04:14,409 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable31,15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:14,409 INFO L396 AbstractCegarLoop]: === Iteration 33 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:14,409 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:14,409 INFO L85 PathProgramCache]: Analyzing trace with hash 434424231, now seen corresponding path program 1 times [2024-12-02 06:04:14,409 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:14,410 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91251448] [2024-12-02 06:04:14,410 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:14,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:14,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:15,097 INFO L134 CoverageAnalysis]: Checked inductivity of 604 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-12-02 06:04:15,097 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:15,097 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91251448] [2024-12-02 06:04:15,097 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91251448] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:15,097 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [431380484] [2024-12-02 06:04:15,097 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:15,097 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:15,097 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:15,099 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:15,100 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-12-02 06:04:16,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:16,401 INFO L256 TraceCheckSpWp]: Trace formula consists of 3400 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:04:16,406 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:16,429 INFO L134 CoverageAnalysis]: Checked inductivity of 604 backedges. 282 proven. 8 refuted. 0 times theorem prover too weak. 314 trivial. 0 not checked. [2024-12-02 06:04:16,429 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:16,470 INFO L134 CoverageAnalysis]: Checked inductivity of 604 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 422 trivial. 0 not checked. [2024-12-02 06:04:16,470 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [431380484] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:16,471 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:04:16,471 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:04:16,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [458197927] [2024-12-02 06:04:16,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:16,471 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:04:16,471 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:16,472 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:04:16,472 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:04:16,472 INFO L87 Difference]: Start difference. First operand 1222 states and 1775 transitions. Second operand has 3 states, 3 states have (on average 195.33333333333334) internal successors, (586), 3 states have internal predecessors, (586), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:16,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:16,493 INFO L93 Difference]: Finished difference Result 1907 states and 2774 transitions. [2024-12-02 06:04:16,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:04:16,493 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 195.33333333333334) internal successors, (586), 3 states have internal predecessors, (586), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 689 [2024-12-02 06:04:16,494 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:16,495 INFO L225 Difference]: With dead ends: 1907 [2024-12-02 06:04:16,495 INFO L226 Difference]: Without dead ends: 1223 [2024-12-02 06:04:16,496 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1380 GetRequests, 1375 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:04:16,496 INFO L435 NwaCegarLoop]: 1093 mSDtfsCounter, 1 mSDsluCounter, 1089 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2182 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:16,497 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2182 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:16,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1223 states. [2024-12-02 06:04:16,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1223 to 1223. [2024-12-02 06:04:16,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1223 states, 1211 states have (on average 1.4500412881915772) internal successors, (1756), 1211 states have internal predecessors, (1756), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:16,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1223 states to 1223 states and 1776 transitions. [2024-12-02 06:04:16,513 INFO L78 Accepts]: Start accepts. Automaton has 1223 states and 1776 transitions. Word has length 689 [2024-12-02 06:04:16,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:16,514 INFO L471 AbstractCegarLoop]: Abstraction has 1223 states and 1776 transitions. [2024-12-02 06:04:16,514 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 195.33333333333334) internal successors, (586), 3 states have internal predecessors, (586), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:16,514 INFO L276 IsEmpty]: Start isEmpty. Operand 1223 states and 1776 transitions. [2024-12-02 06:04:16,516 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 692 [2024-12-02 06:04:16,517 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:16,517 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:16,530 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0 [2024-12-02 06:04:16,717 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable32 [2024-12-02 06:04:16,717 INFO L396 AbstractCegarLoop]: === Iteration 34 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:16,718 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:16,718 INFO L85 PathProgramCache]: Analyzing trace with hash -186461469, now seen corresponding path program 1 times [2024-12-02 06:04:16,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:16,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2120770209] [2024-12-02 06:04:16,718 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:16,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:16,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:17,375 INFO L134 CoverageAnalysis]: Checked inductivity of 605 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 422 trivial. 0 not checked. [2024-12-02 06:04:17,375 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:17,375 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2120770209] [2024-12-02 06:04:17,375 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2120770209] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:17,375 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1233527013] [2024-12-02 06:04:17,375 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:17,375 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:17,375 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:17,377 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:17,377 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-12-02 06:04:18,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:18,767 INFO L256 TraceCheckSpWp]: Trace formula consists of 3409 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:04:18,773 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:18,792 INFO L134 CoverageAnalysis]: Checked inductivity of 605 backedges. 282 proven. 8 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2024-12-02 06:04:18,792 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:18,829 INFO L134 CoverageAnalysis]: Checked inductivity of 605 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-12-02 06:04:18,830 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1233527013] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:18,830 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:04:18,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:04:18,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1756592142] [2024-12-02 06:04:18,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:18,830 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:04:18,830 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:18,831 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:04:18,831 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:04:18,831 INFO L87 Difference]: Start difference. First operand 1223 states and 1776 transitions. Second operand has 3 states, 3 states have (on average 196.0) internal successors, (588), 3 states have internal predecessors, (588), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:18,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:18,861 INFO L93 Difference]: Finished difference Result 1909 states and 2776 transitions. [2024-12-02 06:04:18,861 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:04:18,861 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 196.0) internal successors, (588), 3 states have internal predecessors, (588), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 691 [2024-12-02 06:04:18,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:18,863 INFO L225 Difference]: With dead ends: 1909 [2024-12-02 06:04:18,863 INFO L226 Difference]: Without dead ends: 1224 [2024-12-02 06:04:18,864 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1384 GetRequests, 1379 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:04:18,864 INFO L435 NwaCegarLoop]: 1093 mSDtfsCounter, 1 mSDsluCounter, 1089 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2182 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:18,864 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2182 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:18,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1224 states. [2024-12-02 06:04:18,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1224 to 1224. [2024-12-02 06:04:18,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1224 states, 1212 states have (on average 1.4496699669966997) internal successors, (1757), 1212 states have internal predecessors, (1757), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:18,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1224 states to 1224 states and 1777 transitions. [2024-12-02 06:04:18,882 INFO L78 Accepts]: Start accepts. Automaton has 1224 states and 1777 transitions. Word has length 691 [2024-12-02 06:04:18,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:18,882 INFO L471 AbstractCegarLoop]: Abstraction has 1224 states and 1777 transitions. [2024-12-02 06:04:18,882 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 196.0) internal successors, (588), 3 states have internal predecessors, (588), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:18,882 INFO L276 IsEmpty]: Start isEmpty. Operand 1224 states and 1777 transitions. [2024-12-02 06:04:18,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 694 [2024-12-02 06:04:18,885 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:18,885 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:18,900 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Ended with exit code 0 [2024-12-02 06:04:19,086 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable33 [2024-12-02 06:04:19,086 INFO L396 AbstractCegarLoop]: === Iteration 35 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:19,086 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:19,086 INFO L85 PathProgramCache]: Analyzing trace with hash 1053219807, now seen corresponding path program 1 times [2024-12-02 06:04:19,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:19,086 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339694212] [2024-12-02 06:04:19,087 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:19,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:19,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:19,755 INFO L134 CoverageAnalysis]: Checked inductivity of 606 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-12-02 06:04:19,755 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:19,755 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1339694212] [2024-12-02 06:04:19,755 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1339694212] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:19,755 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2071057809] [2024-12-02 06:04:19,756 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:19,756 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:19,756 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:19,757 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:19,758 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-12-02 06:04:21,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:21,174 INFO L256 TraceCheckSpWp]: Trace formula consists of 3418 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:04:21,180 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:21,205 INFO L134 CoverageAnalysis]: Checked inductivity of 606 backedges. 282 proven. 37 refuted. 0 times theorem prover too weak. 287 trivial. 0 not checked. [2024-12-02 06:04:21,205 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:21,256 INFO L134 CoverageAnalysis]: Checked inductivity of 606 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-12-02 06:04:21,256 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2071057809] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:04:21,256 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:04:21,256 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:04:21,257 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674079329] [2024-12-02 06:04:21,257 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:04:21,258 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:04:21,258 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:21,258 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:04:21,258 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:04:21,258 INFO L87 Difference]: Start difference. First operand 1224 states and 1777 transitions. Second operand has 9 states, 9 states have (on average 67.22222222222223) internal successors, (605), 9 states have internal predecessors, (605), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:04:21,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:21,330 INFO L93 Difference]: Finished difference Result 1916 states and 2785 transitions. [2024-12-02 06:04:21,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:04:21,330 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 67.22222222222223) internal successors, (605), 9 states have internal predecessors, (605), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 693 [2024-12-02 06:04:21,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:21,332 INFO L225 Difference]: With dead ends: 1916 [2024-12-02 06:04:21,332 INFO L226 Difference]: Without dead ends: 1230 [2024-12-02 06:04:21,333 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1389 GetRequests, 1381 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:04:21,333 INFO L435 NwaCegarLoop]: 1097 mSDtfsCounter, 15 mSDsluCounter, 5455 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 6552 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:21,333 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 6552 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:21,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1230 states. [2024-12-02 06:04:21,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1230 to 1230. [2024-12-02 06:04:21,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1230 states, 1218 states have (on average 1.4474548440065682) internal successors, (1763), 1218 states have internal predecessors, (1763), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:21,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1230 states to 1230 states and 1783 transitions. [2024-12-02 06:04:21,351 INFO L78 Accepts]: Start accepts. Automaton has 1230 states and 1783 transitions. Word has length 693 [2024-12-02 06:04:21,351 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:21,351 INFO L471 AbstractCegarLoop]: Abstraction has 1230 states and 1783 transitions. [2024-12-02 06:04:21,351 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 67.22222222222223) internal successors, (605), 9 states have internal predecessors, (605), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:04:21,351 INFO L276 IsEmpty]: Start isEmpty. Operand 1230 states and 1783 transitions. [2024-12-02 06:04:21,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 700 [2024-12-02 06:04:21,354 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:21,354 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:21,368 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Ended with exit code 0 [2024-12-02 06:04:21,555 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable34 [2024-12-02 06:04:21,555 INFO L396 AbstractCegarLoop]: === Iteration 36 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:21,555 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:21,555 INFO L85 PathProgramCache]: Analyzing trace with hash -1992758645, now seen corresponding path program 2 times [2024-12-02 06:04:21,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:21,556 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [157322248] [2024-12-02 06:04:21,556 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:04:21,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:21,694 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:04:21,695 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:04:21,973 INFO L134 CoverageAnalysis]: Checked inductivity of 621 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 539 trivial. 0 not checked. [2024-12-02 06:04:21,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:21,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [157322248] [2024-12-02 06:04:21,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [157322248] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:21,974 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:04:21,974 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:04:21,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [80779585] [2024-12-02 06:04:21,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:21,975 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:04:21,975 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:21,975 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:04:21,975 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:04:21,975 INFO L87 Difference]: Start difference. First operand 1230 states and 1783 transitions. Second operand has 5 states, 5 states have (on average 99.4) internal successors, (497), 5 states have internal predecessors, (497), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:04:22,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:22,024 INFO L93 Difference]: Finished difference Result 2220 states and 3230 transitions. [2024-12-02 06:04:22,025 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:04:22,025 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 99.4) internal successors, (497), 5 states have internal predecessors, (497), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 699 [2024-12-02 06:04:22,025 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:22,027 INFO L225 Difference]: With dead ends: 2220 [2024-12-02 06:04:22,027 INFO L226 Difference]: Without dead ends: 1526 [2024-12-02 06:04:22,028 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:04:22,028 INFO L435 NwaCegarLoop]: 1089 mSDtfsCounter, 142 mSDsluCounter, 3258 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 142 SdHoareTripleChecker+Valid, 4347 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:22,029 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [142 Valid, 4347 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 32 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:22,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1526 states. [2024-12-02 06:04:22,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1526 to 1522. [2024-12-02 06:04:22,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1522 states, 1510 states have (on average 1.4536423841059603) internal successors, (2195), 1510 states have internal predecessors, (2195), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:22,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1522 states to 1522 states and 2215 transitions. [2024-12-02 06:04:22,048 INFO L78 Accepts]: Start accepts. Automaton has 1522 states and 2215 transitions. Word has length 699 [2024-12-02 06:04:22,048 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:22,048 INFO L471 AbstractCegarLoop]: Abstraction has 1522 states and 2215 transitions. [2024-12-02 06:04:22,048 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 99.4) internal successors, (497), 5 states have internal predecessors, (497), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:04:22,048 INFO L276 IsEmpty]: Start isEmpty. Operand 1522 states and 2215 transitions. [2024-12-02 06:04:22,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 702 [2024-12-02 06:04:22,051 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:22,052 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:22,052 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable35 [2024-12-02 06:04:22,052 INFO L396 AbstractCegarLoop]: === Iteration 37 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:22,052 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:22,052 INFO L85 PathProgramCache]: Analyzing trace with hash 706771481, now seen corresponding path program 1 times [2024-12-02 06:04:22,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:22,052 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2036724350] [2024-12-02 06:04:22,053 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:22,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:22,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:22,916 INFO L134 CoverageAnalysis]: Checked inductivity of 622 backedges. 183 proven. 16 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-12-02 06:04:22,916 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:22,916 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2036724350] [2024-12-02 06:04:22,916 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2036724350] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:22,916 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1149488868] [2024-12-02 06:04:22,916 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:22,916 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:22,916 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:22,917 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:22,918 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-12-02 06:04:24,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:24,262 INFO L256 TraceCheckSpWp]: Trace formula consists of 3451 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-12-02 06:04:24,267 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:24,339 INFO L134 CoverageAnalysis]: Checked inductivity of 622 backedges. 283 proven. 112 refuted. 0 times theorem prover too weak. 227 trivial. 0 not checked. [2024-12-02 06:04:24,340 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:24,484 INFO L134 CoverageAnalysis]: Checked inductivity of 622 backedges. 183 proven. 16 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-12-02 06:04:24,484 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1149488868] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:04:24,484 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:04:24,484 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-12-02 06:04:24,484 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1686566768] [2024-12-02 06:04:24,484 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:04:24,485 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-12-02 06:04:24,485 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:24,485 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-12-02 06:04:24,486 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:04:24,486 INFO L87 Difference]: Start difference. First operand 1522 states and 2215 transitions. Second operand has 18 states, 18 states have (on average 35.05555555555556) internal successors, (631), 18 states have internal predecessors, (631), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:04:24,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:24,661 INFO L93 Difference]: Finished difference Result 2368 states and 3448 transitions. [2024-12-02 06:04:24,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-12-02 06:04:24,662 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 35.05555555555556) internal successors, (631), 18 states have internal predecessors, (631), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 701 [2024-12-02 06:04:24,662 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:24,664 INFO L225 Difference]: With dead ends: 2368 [2024-12-02 06:04:24,664 INFO L226 Difference]: Without dead ends: 1530 [2024-12-02 06:04:24,665 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1409 GetRequests, 1391 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:04:24,665 INFO L435 NwaCegarLoop]: 1115 mSDtfsCounter, 28 mSDsluCounter, 12196 mSDsCounter, 0 mSdLazyCounter, 251 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 13311 SdHoareTripleChecker+Invalid, 252 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 251 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:24,665 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 13311 Invalid, 252 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 251 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:04:24,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1530 states. [2024-12-02 06:04:24,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1530 to 1530. [2024-12-02 06:04:24,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1530 states, 1518 states have (on average 1.4512516469038208) internal successors, (2203), 1518 states have internal predecessors, (2203), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:24,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1530 states to 1530 states and 2223 transitions. [2024-12-02 06:04:24,686 INFO L78 Accepts]: Start accepts. Automaton has 1530 states and 2223 transitions. Word has length 701 [2024-12-02 06:04:24,686 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:24,686 INFO L471 AbstractCegarLoop]: Abstraction has 1530 states and 2223 transitions. [2024-12-02 06:04:24,687 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 35.05555555555556) internal successors, (631), 18 states have internal predecessors, (631), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:04:24,687 INFO L276 IsEmpty]: Start isEmpty. Operand 1530 states and 2223 transitions. [2024-12-02 06:04:24,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 710 [2024-12-02 06:04:24,690 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:24,691 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:24,707 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Ended with exit code 0 [2024-12-02 06:04:24,891 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable36 [2024-12-02 06:04:24,891 INFO L396 AbstractCegarLoop]: === Iteration 38 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:24,891 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:24,892 INFO L85 PathProgramCache]: Analyzing trace with hash -310514551, now seen corresponding path program 2 times [2024-12-02 06:04:24,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:24,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894845721] [2024-12-02 06:04:24,892 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:04:24,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:25,055 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:04:25,055 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:04:25,248 INFO L134 CoverageAnalysis]: Checked inductivity of 670 backedges. 2 proven. 176 refuted. 0 times theorem prover too weak. 492 trivial. 0 not checked. [2024-12-02 06:04:25,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:25,248 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894845721] [2024-12-02 06:04:25,248 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [894845721] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:25,248 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [52061450] [2024-12-02 06:04:25,248 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:04:25,249 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:25,249 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:25,250 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:25,252 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-12-02 06:04:26,495 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:04:26,495 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:04:26,501 INFO L256 TraceCheckSpWp]: Trace formula consists of 798 conjuncts, 60 conjuncts are in the unsatisfiable core [2024-12-02 06:04:26,510 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:27,734 INFO L134 CoverageAnalysis]: Checked inductivity of 670 backedges. 277 proven. 3 refuted. 0 times theorem prover too weak. 390 trivial. 0 not checked. [2024-12-02 06:04:27,734 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:28,649 INFO L134 CoverageAnalysis]: Checked inductivity of 670 backedges. 180 proven. 0 refuted. 0 times theorem prover too weak. 490 trivial. 0 not checked. [2024-12-02 06:04:28,650 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [52061450] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:28,650 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:04:28,650 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [7, 8] total 21 [2024-12-02 06:04:28,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1723501135] [2024-12-02 06:04:28,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:28,651 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2024-12-02 06:04:28,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:28,651 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2024-12-02 06:04:28,651 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=336, Unknown=0, NotChecked=0, Total=420 [2024-12-02 06:04:28,652 INFO L87 Difference]: Start difference. First operand 1530 states and 2223 transitions. Second operand has 11 states, 11 states have (on average 53.63636363636363) internal successors, (590), 11 states have internal predecessors, (590), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:30,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:30,229 INFO L93 Difference]: Finished difference Result 3422 states and 4980 transitions. [2024-12-02 06:04:30,230 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-12-02 06:04:30,230 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 53.63636363636363) internal successors, (590), 11 states have internal predecessors, (590), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 709 [2024-12-02 06:04:30,230 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:30,233 INFO L225 Difference]: With dead ends: 3422 [2024-12-02 06:04:30,233 INFO L226 Difference]: Without dead ends: 1842 [2024-12-02 06:04:30,234 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1425 GetRequests, 1405 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=96, Invalid=366, Unknown=0, NotChecked=0, Total=462 [2024-12-02 06:04:30,235 INFO L435 NwaCegarLoop]: 1251 mSDtfsCounter, 958 mSDsluCounter, 6143 mSDsCounter, 0 mSdLazyCounter, 2482 mSolverCounterSat, 18 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 958 SdHoareTripleChecker+Valid, 7394 SdHoareTripleChecker+Invalid, 2500 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 18 IncrementalHoareTripleChecker+Valid, 2482 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:30,235 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [958 Valid, 7394 Invalid, 2500 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [18 Valid, 2482 Invalid, 0 Unknown, 0 Unchecked, 1.5s Time] [2024-12-02 06:04:30,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1842 states. [2024-12-02 06:04:30,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1842 to 1842. [2024-12-02 06:04:30,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1842 states, 1820 states have (on average 1.45) internal successors, (2639), 1820 states have internal predecessors, (2639), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:04:30,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1842 states to 1842 states and 2679 transitions. [2024-12-02 06:04:30,262 INFO L78 Accepts]: Start accepts. Automaton has 1842 states and 2679 transitions. Word has length 709 [2024-12-02 06:04:30,263 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:30,263 INFO L471 AbstractCegarLoop]: Abstraction has 1842 states and 2679 transitions. [2024-12-02 06:04:30,263 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 53.63636363636363) internal successors, (590), 11 states have internal predecessors, (590), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:30,263 INFO L276 IsEmpty]: Start isEmpty. Operand 1842 states and 2679 transitions. [2024-12-02 06:04:30,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 712 [2024-12-02 06:04:30,266 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:30,267 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:30,281 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Ended with exit code 0 [2024-12-02 06:04:30,467 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable37,20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:30,467 INFO L396 AbstractCegarLoop]: === Iteration 39 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:30,467 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:30,468 INFO L85 PathProgramCache]: Analyzing trace with hash 260568597, now seen corresponding path program 1 times [2024-12-02 06:04:30,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:30,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255322892] [2024-12-02 06:04:30,468 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:30,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:30,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:31,404 INFO L134 CoverageAnalysis]: Checked inductivity of 671 backedges. 91 proven. 0 refuted. 0 times theorem prover too weak. 580 trivial. 0 not checked. [2024-12-02 06:04:31,404 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:31,404 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1255322892] [2024-12-02 06:04:31,404 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1255322892] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:31,404 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:04:31,404 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:04:31,405 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [702748278] [2024-12-02 06:04:31,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:31,405 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:04:31,405 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:31,406 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:04:31,406 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:04:31,406 INFO L87 Difference]: Start difference. First operand 1842 states and 2679 transitions. Second operand has 6 states, 6 states have (on average 84.0) internal successors, (504), 6 states have internal predecessors, (504), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:31,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:31,723 INFO L93 Difference]: Finished difference Result 3570 states and 5197 transitions. [2024-12-02 06:04:31,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:04:31,724 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 84.0) internal successors, (504), 6 states have internal predecessors, (504), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 711 [2024-12-02 06:04:31,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:31,726 INFO L225 Difference]: With dead ends: 3570 [2024-12-02 06:04:31,726 INFO L226 Difference]: Without dead ends: 1850 [2024-12-02 06:04:31,727 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:04:31,727 INFO L435 NwaCegarLoop]: 1393 mSDtfsCounter, 323 mSDsluCounter, 4974 mSDsCounter, 0 mSdLazyCounter, 369 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 323 SdHoareTripleChecker+Valid, 6367 SdHoareTripleChecker+Invalid, 378 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 369 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:31,728 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [323 Valid, 6367 Invalid, 378 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 369 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-12-02 06:04:31,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1850 states. [2024-12-02 06:04:31,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1850 to 1846. [2024-12-02 06:04:31,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1846 states, 1824 states have (on average 1.449013157894737) internal successors, (2643), 1824 states have internal predecessors, (2643), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:04:31,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1846 states to 1846 states and 2683 transitions. [2024-12-02 06:04:31,756 INFO L78 Accepts]: Start accepts. Automaton has 1846 states and 2683 transitions. Word has length 711 [2024-12-02 06:04:31,756 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:31,756 INFO L471 AbstractCegarLoop]: Abstraction has 1846 states and 2683 transitions. [2024-12-02 06:04:31,756 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 84.0) internal successors, (504), 6 states have internal predecessors, (504), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:04:31,756 INFO L276 IsEmpty]: Start isEmpty. Operand 1846 states and 2683 transitions. [2024-12-02 06:04:31,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 712 [2024-12-02 06:04:31,760 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:31,760 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:31,760 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable38 [2024-12-02 06:04:31,760 INFO L396 AbstractCegarLoop]: === Iteration 40 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:31,761 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:31,761 INFO L85 PathProgramCache]: Analyzing trace with hash 2103450263, now seen corresponding path program 1 times [2024-12-02 06:04:31,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:31,761 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281010350] [2024-12-02 06:04:31,761 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:31,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:32,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:32,504 INFO L134 CoverageAnalysis]: Checked inductivity of 671 backedges. 184 proven. 1 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-12-02 06:04:32,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:32,504 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [281010350] [2024-12-02 06:04:32,504 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [281010350] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:32,504 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [110115550] [2024-12-02 06:04:32,504 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:32,504 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:32,504 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:32,506 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:32,506 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2024-12-02 06:04:33,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:33,960 INFO L256 TraceCheckSpWp]: Trace formula consists of 3493 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:04:33,968 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:33,996 INFO L134 CoverageAnalysis]: Checked inductivity of 671 backedges. 284 proven. 37 refuted. 0 times theorem prover too weak. 350 trivial. 0 not checked. [2024-12-02 06:04:33,997 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:34,052 INFO L134 CoverageAnalysis]: Checked inductivity of 671 backedges. 184 proven. 1 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-12-02 06:04:34,052 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [110115550] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:04:34,052 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:04:34,052 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:04:34,052 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714405140] [2024-12-02 06:04:34,052 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:04:34,053 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:04:34,053 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:34,053 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:04:34,053 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:04:34,053 INFO L87 Difference]: Start difference. First operand 1846 states and 2683 transitions. Second operand has 9 states, 9 states have (on average 67.66666666666667) internal successors, (609), 9 states have internal predecessors, (609), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:04:34,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:34,133 INFO L93 Difference]: Finished difference Result 2856 states and 4151 transitions. [2024-12-02 06:04:34,133 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:04:34,134 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 67.66666666666667) internal successors, (609), 9 states have internal predecessors, (609), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 711 [2024-12-02 06:04:34,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:34,136 INFO L225 Difference]: With dead ends: 2856 [2024-12-02 06:04:34,136 INFO L226 Difference]: Without dead ends: 1852 [2024-12-02 06:04:34,137 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1425 GetRequests, 1417 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:04:34,137 INFO L435 NwaCegarLoop]: 1097 mSDtfsCounter, 15 mSDsluCounter, 5455 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 6552 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:34,137 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 6552 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:34,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1852 states. [2024-12-02 06:04:34,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1852 to 1852. [2024-12-02 06:04:34,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1852 states, 1830 states have (on average 1.4475409836065574) internal successors, (2649), 1830 states have internal predecessors, (2649), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:04:34,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1852 states to 1852 states and 2689 transitions. [2024-12-02 06:04:34,166 INFO L78 Accepts]: Start accepts. Automaton has 1852 states and 2689 transitions. Word has length 711 [2024-12-02 06:04:34,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:34,166 INFO L471 AbstractCegarLoop]: Abstraction has 1852 states and 2689 transitions. [2024-12-02 06:04:34,166 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 67.66666666666667) internal successors, (609), 9 states have internal predecessors, (609), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:04:34,166 INFO L276 IsEmpty]: Start isEmpty. Operand 1852 states and 2689 transitions. [2024-12-02 06:04:34,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 718 [2024-12-02 06:04:34,170 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:34,170 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:34,184 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Ended with exit code 0 [2024-12-02 06:04:34,370 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable39 [2024-12-02 06:04:34,370 INFO L396 AbstractCegarLoop]: === Iteration 41 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:34,371 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:34,371 INFO L85 PathProgramCache]: Analyzing trace with hash -1769476725, now seen corresponding path program 2 times [2024-12-02 06:04:34,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:34,371 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587853808] [2024-12-02 06:04:34,371 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:04:34,371 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:34,549 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:04:34,549 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:04:34,780 INFO L134 CoverageAnalysis]: Checked inductivity of 686 backedges. 175 proven. 4 refuted. 0 times theorem prover too weak. 507 trivial. 0 not checked. [2024-12-02 06:04:34,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:34,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [587853808] [2024-12-02 06:04:34,780 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [587853808] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:34,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [304073131] [2024-12-02 06:04:34,780 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:04:34,780 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:34,781 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:34,782 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:34,783 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2024-12-02 06:04:36,123 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:04:36,123 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:04:36,128 INFO L256 TraceCheckSpWp]: Trace formula consists of 801 conjuncts, 30 conjuncts are in the unsatisfiable core [2024-12-02 06:04:36,138 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:37,232 INFO L134 CoverageAnalysis]: Checked inductivity of 686 backedges. 275 proven. 4 refuted. 0 times theorem prover too weak. 407 trivial. 0 not checked. [2024-12-02 06:04:37,232 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:38,345 INFO L134 CoverageAnalysis]: Checked inductivity of 686 backedges. 175 proven. 4 refuted. 0 times theorem prover too weak. 507 trivial. 0 not checked. [2024-12-02 06:04:38,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [304073131] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:04:38,345 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:04:38,345 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 13 [2024-12-02 06:04:38,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [594701243] [2024-12-02 06:04:38,345 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:04:38,346 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2024-12-02 06:04:38,346 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:38,346 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-12-02 06:04:38,347 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:04:38,347 INFO L87 Difference]: Start difference. First operand 1852 states and 2689 transitions. Second operand has 13 states, 13 states have (on average 77.76923076923077) internal successors, (1011), 13 states have internal predecessors, (1011), 3 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 3 states have call predecessors, (20), 3 states have call successors, (20) [2024-12-02 06:04:39,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:39,231 INFO L93 Difference]: Finished difference Result 3210 states and 4666 transitions. [2024-12-02 06:04:39,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:04:39,232 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 77.76923076923077) internal successors, (1011), 13 states have internal predecessors, (1011), 3 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 3 states have call predecessors, (20), 3 states have call successors, (20) Word has length 717 [2024-12-02 06:04:39,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:39,234 INFO L225 Difference]: With dead ends: 3210 [2024-12-02 06:04:39,234 INFO L226 Difference]: Without dead ends: 1556 [2024-12-02 06:04:39,236 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1443 GetRequests, 1428 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=212, Unknown=0, NotChecked=0, Total=272 [2024-12-02 06:04:39,236 INFO L435 NwaCegarLoop]: 797 mSDtfsCounter, 680 mSDsluCounter, 3969 mSDsCounter, 0 mSdLazyCounter, 1808 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 680 SdHoareTripleChecker+Valid, 4766 SdHoareTripleChecker+Invalid, 1811 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1808 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:39,236 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [680 Valid, 4766 Invalid, 1811 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1808 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2024-12-02 06:04:39,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1556 states. [2024-12-02 06:04:39,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1556 to 1546. [2024-12-02 06:04:39,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1546 states, 1534 states have (on average 1.4452411994784875) internal successors, (2217), 1534 states have internal predecessors, (2217), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:39,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1546 states to 1546 states and 2237 transitions. [2024-12-02 06:04:39,260 INFO L78 Accepts]: Start accepts. Automaton has 1546 states and 2237 transitions. Word has length 717 [2024-12-02 06:04:39,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:39,260 INFO L471 AbstractCegarLoop]: Abstraction has 1546 states and 2237 transitions. [2024-12-02 06:04:39,260 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 77.76923076923077) internal successors, (1011), 13 states have internal predecessors, (1011), 3 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 3 states have call predecessors, (20), 3 states have call successors, (20) [2024-12-02 06:04:39,260 INFO L276 IsEmpty]: Start isEmpty. Operand 1546 states and 2237 transitions. [2024-12-02 06:04:39,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 720 [2024-12-02 06:04:39,263 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:39,264 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:39,275 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Ended with exit code 0 [2024-12-02 06:04:39,464 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable40,22 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:39,464 INFO L396 AbstractCegarLoop]: === Iteration 42 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:39,465 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:39,465 INFO L85 PathProgramCache]: Analyzing trace with hash 104734005, now seen corresponding path program 1 times [2024-12-02 06:04:39,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:39,465 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [866378625] [2024-12-02 06:04:39,465 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:39,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:39,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:40,380 INFO L134 CoverageAnalysis]: Checked inductivity of 687 backedges. 185 proven. 16 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-12-02 06:04:40,380 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:40,380 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [866378625] [2024-12-02 06:04:40,380 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [866378625] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:40,380 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1331426150] [2024-12-02 06:04:40,380 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:40,380 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:40,380 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:40,382 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:40,384 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2024-12-02 06:04:41,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:41,989 INFO L256 TraceCheckSpWp]: Trace formula consists of 3522 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-12-02 06:04:41,995 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:42,066 INFO L134 CoverageAnalysis]: Checked inductivity of 687 backedges. 285 proven. 112 refuted. 0 times theorem prover too weak. 290 trivial. 0 not checked. [2024-12-02 06:04:42,066 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:42,178 INFO L134 CoverageAnalysis]: Checked inductivity of 687 backedges. 185 proven. 16 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-12-02 06:04:42,178 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1331426150] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:04:42,178 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:04:42,178 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-12-02 06:04:42,179 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [806368744] [2024-12-02 06:04:42,179 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:04:42,180 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-12-02 06:04:42,180 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:42,181 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-12-02 06:04:42,181 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:04:42,182 INFO L87 Difference]: Start difference. First operand 1546 states and 2237 transitions. Second operand has 18 states, 18 states have (on average 35.27777777777778) internal successors, (635), 18 states have internal predecessors, (635), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:04:42,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:42,369 INFO L93 Difference]: Finished difference Result 2411 states and 3488 transitions. [2024-12-02 06:04:42,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-12-02 06:04:42,370 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 35.27777777777778) internal successors, (635), 18 states have internal predecessors, (635), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 719 [2024-12-02 06:04:42,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:42,372 INFO L225 Difference]: With dead ends: 2411 [2024-12-02 06:04:42,372 INFO L226 Difference]: Without dead ends: 1554 [2024-12-02 06:04:42,372 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1445 GetRequests, 1427 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:04:42,373 INFO L435 NwaCegarLoop]: 1114 mSDtfsCounter, 28 mSDsluCounter, 13295 mSDsCounter, 0 mSdLazyCounter, 263 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 14409 SdHoareTripleChecker+Invalid, 264 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 263 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:42,373 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 14409 Invalid, 264 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 263 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:04:42,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1554 states. [2024-12-02 06:04:42,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1554 to 1554. [2024-12-02 06:04:42,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1554 states, 1542 states have (on average 1.4429312581063554) internal successors, (2225), 1542 states have internal predecessors, (2225), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:42,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1554 states to 1554 states and 2245 transitions. [2024-12-02 06:04:42,396 INFO L78 Accepts]: Start accepts. Automaton has 1554 states and 2245 transitions. Word has length 719 [2024-12-02 06:04:42,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:42,397 INFO L471 AbstractCegarLoop]: Abstraction has 1554 states and 2245 transitions. [2024-12-02 06:04:42,397 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 35.27777777777778) internal successors, (635), 18 states have internal predecessors, (635), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:04:42,397 INFO L276 IsEmpty]: Start isEmpty. Operand 1554 states and 2245 transitions. [2024-12-02 06:04:42,400 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 728 [2024-12-02 06:04:42,400 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:42,400 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:42,417 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Ended with exit code 0 [2024-12-02 06:04:42,600 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable41,23 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:42,601 INFO L396 AbstractCegarLoop]: === Iteration 43 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:42,601 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:42,601 INFO L85 PathProgramCache]: Analyzing trace with hash 317190469, now seen corresponding path program 2 times [2024-12-02 06:04:42,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:42,601 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [489799717] [2024-12-02 06:04:42,601 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:04:42,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:42,738 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:04:42,738 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:04:43,030 INFO L134 CoverageAnalysis]: Checked inductivity of 735 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 652 trivial. 0 not checked. [2024-12-02 06:04:43,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:43,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [489799717] [2024-12-02 06:04:43,030 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [489799717] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:43,030 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:04:43,030 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:04:43,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2020497241] [2024-12-02 06:04:43,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:43,031 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:04:43,031 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:43,031 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:04:43,032 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:04:43,032 INFO L87 Difference]: Start difference. First operand 1554 states and 2245 transitions. Second operand has 8 states, 8 states have (on average 62.625) internal successors, (501), 8 states have internal predecessors, (501), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:04:43,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:43,115 INFO L93 Difference]: Finished difference Result 2427 states and 3503 transitions. [2024-12-02 06:04:43,115 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:04:43,115 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 62.625) internal successors, (501), 8 states have internal predecessors, (501), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 727 [2024-12-02 06:04:43,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:43,117 INFO L225 Difference]: With dead ends: 2427 [2024-12-02 06:04:43,117 INFO L226 Difference]: Without dead ends: 1562 [2024-12-02 06:04:43,117 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:04:43,118 INFO L435 NwaCegarLoop]: 1087 mSDtfsCounter, 141 mSDsluCounter, 6499 mSDsCounter, 0 mSdLazyCounter, 71 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 141 SdHoareTripleChecker+Valid, 7586 SdHoareTripleChecker+Invalid, 72 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 71 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:43,118 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [141 Valid, 7586 Invalid, 72 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 71 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:43,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1562 states. [2024-12-02 06:04:43,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1562 to 1555. [2024-12-02 06:04:43,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1555 states, 1543 states have (on average 1.443292287751134) internal successors, (2227), 1543 states have internal predecessors, (2227), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:43,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1555 states to 1555 states and 2247 transitions. [2024-12-02 06:04:43,140 INFO L78 Accepts]: Start accepts. Automaton has 1555 states and 2247 transitions. Word has length 727 [2024-12-02 06:04:43,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:43,141 INFO L471 AbstractCegarLoop]: Abstraction has 1555 states and 2247 transitions. [2024-12-02 06:04:43,141 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 62.625) internal successors, (501), 8 states have internal predecessors, (501), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:04:43,141 INFO L276 IsEmpty]: Start isEmpty. Operand 1555 states and 2247 transitions. [2024-12-02 06:04:43,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 728 [2024-12-02 06:04:43,144 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:43,144 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:43,145 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable42 [2024-12-02 06:04:43,145 INFO L396 AbstractCegarLoop]: === Iteration 44 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:43,145 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:43,145 INFO L85 PathProgramCache]: Analyzing trace with hash -2072821086, now seen corresponding path program 1 times [2024-12-02 06:04:43,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:43,145 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1666764676] [2024-12-02 06:04:43,146 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:43,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:43,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:43,936 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 184 proven. 1 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-12-02 06:04:43,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:43,936 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1666764676] [2024-12-02 06:04:43,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1666764676] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:43,936 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [944939954] [2024-12-02 06:04:43,936 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:43,936 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:43,937 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:43,938 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:43,939 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2024-12-02 06:04:45,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:45,639 INFO L256 TraceCheckSpWp]: Trace formula consists of 3558 conjuncts, 15 conjuncts are in the unsatisfiable core [2024-12-02 06:04:45,644 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:45,749 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 108 proven. 24 refuted. 0 times theorem prover too weak. 602 trivial. 0 not checked. [2024-12-02 06:04:45,749 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:45,839 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 108 proven. 0 refuted. 0 times theorem prover too weak. 626 trivial. 0 not checked. [2024-12-02 06:04:45,839 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [944939954] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:45,839 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:04:45,839 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 8] total 13 [2024-12-02 06:04:45,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [857856211] [2024-12-02 06:04:45,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:45,840 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:04:45,840 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:45,840 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:04:45,840 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:04:45,840 INFO L87 Difference]: Start difference. First operand 1555 states and 2247 transitions. Second operand has 5 states, 5 states have (on average 105.2) internal successors, (526), 5 states have internal predecessors, (526), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:04:45,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:45,883 INFO L93 Difference]: Finished difference Result 2669 states and 3857 transitions. [2024-12-02 06:04:45,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:04:45,883 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 105.2) internal successors, (526), 5 states have internal predecessors, (526), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 727 [2024-12-02 06:04:45,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:45,885 INFO L225 Difference]: With dead ends: 2669 [2024-12-02 06:04:45,885 INFO L226 Difference]: Without dead ends: 1651 [2024-12-02 06:04:45,886 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1456 GetRequests, 1445 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:04:45,886 INFO L435 NwaCegarLoop]: 1091 mSDtfsCounter, 40 mSDsluCounter, 3261 mSDsCounter, 0 mSdLazyCounter, 23 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 4352 SdHoareTripleChecker+Invalid, 23 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 23 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:45,886 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [40 Valid, 4352 Invalid, 23 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 23 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:45,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1651 states. [2024-12-02 06:04:45,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1651 to 1651. [2024-12-02 06:04:45,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1651 states, 1639 states have (on average 1.4405125076266017) internal successors, (2361), 1639 states have internal predecessors, (2361), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:45,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1651 states to 1651 states and 2381 transitions. [2024-12-02 06:04:45,909 INFO L78 Accepts]: Start accepts. Automaton has 1651 states and 2381 transitions. Word has length 727 [2024-12-02 06:04:45,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:45,910 INFO L471 AbstractCegarLoop]: Abstraction has 1651 states and 2381 transitions. [2024-12-02 06:04:45,910 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 105.2) internal successors, (526), 5 states have internal predecessors, (526), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:04:45,910 INFO L276 IsEmpty]: Start isEmpty. Operand 1651 states and 2381 transitions. [2024-12-02 06:04:45,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 729 [2024-12-02 06:04:45,913 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:45,913 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:45,928 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Ended with exit code 0 [2024-12-02 06:04:46,113 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable43,24 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:46,114 INFO L396 AbstractCegarLoop]: === Iteration 45 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:46,114 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:46,114 INFO L85 PathProgramCache]: Analyzing trace with hash 1203079047, now seen corresponding path program 1 times [2024-12-02 06:04:46,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:46,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1578301232] [2024-12-02 06:04:46,114 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:46,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:46,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:47,019 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 184 proven. 1 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-12-02 06:04:47,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:47,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1578301232] [2024-12-02 06:04:47,019 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1578301232] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:47,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1248726205] [2024-12-02 06:04:47,019 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:47,019 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:47,019 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:47,021 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:47,021 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2024-12-02 06:04:48,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:48,791 INFO L256 TraceCheckSpWp]: Trace formula consists of 3561 conjuncts, 15 conjuncts are in the unsatisfiable core [2024-12-02 06:04:48,797 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:48,880 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 110 proven. 24 refuted. 0 times theorem prover too weak. 600 trivial. 0 not checked. [2024-12-02 06:04:48,880 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:48,931 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 110 proven. 0 refuted. 0 times theorem prover too weak. 624 trivial. 0 not checked. [2024-12-02 06:04:48,931 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1248726205] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:48,931 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:04:48,932 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 7] total 11 [2024-12-02 06:04:48,932 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657430659] [2024-12-02 06:04:48,932 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:48,932 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:04:48,932 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:48,933 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:04:48,933 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:04:48,933 INFO L87 Difference]: Start difference. First operand 1651 states and 2381 transitions. Second operand has 4 states, 4 states have (on average 132.25) internal successors, (529), 4 states have internal predecessors, (529), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:04:48,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:48,969 INFO L93 Difference]: Finished difference Result 2917 states and 4215 transitions. [2024-12-02 06:04:48,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:04:48,970 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 132.25) internal successors, (529), 4 states have internal predecessors, (529), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 728 [2024-12-02 06:04:48,970 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:48,972 INFO L225 Difference]: With dead ends: 2917 [2024-12-02 06:04:48,972 INFO L226 Difference]: Without dead ends: 1655 [2024-12-02 06:04:48,973 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1458 GetRequests, 1449 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:04:48,973 INFO L435 NwaCegarLoop]: 1092 mSDtfsCounter, 0 mSDsluCounter, 2174 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3266 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:48,973 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3266 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:48,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1655 states. [2024-12-02 06:04:48,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1655 to 1655. [2024-12-02 06:04:48,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1655 states, 1643 states have (on average 1.439440048691418) internal successors, (2365), 1643 states have internal predecessors, (2365), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:48,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1655 states to 1655 states and 2385 transitions. [2024-12-02 06:04:48,996 INFO L78 Accepts]: Start accepts. Automaton has 1655 states and 2385 transitions. Word has length 728 [2024-12-02 06:04:48,996 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:48,996 INFO L471 AbstractCegarLoop]: Abstraction has 1655 states and 2385 transitions. [2024-12-02 06:04:48,996 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 132.25) internal successors, (529), 4 states have internal predecessors, (529), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:04:48,997 INFO L276 IsEmpty]: Start isEmpty. Operand 1655 states and 2385 transitions. [2024-12-02 06:04:49,000 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 729 [2024-12-02 06:04:49,000 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:49,000 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:49,015 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Ended with exit code 0 [2024-12-02 06:04:49,200 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable44,25 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:49,201 INFO L396 AbstractCegarLoop]: === Iteration 46 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:49,201 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:49,201 INFO L85 PathProgramCache]: Analyzing trace with hash 1562317618, now seen corresponding path program 1 times [2024-12-02 06:04:49,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:49,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2001068692] [2024-12-02 06:04:49,201 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:49,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:49,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:49,962 INFO L134 CoverageAnalysis]: Checked inductivity of 735 backedges. 185 proven. 1 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-12-02 06:04:49,962 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:49,962 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2001068692] [2024-12-02 06:04:49,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2001068692] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:49,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [93671571] [2024-12-02 06:04:49,963 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:49,963 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:49,963 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:49,964 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:49,965 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2024-12-02 06:04:51,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:51,745 INFO L256 TraceCheckSpWp]: Trace formula consists of 3559 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:04:51,750 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:51,780 INFO L134 CoverageAnalysis]: Checked inductivity of 735 backedges. 285 proven. 37 refuted. 0 times theorem prover too weak. 413 trivial. 0 not checked. [2024-12-02 06:04:51,780 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:04:51,831 INFO L134 CoverageAnalysis]: Checked inductivity of 735 backedges. 185 proven. 1 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-12-02 06:04:51,831 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [93671571] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:04:51,831 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:04:51,831 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:04:51,831 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [763977222] [2024-12-02 06:04:51,831 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:04:51,832 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:04:51,832 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:51,832 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:04:51,832 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:04:51,832 INFO L87 Difference]: Start difference. First operand 1655 states and 2385 transitions. Second operand has 9 states, 9 states have (on average 68.0) internal successors, (612), 9 states have internal predecessors, (612), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:04:51,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:51,905 INFO L93 Difference]: Finished difference Result 2579 states and 3715 transitions. [2024-12-02 06:04:51,905 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:04:51,905 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 68.0) internal successors, (612), 9 states have internal predecessors, (612), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 728 [2024-12-02 06:04:51,905 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:51,907 INFO L225 Difference]: With dead ends: 2579 [2024-12-02 06:04:51,907 INFO L226 Difference]: Without dead ends: 1661 [2024-12-02 06:04:51,908 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1459 GetRequests, 1451 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:04:51,908 INFO L435 NwaCegarLoop]: 1096 mSDtfsCounter, 15 mSDsluCounter, 5450 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 6546 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:51,908 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 6546 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:51,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1661 states. [2024-12-02 06:04:51,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1661 to 1661. [2024-12-02 06:04:51,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1661 states, 1649 states have (on average 1.4378411158277744) internal successors, (2371), 1649 states have internal predecessors, (2371), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:04:51,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1661 states to 1661 states and 2391 transitions. [2024-12-02 06:04:51,932 INFO L78 Accepts]: Start accepts. Automaton has 1661 states and 2391 transitions. Word has length 728 [2024-12-02 06:04:51,932 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:51,932 INFO L471 AbstractCegarLoop]: Abstraction has 1661 states and 2391 transitions. [2024-12-02 06:04:51,932 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 68.0) internal successors, (612), 9 states have internal predecessors, (612), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:04:51,932 INFO L276 IsEmpty]: Start isEmpty. Operand 1661 states and 2391 transitions. [2024-12-02 06:04:51,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 735 [2024-12-02 06:04:51,936 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:51,936 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:51,958 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Ended with exit code 0 [2024-12-02 06:04:52,136 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable45,26 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:52,137 INFO L396 AbstractCegarLoop]: === Iteration 47 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:52,137 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:52,137 INFO L85 PathProgramCache]: Analyzing trace with hash -915378394, now seen corresponding path program 2 times [2024-12-02 06:04:52,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:52,137 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928556894] [2024-12-02 06:04:52,137 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:04:52,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:52,310 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:04:52,311 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:04:53,080 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 103 proven. 79 refuted. 0 times theorem prover too weak. 568 trivial. 0 not checked. [2024-12-02 06:04:53,081 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:53,081 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [928556894] [2024-12-02 06:04:53,081 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [928556894] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:53,081 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1112494088] [2024-12-02 06:04:53,081 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:04:53,081 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:53,081 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:53,082 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:53,083 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2024-12-02 06:04:54,745 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:04:54,745 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:04:54,752 INFO L256 TraceCheckSpWp]: Trace formula consists of 803 conjuncts, 85 conjuncts are in the unsatisfiable core [2024-12-02 06:04:54,762 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:56,755 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 4 proven. 178 refuted. 0 times theorem prover too weak. 568 trivial. 0 not checked. [2024-12-02 06:04:56,755 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:02,990 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 98 proven. 84 refuted. 0 times theorem prover too weak. 568 trivial. 0 not checked. [2024-12-02 06:05:02,990 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1112494088] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:05:02,990 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:05:02,991 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 22, 17] total 43 [2024-12-02 06:05:02,991 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1169937196] [2024-12-02 06:05:02,991 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:05:02,991 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 43 states [2024-12-02 06:05:02,992 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:02,992 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2024-12-02 06:05:02,993 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=270, Invalid=1536, Unknown=0, NotChecked=0, Total=1806 [2024-12-02 06:05:02,993 INFO L87 Difference]: Start difference. First operand 1661 states and 2391 transitions. Second operand has 43 states, 43 states have (on average 41.18604651162791) internal successors, (1771), 43 states have internal predecessors, (1771), 6 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) [2024-12-02 06:05:07,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:07,590 INFO L93 Difference]: Finished difference Result 4829 states and 6992 transitions. [2024-12-02 06:05:07,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2024-12-02 06:05:07,591 INFO L78 Accepts]: Start accepts. Automaton has has 43 states, 43 states have (on average 41.18604651162791) internal successors, (1771), 43 states have internal predecessors, (1771), 6 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) Word has length 734 [2024-12-02 06:05:07,591 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:07,594 INFO L225 Difference]: With dead ends: 4829 [2024-12-02 06:05:07,594 INFO L226 Difference]: Without dead ends: 3541 [2024-12-02 06:05:07,598 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1506 GetRequests, 1433 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1170 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=748, Invalid=4802, Unknown=0, NotChecked=0, Total=5550 [2024-12-02 06:05:07,598 INFO L435 NwaCegarLoop]: 880 mSDtfsCounter, 7655 mSDsluCounter, 17222 mSDsCounter, 0 mSdLazyCounter, 8197 mSolverCounterSat, 22 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7655 SdHoareTripleChecker+Valid, 18102 SdHoareTripleChecker+Invalid, 8219 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 22 IncrementalHoareTripleChecker+Valid, 8197 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 3.6s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:07,598 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7655 Valid, 18102 Invalid, 8219 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [22 Valid, 8197 Invalid, 0 Unknown, 0 Unchecked, 3.6s Time] [2024-12-02 06:05:07,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3541 states. [2024-12-02 06:05:07,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3541 to 2064. [2024-12-02 06:05:07,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2064 states, 2042 states have (on average 1.4333986287952987) internal successors, (2927), 2042 states have internal predecessors, (2927), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:05:07,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2064 states to 2064 states and 2967 transitions. [2024-12-02 06:05:07,631 INFO L78 Accepts]: Start accepts. Automaton has 2064 states and 2967 transitions. Word has length 734 [2024-12-02 06:05:07,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:07,631 INFO L471 AbstractCegarLoop]: Abstraction has 2064 states and 2967 transitions. [2024-12-02 06:05:07,631 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 43 states, 43 states have (on average 41.18604651162791) internal successors, (1771), 43 states have internal predecessors, (1771), 6 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) [2024-12-02 06:05:07,631 INFO L276 IsEmpty]: Start isEmpty. Operand 2064 states and 2967 transitions. [2024-12-02 06:05:07,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 736 [2024-12-02 06:05:07,635 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:07,635 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:07,648 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Ended with exit code 0 [2024-12-02 06:05:07,836 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable46,27 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:07,836 INFO L396 AbstractCegarLoop]: === Iteration 48 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:07,836 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:07,837 INFO L85 PathProgramCache]: Analyzing trace with hash 1631054289, now seen corresponding path program 1 times [2024-12-02 06:05:07,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:07,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109660640] [2024-12-02 06:05:07,837 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:07,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:08,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:08,897 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 185 proven. 16 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-12-02 06:05:08,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:08,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109660640] [2024-12-02 06:05:08,897 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109660640] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:08,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1277898274] [2024-12-02 06:05:08,897 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:08,897 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:08,897 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:05:08,899 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:05:08,900 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2024-12-02 06:05:10,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:10,778 INFO L256 TraceCheckSpWp]: Trace formula consists of 3587 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-12-02 06:05:10,783 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:10,852 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 285 proven. 112 refuted. 0 times theorem prover too weak. 353 trivial. 0 not checked. [2024-12-02 06:05:10,852 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:10,949 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 185 proven. 16 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-12-02 06:05:10,949 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1277898274] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:05:10,949 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:05:10,949 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-12-02 06:05:10,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1905166001] [2024-12-02 06:05:10,949 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:05:10,950 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-12-02 06:05:10,950 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:10,950 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-12-02 06:05:10,950 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:05:10,951 INFO L87 Difference]: Start difference. First operand 2064 states and 2967 transitions. Second operand has 18 states, 18 states have (on average 35.388888888888886) internal successors, (637), 18 states have internal predecessors, (637), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:05:11,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:11,150 INFO L93 Difference]: Finished difference Result 3201 states and 4599 transitions. [2024-12-02 06:05:11,151 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-12-02 06:05:11,151 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 35.388888888888886) internal successors, (637), 18 states have internal predecessors, (637), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 735 [2024-12-02 06:05:11,151 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:11,154 INFO L225 Difference]: With dead ends: 3201 [2024-12-02 06:05:11,154 INFO L226 Difference]: Without dead ends: 2072 [2024-12-02 06:05:11,155 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1477 GetRequests, 1459 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:05:11,155 INFO L435 NwaCegarLoop]: 1114 mSDtfsCounter, 27 mSDsluCounter, 13295 mSDsCounter, 0 mSdLazyCounter, 273 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 14409 SdHoareTripleChecker+Invalid, 274 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 273 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:11,156 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 14409 Invalid, 274 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 273 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:05:11,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2072 states. [2024-12-02 06:05:11,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2072 to 2072. [2024-12-02 06:05:11,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2072 states, 2050 states have (on average 1.4317073170731707) internal successors, (2935), 2050 states have internal predecessors, (2935), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:05:11,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2072 states to 2072 states and 2975 transitions. [2024-12-02 06:05:11,193 INFO L78 Accepts]: Start accepts. Automaton has 2072 states and 2975 transitions. Word has length 735 [2024-12-02 06:05:11,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:11,193 INFO L471 AbstractCegarLoop]: Abstraction has 2072 states and 2975 transitions. [2024-12-02 06:05:11,193 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 35.388888888888886) internal successors, (637), 18 states have internal predecessors, (637), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:05:11,193 INFO L276 IsEmpty]: Start isEmpty. Operand 2072 states and 2975 transitions. [2024-12-02 06:05:11,199 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 744 [2024-12-02 06:05:11,199 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:11,200 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:11,216 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Ended with exit code 0 [2024-12-02 06:05:11,400 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable47,28 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:11,400 INFO L396 AbstractCegarLoop]: === Iteration 49 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:11,401 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:11,401 INFO L85 PathProgramCache]: Analyzing trace with hash 1617889761, now seen corresponding path program 2 times [2024-12-02 06:05:11,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:11,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1519261353] [2024-12-02 06:05:11,401 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:05:11,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:11,589 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:05:11,589 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:05:12,634 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 4 proven. 108 refuted. 0 times theorem prover too weak. 686 trivial. 0 not checked. [2024-12-02 06:05:12,634 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:12,634 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1519261353] [2024-12-02 06:05:12,634 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1519261353] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:12,634 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [125752372] [2024-12-02 06:05:12,634 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:05:12,634 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:12,634 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:05:12,636 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:05:12,636 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2024-12-02 06:05:14,337 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:05:14,337 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:05:14,344 INFO L256 TraceCheckSpWp]: Trace formula consists of 804 conjuncts, 26 conjuncts are in the unsatisfiable core [2024-12-02 06:05:14,350 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:17,119 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 2 proven. 110 refuted. 0 times theorem prover too weak. 686 trivial. 0 not checked. [2024-12-02 06:05:17,119 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:27,053 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 2 proven. 110 refuted. 0 times theorem prover too weak. 686 trivial. 0 not checked. [2024-12-02 06:05:27,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [125752372] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:05:27,053 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:05:27,053 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8, 9] total 23 [2024-12-02 06:05:27,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [298107518] [2024-12-02 06:05:27,054 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:05:27,054 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2024-12-02 06:05:27,054 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:27,056 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2024-12-02 06:05:27,056 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=444, Unknown=0, NotChecked=0, Total=506 [2024-12-02 06:05:27,056 INFO L87 Difference]: Start difference. First operand 2072 states and 2975 transitions. Second operand has 23 states, 23 states have (on average 68.56521739130434) internal successors, (1577), 23 states have internal predecessors, (1577), 3 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 3 states have call predecessors, (15), 3 states have call successors, (15) [2024-12-02 06:05:29,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:29,302 INFO L93 Difference]: Finished difference Result 3213 states and 4609 transitions. [2024-12-02 06:05:29,302 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2024-12-02 06:05:29,303 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 23 states have (on average 68.56521739130434) internal successors, (1577), 23 states have internal predecessors, (1577), 3 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 3 states have call predecessors, (15), 3 states have call successors, (15) Word has length 743 [2024-12-02 06:05:29,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:29,306 INFO L225 Difference]: With dead ends: 3213 [2024-12-02 06:05:29,306 INFO L226 Difference]: Without dead ends: 2076 [2024-12-02 06:05:29,308 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1509 GetRequests, 1474 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 243 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=190, Invalid=1142, Unknown=0, NotChecked=0, Total=1332 [2024-12-02 06:05:29,308 INFO L435 NwaCegarLoop]: 785 mSDtfsCounter, 1629 mSDsluCounter, 8346 mSDsCounter, 0 mSdLazyCounter, 3726 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1629 SdHoareTripleChecker+Valid, 9131 SdHoareTripleChecker+Invalid, 3732 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 3726 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.9s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:29,308 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1629 Valid, 9131 Invalid, 3732 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 3726 Invalid, 0 Unknown, 0 Unchecked, 1.9s Time] [2024-12-02 06:05:29,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2076 states. [2024-12-02 06:05:29,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2076 to 2070. [2024-12-02 06:05:29,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2070 states, 2048 states have (on average 1.4306640625) internal successors, (2930), 2048 states have internal predecessors, (2930), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:05:29,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2070 states to 2070 states and 2970 transitions. [2024-12-02 06:05:29,341 INFO L78 Accepts]: Start accepts. Automaton has 2070 states and 2970 transitions. Word has length 743 [2024-12-02 06:05:29,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:29,341 INFO L471 AbstractCegarLoop]: Abstraction has 2070 states and 2970 transitions. [2024-12-02 06:05:29,341 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 68.56521739130434) internal successors, (1577), 23 states have internal predecessors, (1577), 3 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 3 states have call predecessors, (15), 3 states have call successors, (15) [2024-12-02 06:05:29,342 INFO L276 IsEmpty]: Start isEmpty. Operand 2070 states and 2970 transitions. [2024-12-02 06:05:29,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 744 [2024-12-02 06:05:29,345 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:29,345 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:29,357 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Ended with exit code 0 [2024-12-02 06:05:29,546 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable48,29 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:29,546 INFO L396 AbstractCegarLoop]: === Iteration 50 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:29,546 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:29,547 INFO L85 PathProgramCache]: Analyzing trace with hash -1114316960, now seen corresponding path program 1 times [2024-12-02 06:05:29,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:29,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378597776] [2024-12-02 06:05:29,547 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:29,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:29,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:30,323 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 185 proven. 1 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-12-02 06:05:30,323 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:30,323 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1378597776] [2024-12-02 06:05:30,323 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1378597776] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:30,323 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1666489435] [2024-12-02 06:05:30,324 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:30,324 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:30,324 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:05:30,325 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:05:30,326 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2024-12-02 06:05:32,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:32,339 INFO L256 TraceCheckSpWp]: Trace formula consists of 3623 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:05:32,345 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:32,371 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 285 proven. 37 refuted. 0 times theorem prover too weak. 476 trivial. 0 not checked. [2024-12-02 06:05:32,371 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:32,422 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 185 proven. 1 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-12-02 06:05:32,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1666489435] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:05:32,423 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:05:32,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:05:32,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619754086] [2024-12-02 06:05:32,423 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:05:32,424 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:05:32,424 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:32,424 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:05:32,425 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:05:32,425 INFO L87 Difference]: Start difference. First operand 2070 states and 2970 transitions. Second operand has 9 states, 9 states have (on average 68.11111111111111) internal successors, (613), 9 states have internal predecessors, (613), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:05:32,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:32,510 INFO L93 Difference]: Finished difference Result 3211 states and 4602 transitions. [2024-12-02 06:05:32,510 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:05:32,510 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 68.11111111111111) internal successors, (613), 9 states have internal predecessors, (613), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 743 [2024-12-02 06:05:32,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:32,512 INFO L225 Difference]: With dead ends: 3211 [2024-12-02 06:05:32,512 INFO L226 Difference]: Without dead ends: 2076 [2024-12-02 06:05:32,513 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1489 GetRequests, 1481 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:05:32,513 INFO L435 NwaCegarLoop]: 1094 mSDtfsCounter, 15 mSDsluCounter, 5440 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 6534 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:32,513 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 6534 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:05:32,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2076 states. [2024-12-02 06:05:32,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2076 to 2076. [2024-12-02 06:05:32,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2076 states, 2054 states have (on average 1.4294060370009738) internal successors, (2936), 2054 states have internal predecessors, (2936), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:05:32,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2076 states to 2076 states and 2976 transitions. [2024-12-02 06:05:32,544 INFO L78 Accepts]: Start accepts. Automaton has 2076 states and 2976 transitions. Word has length 743 [2024-12-02 06:05:32,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:32,545 INFO L471 AbstractCegarLoop]: Abstraction has 2076 states and 2976 transitions. [2024-12-02 06:05:32,545 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 68.11111111111111) internal successors, (613), 9 states have internal predecessors, (613), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:05:32,545 INFO L276 IsEmpty]: Start isEmpty. Operand 2076 states and 2976 transitions. [2024-12-02 06:05:32,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 750 [2024-12-02 06:05:32,549 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:32,549 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:32,565 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Ended with exit code 0 [2024-12-02 06:05:32,749 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 30 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable49 [2024-12-02 06:05:32,749 INFO L396 AbstractCegarLoop]: === Iteration 51 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:32,750 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:32,750 INFO L85 PathProgramCache]: Analyzing trace with hash 970100908, now seen corresponding path program 2 times [2024-12-02 06:05:32,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:32,750 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101419512] [2024-12-02 06:05:32,750 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:05:32,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:33,119 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:05:33,119 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:05:34,075 INFO L134 CoverageAnalysis]: Checked inductivity of 813 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 628 trivial. 0 not checked. [2024-12-02 06:05:34,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:34,075 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1101419512] [2024-12-02 06:05:34,075 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1101419512] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:05:34,075 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:05:34,075 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:05:34,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1250480464] [2024-12-02 06:05:34,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:05:34,076 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:05:34,076 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:34,077 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:05:34,077 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:05:34,077 INFO L87 Difference]: Start difference. First operand 2076 states and 2976 transitions. Second operand has 7 states, 7 states have (on average 85.42857142857143) internal successors, (598), 7 states have internal predecessors, (598), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:34,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:34,577 INFO L93 Difference]: Finished difference Result 4760 states and 6817 transitions. [2024-12-02 06:05:34,578 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:05:34,578 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 85.42857142857143) internal successors, (598), 7 states have internal predecessors, (598), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 749 [2024-12-02 06:05:34,579 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:34,581 INFO L225 Difference]: With dead ends: 4760 [2024-12-02 06:05:34,581 INFO L226 Difference]: Without dead ends: 3210 [2024-12-02 06:05:34,583 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:05:34,583 INFO L435 NwaCegarLoop]: 1853 mSDtfsCounter, 1321 mSDsluCounter, 8020 mSDsCounter, 0 mSdLazyCounter, 605 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1321 SdHoareTripleChecker+Valid, 9873 SdHoareTripleChecker+Invalid, 613 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 605 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:34,583 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1321 Valid, 9873 Invalid, 613 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 605 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 06:05:34,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3210 states. [2024-12-02 06:05:34,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3210 to 2608. [2024-12-02 06:05:34,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2608 states, 2576 states have (on average 1.423524844720497) internal successors, (3667), 2576 states have internal predecessors, (3667), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-12-02 06:05:34,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2608 states to 2608 states and 3727 transitions. [2024-12-02 06:05:34,625 INFO L78 Accepts]: Start accepts. Automaton has 2608 states and 3727 transitions. Word has length 749 [2024-12-02 06:05:34,626 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:34,626 INFO L471 AbstractCegarLoop]: Abstraction has 2608 states and 3727 transitions. [2024-12-02 06:05:34,626 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 85.42857142857143) internal successors, (598), 7 states have internal predecessors, (598), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:34,626 INFO L276 IsEmpty]: Start isEmpty. Operand 2608 states and 3727 transitions. [2024-12-02 06:05:34,630 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 751 [2024-12-02 06:05:34,630 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:34,630 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:34,631 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable50 [2024-12-02 06:05:34,631 INFO L396 AbstractCegarLoop]: === Iteration 52 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:34,631 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:34,631 INFO L85 PathProgramCache]: Analyzing trace with hash 905986860, now seen corresponding path program 1 times [2024-12-02 06:05:34,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:34,631 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [30317323] [2024-12-02 06:05:34,631 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:34,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:34,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:35,637 INFO L134 CoverageAnalysis]: Checked inductivity of 814 backedges. 186 proven. 16 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-12-02 06:05:35,637 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:35,637 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [30317323] [2024-12-02 06:05:35,637 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [30317323] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:35,638 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1951850810] [2024-12-02 06:05:35,638 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:35,638 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:35,638 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:05:35,639 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:05:35,640 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2024-12-02 06:05:37,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:37,745 INFO L256 TraceCheckSpWp]: Trace formula consists of 3653 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-12-02 06:05:37,750 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:37,830 INFO L134 CoverageAnalysis]: Checked inductivity of 814 backedges. 286 proven. 112 refuted. 0 times theorem prover too weak. 416 trivial. 0 not checked. [2024-12-02 06:05:37,830 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:37,941 INFO L134 CoverageAnalysis]: Checked inductivity of 814 backedges. 186 proven. 16 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-12-02 06:05:37,942 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1951850810] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:05:37,942 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:05:37,942 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-12-02 06:05:37,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1294678022] [2024-12-02 06:05:37,942 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:05:37,942 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-12-02 06:05:37,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:37,943 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-12-02 06:05:37,943 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:05:37,943 INFO L87 Difference]: Start difference. First operand 2608 states and 3727 transitions. Second operand has 18 states, 18 states have (on average 35.44444444444444) internal successors, (638), 18 states have internal predecessors, (638), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:05:38,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:38,143 INFO L93 Difference]: Finished difference Result 4297 states and 6131 transitions. [2024-12-02 06:05:38,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-12-02 06:05:38,143 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 35.44444444444444) internal successors, (638), 18 states have internal predecessors, (638), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 750 [2024-12-02 06:05:38,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:38,146 INFO L225 Difference]: With dead ends: 4297 [2024-12-02 06:05:38,146 INFO L226 Difference]: Without dead ends: 2624 [2024-12-02 06:05:38,147 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1507 GetRequests, 1489 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:05:38,147 INFO L435 NwaCegarLoop]: 1112 mSDtfsCounter, 27 mSDsluCounter, 13271 mSDsCounter, 0 mSdLazyCounter, 264 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 14383 SdHoareTripleChecker+Invalid, 265 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 264 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:38,147 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 14383 Invalid, 265 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 264 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:05:38,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2624 states. [2024-12-02 06:05:38,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2624 to 2624. [2024-12-02 06:05:38,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2624 states, 2592 states have (on average 1.4209104938271604) internal successors, (3683), 2592 states have internal predecessors, (3683), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-12-02 06:05:38,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2624 states to 2624 states and 3743 transitions. [2024-12-02 06:05:38,189 INFO L78 Accepts]: Start accepts. Automaton has 2624 states and 3743 transitions. Word has length 750 [2024-12-02 06:05:38,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:38,189 INFO L471 AbstractCegarLoop]: Abstraction has 2624 states and 3743 transitions. [2024-12-02 06:05:38,189 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 35.44444444444444) internal successors, (638), 18 states have internal predecessors, (638), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:05:38,189 INFO L276 IsEmpty]: Start isEmpty. Operand 2624 states and 3743 transitions. [2024-12-02 06:05:38,193 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 759 [2024-12-02 06:05:38,193 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:38,194 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:38,210 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Ended with exit code 0 [2024-12-02 06:05:38,394 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable51,31 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:38,394 INFO L396 AbstractCegarLoop]: === Iteration 53 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:38,394 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:38,395 INFO L85 PathProgramCache]: Analyzing trace with hash 794369052, now seen corresponding path program 2 times [2024-12-02 06:05:38,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:38,395 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1331106169] [2024-12-02 06:05:38,395 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:05:38,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:38,747 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:05:38,747 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:05:39,725 INFO L134 CoverageAnalysis]: Checked inductivity of 862 backedges. 186 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:05:39,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:39,725 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1331106169] [2024-12-02 06:05:39,725 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1331106169] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:05:39,725 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:05:39,725 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:05:39,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048020760] [2024-12-02 06:05:39,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:05:39,726 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:05:39,726 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:39,727 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:05:39,727 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:05:39,727 INFO L87 Difference]: Start difference. First operand 2624 states and 3743 transitions. Second operand has 7 states, 7 states have (on average 85.57142857142857) internal successors, (599), 7 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:40,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:40,833 INFO L93 Difference]: Finished difference Result 4915 states and 7007 transitions. [2024-12-02 06:05:40,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:05:40,834 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 85.57142857142857) internal successors, (599), 7 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 758 [2024-12-02 06:05:40,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:40,837 INFO L225 Difference]: With dead ends: 4915 [2024-12-02 06:05:40,837 INFO L226 Difference]: Without dead ends: 3226 [2024-12-02 06:05:40,838 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:05:40,839 INFO L435 NwaCegarLoop]: 1413 mSDtfsCounter, 1514 mSDsluCounter, 5010 mSDsCounter, 0 mSdLazyCounter, 2185 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1514 SdHoareTripleChecker+Valid, 6423 SdHoareTripleChecker+Invalid, 2185 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 2185 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:40,839 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1514 Valid, 6423 Invalid, 2185 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 2185 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-12-02 06:05:40,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3226 states. [2024-12-02 06:05:40,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3226 to 2626. [2024-12-02 06:05:40,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2626 states, 2594 states have (on average 1.420585967617579) internal successors, (3685), 2594 states have internal predecessors, (3685), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-12-02 06:05:40,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2626 states to 2626 states and 3745 transitions. [2024-12-02 06:05:40,882 INFO L78 Accepts]: Start accepts. Automaton has 2626 states and 3745 transitions. Word has length 758 [2024-12-02 06:05:40,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:40,882 INFO L471 AbstractCegarLoop]: Abstraction has 2626 states and 3745 transitions. [2024-12-02 06:05:40,883 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 85.57142857142857) internal successors, (599), 7 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:40,883 INFO L276 IsEmpty]: Start isEmpty. Operand 2626 states and 3745 transitions. [2024-12-02 06:05:40,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 759 [2024-12-02 06:05:40,887 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:40,887 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:40,887 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable52 [2024-12-02 06:05:40,887 INFO L396 AbstractCegarLoop]: === Iteration 54 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:40,887 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:40,887 INFO L85 PathProgramCache]: Analyzing trace with hash -1684021553, now seen corresponding path program 1 times [2024-12-02 06:05:40,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:40,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616364845] [2024-12-02 06:05:40,887 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:40,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:41,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:42,605 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:05:42,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:42,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1616364845] [2024-12-02 06:05:42,605 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1616364845] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:05:42,605 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:05:42,605 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:05:42,605 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1175153461] [2024-12-02 06:05:42,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:05:42,605 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:05:42,605 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:42,606 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:05:42,606 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:05:42,606 INFO L87 Difference]: Start difference. First operand 2626 states and 3745 transitions. Second operand has 4 states, 4 states have (on average 149.75) internal successors, (599), 4 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:42,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:42,765 INFO L93 Difference]: Finished difference Result 4317 states and 6143 transitions. [2024-12-02 06:05:42,765 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:05:42,765 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 149.75) internal successors, (599), 4 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 758 [2024-12-02 06:05:42,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:42,768 INFO L225 Difference]: With dead ends: 4317 [2024-12-02 06:05:42,768 INFO L226 Difference]: Without dead ends: 2626 [2024-12-02 06:05:42,771 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:05:42,771 INFO L435 NwaCegarLoop]: 999 mSDtfsCounter, 774 mSDsluCounter, 1001 mSDsCounter, 0 mSdLazyCounter, 188 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 774 SdHoareTripleChecker+Valid, 2000 SdHoareTripleChecker+Invalid, 188 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 188 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:42,771 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [774 Valid, 2000 Invalid, 188 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 188 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:05:42,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2626 states. [2024-12-02 06:05:42,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2626 to 2626. [2024-12-02 06:05:42,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2626 states, 2594 states have (on average 1.4202004626060138) internal successors, (3684), 2594 states have internal predecessors, (3684), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-12-02 06:05:42,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2626 states to 2626 states and 3744 transitions. [2024-12-02 06:05:42,811 INFO L78 Accepts]: Start accepts. Automaton has 2626 states and 3744 transitions. Word has length 758 [2024-12-02 06:05:42,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:42,812 INFO L471 AbstractCegarLoop]: Abstraction has 2626 states and 3744 transitions. [2024-12-02 06:05:42,812 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 149.75) internal successors, (599), 4 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:42,812 INFO L276 IsEmpty]: Start isEmpty. Operand 2626 states and 3744 transitions. [2024-12-02 06:05:42,816 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 760 [2024-12-02 06:05:42,816 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:42,816 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:42,816 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable53 [2024-12-02 06:05:42,816 INFO L396 AbstractCegarLoop]: === Iteration 55 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:42,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:42,817 INFO L85 PathProgramCache]: Analyzing trace with hash 2126536928, now seen corresponding path program 1 times [2024-12-02 06:05:42,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:42,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074956678] [2024-12-02 06:05:42,817 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:42,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:43,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:44,310 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:05:44,310 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:44,310 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1074956678] [2024-12-02 06:05:44,310 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1074956678] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:05:44,310 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:05:44,311 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:05:44,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1536521835] [2024-12-02 06:05:44,311 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:05:44,311 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:05:44,311 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:44,311 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:05:44,312 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:05:44,312 INFO L87 Difference]: Start difference. First operand 2626 states and 3744 transitions. Second operand has 5 states, 5 states have (on average 120.0) internal successors, (600), 5 states have internal predecessors, (600), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:44,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:44,517 INFO L93 Difference]: Finished difference Result 4317 states and 6141 transitions. [2024-12-02 06:05:44,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:05:44,517 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 120.0) internal successors, (600), 5 states have internal predecessors, (600), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 759 [2024-12-02 06:05:44,517 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:44,520 INFO L225 Difference]: With dead ends: 4317 [2024-12-02 06:05:44,520 INFO L226 Difference]: Without dead ends: 2626 [2024-12-02 06:05:44,521 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:05:44,521 INFO L435 NwaCegarLoop]: 999 mSDtfsCounter, 1070 mSDsluCounter, 1010 mSDsCounter, 0 mSdLazyCounter, 186 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1075 SdHoareTripleChecker+Valid, 2009 SdHoareTripleChecker+Invalid, 186 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 186 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:44,521 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1075 Valid, 2009 Invalid, 186 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 186 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:05:44,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2626 states. [2024-12-02 06:05:44,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2626 to 2626. [2024-12-02 06:05:44,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2626 states, 2594 states have (on average 1.4198149575944488) internal successors, (3683), 2594 states have internal predecessors, (3683), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-12-02 06:05:44,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2626 states to 2626 states and 3743 transitions. [2024-12-02 06:05:44,564 INFO L78 Accepts]: Start accepts. Automaton has 2626 states and 3743 transitions. Word has length 759 [2024-12-02 06:05:44,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:44,565 INFO L471 AbstractCegarLoop]: Abstraction has 2626 states and 3743 transitions. [2024-12-02 06:05:44,565 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 120.0) internal successors, (600), 5 states have internal predecessors, (600), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:44,565 INFO L276 IsEmpty]: Start isEmpty. Operand 2626 states and 3743 transitions. [2024-12-02 06:05:44,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 761 [2024-12-02 06:05:44,568 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:44,569 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:44,569 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable54 [2024-12-02 06:05:44,569 INFO L396 AbstractCegarLoop]: === Iteration 56 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:44,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:44,569 INFO L85 PathProgramCache]: Analyzing trace with hash -193696654, now seen corresponding path program 1 times [2024-12-02 06:05:44,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:44,569 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [657788356] [2024-12-02 06:05:44,569 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:44,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:45,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:46,366 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:05:46,366 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:46,366 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [657788356] [2024-12-02 06:05:46,366 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [657788356] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:05:46,366 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:05:46,366 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:05:46,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1138136058] [2024-12-02 06:05:46,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:05:46,367 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:05:46,367 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:46,367 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:05:46,367 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:05:46,368 INFO L87 Difference]: Start difference. First operand 2626 states and 3743 transitions. Second operand has 5 states, 5 states have (on average 120.2) internal successors, (601), 5 states have internal predecessors, (601), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:46,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:46,580 INFO L93 Difference]: Finished difference Result 4317 states and 6139 transitions. [2024-12-02 06:05:46,580 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:05:46,580 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 120.2) internal successors, (601), 5 states have internal predecessors, (601), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 760 [2024-12-02 06:05:46,581 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:46,583 INFO L225 Difference]: With dead ends: 4317 [2024-12-02 06:05:46,583 INFO L226 Difference]: Without dead ends: 2626 [2024-12-02 06:05:46,584 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:05:46,584 INFO L435 NwaCegarLoop]: 999 mSDtfsCounter, 1822 mSDsluCounter, 1001 mSDsCounter, 0 mSdLazyCounter, 184 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1827 SdHoareTripleChecker+Valid, 2000 SdHoareTripleChecker+Invalid, 184 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 184 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:46,584 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1827 Valid, 2000 Invalid, 184 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 184 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:05:46,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2626 states. [2024-12-02 06:05:46,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2626 to 2626. [2024-12-02 06:05:46,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2626 states, 2594 states have (on average 1.4194294525828837) internal successors, (3682), 2594 states have internal predecessors, (3682), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-12-02 06:05:46,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2626 states to 2626 states and 3742 transitions. [2024-12-02 06:05:46,624 INFO L78 Accepts]: Start accepts. Automaton has 2626 states and 3742 transitions. Word has length 760 [2024-12-02 06:05:46,624 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:46,624 INFO L471 AbstractCegarLoop]: Abstraction has 2626 states and 3742 transitions. [2024-12-02 06:05:46,624 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 120.2) internal successors, (601), 5 states have internal predecessors, (601), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:46,624 INFO L276 IsEmpty]: Start isEmpty. Operand 2626 states and 3742 transitions. [2024-12-02 06:05:46,628 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 762 [2024-12-02 06:05:46,628 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:46,628 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:46,628 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable55 [2024-12-02 06:05:46,628 INFO L396 AbstractCegarLoop]: === Iteration 57 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:46,629 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:46,629 INFO L85 PathProgramCache]: Analyzing trace with hash -1004198968, now seen corresponding path program 1 times [2024-12-02 06:05:46,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:46,629 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1442377138] [2024-12-02 06:05:46,629 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:46,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:47,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:48,153 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:05:48,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:48,153 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1442377138] [2024-12-02 06:05:48,153 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1442377138] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:05:48,153 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:05:48,154 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:05:48,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [186503061] [2024-12-02 06:05:48,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:05:48,154 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:05:48,155 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:48,155 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:05:48,155 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:05:48,155 INFO L87 Difference]: Start difference. First operand 2626 states and 3742 transitions. Second operand has 4 states, 4 states have (on average 150.5) internal successors, (602), 4 states have internal predecessors, (602), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:48,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:48,348 INFO L93 Difference]: Finished difference Result 4317 states and 6137 transitions. [2024-12-02 06:05:48,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:05:48,349 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 150.5) internal successors, (602), 4 states have internal predecessors, (602), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 761 [2024-12-02 06:05:48,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:48,351 INFO L225 Difference]: With dead ends: 4317 [2024-12-02 06:05:48,351 INFO L226 Difference]: Without dead ends: 2626 [2024-12-02 06:05:48,353 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:05:48,353 INFO L435 NwaCegarLoop]: 999 mSDtfsCounter, 741 mSDsluCounter, 1001 mSDsCounter, 0 mSdLazyCounter, 182 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 741 SdHoareTripleChecker+Valid, 2000 SdHoareTripleChecker+Invalid, 182 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 182 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:48,353 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [741 Valid, 2000 Invalid, 182 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 182 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:05:48,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2626 states. [2024-12-02 06:05:48,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2626 to 2626. [2024-12-02 06:05:48,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2626 states, 2594 states have (on average 1.4190439475713184) internal successors, (3681), 2594 states have internal predecessors, (3681), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-12-02 06:05:48,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2626 states to 2626 states and 3741 transitions. [2024-12-02 06:05:48,392 INFO L78 Accepts]: Start accepts. Automaton has 2626 states and 3741 transitions. Word has length 761 [2024-12-02 06:05:48,393 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:48,393 INFO L471 AbstractCegarLoop]: Abstraction has 2626 states and 3741 transitions. [2024-12-02 06:05:48,393 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 150.5) internal successors, (602), 4 states have internal predecessors, (602), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:48,393 INFO L276 IsEmpty]: Start isEmpty. Operand 2626 states and 3741 transitions. [2024-12-02 06:05:48,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 763 [2024-12-02 06:05:48,397 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:48,397 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:48,397 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable56 [2024-12-02 06:05:48,397 INFO L396 AbstractCegarLoop]: === Iteration 58 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:48,397 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:48,397 INFO L85 PathProgramCache]: Analyzing trace with hash -135984971, now seen corresponding path program 1 times [2024-12-02 06:05:48,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:48,398 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764741758] [2024-12-02 06:05:48,398 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:48,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:50,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:51,571 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:05:51,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:51,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764741758] [2024-12-02 06:05:51,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764741758] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:05:51,571 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:05:51,571 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:05:51,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2116660926] [2024-12-02 06:05:51,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:05:51,572 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:05:51,572 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:51,573 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:05:51,573 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:05:51,573 INFO L87 Difference]: Start difference. First operand 2626 states and 3741 transitions. Second operand has 6 states, 6 states have (on average 100.5) internal successors, (603), 6 states have internal predecessors, (603), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:51,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:51,659 INFO L93 Difference]: Finished difference Result 5304 states and 7550 transitions. [2024-12-02 06:05:51,659 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:05:51,659 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 100.5) internal successors, (603), 6 states have internal predecessors, (603), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 762 [2024-12-02 06:05:51,659 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:51,662 INFO L225 Difference]: With dead ends: 5304 [2024-12-02 06:05:51,662 INFO L226 Difference]: Without dead ends: 3613 [2024-12-02 06:05:51,664 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:05:51,664 INFO L435 NwaCegarLoop]: 1079 mSDtfsCounter, 307 mSDsluCounter, 4299 mSDsCounter, 0 mSdLazyCounter, 61 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 307 SdHoareTripleChecker+Valid, 5378 SdHoareTripleChecker+Invalid, 61 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 61 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:51,664 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [307 Valid, 5378 Invalid, 61 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 61 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:05:51,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3613 states. [2024-12-02 06:05:51,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3613 to 3609. [2024-12-02 06:05:51,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3609 states, 3577 states have (on average 1.423259714844842) internal successors, (5091), 3577 states have internal predecessors, (5091), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-12-02 06:05:51,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3609 states to 3609 states and 5151 transitions. [2024-12-02 06:05:51,713 INFO L78 Accepts]: Start accepts. Automaton has 3609 states and 5151 transitions. Word has length 762 [2024-12-02 06:05:51,714 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:51,714 INFO L471 AbstractCegarLoop]: Abstraction has 3609 states and 5151 transitions. [2024-12-02 06:05:51,714 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 100.5) internal successors, (603), 6 states have internal predecessors, (603), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:51,714 INFO L276 IsEmpty]: Start isEmpty. Operand 3609 states and 5151 transitions. [2024-12-02 06:05:51,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 764 [2024-12-02 06:05:51,718 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:51,718 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:51,718 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable57 [2024-12-02 06:05:51,719 INFO L396 AbstractCegarLoop]: === Iteration 59 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:51,719 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:51,719 INFO L85 PathProgramCache]: Analyzing trace with hash 1471099119, now seen corresponding path program 1 times [2024-12-02 06:05:51,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:51,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843894823] [2024-12-02 06:05:51,719 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:51,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:54,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:55,447 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:05:55,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:55,447 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [843894823] [2024-12-02 06:05:55,447 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [843894823] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:05:55,447 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:05:55,447 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:05:55,447 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953979256] [2024-12-02 06:05:55,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:05:55,447 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:05:55,447 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:55,448 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:05:55,448 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:05:55,448 INFO L87 Difference]: Start difference. First operand 3609 states and 5151 transitions. Second operand has 6 states, 6 states have (on average 100.66666666666667) internal successors, (604), 6 states have internal predecessors, (604), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:55,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:55,532 INFO L93 Difference]: Finished difference Result 7453 states and 10654 transitions. [2024-12-02 06:05:55,533 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:05:55,533 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 100.66666666666667) internal successors, (604), 6 states have internal predecessors, (604), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 763 [2024-12-02 06:05:55,533 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:55,536 INFO L225 Difference]: With dead ends: 7453 [2024-12-02 06:05:55,536 INFO L226 Difference]: Without dead ends: 5163 [2024-12-02 06:05:55,539 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:05:55,539 INFO L435 NwaCegarLoop]: 1083 mSDtfsCounter, 292 mSDsluCounter, 4317 mSDsCounter, 0 mSdLazyCounter, 55 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 292 SdHoareTripleChecker+Valid, 5400 SdHoareTripleChecker+Invalid, 55 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 55 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:55,539 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [292 Valid, 5400 Invalid, 55 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 55 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:05:55,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5163 states. [2024-12-02 06:05:55,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5163 to 5159. [2024-12-02 06:05:55,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5159 states, 5127 states have (on average 1.4322215720694362) internal successors, (7343), 5127 states have internal predecessors, (7343), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-12-02 06:05:55,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5159 states to 5159 states and 7403 transitions. [2024-12-02 06:05:55,602 INFO L78 Accepts]: Start accepts. Automaton has 5159 states and 7403 transitions. Word has length 763 [2024-12-02 06:05:55,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:55,602 INFO L471 AbstractCegarLoop]: Abstraction has 5159 states and 7403 transitions. [2024-12-02 06:05:55,602 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 100.66666666666667) internal successors, (604), 6 states have internal predecessors, (604), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:55,602 INFO L276 IsEmpty]: Start isEmpty. Operand 5159 states and 7403 transitions. [2024-12-02 06:05:55,607 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 765 [2024-12-02 06:05:55,607 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:55,607 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:55,607 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable58 [2024-12-02 06:05:55,607 INFO L396 AbstractCegarLoop]: === Iteration 60 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:55,608 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:55,608 INFO L85 PathProgramCache]: Analyzing trace with hash 1993213138, now seen corresponding path program 1 times [2024-12-02 06:05:55,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:55,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972704805] [2024-12-02 06:05:55,608 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:55,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:57,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:58,610 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:05:58,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:58,610 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972704805] [2024-12-02 06:05:58,610 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972704805] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:05:58,610 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:05:58,610 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:05:58,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [536633803] [2024-12-02 06:05:58,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:05:58,611 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:05:58,611 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:58,612 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:05:58,612 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:05:58,612 INFO L87 Difference]: Start difference. First operand 5159 states and 7403 transitions. Second operand has 6 states, 6 states have (on average 100.83333333333333) internal successors, (605), 6 states have internal predecessors, (605), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:59,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:59,262 INFO L93 Difference]: Finished difference Result 8817 states and 12591 transitions. [2024-12-02 06:05:59,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:05:59,263 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 100.83333333333333) internal successors, (605), 6 states have internal predecessors, (605), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 764 [2024-12-02 06:05:59,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:59,266 INFO L225 Difference]: With dead ends: 8817 [2024-12-02 06:05:59,267 INFO L226 Difference]: Without dead ends: 5549 [2024-12-02 06:05:59,270 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:05:59,270 INFO L435 NwaCegarLoop]: 804 mSDtfsCounter, 1039 mSDsluCounter, 2391 mSDsCounter, 0 mSdLazyCounter, 1156 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1044 SdHoareTripleChecker+Valid, 3195 SdHoareTripleChecker+Invalid, 1157 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1156 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:59,270 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1044 Valid, 3195 Invalid, 1157 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1156 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-12-02 06:05:59,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5549 states. [2024-12-02 06:05:59,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5549 to 5545. [2024-12-02 06:05:59,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5545 states, 5513 states have (on average 1.4280790857972065) internal successors, (7873), 5513 states have internal predecessors, (7873), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-12-02 06:05:59,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5545 states to 5545 states and 7933 transitions. [2024-12-02 06:05:59,341 INFO L78 Accepts]: Start accepts. Automaton has 5545 states and 7933 transitions. Word has length 764 [2024-12-02 06:05:59,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:59,341 INFO L471 AbstractCegarLoop]: Abstraction has 5545 states and 7933 transitions. [2024-12-02 06:05:59,341 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 100.83333333333333) internal successors, (605), 6 states have internal predecessors, (605), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:05:59,341 INFO L276 IsEmpty]: Start isEmpty. Operand 5545 states and 7933 transitions. [2024-12-02 06:05:59,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 766 [2024-12-02 06:05:59,346 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:59,347 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:59,347 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable59 [2024-12-02 06:05:59,347 INFO L396 AbstractCegarLoop]: === Iteration 61 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:59,347 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:59,347 INFO L85 PathProgramCache]: Analyzing trace with hash -212438930, now seen corresponding path program 1 times [2024-12-02 06:05:59,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:59,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560633435] [2024-12-02 06:05:59,348 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:59,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:06:01,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:06:02,514 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:06:02,514 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:06:02,514 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [560633435] [2024-12-02 06:06:02,514 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [560633435] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:06:02,515 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:06:02,515 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:06:02,515 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2129587202] [2024-12-02 06:06:02,515 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:06:02,516 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:06:02,516 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:06:02,516 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:06:02,516 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:06:02,517 INFO L87 Difference]: Start difference. First operand 5545 states and 7933 transitions. Second operand has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:03,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:06:03,153 INFO L93 Difference]: Finished difference Result 9203 states and 13119 transitions. [2024-12-02 06:06:03,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:06:03,153 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 765 [2024-12-02 06:06:03,153 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:06:03,157 INFO L225 Difference]: With dead ends: 9203 [2024-12-02 06:06:03,157 INFO L226 Difference]: Without dead ends: 5549 [2024-12-02 06:06:03,160 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:06:03,160 INFO L435 NwaCegarLoop]: 804 mSDtfsCounter, 897 mSDsluCounter, 2391 mSDsCounter, 0 mSdLazyCounter, 1156 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 897 SdHoareTripleChecker+Valid, 3195 SdHoareTripleChecker+Invalid, 1156 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1156 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-12-02 06:06:03,160 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [897 Valid, 3195 Invalid, 1156 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1156 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-12-02 06:06:03,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5549 states. [2024-12-02 06:06:03,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5549 to 5547. [2024-12-02 06:06:03,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5547 states, 5515 states have (on average 1.42792384406165) internal successors, (7875), 5515 states have internal predecessors, (7875), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-12-02 06:06:03,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5547 states to 5547 states and 7935 transitions. [2024-12-02 06:06:03,232 INFO L78 Accepts]: Start accepts. Automaton has 5547 states and 7935 transitions. Word has length 765 [2024-12-02 06:06:03,232 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:06:03,232 INFO L471 AbstractCegarLoop]: Abstraction has 5547 states and 7935 transitions. [2024-12-02 06:06:03,232 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:03,233 INFO L276 IsEmpty]: Start isEmpty. Operand 5547 states and 7935 transitions. [2024-12-02 06:06:03,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 766 [2024-12-02 06:06:03,238 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:06:03,238 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:06:03,238 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable60 [2024-12-02 06:06:03,238 INFO L396 AbstractCegarLoop]: === Iteration 62 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:06:03,239 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:06:03,239 INFO L85 PathProgramCache]: Analyzing trace with hash 1488522947, now seen corresponding path program 1 times [2024-12-02 06:06:03,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:06:03,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37545356] [2024-12-02 06:06:03,239 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:06:03,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:06:05,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:06:06,583 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:06:06,583 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:06:06,583 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37545356] [2024-12-02 06:06:06,583 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [37545356] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:06:06,583 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:06:06,583 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:06:06,583 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695762618] [2024-12-02 06:06:06,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:06:06,583 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:06:06,583 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:06:06,584 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:06:06,584 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:06:06,584 INFO L87 Difference]: Start difference. First operand 5547 states and 7935 transitions. Second operand has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:07,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:06:07,190 INFO L93 Difference]: Finished difference Result 9203 states and 13117 transitions. [2024-12-02 06:06:07,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:06:07,191 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 765 [2024-12-02 06:06:07,191 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:06:07,196 INFO L225 Difference]: With dead ends: 9203 [2024-12-02 06:06:07,196 INFO L226 Difference]: Without dead ends: 5547 [2024-12-02 06:06:07,200 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:06:07,200 INFO L435 NwaCegarLoop]: 804 mSDtfsCounter, 689 mSDsluCounter, 2249 mSDsCounter, 0 mSdLazyCounter, 1094 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 689 SdHoareTripleChecker+Valid, 3053 SdHoareTripleChecker+Invalid, 1097 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1094 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:06:07,200 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [689 Valid, 3053 Invalid, 1097 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1094 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-12-02 06:06:07,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5547 states. [2024-12-02 06:06:07,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5547 to 5159. [2024-12-02 06:06:07,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5159 states, 5127 states have (on average 1.4314413887263506) internal successors, (7339), 5127 states have internal predecessors, (7339), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-12-02 06:06:07,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5159 states to 5159 states and 7399 transitions. [2024-12-02 06:06:07,281 INFO L78 Accepts]: Start accepts. Automaton has 5159 states and 7399 transitions. Word has length 765 [2024-12-02 06:06:07,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:06:07,281 INFO L471 AbstractCegarLoop]: Abstraction has 5159 states and 7399 transitions. [2024-12-02 06:06:07,282 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:07,282 INFO L276 IsEmpty]: Start isEmpty. Operand 5159 states and 7399 transitions. [2024-12-02 06:06:07,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 767 [2024-12-02 06:06:07,288 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:06:07,288 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:06:07,288 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable61 [2024-12-02 06:06:07,288 INFO L396 AbstractCegarLoop]: === Iteration 63 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:06:07,288 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:06:07,289 INFO L85 PathProgramCache]: Analyzing trace with hash -896827729, now seen corresponding path program 1 times [2024-12-02 06:06:07,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:06:07,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129690679] [2024-12-02 06:06:07,289 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:06:07,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:06:09,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:06:10,767 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:06:10,767 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:06:10,767 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1129690679] [2024-12-02 06:06:10,767 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1129690679] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:06:10,767 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:06:10,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:06:10,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [158856691] [2024-12-02 06:06:10,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:06:10,768 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:06:10,768 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:06:10,768 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:06:10,768 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:06:10,768 INFO L87 Difference]: Start difference. First operand 5159 states and 7399 transitions. Second operand has 7 states, 7 states have (on average 86.71428571428571) internal successors, (607), 7 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:11,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:06:11,880 INFO L93 Difference]: Finished difference Result 9198 states and 13104 transitions. [2024-12-02 06:06:11,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:06:11,880 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 86.71428571428571) internal successors, (607), 7 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 766 [2024-12-02 06:06:11,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:06:11,885 INFO L225 Difference]: With dead ends: 9198 [2024-12-02 06:06:11,885 INFO L226 Difference]: Without dead ends: 5930 [2024-12-02 06:06:11,887 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:06:11,887 INFO L435 NwaCegarLoop]: 1399 mSDtfsCounter, 1429 mSDsluCounter, 4787 mSDsCounter, 0 mSdLazyCounter, 2113 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1429 SdHoareTripleChecker+Valid, 6186 SdHoareTripleChecker+Invalid, 2116 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 2113 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:06:11,888 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1429 Valid, 6186 Invalid, 2116 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 2113 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-12-02 06:06:11,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5930 states. [2024-12-02 06:06:11,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5930 to 4595. [2024-12-02 06:06:11,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4595 states, 4573 states have (on average 1.4358189372403236) internal successors, (6566), 4573 states have internal predecessors, (6566), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:06:11,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4595 states to 4595 states and 6606 transitions. [2024-12-02 06:06:11,975 INFO L78 Accepts]: Start accepts. Automaton has 4595 states and 6606 transitions. Word has length 766 [2024-12-02 06:06:11,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:06:11,976 INFO L471 AbstractCegarLoop]: Abstraction has 4595 states and 6606 transitions. [2024-12-02 06:06:11,976 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 86.71428571428571) internal successors, (607), 7 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:11,976 INFO L276 IsEmpty]: Start isEmpty. Operand 4595 states and 6606 transitions. [2024-12-02 06:06:11,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 768 [2024-12-02 06:06:11,981 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:06:11,981 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:06:11,981 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable62 [2024-12-02 06:06:11,981 INFO L396 AbstractCegarLoop]: === Iteration 64 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:06:11,981 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:06:11,982 INFO L85 PathProgramCache]: Analyzing trace with hash -1085093831, now seen corresponding path program 1 times [2024-12-02 06:06:11,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:06:11,982 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156884727] [2024-12-02 06:06:11,982 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:06:11,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:06:14,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:06:17,541 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 183 proven. 4 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:06:17,541 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:06:17,541 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156884727] [2024-12-02 06:06:17,541 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1156884727] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:06:17,541 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2033298756] [2024-12-02 06:06:17,541 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:06:17,541 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:06:17,542 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:06:17,543 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:06:17,544 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2024-12-02 06:06:21,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:06:21,196 INFO L256 TraceCheckSpWp]: Trace formula consists of 3704 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 06:06:21,202 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:06:21,245 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 87 proven. 0 refuted. 0 times theorem prover too weak. 776 trivial. 0 not checked. [2024-12-02 06:06:21,245 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:06:21,245 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2033298756] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:06:21,245 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:06:21,245 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [9] total 13 [2024-12-02 06:06:21,245 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [932931332] [2024-12-02 06:06:21,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:06:21,246 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:06:21,246 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:06:21,246 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:06:21,246 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=130, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:06:21,247 INFO L87 Difference]: Start difference. First operand 4595 states and 6606 transitions. Second operand has 6 states, 5 states have (on average 90.8) internal successors, (454), 6 states have internal predecessors, (454), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) [2024-12-02 06:06:21,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:06:21,330 INFO L93 Difference]: Finished difference Result 8959 states and 12887 transitions. [2024-12-02 06:06:21,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:06:21,331 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 90.8) internal successors, (454), 6 states have internal predecessors, (454), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) Word has length 767 [2024-12-02 06:06:21,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:06:21,336 INFO L225 Difference]: With dead ends: 8959 [2024-12-02 06:06:21,336 INFO L226 Difference]: Without dead ends: 4595 [2024-12-02 06:06:21,340 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 775 GetRequests, 764 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=26, Invalid=130, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:06:21,341 INFO L435 NwaCegarLoop]: 1077 mSDtfsCounter, 0 mSDsluCounter, 4289 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5366 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:06:21,341 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5366 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:06:21,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4595 states. [2024-12-02 06:06:21,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4595 to 4595. [2024-12-02 06:06:21,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4595 states, 4573 states have (on average 1.4349442379182156) internal successors, (6562), 4573 states have internal predecessors, (6562), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:06:21,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4595 states to 4595 states and 6602 transitions. [2024-12-02 06:06:21,441 INFO L78 Accepts]: Start accepts. Automaton has 4595 states and 6602 transitions. Word has length 767 [2024-12-02 06:06:21,441 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:06:21,441 INFO L471 AbstractCegarLoop]: Abstraction has 4595 states and 6602 transitions. [2024-12-02 06:06:21,441 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 90.8) internal successors, (454), 6 states have internal predecessors, (454), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) [2024-12-02 06:06:21,441 INFO L276 IsEmpty]: Start isEmpty. Operand 4595 states and 6602 transitions. [2024-12-02 06:06:21,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 770 [2024-12-02 06:06:21,449 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:06:21,450 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:06:21,481 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Forceful destruction successful, exit code 0 [2024-12-02 06:06:21,650 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 32 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable63 [2024-12-02 06:06:21,650 INFO L396 AbstractCegarLoop]: === Iteration 65 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:06:21,650 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:06:21,651 INFO L85 PathProgramCache]: Analyzing trace with hash -273292665, now seen corresponding path program 1 times [2024-12-02 06:06:21,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:06:21,651 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [506653448] [2024-12-02 06:06:21,651 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:06:21,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:06:23,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:06:25,272 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 188 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:06:25,273 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:06:25,273 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [506653448] [2024-12-02 06:06:25,273 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [506653448] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:06:25,273 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:06:25,273 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:06:25,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [276188830] [2024-12-02 06:06:25,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:06:25,274 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:06:25,274 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:06:25,275 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:06:25,275 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:06:25,275 INFO L87 Difference]: Start difference. First operand 4595 states and 6602 transitions. Second operand has 8 states, 8 states have (on average 76.25) internal successors, (610), 8 states have internal predecessors, (610), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:06:26,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:06:26,012 INFO L93 Difference]: Finished difference Result 12673 states and 18262 transitions. [2024-12-02 06:06:26,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:06:26,012 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 76.25) internal successors, (610), 8 states have internal predecessors, (610), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 769 [2024-12-02 06:06:26,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:06:26,017 INFO L225 Difference]: With dead ends: 12673 [2024-12-02 06:06:26,017 INFO L226 Difference]: Without dead ends: 6333 [2024-12-02 06:06:26,021 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:06:26,022 INFO L435 NwaCegarLoop]: 1016 mSDtfsCounter, 1633 mSDsluCounter, 4614 mSDsCounter, 0 mSdLazyCounter, 1124 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1637 SdHoareTripleChecker+Valid, 5630 SdHoareTripleChecker+Invalid, 1125 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1124 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-12-02 06:06:26,022 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1637 Valid, 5630 Invalid, 1125 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1124 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-12-02 06:06:26,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6333 states. [2024-12-02 06:06:26,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6333 to 5321. [2024-12-02 06:06:26,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5321 states, 5291 states have (on average 1.433944433944434) internal successors, (7587), 5291 states have internal predecessors, (7587), 28 states have call successors, (28), 1 states have call predecessors, (28), 1 states have return successors, (28), 28 states have call predecessors, (28), 28 states have call successors, (28) [2024-12-02 06:06:26,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5321 states to 5321 states and 7643 transitions. [2024-12-02 06:06:26,092 INFO L78 Accepts]: Start accepts. Automaton has 5321 states and 7643 transitions. Word has length 769 [2024-12-02 06:06:26,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:06:26,092 INFO L471 AbstractCegarLoop]: Abstraction has 5321 states and 7643 transitions. [2024-12-02 06:06:26,092 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 76.25) internal successors, (610), 8 states have internal predecessors, (610), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:06:26,092 INFO L276 IsEmpty]: Start isEmpty. Operand 5321 states and 7643 transitions. [2024-12-02 06:06:26,101 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 771 [2024-12-02 06:06:26,101 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:06:26,101 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:06:26,102 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable64 [2024-12-02 06:06:26,102 INFO L396 AbstractCegarLoop]: === Iteration 66 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:06:26,102 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:06:26,102 INFO L85 PathProgramCache]: Analyzing trace with hash -540838156, now seen corresponding path program 1 times [2024-12-02 06:06:26,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:06:26,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902507690] [2024-12-02 06:06:26,102 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:06:26,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:06:28,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:06:30,116 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 184 proven. 4 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:06:30,116 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:06:30,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [902507690] [2024-12-02 06:06:30,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [902507690] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:06:30,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2069579989] [2024-12-02 06:06:30,116 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:06:30,116 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:06:30,116 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:06:30,118 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:06:30,118 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2024-12-02 06:06:32,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:06:32,838 INFO L256 TraceCheckSpWp]: Trace formula consists of 3711 conjuncts, 29 conjuncts are in the unsatisfiable core [2024-12-02 06:06:32,845 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:06:33,363 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 167 proven. 0 refuted. 0 times theorem prover too weak. 697 trivial. 0 not checked. [2024-12-02 06:06:33,363 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:06:33,363 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2069579989] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:06:33,363 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:06:33,363 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [8] total 15 [2024-12-02 06:06:33,364 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [781089680] [2024-12-02 06:06:33,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:06:33,364 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:06:33,364 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:06:33,365 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:06:33,365 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=167, Unknown=0, NotChecked=0, Total=210 [2024-12-02 06:06:33,365 INFO L87 Difference]: Start difference. First operand 5321 states and 7643 transitions. Second operand has 9 states, 9 states have (on average 55.77777777777778) internal successors, (502), 9 states have internal predecessors, (502), 2 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2024-12-02 06:06:34,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:06:34,341 INFO L93 Difference]: Finished difference Result 9479 states and 13618 transitions. [2024-12-02 06:06:34,341 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:06:34,341 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 55.77777777777778) internal successors, (502), 9 states have internal predecessors, (502), 2 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) Word has length 770 [2024-12-02 06:06:34,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:06:34,345 INFO L225 Difference]: With dead ends: 9479 [2024-12-02 06:06:34,345 INFO L226 Difference]: Without dead ends: 4627 [2024-12-02 06:06:34,347 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 782 GetRequests, 766 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=245, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:06:34,348 INFO L435 NwaCegarLoop]: 786 mSDtfsCounter, 962 mSDsluCounter, 4685 mSDsCounter, 0 mSdLazyCounter, 2097 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 963 SdHoareTripleChecker+Valid, 5471 SdHoareTripleChecker+Invalid, 2100 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 2097 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-12-02 06:06:34,348 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [963 Valid, 5471 Invalid, 2100 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 2097 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-12-02 06:06:34,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4627 states. [2024-12-02 06:06:34,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4627 to 4619. [2024-12-02 06:06:34,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4619 states, 4597 states have (on average 1.4309332173156406) internal successors, (6578), 4597 states have internal predecessors, (6578), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:06:34,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4619 states to 4619 states and 6618 transitions. [2024-12-02 06:06:34,407 INFO L78 Accepts]: Start accepts. Automaton has 4619 states and 6618 transitions. Word has length 770 [2024-12-02 06:06:34,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:06:34,407 INFO L471 AbstractCegarLoop]: Abstraction has 4619 states and 6618 transitions. [2024-12-02 06:06:34,407 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 55.77777777777778) internal successors, (502), 9 states have internal predecessors, (502), 2 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2024-12-02 06:06:34,407 INFO L276 IsEmpty]: Start isEmpty. Operand 4619 states and 6618 transitions. [2024-12-02 06:06:34,412 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 776 [2024-12-02 06:06:34,412 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:06:34,412 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:06:34,431 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Ended with exit code 0 [2024-12-02 06:06:34,612 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 33 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable65 [2024-12-02 06:06:34,613 INFO L396 AbstractCegarLoop]: === Iteration 67 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:06:34,613 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:06:34,613 INFO L85 PathProgramCache]: Analyzing trace with hash 856036729, now seen corresponding path program 1 times [2024-12-02 06:06:34,613 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:06:34,613 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [904684626] [2024-12-02 06:06:34,613 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:06:34,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:06:38,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:06:40,577 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:06:40,578 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:06:40,578 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [904684626] [2024-12-02 06:06:40,578 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [904684626] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:06:40,578 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:06:40,578 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:06:40,578 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1209689807] [2024-12-02 06:06:40,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:06:40,579 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:06:40,579 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:06:40,579 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:06:40,579 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:06:40,579 INFO L87 Difference]: Start difference. First operand 4619 states and 6618 transitions. Second operand has 7 states, 7 states have (on average 88.0) internal successors, (616), 7 states have internal predecessors, (616), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:40,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:06:40,779 INFO L93 Difference]: Finished difference Result 7355 states and 10501 transitions. [2024-12-02 06:06:40,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:06:40,780 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 88.0) internal successors, (616), 7 states have internal predecessors, (616), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 775 [2024-12-02 06:06:40,780 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:06:40,783 INFO L225 Difference]: With dead ends: 7355 [2024-12-02 06:06:40,783 INFO L226 Difference]: Without dead ends: 4639 [2024-12-02 06:06:40,785 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:06:40,785 INFO L435 NwaCegarLoop]: 1037 mSDtfsCounter, 805 mSDsluCounter, 4127 mSDsCounter, 0 mSdLazyCounter, 247 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 805 SdHoareTripleChecker+Valid, 5164 SdHoareTripleChecker+Invalid, 248 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 247 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:06:40,786 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [805 Valid, 5164 Invalid, 248 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 247 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:06:40,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4639 states. [2024-12-02 06:06:40,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4639 to 4639. [2024-12-02 06:06:40,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4639 states, 4617 states have (on average 1.4290664933939787) internal successors, (6598), 4617 states have internal predecessors, (6598), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:06:40,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4639 states to 4639 states and 6638 transitions. [2024-12-02 06:06:40,844 INFO L78 Accepts]: Start accepts. Automaton has 4639 states and 6638 transitions. Word has length 775 [2024-12-02 06:06:40,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:06:40,844 INFO L471 AbstractCegarLoop]: Abstraction has 4639 states and 6638 transitions. [2024-12-02 06:06:40,844 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 88.0) internal successors, (616), 7 states have internal predecessors, (616), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:40,845 INFO L276 IsEmpty]: Start isEmpty. Operand 4639 states and 6638 transitions. [2024-12-02 06:06:40,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 777 [2024-12-02 06:06:40,852 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:06:40,853 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:06:40,853 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable66 [2024-12-02 06:06:40,853 INFO L396 AbstractCegarLoop]: === Iteration 68 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:06:40,853 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:06:40,854 INFO L85 PathProgramCache]: Analyzing trace with hash -1439769918, now seen corresponding path program 1 times [2024-12-02 06:06:40,854 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:06:40,854 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [845925095] [2024-12-02 06:06:40,854 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:06:40,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:06:44,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:06:46,043 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:06:46,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:06:46,043 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [845925095] [2024-12-02 06:06:46,043 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [845925095] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:06:46,043 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:06:46,043 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:06:46,043 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [604388861] [2024-12-02 06:06:46,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:06:46,043 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:06:46,043 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:06:46,044 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:06:46,044 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:06:46,044 INFO L87 Difference]: Start difference. First operand 4639 states and 6638 transitions. Second operand has 7 states, 7 states have (on average 88.14285714285714) internal successors, (617), 7 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:46,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:06:46,281 INFO L93 Difference]: Finished difference Result 7383 states and 10529 transitions. [2024-12-02 06:06:46,281 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:06:46,281 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 88.14285714285714) internal successors, (617), 7 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 776 [2024-12-02 06:06:46,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:06:46,285 INFO L225 Difference]: With dead ends: 7383 [2024-12-02 06:06:46,285 INFO L226 Difference]: Without dead ends: 4647 [2024-12-02 06:06:46,287 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:06:46,287 INFO L435 NwaCegarLoop]: 1037 mSDtfsCounter, 806 mSDsluCounter, 4127 mSDsCounter, 0 mSdLazyCounter, 249 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 806 SdHoareTripleChecker+Valid, 5164 SdHoareTripleChecker+Invalid, 249 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 249 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:06:46,287 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [806 Valid, 5164 Invalid, 249 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 249 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:06:46,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4647 states. [2024-12-02 06:06:46,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4647 to 4643. [2024-12-02 06:06:46,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4643 states, 4621 states have (on average 1.4286950876433673) internal successors, (6602), 4621 states have internal predecessors, (6602), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:06:46,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4643 states to 4643 states and 6642 transitions. [2024-12-02 06:06:46,345 INFO L78 Accepts]: Start accepts. Automaton has 4643 states and 6642 transitions. Word has length 776 [2024-12-02 06:06:46,345 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:06:46,345 INFO L471 AbstractCegarLoop]: Abstraction has 4643 states and 6642 transitions. [2024-12-02 06:06:46,345 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 88.14285714285714) internal successors, (617), 7 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:46,345 INFO L276 IsEmpty]: Start isEmpty. Operand 4643 states and 6642 transitions. [2024-12-02 06:06:46,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 777 [2024-12-02 06:06:46,350 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:06:46,350 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:06:46,350 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable67 [2024-12-02 06:06:46,350 INFO L396 AbstractCegarLoop]: === Iteration 69 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:06:46,350 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:06:46,350 INFO L85 PathProgramCache]: Analyzing trace with hash -961437342, now seen corresponding path program 1 times [2024-12-02 06:06:46,350 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:06:46,350 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448008639] [2024-12-02 06:06:46,351 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:06:46,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:06:46,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:06:47,386 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:06:47,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:06:47,387 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [448008639] [2024-12-02 06:06:47,387 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [448008639] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:06:47,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:06:47,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:06:47,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1026162500] [2024-12-02 06:06:47,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:06:47,388 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:06:47,388 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:06:47,388 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:06:47,388 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:06:47,388 INFO L87 Difference]: Start difference. First operand 4643 states and 6642 transitions. Second operand has 5 states, 5 states have (on average 123.4) internal successors, (617), 5 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:47,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:06:47,506 INFO L93 Difference]: Finished difference Result 9982 states and 14231 transitions. [2024-12-02 06:06:47,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:06:47,506 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 123.4) internal successors, (617), 5 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 776 [2024-12-02 06:06:47,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:06:47,511 INFO L225 Difference]: With dead ends: 9982 [2024-12-02 06:06:47,511 INFO L226 Difference]: Without dead ends: 7242 [2024-12-02 06:06:47,514 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:06:47,514 INFO L435 NwaCegarLoop]: 1325 mSDtfsCounter, 605 mSDsluCounter, 3710 mSDsCounter, 0 mSdLazyCounter, 55 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 605 SdHoareTripleChecker+Valid, 5035 SdHoareTripleChecker+Invalid, 55 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 55 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:06:47,514 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [605 Valid, 5035 Invalid, 55 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 55 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:06:47,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7242 states. [2024-12-02 06:06:47,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7242 to 6775. [2024-12-02 06:06:47,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6775 states, 6743 states have (on average 1.4303722378763162) internal successors, (9645), 6743 states have internal predecessors, (9645), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-12-02 06:06:47,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6775 states to 6775 states and 9705 transitions. [2024-12-02 06:06:47,609 INFO L78 Accepts]: Start accepts. Automaton has 6775 states and 9705 transitions. Word has length 776 [2024-12-02 06:06:47,610 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:06:47,610 INFO L471 AbstractCegarLoop]: Abstraction has 6775 states and 9705 transitions. [2024-12-02 06:06:47,610 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 123.4) internal successors, (617), 5 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:47,610 INFO L276 IsEmpty]: Start isEmpty. Operand 6775 states and 9705 transitions. [2024-12-02 06:06:47,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 778 [2024-12-02 06:06:47,616 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:06:47,617 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:06:47,617 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable68 [2024-12-02 06:06:47,617 INFO L396 AbstractCegarLoop]: === Iteration 70 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:06:47,617 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:06:47,617 INFO L85 PathProgramCache]: Analyzing trace with hash 1414783750, now seen corresponding path program 1 times [2024-12-02 06:06:47,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:06:47,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764451789] [2024-12-02 06:06:47,617 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:06:47,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:06:48,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:06:49,585 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:06:49,586 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:06:49,586 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764451789] [2024-12-02 06:06:49,586 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764451789] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:06:49,586 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:06:49,586 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:06:49,586 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [311844750] [2024-12-02 06:06:49,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:06:49,586 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:06:49,586 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:06:49,587 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:06:49,587 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:06:49,587 INFO L87 Difference]: Start difference. First operand 6775 states and 9705 transitions. Second operand has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:49,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:06:49,779 INFO L93 Difference]: Finished difference Result 12150 states and 17344 transitions. [2024-12-02 06:06:49,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:06:49,780 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 777 [2024-12-02 06:06:49,780 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:06:49,786 INFO L225 Difference]: With dead ends: 12150 [2024-12-02 06:06:49,786 INFO L226 Difference]: Without dead ends: 9410 [2024-12-02 06:06:49,790 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:06:49,790 INFO L435 NwaCegarLoop]: 1556 mSDtfsCounter, 540 mSDsluCounter, 8113 mSDsCounter, 0 mSdLazyCounter, 152 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 540 SdHoareTripleChecker+Valid, 9669 SdHoareTripleChecker+Invalid, 152 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 152 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:06:49,790 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [540 Valid, 9669 Invalid, 152 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 152 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:06:49,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9410 states. [2024-12-02 06:06:49,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9410 to 9386. [2024-12-02 06:06:49,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9386 states, 9344 states have (on average 1.4281892123287672) internal successors, (13345), 9344 states have internal predecessors, (13345), 40 states have call successors, (40), 1 states have call predecessors, (40), 1 states have return successors, (40), 40 states have call predecessors, (40), 40 states have call successors, (40) [2024-12-02 06:06:49,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9386 states to 9386 states and 13425 transitions. [2024-12-02 06:06:49,916 INFO L78 Accepts]: Start accepts. Automaton has 9386 states and 13425 transitions. Word has length 777 [2024-12-02 06:06:49,916 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:06:49,916 INFO L471 AbstractCegarLoop]: Abstraction has 9386 states and 13425 transitions. [2024-12-02 06:06:49,916 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:49,916 INFO L276 IsEmpty]: Start isEmpty. Operand 9386 states and 13425 transitions. [2024-12-02 06:06:49,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 778 [2024-12-02 06:06:49,923 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:06:49,924 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:06:49,924 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable69 [2024-12-02 06:06:49,924 INFO L396 AbstractCegarLoop]: === Iteration 71 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:06:49,924 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:06:49,925 INFO L85 PathProgramCache]: Analyzing trace with hash -722585695, now seen corresponding path program 1 times [2024-12-02 06:06:49,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:06:49,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636671202] [2024-12-02 06:06:49,925 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:06:49,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:06:51,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:06:53,157 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:06:53,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:06:53,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636671202] [2024-12-02 06:06:53,157 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1636671202] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:06:53,157 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:06:53,157 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:06:53,157 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1049138996] [2024-12-02 06:06:53,157 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:06:53,158 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:06:53,158 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:06:53,158 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:06:53,158 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:06:53,158 INFO L87 Difference]: Start difference. First operand 9386 states and 13425 transitions. Second operand has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:53,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:06:53,350 INFO L93 Difference]: Finished difference Result 13791 states and 19709 transitions. [2024-12-02 06:06:53,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:06:53,350 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 777 [2024-12-02 06:06:53,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:06:53,361 INFO L225 Difference]: With dead ends: 13791 [2024-12-02 06:06:53,361 INFO L226 Difference]: Without dead ends: 10905 [2024-12-02 06:06:53,365 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:06:53,366 INFO L435 NwaCegarLoop]: 1455 mSDtfsCounter, 739 mSDsluCounter, 6117 mSDsCounter, 0 mSdLazyCounter, 95 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 739 SdHoareTripleChecker+Valid, 7572 SdHoareTripleChecker+Invalid, 96 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 95 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:06:53,366 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [739 Valid, 7572 Invalid, 96 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 95 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:06:53,371 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10905 states. [2024-12-02 06:06:53,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10905 to 10747. [2024-12-02 06:06:53,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10747 states, 10705 states have (on average 1.43176085941149) internal successors, (15327), 10705 states have internal predecessors, (15327), 40 states have call successors, (40), 1 states have call predecessors, (40), 1 states have return successors, (40), 40 states have call predecessors, (40), 40 states have call successors, (40) [2024-12-02 06:06:53,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10747 states to 10747 states and 15407 transitions. [2024-12-02 06:06:53,518 INFO L78 Accepts]: Start accepts. Automaton has 10747 states and 15407 transitions. Word has length 777 [2024-12-02 06:06:53,518 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:06:53,518 INFO L471 AbstractCegarLoop]: Abstraction has 10747 states and 15407 transitions. [2024-12-02 06:06:53,518 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:53,518 INFO L276 IsEmpty]: Start isEmpty. Operand 10747 states and 15407 transitions. [2024-12-02 06:06:53,554 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 778 [2024-12-02 06:06:53,554 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:06:53,554 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:06:53,555 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable70 [2024-12-02 06:06:53,555 INFO L396 AbstractCegarLoop]: === Iteration 72 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:06:53,555 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:06:53,555 INFO L85 PathProgramCache]: Analyzing trace with hash -558029514, now seen corresponding path program 1 times [2024-12-02 06:06:53,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:06:53,555 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143669453] [2024-12-02 06:06:53,555 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:06:53,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:06:53,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:06:54,560 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 88 proven. 0 refuted. 0 times theorem prover too weak. 779 trivial. 0 not checked. [2024-12-02 06:06:54,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:06:54,560 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143669453] [2024-12-02 06:06:54,561 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2143669453] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:06:54,561 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:06:54,561 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:06:54,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1609381363] [2024-12-02 06:06:54,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:06:54,561 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:06:54,561 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:06:54,562 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:06:54,562 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:06:54,562 INFO L87 Difference]: Start difference. First operand 10747 states and 15407 transitions. Second operand has 4 states, 4 states have (on average 130.0) internal successors, (520), 4 states have internal predecessors, (520), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:54,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:06:54,679 INFO L93 Difference]: Finished difference Result 16451 states and 23567 transitions. [2024-12-02 06:06:54,679 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:06:54,679 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 130.0) internal successors, (520), 4 states have internal predecessors, (520), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 777 [2024-12-02 06:06:54,679 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:06:54,687 INFO L225 Difference]: With dead ends: 16451 [2024-12-02 06:06:54,687 INFO L226 Difference]: Without dead ends: 10763 [2024-12-02 06:06:54,691 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:06:54,691 INFO L435 NwaCegarLoop]: 1079 mSDtfsCounter, 0 mSDsluCounter, 2144 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3223 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:06:54,691 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3223 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:06:54,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10763 states. [2024-12-02 06:06:54,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10763 to 10763. [2024-12-02 06:06:54,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10763 states, 10721 states have (on average 1.431116500326462) internal successors, (15343), 10721 states have internal predecessors, (15343), 40 states have call successors, (40), 1 states have call predecessors, (40), 1 states have return successors, (40), 40 states have call predecessors, (40), 40 states have call successors, (40) [2024-12-02 06:06:54,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10763 states to 10763 states and 15423 transitions. [2024-12-02 06:06:54,839 INFO L78 Accepts]: Start accepts. Automaton has 10763 states and 15423 transitions. Word has length 777 [2024-12-02 06:06:54,839 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:06:54,839 INFO L471 AbstractCegarLoop]: Abstraction has 10763 states and 15423 transitions. [2024-12-02 06:06:54,839 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 130.0) internal successors, (520), 4 states have internal predecessors, (520), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:06:54,839 INFO L276 IsEmpty]: Start isEmpty. Operand 10763 states and 15423 transitions. [2024-12-02 06:06:54,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 778 [2024-12-02 06:06:54,847 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:06:54,847 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:06:54,848 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable71 [2024-12-02 06:06:54,848 INFO L396 AbstractCegarLoop]: === Iteration 73 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:06:54,848 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:06:54,848 INFO L85 PathProgramCache]: Analyzing trace with hash -262177162, now seen corresponding path program 1 times [2024-12-02 06:06:54,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:06:54,848 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620808820] [2024-12-02 06:06:54,848 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:06:54,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:06:57,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:07:01,823 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 110 proven. 0 refuted. 0 times theorem prover too weak. 757 trivial. 0 not checked. [2024-12-02 06:07:01,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:07:01,823 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [620808820] [2024-12-02 06:07:01,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [620808820] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:07:01,823 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:07:01,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:07:01,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [117846352] [2024-12-02 06:07:01,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:07:01,824 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:07:01,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:07:01,824 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:07:01,824 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:07:01,824 INFO L87 Difference]: Start difference. First operand 10763 states and 15423 transitions. Second operand has 8 states, 8 states have (on average 67.625) internal successors, (541), 8 states have internal predecessors, (541), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:07:02,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:07:02,115 INFO L93 Difference]: Finished difference Result 18269 states and 26110 transitions. [2024-12-02 06:07:02,115 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:07:02,115 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 67.625) internal successors, (541), 8 states have internal predecessors, (541), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 777 [2024-12-02 06:07:02,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:07:02,127 INFO L225 Difference]: With dead ends: 18269 [2024-12-02 06:07:02,127 INFO L226 Difference]: Without dead ends: 12867 [2024-12-02 06:07:02,133 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:07:02,134 INFO L435 NwaCegarLoop]: 1102 mSDtfsCounter, 1306 mSDsluCounter, 5443 mSDsCounter, 0 mSdLazyCounter, 188 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1310 SdHoareTripleChecker+Valid, 6545 SdHoareTripleChecker+Invalid, 190 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 188 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:07:02,134 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1310 Valid, 6545 Invalid, 190 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 188 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:07:02,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12867 states. [2024-12-02 06:07:02,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12867 to 12643. [2024-12-02 06:07:02,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12643 states, 12569 states have (on average 1.4243774365502426) internal successors, (17903), 12569 states have internal predecessors, (17903), 72 states have call successors, (72), 1 states have call predecessors, (72), 1 states have return successors, (72), 72 states have call predecessors, (72), 72 states have call successors, (72) [2024-12-02 06:07:02,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12643 states to 12643 states and 18047 transitions. [2024-12-02 06:07:02,321 INFO L78 Accepts]: Start accepts. Automaton has 12643 states and 18047 transitions. Word has length 777 [2024-12-02 06:07:02,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:07:02,321 INFO L471 AbstractCegarLoop]: Abstraction has 12643 states and 18047 transitions. [2024-12-02 06:07:02,321 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 67.625) internal successors, (541), 8 states have internal predecessors, (541), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:07:02,321 INFO L276 IsEmpty]: Start isEmpty. Operand 12643 states and 18047 transitions. [2024-12-02 06:07:02,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 780 [2024-12-02 06:07:02,331 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:07:02,331 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:07:02,331 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable72 [2024-12-02 06:07:02,331 INFO L396 AbstractCegarLoop]: === Iteration 74 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:07:02,331 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:07:02,331 INFO L85 PathProgramCache]: Analyzing trace with hash 114641850, now seen corresponding path program 1 times [2024-12-02 06:07:02,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:07:02,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368304234] [2024-12-02 06:07:02,332 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:07:02,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:07:04,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:07:06,163 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 188 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:07:06,163 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:07:06,163 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [368304234] [2024-12-02 06:07:06,163 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [368304234] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:07:06,163 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:07:06,163 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-12-02 06:07:06,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922892845] [2024-12-02 06:07:06,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:07:06,164 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:07:06,164 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:07:06,164 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:07:06,164 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:07:06,165 INFO L87 Difference]: Start difference. First operand 12643 states and 18047 transitions. Second operand has 9 states, 9 states have (on average 68.88888888888889) internal successors, (620), 9 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:07:06,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:07:06,552 INFO L93 Difference]: Finished difference Result 18048 states and 25744 transitions. [2024-12-02 06:07:06,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:07:06,553 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 68.88888888888889) internal successors, (620), 9 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 779 [2024-12-02 06:07:06,553 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:07:06,562 INFO L225 Difference]: With dead ends: 18048 [2024-12-02 06:07:06,563 INFO L226 Difference]: Without dead ends: 14329 [2024-12-02 06:07:06,567 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:07:06,567 INFO L435 NwaCegarLoop]: 1405 mSDtfsCounter, 1197 mSDsluCounter, 7987 mSDsCounter, 0 mSdLazyCounter, 518 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1197 SdHoareTripleChecker+Valid, 9392 SdHoareTripleChecker+Invalid, 518 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 518 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:07:06,567 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1197 Valid, 9392 Invalid, 518 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 518 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:07:06,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14329 states. [2024-12-02 06:07:06,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14329 to 14007. [2024-12-02 06:07:06,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14007 states, 13933 states have (on average 1.4276178855953492) internal successors, (19891), 13933 states have internal predecessors, (19891), 72 states have call successors, (72), 1 states have call predecessors, (72), 1 states have return successors, (72), 72 states have call predecessors, (72), 72 states have call successors, (72) [2024-12-02 06:07:06,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14007 states to 14007 states and 20035 transitions. [2024-12-02 06:07:06,768 INFO L78 Accepts]: Start accepts. Automaton has 14007 states and 20035 transitions. Word has length 779 [2024-12-02 06:07:06,768 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:07:06,768 INFO L471 AbstractCegarLoop]: Abstraction has 14007 states and 20035 transitions. [2024-12-02 06:07:06,768 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 68.88888888888889) internal successors, (620), 9 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:07:06,768 INFO L276 IsEmpty]: Start isEmpty. Operand 14007 states and 20035 transitions. [2024-12-02 06:07:06,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 780 [2024-12-02 06:07:06,781 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:07:06,781 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:07:06,781 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable73 [2024-12-02 06:07:06,782 INFO L396 AbstractCegarLoop]: === Iteration 75 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:07:06,782 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:07:06,782 INFO L85 PathProgramCache]: Analyzing trace with hash 248295512, now seen corresponding path program 1 times [2024-12-02 06:07:06,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:07:06,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362525506] [2024-12-02 06:07:06,782 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:07:06,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:07:09,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:07:11,925 INFO L134 CoverageAnalysis]: Checked inductivity of 866 backedges. 190 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:07:11,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:07:11,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1362525506] [2024-12-02 06:07:11,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1362525506] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:07:11,925 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:07:11,925 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:07:11,925 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [300384643] [2024-12-02 06:07:11,925 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:07:11,926 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:07:11,926 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:07:11,926 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:07:11,926 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:07:11,926 INFO L87 Difference]: Start difference. First operand 14007 states and 20035 transitions. Second operand has 8 states, 8 states have (on average 77.5) internal successors, (620), 8 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:07:12,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:07:12,760 INFO L93 Difference]: Finished difference Result 18319 states and 26141 transitions. [2024-12-02 06:07:12,760 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:07:12,760 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 77.5) internal successors, (620), 8 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 779 [2024-12-02 06:07:12,760 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:07:12,770 INFO L225 Difference]: With dead ends: 18319 [2024-12-02 06:07:12,770 INFO L226 Difference]: Without dead ends: 14047 [2024-12-02 06:07:12,774 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=79, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:07:12,775 INFO L435 NwaCegarLoop]: 795 mSDtfsCounter, 797 mSDsluCounter, 3159 mSDsCounter, 0 mSdLazyCounter, 1457 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 797 SdHoareTripleChecker+Valid, 3954 SdHoareTripleChecker+Invalid, 1459 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 1457 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-12-02 06:07:12,775 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [797 Valid, 3954 Invalid, 1459 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 1457 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-12-02 06:07:12,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14047 states. [2024-12-02 06:07:12,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14047 to 14047. [2024-12-02 06:07:12,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14047 states, 13973 states have (on average 1.4263937593931153) internal successors, (19931), 13973 states have internal predecessors, (19931), 72 states have call successors, (72), 1 states have call predecessors, (72), 1 states have return successors, (72), 72 states have call predecessors, (72), 72 states have call successors, (72) [2024-12-02 06:07:12,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14047 states to 14047 states and 20075 transitions. [2024-12-02 06:07:12,967 INFO L78 Accepts]: Start accepts. Automaton has 14047 states and 20075 transitions. Word has length 779 [2024-12-02 06:07:12,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:07:12,967 INFO L471 AbstractCegarLoop]: Abstraction has 14047 states and 20075 transitions. [2024-12-02 06:07:12,967 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 77.5) internal successors, (620), 8 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:07:12,967 INFO L276 IsEmpty]: Start isEmpty. Operand 14047 states and 20075 transitions. [2024-12-02 06:07:12,978 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 781 [2024-12-02 06:07:12,978 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:07:12,978 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:07:12,978 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable74 [2024-12-02 06:07:12,978 INFO L396 AbstractCegarLoop]: === Iteration 76 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:07:12,978 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:07:12,979 INFO L85 PathProgramCache]: Analyzing trace with hash -58242511, now seen corresponding path program 1 times [2024-12-02 06:07:12,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:07:12,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1243446820] [2024-12-02 06:07:12,979 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:07:12,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:07:16,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:07:19,878 INFO L134 CoverageAnalysis]: Checked inductivity of 866 backedges. 109 proven. 0 refuted. 0 times theorem prover too weak. 757 trivial. 0 not checked. [2024-12-02 06:07:19,879 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:07:19,879 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1243446820] [2024-12-02 06:07:19,879 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1243446820] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:07:19,879 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:07:19,879 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:07:19,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449537140] [2024-12-02 06:07:19,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:07:19,879 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:07:19,880 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:07:19,880 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:07:19,880 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:07:19,880 INFO L87 Difference]: Start difference. First operand 14047 states and 20075 transitions. Second operand has 8 states, 8 states have (on average 68.0) internal successors, (544), 8 states have internal predecessors, (544), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:07:20,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:07:20,159 INFO L93 Difference]: Finished difference Result 23049 states and 32839 transitions. [2024-12-02 06:07:20,159 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:07:20,160 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 68.0) internal successors, (544), 8 states have internal predecessors, (544), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 780 [2024-12-02 06:07:20,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:07:20,209 INFO L225 Difference]: With dead ends: 23049 [2024-12-02 06:07:20,209 INFO L226 Difference]: Without dead ends: 16811 [2024-12-02 06:07:20,211 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:07:20,211 INFO L435 NwaCegarLoop]: 1064 mSDtfsCounter, 140 mSDsluCounter, 6358 mSDsCounter, 0 mSdLazyCounter, 141 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 140 SdHoareTripleChecker+Valid, 7422 SdHoareTripleChecker+Invalid, 141 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 141 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:07:20,212 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [140 Valid, 7422 Invalid, 141 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 141 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:07:20,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16811 states. [2024-12-02 06:07:20,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16811 to 16795. [2024-12-02 06:07:20,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16795 states, 16685 states have (on average 1.4191789032064728) internal successors, (23679), 16685 states have internal predecessors, (23679), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:07:20,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16795 states to 16795 states and 23895 transitions. [2024-12-02 06:07:20,420 INFO L78 Accepts]: Start accepts. Automaton has 16795 states and 23895 transitions. Word has length 780 [2024-12-02 06:07:20,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:07:20,420 INFO L471 AbstractCegarLoop]: Abstraction has 16795 states and 23895 transitions. [2024-12-02 06:07:20,421 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 68.0) internal successors, (544), 8 states have internal predecessors, (544), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:07:20,421 INFO L276 IsEmpty]: Start isEmpty. Operand 16795 states and 23895 transitions. [2024-12-02 06:07:20,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 781 [2024-12-02 06:07:20,433 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:07:20,433 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:07:20,433 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable75 [2024-12-02 06:07:20,433 INFO L396 AbstractCegarLoop]: === Iteration 77 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:07:20,433 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:07:20,434 INFO L85 PathProgramCache]: Analyzing trace with hash -167713359, now seen corresponding path program 1 times [2024-12-02 06:07:20,434 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:07:20,434 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1783247110] [2024-12-02 06:07:20,434 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:07:20,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:07:24,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:07:27,052 INFO L134 CoverageAnalysis]: Checked inductivity of 866 backedges. 190 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:07:27,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:07:27,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1783247110] [2024-12-02 06:07:27,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1783247110] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:07:27,053 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:07:27,053 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-12-02 06:07:27,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596948739] [2024-12-02 06:07:27,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:07:27,053 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:07:27,053 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:07:27,053 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:07:27,054 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:07:27,054 INFO L87 Difference]: Start difference. First operand 16795 states and 23895 transitions. Second operand has 9 states, 9 states have (on average 69.0) internal successors, (621), 9 states have internal predecessors, (621), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:07:28,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:07:28,481 INFO L93 Difference]: Finished difference Result 21764 states and 30912 transitions. [2024-12-02 06:07:28,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:07:28,481 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 69.0) internal successors, (621), 9 states have internal predecessors, (621), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 780 [2024-12-02 06:07:28,482 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:07:28,494 INFO L225 Difference]: With dead ends: 21764 [2024-12-02 06:07:28,494 INFO L226 Difference]: Without dead ends: 16861 [2024-12-02 06:07:28,500 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:07:28,500 INFO L435 NwaCegarLoop]: 1546 mSDtfsCounter, 603 mSDsluCounter, 6660 mSDsCounter, 0 mSdLazyCounter, 2618 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 603 SdHoareTripleChecker+Valid, 8206 SdHoareTripleChecker+Invalid, 2619 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 2618 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:07:28,500 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [603 Valid, 8206 Invalid, 2619 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 2618 Invalid, 0 Unknown, 0 Unchecked, 1.2s Time] [2024-12-02 06:07:28,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16861 states. [2024-12-02 06:07:28,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16861 to 16827. [2024-12-02 06:07:28,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16827 states, 16717 states have (on average 1.419094335107974) internal successors, (23723), 16717 states have internal predecessors, (23723), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:07:28,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16827 states to 16827 states and 23939 transitions. [2024-12-02 06:07:28,721 INFO L78 Accepts]: Start accepts. Automaton has 16827 states and 23939 transitions. Word has length 780 [2024-12-02 06:07:28,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:07:28,721 INFO L471 AbstractCegarLoop]: Abstraction has 16827 states and 23939 transitions. [2024-12-02 06:07:28,721 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 69.0) internal successors, (621), 9 states have internal predecessors, (621), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:07:28,722 INFO L276 IsEmpty]: Start isEmpty. Operand 16827 states and 23939 transitions. [2024-12-02 06:07:28,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 781 [2024-12-02 06:07:28,733 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:07:28,734 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:07:28,734 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable76 [2024-12-02 06:07:28,734 INFO L396 AbstractCegarLoop]: === Iteration 78 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:07:28,734 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:07:28,734 INFO L85 PathProgramCache]: Analyzing trace with hash -320502005, now seen corresponding path program 1 times [2024-12-02 06:07:28,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:07:28,735 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020446095] [2024-12-02 06:07:28,735 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:07:28,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:07:33,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:07:36,201 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 192 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:07:36,201 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:07:36,201 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1020446095] [2024-12-02 06:07:36,201 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1020446095] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:07:36,201 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:07:36,202 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2024-12-02 06:07:36,202 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366426505] [2024-12-02 06:07:36,202 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:07:36,202 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2024-12-02 06:07:36,202 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:07:36,203 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2024-12-02 06:07:36,203 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:07:36,203 INFO L87 Difference]: Start difference. First operand 16827 states and 23939 transitions. Second operand has 12 states, 12 states have (on average 51.75) internal successors, (621), 12 states have internal predecessors, (621), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:07:37,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:07:37,494 INFO L93 Difference]: Finished difference Result 21978 states and 31192 transitions. [2024-12-02 06:07:37,494 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2024-12-02 06:07:37,494 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 51.75) internal successors, (621), 12 states have internal predecessors, (621), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 780 [2024-12-02 06:07:37,494 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:07:37,506 INFO L225 Difference]: With dead ends: 21978 [2024-12-02 06:07:37,506 INFO L226 Difference]: Without dead ends: 16875 [2024-12-02 06:07:37,511 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=163, Unknown=0, NotChecked=0, Total=210 [2024-12-02 06:07:37,511 INFO L435 NwaCegarLoop]: 791 mSDtfsCounter, 1675 mSDsluCounter, 6252 mSDsCounter, 0 mSdLazyCounter, 2664 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1676 SdHoareTripleChecker+Valid, 7043 SdHoareTripleChecker+Invalid, 2667 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 2664 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:07:37,511 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1676 Valid, 7043 Invalid, 2667 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 2664 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-12-02 06:07:37,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16875 states. [2024-12-02 06:07:37,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16875 to 16875. [2024-12-02 06:07:37,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16875 states, 16765 states have (on average 1.4178944229048613) internal successors, (23771), 16765 states have internal predecessors, (23771), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:07:37,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16875 states to 16875 states and 23987 transitions. [2024-12-02 06:07:37,729 INFO L78 Accepts]: Start accepts. Automaton has 16875 states and 23987 transitions. Word has length 780 [2024-12-02 06:07:37,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:07:37,729 INFO L471 AbstractCegarLoop]: Abstraction has 16875 states and 23987 transitions. [2024-12-02 06:07:37,729 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 51.75) internal successors, (621), 12 states have internal predecessors, (621), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:07:37,729 INFO L276 IsEmpty]: Start isEmpty. Operand 16875 states and 23987 transitions. [2024-12-02 06:07:37,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 782 [2024-12-02 06:07:37,741 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:07:37,741 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:07:37,741 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable77 [2024-12-02 06:07:37,742 INFO L396 AbstractCegarLoop]: === Iteration 79 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:07:37,742 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:07:37,742 INFO L85 PathProgramCache]: Analyzing trace with hash -575460998, now seen corresponding path program 1 times [2024-12-02 06:07:37,742 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:07:37,742 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1501503670] [2024-12-02 06:07:37,742 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:07:37,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:07:42,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:07:43,847 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 12 proven. 27 refuted. 0 times theorem prover too weak. 829 trivial. 0 not checked. [2024-12-02 06:07:43,847 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:07:43,847 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1501503670] [2024-12-02 06:07:43,847 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1501503670] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:07:43,847 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1479776137] [2024-12-02 06:07:43,847 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:07:43,847 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:07:43,847 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:07:43,849 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:07:43,849 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2024-12-02 06:07:49,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:07:49,463 INFO L256 TraceCheckSpWp]: Trace formula consists of 3736 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 06:07:49,469 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:07:49,496 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 232 proven. 0 refuted. 0 times theorem prover too weak. 636 trivial. 0 not checked. [2024-12-02 06:07:49,496 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:07:49,496 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1479776137] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:07:49,496 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:07:49,496 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 9 [2024-12-02 06:07:49,497 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [849244014] [2024-12-02 06:07:49,497 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:07:49,497 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:07:49,497 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:07:49,498 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:07:49,498 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:07:49,498 INFO L87 Difference]: Start difference. First operand 16875 states and 23987 transitions. Second operand has 6 states, 5 states have (on average 117.2) internal successors, (586), 6 states have internal predecessors, (586), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) [2024-12-02 06:07:49,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:07:49,710 INFO L93 Difference]: Finished difference Result 32042 states and 45566 transitions. [2024-12-02 06:07:49,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:07:49,711 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 117.2) internal successors, (586), 6 states have internal predecessors, (586), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) Word has length 781 [2024-12-02 06:07:49,711 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:07:49,722 INFO L225 Difference]: With dead ends: 32042 [2024-12-02 06:07:49,723 INFO L226 Difference]: Without dead ends: 16875 [2024-12-02 06:07:49,731 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 786 GetRequests, 779 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:07:49,731 INFO L435 NwaCegarLoop]: 1074 mSDtfsCounter, 0 mSDsluCounter, 4277 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5351 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:07:49,731 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5351 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:07:49,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16875 states. [2024-12-02 06:07:49,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16875 to 16875. [2024-12-02 06:07:49,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16875 states, 16765 states have (on average 1.4164628690724723) internal successors, (23747), 16765 states have internal predecessors, (23747), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:07:49,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16875 states to 16875 states and 23963 transitions. [2024-12-02 06:07:49,996 INFO L78 Accepts]: Start accepts. Automaton has 16875 states and 23963 transitions. Word has length 781 [2024-12-02 06:07:49,996 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:07:49,996 INFO L471 AbstractCegarLoop]: Abstraction has 16875 states and 23963 transitions. [2024-12-02 06:07:49,996 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 117.2) internal successors, (586), 6 states have internal predecessors, (586), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) [2024-12-02 06:07:49,996 INFO L276 IsEmpty]: Start isEmpty. Operand 16875 states and 23963 transitions. [2024-12-02 06:07:50,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 784 [2024-12-02 06:07:50,008 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:07:50,008 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:07:50,032 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Ended with exit code 0 [2024-12-02 06:07:50,209 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 34 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable78 [2024-12-02 06:07:50,209 INFO L396 AbstractCegarLoop]: === Iteration 80 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:07:50,209 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:07:50,209 INFO L85 PathProgramCache]: Analyzing trace with hash 818835622, now seen corresponding path program 1 times [2024-12-02 06:07:50,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:07:50,209 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562684982] [2024-12-02 06:07:50,209 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:07:50,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:07:55,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:07:56,631 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 12 proven. 27 refuted. 0 times theorem prover too weak. 830 trivial. 0 not checked. [2024-12-02 06:07:56,631 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:07:56,632 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [562684982] [2024-12-02 06:07:56,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [562684982] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:07:56,632 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2017114783] [2024-12-02 06:07:56,632 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:07:56,632 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:07:56,632 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:07:56,633 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:07:56,634 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2024-12-02 06:08:00,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:08:00,443 INFO L256 TraceCheckSpWp]: Trace formula consists of 3742 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 06:08:00,448 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:08:00,466 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 48 proven. 0 refuted. 0 times theorem prover too weak. 821 trivial. 0 not checked. [2024-12-02 06:08:00,466 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:08:00,466 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2017114783] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:08:00,466 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:08:00,467 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 7 [2024-12-02 06:08:00,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [464883209] [2024-12-02 06:08:00,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:08:00,467 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:08:00,467 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:08:00,467 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:08:00,467 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:08:00,467 INFO L87 Difference]: Start difference. First operand 16875 states and 23963 transitions. Second operand has 6 states, 5 states have (on average 90.8) internal successors, (454), 6 states have internal predecessors, (454), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 1 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:08:00,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:08:00,666 INFO L93 Difference]: Finished difference Result 32262 states and 45830 transitions. [2024-12-02 06:08:00,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:08:00,666 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 90.8) internal successors, (454), 6 states have internal predecessors, (454), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 1 states have call predecessors, (6), 2 states have call successors, (6) Word has length 783 [2024-12-02 06:08:00,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:08:00,679 INFO L225 Difference]: With dead ends: 32262 [2024-12-02 06:08:00,679 INFO L226 Difference]: Without dead ends: 16875 [2024-12-02 06:08:00,688 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 788 GetRequests, 783 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:08:00,689 INFO L435 NwaCegarLoop]: 1075 mSDtfsCounter, 0 mSDsluCounter, 4277 mSDsCounter, 0 mSdLazyCounter, 53 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5352 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 53 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:08:00,689 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5352 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 53 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:08:00,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16875 states. [2024-12-02 06:08:00,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16875 to 16875. [2024-12-02 06:08:00,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16875 states, 16765 states have (on average 1.415985684461676) internal successors, (23739), 16765 states have internal predecessors, (23739), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:08:00,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16875 states to 16875 states and 23955 transitions. [2024-12-02 06:08:00,908 INFO L78 Accepts]: Start accepts. Automaton has 16875 states and 23955 transitions. Word has length 783 [2024-12-02 06:08:00,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:08:00,908 INFO L471 AbstractCegarLoop]: Abstraction has 16875 states and 23955 transitions. [2024-12-02 06:08:00,908 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 90.8) internal successors, (454), 6 states have internal predecessors, (454), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 1 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:08:00,909 INFO L276 IsEmpty]: Start isEmpty. Operand 16875 states and 23955 transitions. [2024-12-02 06:08:00,920 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 786 [2024-12-02 06:08:00,920 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:08:00,921 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:08:00,943 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Ended with exit code 0 [2024-12-02 06:08:01,121 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 35 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable79 [2024-12-02 06:08:01,121 INFO L396 AbstractCegarLoop]: === Iteration 81 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:08:01,121 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:08:01,122 INFO L85 PathProgramCache]: Analyzing trace with hash -534796464, now seen corresponding path program 1 times [2024-12-02 06:08:01,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:08:01,122 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834573488] [2024-12-02 06:08:01,122 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:08:01,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:08:04,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:08:06,079 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 87 proven. 0 refuted. 0 times theorem prover too weak. 781 trivial. 0 not checked. [2024-12-02 06:08:06,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:08:06,079 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834573488] [2024-12-02 06:08:06,079 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1834573488] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:08:06,079 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:08:06,079 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:08:06,079 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1158618784] [2024-12-02 06:08:06,079 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:08:06,080 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:08:06,080 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:08:06,081 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:08:06,081 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:08:06,081 INFO L87 Difference]: Start difference. First operand 16875 states and 23955 transitions. Second operand has 5 states, 5 states have (on average 105.2) internal successors, (526), 5 states have internal predecessors, (526), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:08:06,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:08:06,289 INFO L93 Difference]: Finished difference Result 24378 states and 34590 transitions. [2024-12-02 06:08:06,290 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:08:06,290 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 105.2) internal successors, (526), 5 states have internal predecessors, (526), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 785 [2024-12-02 06:08:06,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:08:06,301 INFO L225 Difference]: With dead ends: 24378 [2024-12-02 06:08:06,301 INFO L226 Difference]: Without dead ends: 16843 [2024-12-02 06:08:06,308 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:08:06,308 INFO L435 NwaCegarLoop]: 1070 mSDtfsCounter, 104 mSDsluCounter, 3195 mSDsCounter, 0 mSdLazyCounter, 51 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 104 SdHoareTripleChecker+Valid, 4265 SdHoareTripleChecker+Invalid, 51 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 51 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:08:06,308 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [104 Valid, 4265 Invalid, 51 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 51 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:08:06,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16843 states. [2024-12-02 06:08:06,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16843 to 16843. [2024-12-02 06:08:06,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16843 states, 16733 states have (on average 1.4158250164345902) internal successors, (23691), 16733 states have internal predecessors, (23691), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:08:06,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16843 states to 16843 states and 23907 transitions. [2024-12-02 06:08:06,532 INFO L78 Accepts]: Start accepts. Automaton has 16843 states and 23907 transitions. Word has length 785 [2024-12-02 06:08:06,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:08:06,532 INFO L471 AbstractCegarLoop]: Abstraction has 16843 states and 23907 transitions. [2024-12-02 06:08:06,533 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 105.2) internal successors, (526), 5 states have internal predecessors, (526), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:08:06,533 INFO L276 IsEmpty]: Start isEmpty. Operand 16843 states and 23907 transitions. [2024-12-02 06:08:06,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 786 [2024-12-02 06:08:06,544 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:08:06,545 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:08:06,545 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable80 [2024-12-02 06:08:06,545 INFO L396 AbstractCegarLoop]: === Iteration 82 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:08:06,545 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:08:06,545 INFO L85 PathProgramCache]: Analyzing trace with hash -2123494800, now seen corresponding path program 1 times [2024-12-02 06:08:06,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:08:06,545 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673242087] [2024-12-02 06:08:06,545 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:08:06,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:08:11,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:08:12,396 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 80 proven. 18 refuted. 0 times theorem prover too weak. 772 trivial. 0 not checked. [2024-12-02 06:08:12,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:08:12,396 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673242087] [2024-12-02 06:08:12,396 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1673242087] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:08:12,396 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [118598288] [2024-12-02 06:08:12,396 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:08:12,396 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:08:12,396 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:08:12,398 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:08:12,398 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2024-12-02 06:08:17,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:08:17,410 INFO L256 TraceCheckSpWp]: Trace formula consists of 3748 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 06:08:17,416 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:08:17,434 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 176 proven. 0 refuted. 0 times theorem prover too weak. 694 trivial. 0 not checked. [2024-12-02 06:08:17,434 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:08:17,435 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [118598288] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:08:17,435 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:08:17,435 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 7 [2024-12-02 06:08:17,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461287887] [2024-12-02 06:08:17,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:08:17,435 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:08:17,435 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:08:17,435 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:08:17,436 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:08:17,436 INFO L87 Difference]: Start difference. First operand 16843 states and 23907 transitions. Second operand has 6 states, 5 states have (on average 102.8) internal successors, (514), 6 states have internal predecessors, (514), 3 states have call successors, (9), 2 states have call predecessors, (9), 3 states have return successors, (9), 2 states have call predecessors, (9), 3 states have call successors, (9) [2024-12-02 06:08:17,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:08:17,645 INFO L93 Difference]: Finished difference Result 31042 states and 44062 transitions. [2024-12-02 06:08:17,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:08:17,645 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 102.8) internal successors, (514), 6 states have internal predecessors, (514), 3 states have call successors, (9), 2 states have call predecessors, (9), 3 states have return successors, (9), 2 states have call predecessors, (9), 3 states have call successors, (9) Word has length 785 [2024-12-02 06:08:17,646 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:08:17,657 INFO L225 Difference]: With dead ends: 31042 [2024-12-02 06:08:17,657 INFO L226 Difference]: Without dead ends: 16843 [2024-12-02 06:08:17,666 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 790 GetRequests, 785 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:08:17,666 INFO L435 NwaCegarLoop]: 1072 mSDtfsCounter, 0 mSDsluCounter, 4269 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5341 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:08:17,666 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5341 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:08:17,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16843 states. [2024-12-02 06:08:17,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16843 to 16795. [2024-12-02 06:08:17,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16795 states, 16685 states have (on average 1.4155828588552593) internal successors, (23619), 16685 states have internal predecessors, (23619), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:08:17,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16795 states to 16795 states and 23835 transitions. [2024-12-02 06:08:17,888 INFO L78 Accepts]: Start accepts. Automaton has 16795 states and 23835 transitions. Word has length 785 [2024-12-02 06:08:17,888 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:08:17,888 INFO L471 AbstractCegarLoop]: Abstraction has 16795 states and 23835 transitions. [2024-12-02 06:08:17,889 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 102.8) internal successors, (514), 6 states have internal predecessors, (514), 3 states have call successors, (9), 2 states have call predecessors, (9), 3 states have return successors, (9), 2 states have call predecessors, (9), 3 states have call successors, (9) [2024-12-02 06:08:17,889 INFO L276 IsEmpty]: Start isEmpty. Operand 16795 states and 23835 transitions. [2024-12-02 06:08:17,900 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 786 [2024-12-02 06:08:17,900 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:08:17,900 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:08:17,924 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Ended with exit code 0 [2024-12-02 06:08:18,101 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable81,36 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:08:18,101 INFO L396 AbstractCegarLoop]: === Iteration 83 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:08:18,101 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:08:18,101 INFO L85 PathProgramCache]: Analyzing trace with hash -1141675208, now seen corresponding path program 1 times [2024-12-02 06:08:18,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:08:18,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139819491] [2024-12-02 06:08:18,102 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:08:18,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:08:20,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:08:20,792 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 66 proven. 0 refuted. 0 times theorem prover too weak. 804 trivial. 0 not checked. [2024-12-02 06:08:20,792 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:08:20,792 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139819491] [2024-12-02 06:08:20,792 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [139819491] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:08:20,792 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:08:20,792 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:08:20,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [398043442] [2024-12-02 06:08:20,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:08:20,792 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:08:20,792 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:08:20,793 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:08:20,793 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:08:20,793 INFO L87 Difference]: Start difference. First operand 16795 states and 23835 transitions. Second operand has 4 states, 4 states have (on average 126.0) internal successors, (504), 4 states have internal predecessors, (504), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-12-02 06:08:21,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:08:21,042 INFO L93 Difference]: Finished difference Result 31042 states and 44044 transitions. [2024-12-02 06:08:21,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:08:21,043 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 126.0) internal successors, (504), 4 states have internal predecessors, (504), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 785 [2024-12-02 06:08:21,043 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:08:21,059 INFO L225 Difference]: With dead ends: 31042 [2024-12-02 06:08:21,059 INFO L226 Difference]: Without dead ends: 16795 [2024-12-02 06:08:21,069 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:08:21,069 INFO L435 NwaCegarLoop]: 1062 mSDtfsCounter, 951 mSDsluCounter, 1069 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 953 SdHoareTripleChecker+Valid, 2131 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:08:21,069 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [953 Valid, 2131 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:08:21,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16795 states. [2024-12-02 06:08:21,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16795 to 16795. [2024-12-02 06:08:21,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16795 states, 16685 states have (on average 1.4141444411147737) internal successors, (23595), 16685 states have internal predecessors, (23595), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:08:21,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16795 states to 16795 states and 23811 transitions. [2024-12-02 06:08:21,293 INFO L78 Accepts]: Start accepts. Automaton has 16795 states and 23811 transitions. Word has length 785 [2024-12-02 06:08:21,293 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:08:21,293 INFO L471 AbstractCegarLoop]: Abstraction has 16795 states and 23811 transitions. [2024-12-02 06:08:21,293 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 126.0) internal successors, (504), 4 states have internal predecessors, (504), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-12-02 06:08:21,293 INFO L276 IsEmpty]: Start isEmpty. Operand 16795 states and 23811 transitions. [2024-12-02 06:08:21,305 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 788 [2024-12-02 06:08:21,305 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:08:21,305 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:08:21,305 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable82 [2024-12-02 06:08:21,305 INFO L396 AbstractCegarLoop]: === Iteration 84 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:08:21,306 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:08:21,306 INFO L85 PathProgramCache]: Analyzing trace with hash -967026906, now seen corresponding path program 1 times [2024-12-02 06:08:21,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:08:21,306 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664138235] [2024-12-02 06:08:21,306 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:08:21,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:08:26,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:08:29,894 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 852 trivial. 0 not checked. [2024-12-02 06:08:29,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:08:29,894 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [664138235] [2024-12-02 06:08:29,894 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [664138235] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:08:29,894 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:08:29,895 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2024-12-02 06:08:29,895 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1609362211] [2024-12-02 06:08:29,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:08:29,895 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2024-12-02 06:08:29,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:08:29,896 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2024-12-02 06:08:29,896 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:08:29,896 INFO L87 Difference]: Start difference. First operand 16795 states and 23811 transitions. Second operand has 11 states, 11 states have (on average 41.90909090909091) internal successors, (461), 11 states have internal predecessors, (461), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:08:31,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:08:31,482 INFO L93 Difference]: Finished difference Result 52833 states and 75280 transitions. [2024-12-02 06:08:31,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:08:31,483 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 41.90909090909091) internal successors, (461), 11 states have internal predecessors, (461), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 787 [2024-12-02 06:08:31,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:08:31,509 INFO L225 Difference]: With dead ends: 52833 [2024-12-02 06:08:31,509 INFO L226 Difference]: Without dead ends: 38955 [2024-12-02 06:08:31,522 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2024-12-02 06:08:31,522 INFO L435 NwaCegarLoop]: 786 mSDtfsCounter, 2792 mSDsluCounter, 5550 mSDsCounter, 0 mSdLazyCounter, 2472 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2806 SdHoareTripleChecker+Valid, 6336 SdHoareTripleChecker+Invalid, 2477 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 2472 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:08:31,522 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2806 Valid, 6336 Invalid, 2477 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 2472 Invalid, 0 Unknown, 0 Unchecked, 1.2s Time] [2024-12-02 06:08:31,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38955 states. [2024-12-02 06:08:31,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38955 to 17324. [2024-12-02 06:08:31,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17324 states, 17205 states have (on average 1.4129032258064516) internal successors, (24309), 17205 states have internal predecessors, (24309), 117 states have call successors, (117), 1 states have call predecessors, (117), 1 states have return successors, (117), 117 states have call predecessors, (117), 117 states have call successors, (117) [2024-12-02 06:08:31,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17324 states to 17324 states and 24543 transitions. [2024-12-02 06:08:31,888 INFO L78 Accepts]: Start accepts. Automaton has 17324 states and 24543 transitions. Word has length 787 [2024-12-02 06:08:31,888 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:08:31,888 INFO L471 AbstractCegarLoop]: Abstraction has 17324 states and 24543 transitions. [2024-12-02 06:08:31,889 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 41.90909090909091) internal successors, (461), 11 states have internal predecessors, (461), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:08:31,889 INFO L276 IsEmpty]: Start isEmpty. Operand 17324 states and 24543 transitions. [2024-12-02 06:08:31,904 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 788 [2024-12-02 06:08:31,904 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:08:31,905 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:08:31,905 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable83 [2024-12-02 06:08:31,905 INFO L396 AbstractCegarLoop]: === Iteration 85 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:08:31,905 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:08:31,905 INFO L85 PathProgramCache]: Analyzing trace with hash 848315724, now seen corresponding path program 1 times [2024-12-02 06:08:31,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:08:31,905 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [768951585] [2024-12-02 06:08:31,905 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:08:31,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:08:35,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:08:37,328 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 193 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:08:37,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:08:37,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [768951585] [2024-12-02 06:08:37,328 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [768951585] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:08:37,328 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:08:37,328 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:08:37,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1950146089] [2024-12-02 06:08:37,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:08:37,329 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:08:37,329 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:08:37,329 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:08:37,329 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:08:37,330 INFO L87 Difference]: Start difference. First operand 17324 states and 24543 transitions. Second operand has 8 states, 8 states have (on average 78.5) internal successors, (628), 8 states have internal predecessors, (628), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:08:37,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:08:37,603 INFO L93 Difference]: Finished difference Result 21988 states and 31111 transitions. [2024-12-02 06:08:37,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:08:37,604 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 78.5) internal successors, (628), 8 states have internal predecessors, (628), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 787 [2024-12-02 06:08:37,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:08:37,615 INFO L225 Difference]: With dead ends: 21988 [2024-12-02 06:08:37,615 INFO L226 Difference]: Without dead ends: 17324 [2024-12-02 06:08:37,620 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:08:37,620 INFO L435 NwaCegarLoop]: 1061 mSDtfsCounter, 415 mSDsluCounter, 5659 mSDsCounter, 0 mSdLazyCounter, 103 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 415 SdHoareTripleChecker+Valid, 6720 SdHoareTripleChecker+Invalid, 105 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 103 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:08:37,620 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [415 Valid, 6720 Invalid, 105 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 103 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:08:37,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17324 states. [2024-12-02 06:08:37,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17324 to 14024. [2024-12-02 06:08:37,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14024 states, 13905 states have (on average 1.406616325062927) internal successors, (19559), 13905 states have internal predecessors, (19559), 117 states have call successors, (117), 1 states have call predecessors, (117), 1 states have return successors, (117), 117 states have call predecessors, (117), 117 states have call successors, (117) [2024-12-02 06:08:37,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14024 states to 14024 states and 19793 transitions. [2024-12-02 06:08:37,848 INFO L78 Accepts]: Start accepts. Automaton has 14024 states and 19793 transitions. Word has length 787 [2024-12-02 06:08:37,848 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:08:37,848 INFO L471 AbstractCegarLoop]: Abstraction has 14024 states and 19793 transitions. [2024-12-02 06:08:37,848 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 78.5) internal successors, (628), 8 states have internal predecessors, (628), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:08:37,848 INFO L276 IsEmpty]: Start isEmpty. Operand 14024 states and 19793 transitions. [2024-12-02 06:08:37,859 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 788 [2024-12-02 06:08:37,859 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:08:37,859 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:08:37,859 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable84 [2024-12-02 06:08:37,859 INFO L396 AbstractCegarLoop]: === Iteration 86 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:08:37,860 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:08:37,860 INFO L85 PathProgramCache]: Analyzing trace with hash -304177618, now seen corresponding path program 1 times [2024-12-02 06:08:37,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:08:37,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [952610485] [2024-12-02 06:08:37,860 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:08:37,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:08:41,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:08:42,165 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 854 trivial. 0 not checked. [2024-12-02 06:08:42,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:08:42,165 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [952610485] [2024-12-02 06:08:42,165 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [952610485] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:08:42,165 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:08:42,165 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:08:42,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918537878] [2024-12-02 06:08:42,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:08:42,166 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:08:42,166 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:08:42,166 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:08:42,166 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:08:42,166 INFO L87 Difference]: Start difference. First operand 14024 states and 19793 transitions. Second operand has 3 states, 3 states have (on average 153.33333333333334) internal successors, (460), 3 states have internal predecessors, (460), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:08:42,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:08:42,337 INFO L93 Difference]: Finished difference Result 24647 states and 34877 transitions. [2024-12-02 06:08:42,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:08:42,337 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 153.33333333333334) internal successors, (460), 3 states have internal predecessors, (460), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 787 [2024-12-02 06:08:42,337 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:08:42,347 INFO L225 Difference]: With dead ends: 24647 [2024-12-02 06:08:42,347 INFO L226 Difference]: Without dead ends: 14006 [2024-12-02 06:08:42,354 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:08:42,355 INFO L435 NwaCegarLoop]: 1071 mSDtfsCounter, 1 mSDsluCounter, 1068 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2139 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:08:42,355 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2139 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:08:42,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14006 states. [2024-12-02 06:08:42,550 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14006 to 13997. [2024-12-02 06:08:42,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13997 states, 13878 states have (on average 1.4058942210693184) internal successors, (19511), 13878 states have internal predecessors, (19511), 117 states have call successors, (117), 1 states have call predecessors, (117), 1 states have return successors, (117), 117 states have call predecessors, (117), 117 states have call successors, (117) [2024-12-02 06:08:42,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13997 states to 13997 states and 19745 transitions. [2024-12-02 06:08:42,572 INFO L78 Accepts]: Start accepts. Automaton has 13997 states and 19745 transitions. Word has length 787 [2024-12-02 06:08:42,572 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:08:42,572 INFO L471 AbstractCegarLoop]: Abstraction has 13997 states and 19745 transitions. [2024-12-02 06:08:42,572 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 153.33333333333334) internal successors, (460), 3 states have internal predecessors, (460), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:08:42,572 INFO L276 IsEmpty]: Start isEmpty. Operand 13997 states and 19745 transitions. [2024-12-02 06:08:42,582 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 789 [2024-12-02 06:08:42,583 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:08:42,583 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:08:42,583 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable85 [2024-12-02 06:08:42,583 INFO L396 AbstractCegarLoop]: === Iteration 87 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:08:42,583 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:08:42,583 INFO L85 PathProgramCache]: Analyzing trace with hash 689269577, now seen corresponding path program 1 times [2024-12-02 06:08:42,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:08:42,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437116712] [2024-12-02 06:08:42,584 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:08:42,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:08:47,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:08:51,692 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 852 trivial. 0 not checked. [2024-12-02 06:08:51,692 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:08:51,692 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437116712] [2024-12-02 06:08:51,692 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437116712] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:08:51,692 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:08:51,692 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:08:51,692 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528917085] [2024-12-02 06:08:51,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:08:51,693 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:08:51,693 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:08:51,694 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:08:51,694 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:08:51,694 INFO L87 Difference]: Start difference. First operand 13997 states and 19745 transitions. Second operand has 8 states, 8 states have (on average 57.875) internal successors, (463), 8 states have internal predecessors, (463), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:08:52,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:08:52,022 INFO L93 Difference]: Finished difference Result 19522 states and 27591 transitions. [2024-12-02 06:08:52,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:08:52,023 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 57.875) internal successors, (463), 8 states have internal predecessors, (463), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 788 [2024-12-02 06:08:52,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:08:52,032 INFO L225 Difference]: With dead ends: 19522 [2024-12-02 06:08:52,032 INFO L226 Difference]: Without dead ends: 12169 [2024-12-02 06:08:52,037 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:08:52,037 INFO L435 NwaCegarLoop]: 1054 mSDtfsCounter, 1016 mSDsluCounter, 5225 mSDsCounter, 0 mSdLazyCounter, 174 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1021 SdHoareTripleChecker+Valid, 6279 SdHoareTripleChecker+Invalid, 174 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 174 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:08:52,037 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1021 Valid, 6279 Invalid, 174 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 174 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:08:52,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12169 states. [2024-12-02 06:08:52,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12169 to 12153. [2024-12-02 06:08:52,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12153 states, 12066 states have (on average 1.4099950273495774) internal successors, (17013), 12066 states have internal predecessors, (17013), 85 states have call successors, (85), 1 states have call predecessors, (85), 1 states have return successors, (85), 85 states have call predecessors, (85), 85 states have call successors, (85) [2024-12-02 06:08:52,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12153 states to 12153 states and 17183 transitions. [2024-12-02 06:08:52,222 INFO L78 Accepts]: Start accepts. Automaton has 12153 states and 17183 transitions. Word has length 788 [2024-12-02 06:08:52,223 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:08:52,223 INFO L471 AbstractCegarLoop]: Abstraction has 12153 states and 17183 transitions. [2024-12-02 06:08:52,223 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 57.875) internal successors, (463), 8 states have internal predecessors, (463), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:08:52,223 INFO L276 IsEmpty]: Start isEmpty. Operand 12153 states and 17183 transitions. [2024-12-02 06:08:52,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 789 [2024-12-02 06:08:52,232 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:08:52,232 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:08:52,232 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable86 [2024-12-02 06:08:52,232 INFO L396 AbstractCegarLoop]: === Iteration 88 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:08:52,232 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:08:52,233 INFO L85 PathProgramCache]: Analyzing trace with hash 1345986953, now seen corresponding path program 1 times [2024-12-02 06:08:52,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:08:52,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553724924] [2024-12-02 06:08:52,233 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:08:52,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:08:58,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:09:01,306 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 88 proven. 0 refuted. 0 times theorem prover too weak. 781 trivial. 0 not checked. [2024-12-02 06:09:01,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:09:01,306 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553724924] [2024-12-02 06:09:01,306 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [553724924] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:09:01,307 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:09:01,307 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-12-02 06:09:01,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1058714048] [2024-12-02 06:09:01,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:09:01,307 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:09:01,307 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:09:01,307 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:09:01,307 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:09:01,308 INFO L87 Difference]: Start difference. First operand 12153 states and 17183 transitions. Second operand has 9 states, 9 states have (on average 58.666666666666664) internal successors, (528), 9 states have internal predecessors, (528), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:09:01,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:09:01,792 INFO L93 Difference]: Finished difference Result 35062 states and 49577 transitions. [2024-12-02 06:09:01,793 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:09:01,793 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 58.666666666666664) internal successors, (528), 9 states have internal predecessors, (528), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 788 [2024-12-02 06:09:01,793 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:09:01,813 INFO L225 Difference]: With dead ends: 35062 [2024-12-02 06:09:01,813 INFO L226 Difference]: Without dead ends: 30405 [2024-12-02 06:09:01,820 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:09:01,821 INFO L435 NwaCegarLoop]: 1060 mSDtfsCounter, 2838 mSDsluCounter, 7218 mSDsCounter, 0 mSdLazyCounter, 148 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2848 SdHoareTripleChecker+Valid, 8278 SdHoareTripleChecker+Invalid, 159 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 148 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:09:01,821 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2848 Valid, 8278 Invalid, 159 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 148 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:09:01,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30405 states. [2024-12-02 06:09:02,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30405 to 12585. [2024-12-02 06:09:02,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12585 states, 12498 states have (on average 1.4121459433509362) internal successors, (17649), 12498 states have internal predecessors, (17649), 85 states have call successors, (85), 1 states have call predecessors, (85), 1 states have return successors, (85), 85 states have call predecessors, (85), 85 states have call successors, (85) [2024-12-02 06:09:02,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12585 states to 12585 states and 17819 transitions. [2024-12-02 06:09:02,069 INFO L78 Accepts]: Start accepts. Automaton has 12585 states and 17819 transitions. Word has length 788 [2024-12-02 06:09:02,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:09:02,069 INFO L471 AbstractCegarLoop]: Abstraction has 12585 states and 17819 transitions. [2024-12-02 06:09:02,070 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 58.666666666666664) internal successors, (528), 9 states have internal predecessors, (528), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:09:02,070 INFO L276 IsEmpty]: Start isEmpty. Operand 12585 states and 17819 transitions. [2024-12-02 06:09:02,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 789 [2024-12-02 06:09:02,079 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:09:02,079 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:09:02,079 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable87 [2024-12-02 06:09:02,079 INFO L396 AbstractCegarLoop]: === Iteration 89 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:09:02,080 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:09:02,080 INFO L85 PathProgramCache]: Analyzing trace with hash -1698584879, now seen corresponding path program 1 times [2024-12-02 06:09:02,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:09:02,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [157901553] [2024-12-02 06:09:02,080 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:09:02,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:09:05,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:09:07,304 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 86 proven. 0 refuted. 0 times theorem prover too weak. 781 trivial. 0 not checked. [2024-12-02 06:09:07,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:09:07,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [157901553] [2024-12-02 06:09:07,304 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [157901553] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:09:07,305 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:09:07,305 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:09:07,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [487581860] [2024-12-02 06:09:07,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:09:07,305 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:09:07,305 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:09:07,305 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:09:07,305 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:09:07,305 INFO L87 Difference]: Start difference. First operand 12585 states and 17819 transitions. Second operand has 6 states, 6 states have (on average 88.16666666666667) internal successors, (529), 6 states have internal predecessors, (529), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:09:07,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:09:07,512 INFO L93 Difference]: Finished difference Result 19871 states and 28122 transitions. [2024-12-02 06:09:07,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:09:07,512 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 88.16666666666667) internal successors, (529), 6 states have internal predecessors, (529), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 788 [2024-12-02 06:09:07,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:09:07,522 INFO L225 Difference]: With dead ends: 19871 [2024-12-02 06:09:07,522 INFO L226 Difference]: Without dead ends: 14012 [2024-12-02 06:09:07,528 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:09:07,528 INFO L435 NwaCegarLoop]: 1255 mSDtfsCounter, 201 mSDsluCounter, 2493 mSDsCounter, 0 mSdLazyCounter, 44 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 201 SdHoareTripleChecker+Valid, 3748 SdHoareTripleChecker+Invalid, 44 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 44 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:09:07,528 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [201 Valid, 3748 Invalid, 44 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 44 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:09:07,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14012 states. [2024-12-02 06:09:07,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14012 to 13980. [2024-12-02 06:09:07,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13980 states, 13854 states have (on average 1.4082575429478852) internal successors, (19510), 13854 states have internal predecessors, (19510), 124 states have call successors, (124), 1 states have call predecessors, (124), 1 states have return successors, (124), 124 states have call predecessors, (124), 124 states have call successors, (124) [2024-12-02 06:09:07,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13980 states to 13980 states and 19758 transitions. [2024-12-02 06:09:07,783 INFO L78 Accepts]: Start accepts. Automaton has 13980 states and 19758 transitions. Word has length 788 [2024-12-02 06:09:07,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:09:07,783 INFO L471 AbstractCegarLoop]: Abstraction has 13980 states and 19758 transitions. [2024-12-02 06:09:07,784 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 88.16666666666667) internal successors, (529), 6 states have internal predecessors, (529), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:09:07,784 INFO L276 IsEmpty]: Start isEmpty. Operand 13980 states and 19758 transitions. [2024-12-02 06:09:07,794 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 790 [2024-12-02 06:09:07,794 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:09:07,794 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:09:07,794 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable88 [2024-12-02 06:09:07,794 INFO L396 AbstractCegarLoop]: === Iteration 90 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:09:07,794 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:09:07,794 INFO L85 PathProgramCache]: Analyzing trace with hash -1068037669, now seen corresponding path program 1 times [2024-12-02 06:09:07,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:09:07,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1180586987] [2024-12-02 06:09:07,795 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:09:07,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:09:13,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:09:15,069 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 682 trivial. 0 not checked. [2024-12-02 06:09:15,069 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:09:15,069 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1180586987] [2024-12-02 06:09:15,069 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1180586987] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:09:15,069 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:09:15,069 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:09:15,069 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585737170] [2024-12-02 06:09:15,069 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:09:15,070 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:09:15,070 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:09:15,070 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:09:15,070 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:09:15,071 INFO L87 Difference]: Start difference. First operand 13980 states and 19758 transitions. Second operand has 6 states, 6 states have (on average 104.5) internal successors, (627), 6 states have internal predecessors, (627), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:09:15,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:09:15,390 INFO L93 Difference]: Finished difference Result 28880 states and 40698 transitions. [2024-12-02 06:09:15,390 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:09:15,390 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 104.5) internal successors, (627), 6 states have internal predecessors, (627), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 789 [2024-12-02 06:09:15,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:09:15,407 INFO L225 Difference]: With dead ends: 28880 [2024-12-02 06:09:15,407 INFO L226 Difference]: Without dead ends: 24505 [2024-12-02 06:09:15,414 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:09:15,414 INFO L435 NwaCegarLoop]: 1068 mSDtfsCounter, 756 mSDsluCounter, 4257 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 756 SdHoareTripleChecker+Valid, 5325 SdHoareTripleChecker+Invalid, 49 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:09:15,414 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [756 Valid, 5325 Invalid, 49 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:09:15,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24505 states. [2024-12-02 06:09:15,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24505 to 22848. [2024-12-02 06:09:15,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22848 states, 22626 states have (on average 1.4114735260319986) internal successors, (31936), 22626 states have internal predecessors, (31936), 220 states have call successors, (220), 1 states have call predecessors, (220), 1 states have return successors, (220), 220 states have call predecessors, (220), 220 states have call successors, (220) [2024-12-02 06:09:15,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22848 states to 22848 states and 32376 transitions. [2024-12-02 06:09:15,766 INFO L78 Accepts]: Start accepts. Automaton has 22848 states and 32376 transitions. Word has length 789 [2024-12-02 06:09:15,766 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:09:15,766 INFO L471 AbstractCegarLoop]: Abstraction has 22848 states and 32376 transitions. [2024-12-02 06:09:15,766 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 104.5) internal successors, (627), 6 states have internal predecessors, (627), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:09:15,766 INFO L276 IsEmpty]: Start isEmpty. Operand 22848 states and 32376 transitions. [2024-12-02 06:09:15,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 791 [2024-12-02 06:09:15,784 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:09:15,784 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:09:15,784 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable89 [2024-12-02 06:09:15,784 INFO L396 AbstractCegarLoop]: === Iteration 91 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:09:15,784 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:09:15,785 INFO L85 PathProgramCache]: Analyzing trace with hash 1666567700, now seen corresponding path program 1 times [2024-12-02 06:09:15,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:09:15,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265109986] [2024-12-02 06:09:15,785 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:09:15,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:09:19,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:09:20,729 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 685 trivial. 0 not checked. [2024-12-02 06:09:20,730 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:09:20,730 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [265109986] [2024-12-02 06:09:20,730 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [265109986] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:09:20,730 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:09:20,730 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:09:20,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [363173924] [2024-12-02 06:09:20,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:09:20,731 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:09:20,731 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:09:20,731 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:09:20,731 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:09:20,732 INFO L87 Difference]: Start difference. First operand 22848 states and 32376 transitions. Second operand has 7 states, 7 states have (on average 89.42857142857143) internal successors, (626), 7 states have internal predecessors, (626), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:09:21,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:09:21,170 INFO L93 Difference]: Finished difference Result 27827 states and 39341 transitions. [2024-12-02 06:09:21,170 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:09:21,170 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 89.42857142857143) internal successors, (626), 7 states have internal predecessors, (626), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 790 [2024-12-02 06:09:21,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:09:21,187 INFO L225 Difference]: With dead ends: 27827 [2024-12-02 06:09:21,187 INFO L226 Difference]: Without dead ends: 23128 [2024-12-02 06:09:21,193 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:09:21,194 INFO L435 NwaCegarLoop]: 1010 mSDtfsCounter, 834 mSDsluCounter, 4008 mSDsCounter, 0 mSdLazyCounter, 356 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 834 SdHoareTripleChecker+Valid, 5018 SdHoareTripleChecker+Invalid, 358 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 356 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:09:21,194 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [834 Valid, 5018 Invalid, 358 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 356 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:09:21,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23128 states. [2024-12-02 06:09:21,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23128 to 23128. [2024-12-02 06:09:21,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23128 states, 22906 states have (on average 1.408888500829477) internal successors, (32272), 22906 states have internal predecessors, (32272), 220 states have call successors, (220), 1 states have call predecessors, (220), 1 states have return successors, (220), 220 states have call predecessors, (220), 220 states have call successors, (220) [2024-12-02 06:09:21,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23128 states to 23128 states and 32712 transitions. [2024-12-02 06:09:21,580 INFO L78 Accepts]: Start accepts. Automaton has 23128 states and 32712 transitions. Word has length 790 [2024-12-02 06:09:21,581 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:09:21,581 INFO L471 AbstractCegarLoop]: Abstraction has 23128 states and 32712 transitions. [2024-12-02 06:09:21,581 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 89.42857142857143) internal successors, (626), 7 states have internal predecessors, (626), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:09:21,581 INFO L276 IsEmpty]: Start isEmpty. Operand 23128 states and 32712 transitions. [2024-12-02 06:09:21,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 791 [2024-12-02 06:09:21,597 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:09:21,597 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:09:21,597 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable90 [2024-12-02 06:09:21,597 INFO L396 AbstractCegarLoop]: === Iteration 92 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:09:21,597 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:09:21,597 INFO L85 PathProgramCache]: Analyzing trace with hash -1138924976, now seen corresponding path program 1 times [2024-12-02 06:09:21,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:09:21,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076391352] [2024-12-02 06:09:21,597 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:09:21,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:09:27,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:09:30,083 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 122 proven. 70 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:09:30,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:09:30,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1076391352] [2024-12-02 06:09:30,083 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1076391352] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:09:30,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1070137919] [2024-12-02 06:09:30,083 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:09:30,083 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:09:30,083 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:09:30,085 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:09:30,086 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2024-12-02 06:09:38,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:09:38,274 INFO L256 TraceCheckSpWp]: Trace formula consists of 3757 conjuncts, 205 conjuncts are in the unsatisfiable core [2024-12-02 06:09:38,288 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:09:41,200 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 273 proven. 66 refuted. 0 times theorem prover too weak. 529 trivial. 0 not checked. [2024-12-02 06:09:41,200 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:09:46,056 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 109 proven. 83 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:09:46,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1070137919] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:09:46,057 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:09:46,057 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 36, 31] total 71 [2024-12-02 06:09:46,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [411316191] [2024-12-02 06:09:46,057 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:09:46,058 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 71 states [2024-12-02 06:09:46,058 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:09:46,059 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2024-12-02 06:09:46,059 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=942, Invalid=4028, Unknown=0, NotChecked=0, Total=4970 [2024-12-02 06:09:46,059 INFO L87 Difference]: Start difference. First operand 23128 states and 32712 transitions. Second operand has 71 states, 71 states have (on average 23.380281690140844) internal successors, (1660), 71 states have internal predecessors, (1660), 9 states have call successors, (30), 2 states have call predecessors, (30), 2 states have return successors, (30), 9 states have call predecessors, (30), 9 states have call successors, (30) [2024-12-02 06:10:00,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:10:00,560 INFO L93 Difference]: Finished difference Result 37018 states and 52012 transitions. [2024-12-02 06:10:00,560 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2024-12-02 06:10:00,560 INFO L78 Accepts]: Start accepts. Automaton has has 71 states, 71 states have (on average 23.380281690140844) internal successors, (1660), 71 states have internal predecessors, (1660), 9 states have call successors, (30), 2 states have call predecessors, (30), 2 states have return successors, (30), 9 states have call predecessors, (30), 9 states have call successors, (30) Word has length 790 [2024-12-02 06:10:00,561 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:10:00,583 INFO L225 Difference]: With dead ends: 37018 [2024-12-02 06:10:00,583 INFO L226 Difference]: Without dead ends: 33444 [2024-12-02 06:10:00,589 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1667 GetRequests, 1523 SyntacticMatches, 0 SemanticMatches, 144 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5781 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=3269, Invalid=17901, Unknown=0, NotChecked=0, Total=21170 [2024-12-02 06:10:00,589 INFO L435 NwaCegarLoop]: 1634 mSDtfsCounter, 16618 mSDsluCounter, 37666 mSDsCounter, 0 mSdLazyCounter, 21490 mSolverCounterSat, 86 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 9.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 16618 SdHoareTripleChecker+Valid, 39300 SdHoareTripleChecker+Invalid, 21576 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 86 IncrementalHoareTripleChecker+Valid, 21490 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 10.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:10:00,589 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [16618 Valid, 39300 Invalid, 21576 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [86 Valid, 21490 Invalid, 0 Unknown, 0 Unchecked, 10.4s Time] [2024-12-02 06:10:00,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33444 states. [2024-12-02 06:10:01,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33444 to 25209. [2024-12-02 06:10:01,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25209 states, 24961 states have (on average 1.403108849805697) internal successors, (35023), 24961 states have internal predecessors, (35023), 246 states have call successors, (246), 1 states have call predecessors, (246), 1 states have return successors, (246), 246 states have call predecessors, (246), 246 states have call successors, (246) [2024-12-02 06:10:01,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25209 states to 25209 states and 35515 transitions. [2024-12-02 06:10:01,161 INFO L78 Accepts]: Start accepts. Automaton has 25209 states and 35515 transitions. Word has length 790 [2024-12-02 06:10:01,161 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:10:01,161 INFO L471 AbstractCegarLoop]: Abstraction has 25209 states and 35515 transitions. [2024-12-02 06:10:01,161 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 71 states, 71 states have (on average 23.380281690140844) internal successors, (1660), 71 states have internal predecessors, (1660), 9 states have call successors, (30), 2 states have call predecessors, (30), 2 states have return successors, (30), 9 states have call predecessors, (30), 9 states have call successors, (30) [2024-12-02 06:10:01,161 INFO L276 IsEmpty]: Start isEmpty. Operand 25209 states and 35515 transitions. [2024-12-02 06:10:01,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 792 [2024-12-02 06:10:01,180 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:10:01,180 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:10:01,207 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Forceful destruction successful, exit code 0 [2024-12-02 06:10:01,380 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable91,37 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:10:01,380 INFO L396 AbstractCegarLoop]: === Iteration 93 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:10:01,381 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:10:01,381 INFO L85 PathProgramCache]: Analyzing trace with hash 1029824092, now seen corresponding path program 1 times [2024-12-02 06:10:01,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:10:01,381 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2064489759] [2024-12-02 06:10:01,381 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:10:01,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:10:05,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:10:07,369 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 128 proven. 3 refuted. 0 times theorem prover too weak. 738 trivial. 0 not checked. [2024-12-02 06:10:07,369 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:10:07,369 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2064489759] [2024-12-02 06:10:07,369 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2064489759] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:10:07,369 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1290773838] [2024-12-02 06:10:07,369 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:10:07,369 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:10:07,369 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:10:07,371 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:10:07,372 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2024-12-02 06:10:16,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:10:16,441 INFO L256 TraceCheckSpWp]: Trace formula consists of 3758 conjuncts, 192 conjuncts are in the unsatisfiable core [2024-12-02 06:10:16,453 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:10:20,538 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 273 proven. 52 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2024-12-02 06:10:20,539 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:10:27,400 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 212 proven. 17 refuted. 0 times theorem prover too weak. 640 trivial. 0 not checked. [2024-12-02 06:10:27,400 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1290773838] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:10:27,400 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:10:27,400 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 36, 33] total 72 [2024-12-02 06:10:27,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1907756557] [2024-12-02 06:10:27,400 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:10:27,401 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 72 states [2024-12-02 06:10:27,401 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:10:27,402 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2024-12-02 06:10:27,402 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1021, Invalid=4091, Unknown=0, NotChecked=0, Total=5112 [2024-12-02 06:10:27,403 INFO L87 Difference]: Start difference. First operand 25209 states and 35515 transitions. Second operand has 72 states, 72 states have (on average 21.430555555555557) internal successors, (1543), 72 states have internal predecessors, (1543), 8 states have call successors, (25), 2 states have call predecessors, (25), 2 states have return successors, (25), 8 states have call predecessors, (25), 8 states have call successors, (25) [2024-12-02 06:10:39,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:10:39,362 INFO L93 Difference]: Finished difference Result 57810 states and 81319 transitions. [2024-12-02 06:10:39,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2024-12-02 06:10:39,362 INFO L78 Accepts]: Start accepts. Automaton has has 72 states, 72 states have (on average 21.430555555555557) internal successors, (1543), 72 states have internal predecessors, (1543), 8 states have call successors, (25), 2 states have call predecessors, (25), 2 states have return successors, (25), 8 states have call predecessors, (25), 8 states have call successors, (25) Word has length 791 [2024-12-02 06:10:39,363 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:10:39,393 INFO L225 Difference]: With dead ends: 57810 [2024-12-02 06:10:39,393 INFO L226 Difference]: Without dead ends: 39730 [2024-12-02 06:10:39,408 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1633 GetRequests, 1517 SyntacticMatches, 1 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3716 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=2601, Invalid=10971, Unknown=0, NotChecked=0, Total=13572 [2024-12-02 06:10:39,408 INFO L435 NwaCegarLoop]: 1314 mSDtfsCounter, 11764 mSDsluCounter, 37042 mSDsCounter, 0 mSdLazyCounter, 18460 mSolverCounterSat, 42 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 7.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 11773 SdHoareTripleChecker+Valid, 38356 SdHoareTripleChecker+Invalid, 18502 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 42 IncrementalHoareTripleChecker+Valid, 18460 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 8.9s IncrementalHoareTripleChecker+Time [2024-12-02 06:10:39,409 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [11773 Valid, 38356 Invalid, 18502 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [42 Valid, 18460 Invalid, 0 Unknown, 0 Unchecked, 8.9s Time] [2024-12-02 06:10:39,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39730 states. [2024-12-02 06:10:39,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39730 to 25133. [2024-12-02 06:10:39,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25133 states, 24881 states have (on average 1.4011896627949036) internal successors, (34863), 24881 states have internal predecessors, (34863), 250 states have call successors, (250), 1 states have call predecessors, (250), 1 states have return successors, (250), 250 states have call predecessors, (250), 250 states have call successors, (250) [2024-12-02 06:10:39,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25133 states to 25133 states and 35363 transitions. [2024-12-02 06:10:39,949 INFO L78 Accepts]: Start accepts. Automaton has 25133 states and 35363 transitions. Word has length 791 [2024-12-02 06:10:39,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:10:39,949 INFO L471 AbstractCegarLoop]: Abstraction has 25133 states and 35363 transitions. [2024-12-02 06:10:39,949 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 72 states, 72 states have (on average 21.430555555555557) internal successors, (1543), 72 states have internal predecessors, (1543), 8 states have call successors, (25), 2 states have call predecessors, (25), 2 states have return successors, (25), 8 states have call predecessors, (25), 8 states have call successors, (25) [2024-12-02 06:10:39,950 INFO L276 IsEmpty]: Start isEmpty. Operand 25133 states and 35363 transitions. [2024-12-02 06:10:39,969 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 793 [2024-12-02 06:10:39,969 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:10:39,969 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:10:39,997 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Ended with exit code 0 [2024-12-02 06:10:40,169 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable92,38 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:10:40,170 INFO L396 AbstractCegarLoop]: === Iteration 94 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:10:40,170 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:10:40,170 INFO L85 PathProgramCache]: Analyzing trace with hash -2126866009, now seen corresponding path program 1 times [2024-12-02 06:10:40,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:10:40,170 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [656309217] [2024-12-02 06:10:40,170 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:10:40,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:10:45,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:10:49,060 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 195 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:10:49,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:10:49,060 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [656309217] [2024-12-02 06:10:49,060 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [656309217] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:10:49,060 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:10:49,060 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2024-12-02 06:10:49,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928151924] [2024-12-02 06:10:49,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:10:49,060 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 06:10:49,060 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:10:49,061 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 06:10:49,061 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:10:49,061 INFO L87 Difference]: Start difference. First operand 25133 states and 35363 transitions. Second operand has 10 states, 10 states have (on average 63.3) internal successors, (633), 10 states have internal predecessors, (633), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:10:49,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:10:49,649 INFO L93 Difference]: Finished difference Result 35453 states and 49672 transitions. [2024-12-02 06:10:49,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:10:49,649 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 63.3) internal successors, (633), 10 states have internal predecessors, (633), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 792 [2024-12-02 06:10:49,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:10:49,674 INFO L225 Difference]: With dead ends: 35453 [2024-12-02 06:10:49,674 INFO L226 Difference]: Without dead ends: 30391 [2024-12-02 06:10:49,683 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:10:49,683 INFO L435 NwaCegarLoop]: 1955 mSDtfsCounter, 1199 mSDsluCounter, 12769 mSDsCounter, 0 mSdLazyCounter, 178 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1204 SdHoareTripleChecker+Valid, 14724 SdHoareTripleChecker+Invalid, 179 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 178 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:10:49,683 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1204 Valid, 14724 Invalid, 179 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 178 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:10:49,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30391 states. [2024-12-02 06:10:50,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30391 to 25435. [2024-12-02 06:10:50,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25435 states, 25183 states have (on average 1.400031767462177) internal successors, (35257), 25183 states have internal predecessors, (35257), 250 states have call successors, (250), 1 states have call predecessors, (250), 1 states have return successors, (250), 250 states have call predecessors, (250), 250 states have call successors, (250) [2024-12-02 06:10:50,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25435 states to 25435 states and 35757 transitions. [2024-12-02 06:10:50,276 INFO L78 Accepts]: Start accepts. Automaton has 25435 states and 35757 transitions. Word has length 792 [2024-12-02 06:10:50,277 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:10:50,277 INFO L471 AbstractCegarLoop]: Abstraction has 25435 states and 35757 transitions. [2024-12-02 06:10:50,277 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 63.3) internal successors, (633), 10 states have internal predecessors, (633), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:10:50,277 INFO L276 IsEmpty]: Start isEmpty. Operand 25435 states and 35757 transitions. [2024-12-02 06:10:50,296 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 793 [2024-12-02 06:10:50,296 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:10:50,297 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:10:50,297 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable93 [2024-12-02 06:10:50,297 INFO L396 AbstractCegarLoop]: === Iteration 95 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:10:50,297 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:10:50,298 INFO L85 PathProgramCache]: Analyzing trace with hash 2061226320, now seen corresponding path program 1 times [2024-12-02 06:10:50,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:10:50,298 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912513842] [2024-12-02 06:10:50,298 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:10:50,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:10:55,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:10:57,714 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 181 proven. 0 refuted. 0 times theorem prover too weak. 689 trivial. 0 not checked. [2024-12-02 06:10:57,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:10:57,714 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [912513842] [2024-12-02 06:10:57,714 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [912513842] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:10:57,714 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:10:57,714 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:10:57,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497818423] [2024-12-02 06:10:57,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:10:57,715 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:10:57,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:10:57,716 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:10:57,716 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:10:57,716 INFO L87 Difference]: Start difference. First operand 25435 states and 35757 transitions. Second operand has 6 states, 6 states have (on average 104.0) internal successors, (624), 6 states have internal predecessors, (624), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2024-12-02 06:10:58,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:10:58,244 INFO L93 Difference]: Finished difference Result 42939 states and 60321 transitions. [2024-12-02 06:10:58,244 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:10:58,244 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 104.0) internal successors, (624), 6 states have internal predecessors, (624), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) Word has length 792 [2024-12-02 06:10:58,245 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:10:58,268 INFO L225 Difference]: With dead ends: 42939 [2024-12-02 06:10:58,268 INFO L226 Difference]: Without dead ends: 33011 [2024-12-02 06:10:58,279 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:10:58,279 INFO L435 NwaCegarLoop]: 1289 mSDtfsCounter, 126 mSDsluCounter, 4912 mSDsCounter, 0 mSdLazyCounter, 64 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 126 SdHoareTripleChecker+Valid, 6201 SdHoareTripleChecker+Invalid, 64 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 64 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:10:58,279 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [126 Valid, 6201 Invalid, 64 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 64 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:10:58,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33011 states. [2024-12-02 06:10:58,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33011 to 27865. [2024-12-02 06:10:58,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27865 states, 27551 states have (on average 1.3994047402998075) internal successors, (38555), 27551 states have internal predecessors, (38555), 312 states have call successors, (312), 1 states have call predecessors, (312), 1 states have return successors, (312), 312 states have call predecessors, (312), 312 states have call successors, (312) [2024-12-02 06:10:58,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27865 states to 27865 states and 39179 transitions. [2024-12-02 06:10:58,989 INFO L78 Accepts]: Start accepts. Automaton has 27865 states and 39179 transitions. Word has length 792 [2024-12-02 06:10:58,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:10:58,990 INFO L471 AbstractCegarLoop]: Abstraction has 27865 states and 39179 transitions. [2024-12-02 06:10:58,990 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 104.0) internal successors, (624), 6 states have internal predecessors, (624), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2024-12-02 06:10:58,990 INFO L276 IsEmpty]: Start isEmpty. Operand 27865 states and 39179 transitions. [2024-12-02 06:10:59,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 794 [2024-12-02 06:10:59,017 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:10:59,018 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:10:59,018 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable94 [2024-12-02 06:10:59,018 INFO L396 AbstractCegarLoop]: === Iteration 96 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:10:59,018 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:10:59,018 INFO L85 PathProgramCache]: Analyzing trace with hash 1134932309, now seen corresponding path program 1 times [2024-12-02 06:10:59,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:10:59,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [727945120] [2024-12-02 06:10:59,019 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:10:59,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:11:09,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 06:11:09,522 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 06:11:19,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 06:11:19,602 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-12-02 06:11:19,602 INFO L340 BasicCegarLoop]: Counterexample is feasible [2024-12-02 06:11:19,603 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-12-02 06:11:19,604 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable95 [2024-12-02 06:11:19,607 INFO L422 BasicCegarLoop]: Path program histogram: [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:19,902 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-12-02 06:11:19,904 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.12 06:11:19 BoogieIcfgContainer [2024-12-02 06:11:19,905 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-12-02 06:11:19,905 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-12-02 06:11:19,905 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-12-02 06:11:19,905 INFO L274 PluginConnector]: Witness Printer initialized [2024-12-02 06:11:19,906 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:03:19" (3/4) ... [2024-12-02 06:11:19,907 INFO L149 WitnessPrinter]: No result that supports witness generation found [2024-12-02 06:11:19,908 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-12-02 06:11:19,908 INFO L158 Benchmark]: Toolchain (without parser) took 484220.00ms. Allocated memory was 142.6MB in the beginning and 2.7GB in the end (delta: 2.6GB). Free memory was 115.4MB in the beginning and 1.5GB in the end (delta: -1.4GB). Peak memory consumption was 1.2GB. Max. memory is 16.1GB. [2024-12-02 06:11:19,908 INFO L158 Benchmark]: CDTParser took 0.34ms. Allocated memory is still 142.6MB. Free memory was 82.5MB in the beginning and 82.5MB in the end (delta: 33.2kB). There was no memory consumed. Max. memory is 16.1GB. [2024-12-02 06:11:19,908 INFO L158 Benchmark]: CACSL2BoogieTranslator took 501.78ms. Allocated memory is still 142.6MB. Free memory was 115.2MB in the beginning and 74.8MB in the end (delta: 40.5MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2024-12-02 06:11:19,909 INFO L158 Benchmark]: Boogie Procedure Inliner took 248.15ms. Allocated memory is still 142.6MB. Free memory was 74.8MB in the beginning and 67.5MB in the end (delta: 7.3MB). Peak memory consumption was 42.3MB. Max. memory is 16.1GB. [2024-12-02 06:11:19,909 INFO L158 Benchmark]: Boogie Preprocessor took 298.80ms. Allocated memory is still 142.6MB. Free memory was 67.5MB in the beginning and 69.8MB in the end (delta: -2.2MB). Peak memory consumption was 44.1MB. Max. memory is 16.1GB. [2024-12-02 06:11:19,909 INFO L158 Benchmark]: RCFGBuilder took 2868.11ms. Allocated memory was 142.6MB in the beginning and 327.2MB in the end (delta: 184.5MB). Free memory was 69.8MB in the beginning and 87.5MB in the end (delta: -17.7MB). Peak memory consumption was 164.5MB. Max. memory is 16.1GB. [2024-12-02 06:11:19,909 INFO L158 Benchmark]: TraceAbstraction took 480294.35ms. Allocated memory was 327.2MB in the beginning and 2.7GB in the end (delta: 2.4GB). Free memory was 85.1MB in the beginning and 1.5GB in the end (delta: -1.4GB). Peak memory consumption was 1.5GB. Max. memory is 16.1GB. [2024-12-02 06:11:19,909 INFO L158 Benchmark]: Witness Printer took 2.84ms. Allocated memory is still 2.7GB. Free memory was 1.5GB in the beginning and 1.5GB in the end (delta: 4.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-12-02 06:11:19,910 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.34ms. Allocated memory is still 142.6MB. Free memory was 82.5MB in the beginning and 82.5MB in the end (delta: 33.2kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 501.78ms. Allocated memory is still 142.6MB. Free memory was 115.2MB in the beginning and 74.8MB in the end (delta: 40.5MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 248.15ms. Allocated memory is still 142.6MB. Free memory was 74.8MB in the beginning and 67.5MB in the end (delta: 7.3MB). Peak memory consumption was 42.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 298.80ms. Allocated memory is still 142.6MB. Free memory was 67.5MB in the beginning and 69.8MB in the end (delta: -2.2MB). Peak memory consumption was 44.1MB. Max. memory is 16.1GB. * RCFGBuilder took 2868.11ms. Allocated memory was 142.6MB in the beginning and 327.2MB in the end (delta: 184.5MB). Free memory was 69.8MB in the beginning and 87.5MB in the end (delta: -17.7MB). Peak memory consumption was 164.5MB. Max. memory is 16.1GB. * TraceAbstraction took 480294.35ms. Allocated memory was 327.2MB in the beginning and 2.7GB in the end (delta: 2.4GB). Free memory was 85.1MB in the beginning and 1.5GB in the end (delta: -1.4GB). Peak memory consumption was 1.5GB. Max. memory is 16.1GB. * Witness Printer took 2.84ms. Allocated memory is still 2.7GB. Free memory was 1.5GB in the beginning and 1.5GB in the end (delta: 4.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 21]: Unable to prove that a call to reach_error is unreachable Unable to prove that a call to reach_error is unreachable Reason: overapproximation of bitwiseOr at line 403, overapproximation of bitwiseOr at line 142, overapproximation of bitwiseOr at line 187, overapproximation of bitwiseOr at line 226, overapproximation of bitwiseAnd at line 274, overapproximation of bitwiseAnd at line 318, overapproximation of bitwiseAnd at line 502, overapproximation of bitwiseAnd at line 578, overapproximation of bitwiseAnd at line 408, overapproximation of bitwiseAnd at line 238, overapproximation of bitwiseAnd at line 641, overapproximation of bitwiseAnd at line 765, overapproximation of bitwiseAnd at line 657, overapproximation of bitwiseAnd at line 148, overapproximation of bitwiseAnd at line 128, overapproximation of bitwiseAnd at line 622, overapproximation of bitwiseAnd at line 271, overapproximation of bitwiseAnd at line 284. Possible FailurePath: [L26] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L27] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L29] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 16); [L30] const SORT_3 msb_SORT_3 = (SORT_3)1 << (16 - 1); [L32] const SORT_5 mask_SORT_5 = (SORT_5)-1 >> (sizeof(SORT_5) * 8 - 2); [L33] const SORT_5 msb_SORT_5 = (SORT_5)1 << (2 - 1); [L35] const SORT_11 mask_SORT_11 = (SORT_11)-1 >> (sizeof(SORT_11) * 8 - 8); [L36] const SORT_11 msb_SORT_11 = (SORT_11)1 << (8 - 1); [L38] const SORT_12 mask_SORT_12 = (SORT_12)-1 >> (sizeof(SORT_12) * 8 - 3); [L39] const SORT_12 msb_SORT_12 = (SORT_12)1 << (3 - 1); [L42] const SORT_15 mask_SORT_15 = (SORT_15)-1 >> (sizeof(SORT_15) * 8 - 4); [L43] const SORT_15 msb_SORT_15 = (SORT_15)1 << (4 - 1); [L45] const SORT_36 mask_SORT_36 = (SORT_36)-1 >> (sizeof(SORT_36) * 8 - 5); [L46] const SORT_36 msb_SORT_36 = (SORT_36)1 << (5 - 1); [L48] const SORT_38 mask_SORT_38 = (SORT_38)-1 >> (sizeof(SORT_38) * 8 - 6); [L49] const SORT_38 msb_SORT_38 = (SORT_38)1 << (6 - 1); [L51] const SORT_40 mask_SORT_40 = (SORT_40)-1 >> (sizeof(SORT_40) * 8 - 7); [L52] const SORT_40 msb_SORT_40 = (SORT_40)1 << (7 - 1); [L54] const SORT_229 mask_SORT_229 = (SORT_229)-1 >> (sizeof(SORT_229) * 8 - 32); [L55] const SORT_229 msb_SORT_229 = (SORT_229)1 << (32 - 1); [L57] const SORT_15 var_27 = 8; [L58] const SORT_15 var_99 = 0; [L59] const SORT_1 var_109 = 1; [L60] const SORT_1 var_110 = 0; [L61] const SORT_11 var_183 = 0; [L62] const SORT_229 var_230 = 2; [L63] const SORT_11 var_410 = 255; [L65] SORT_1 input_2; [L66] SORT_3 input_4; [L67] SORT_5 input_6; [L68] SORT_3 input_7; [L69] SORT_5 input_8; [L70] SORT_1 input_9; [L71] SORT_1 input_10; [L73] SORT_13 state_14; [L74] unsigned char i = 0; VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND FALSE !(i < (1 << 3)) VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L75] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L75] SORT_15 state_16 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L76] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L76] SORT_15 state_19 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L77] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L77] SORT_11 state_26 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L78] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L78] SORT_1 state_31 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L79] SORT_13 state_44; [L80] unsigned char i = 0; VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND FALSE !(i < (1 << 3)) VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L81] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L81] SORT_15 state_45 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L82] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L82] SORT_15 state_48 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L83] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L83] SORT_11 state_55 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L84] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L84] SORT_1 state_85 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L85] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L85] SORT_1 state_86 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L86] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L86] SORT_15 state_89 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L87] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L87] SORT_11 state_105 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L88] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L88] SORT_1 state_111 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L89] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L89] SORT_1 state_333 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L90] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L90] SORT_1 state_334 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L91] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L91] SORT_1 state_335 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L92] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L92] SORT_1 state_336 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L93] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L93] SORT_1 state_337 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L94] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L94] SORT_1 state_338 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L95] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L95] SORT_1 state_339 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L96] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L96] SORT_1 state_340 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L98] SORT_1 init_112_arg_1 = var_109; [L99] state_111 = init_112_arg_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L102] input_2 = __VERIFIER_nondet_uchar() [L103] input_4 = __VERIFIER_nondet_ushort() [L104] input_6 = __VERIFIER_nondet_uchar() [L105] input_7 = __VERIFIER_nondet_ushort() [L106] input_8 = __VERIFIER_nondet_uchar() [L107] input_9 = __VERIFIER_nondet_uchar() [L108] EXPR input_9 & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L108] input_9 = input_9 & mask_SORT_1 [L109] input_10 = __VERIFIER_nondet_uchar() [L111] SORT_15 var_52_arg_0 = state_48; [L112] SORT_15 var_52_arg_1 = state_45; [L113] SORT_1 var_52 = var_52_arg_0 == var_52_arg_1; [L114] SORT_1 var_117_arg_0 = var_52; [L115] SORT_1 var_117 = ~var_117_arg_0; [L116] SORT_5 var_51_arg_0 = input_8; [L117] SORT_1 var_51 = var_51_arg_0 >> 0; [L118] SORT_1 var_118_arg_0 = var_51; [L119] SORT_1 var_118 = ~var_118_arg_0; [L120] SORT_1 var_119_arg_0 = var_117; [L121] SORT_1 var_119_arg_1 = var_118; VAL [input_8=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_119_arg_0=-2, var_119_arg_1=-2, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L122] EXPR var_119_arg_0 | var_119_arg_1 VAL [input_8=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L122] SORT_1 var_119 = var_119_arg_0 | var_119_arg_1; [L123] SORT_1 var_120_arg_0 = var_109; [L124] SORT_1 var_120 = ~var_120_arg_0; [L125] SORT_1 var_121_arg_0 = var_119; [L126] SORT_1 var_121_arg_1 = var_120; VAL [input_8=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_121_arg_0=254, var_121_arg_1=-2, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L127] EXPR var_121_arg_0 | var_121_arg_1 VAL [input_8=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L127] SORT_1 var_121 = var_121_arg_0 | var_121_arg_1; [L128] EXPR var_121 & mask_SORT_1 VAL [input_8=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L128] var_121 = var_121 & mask_SORT_1 [L129] SORT_1 constr_122_arg_0 = var_121; VAL [constr_122_arg_0=1, input_8=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L130] CALL assume_abort_if_not(constr_122_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L130] RET assume_abort_if_not(constr_122_arg_0) VAL [constr_122_arg_0=1, input_8=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L131] SORT_15 var_23_arg_0 = state_19; [L132] SORT_15 var_23_arg_1 = state_16; [L133] SORT_1 var_23 = var_23_arg_0 == var_23_arg_1; [L134] SORT_1 var_123_arg_0 = var_23; [L135] SORT_1 var_123 = ~var_123_arg_0; [L136] SORT_5 var_22_arg_0 = input_8; [L137] SORT_1 var_22 = var_22_arg_0 >> 1; [L138] SORT_1 var_124_arg_0 = var_22; [L139] SORT_1 var_124 = ~var_124_arg_0; [L140] SORT_1 var_125_arg_0 = var_123; [L141] SORT_1 var_125_arg_1 = var_124; VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_125_arg_0=-2, var_125_arg_1=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L142] EXPR var_125_arg_0 | var_125_arg_1 VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L142] SORT_1 var_125 = var_125_arg_0 | var_125_arg_1; [L143] SORT_1 var_126_arg_0 = var_109; [L144] SORT_1 var_126 = ~var_126_arg_0; [L145] SORT_1 var_127_arg_0 = var_125; [L146] SORT_1 var_127_arg_1 = var_126; VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_127_arg_0=256, var_127_arg_1=-2, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L147] EXPR var_127_arg_0 | var_127_arg_1 VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L147] SORT_1 var_127 = var_127_arg_0 | var_127_arg_1; [L148] EXPR var_127 & mask_SORT_1 VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L148] var_127 = var_127 & mask_SORT_1 [L149] SORT_1 constr_128_arg_0 = var_127; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L150] CALL assume_abort_if_not(constr_128_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L150] RET assume_abort_if_not(constr_128_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L151] SORT_15 var_49_arg_0 = state_48; [L152] SORT_12 var_49 = var_49_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_49=0, var_51=1, var_52=1, var_99=0] [L153] EXPR var_49 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L153] var_49 = var_49 & mask_SORT_12 [L154] SORT_15 var_46_arg_0 = state_45; [L155] SORT_12 var_46 = var_46_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L156] EXPR var_46 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_49=0, var_51=1, var_52=1, var_99=0] [L156] var_46 = var_46 & mask_SORT_12 [L157] SORT_12 var_73_arg_0 = var_49; [L158] SORT_12 var_73_arg_1 = var_46; [L159] SORT_1 var_73 = var_73_arg_0 == var_73_arg_1; [L160] SORT_15 var_74_arg_0 = state_48; [L161] SORT_1 var_74 = var_74_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_99=0] [L162] EXPR var_74 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_99=0] [L162] var_74 = var_74 & mask_SORT_1 [L163] SORT_15 var_75_arg_0 = state_45; [L164] SORT_1 var_75 = var_75_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_75=0, var_99=0] [L165] EXPR var_75 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_99=0] [L165] var_75 = var_75 & mask_SORT_1 [L166] SORT_1 var_76_arg_0 = var_74; [L167] SORT_1 var_76_arg_1 = var_75; [L168] SORT_1 var_76 = var_76_arg_0 != var_76_arg_1; [L169] SORT_1 var_77_arg_0 = var_73; [L170] SORT_1 var_77_arg_1 = var_76; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_77_arg_0=1, var_77_arg_1=0, var_99=0] [L171] EXPR var_77_arg_0 & var_77_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L171] SORT_1 var_77 = var_77_arg_0 & var_77_arg_1; [L172] EXPR var_77 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L172] var_77 = var_77 & mask_SORT_1 [L173] SORT_1 var_129_arg_0 = var_77; [L174] SORT_1 var_129 = ~var_129_arg_0; [L175] SORT_5 var_92_arg_0 = input_6; [L176] SORT_1 var_92 = var_92_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_129=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L177] EXPR var_92 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_129=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L177] var_92 = var_92 & mask_SORT_1 [L178] SORT_1 var_130_arg_0 = var_92; [L179] SORT_1 var_130 = ~var_130_arg_0; [L180] SORT_1 var_131_arg_0 = var_129; [L181] SORT_1 var_131_arg_1 = var_130; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_131_arg_0=-1, var_131_arg_1=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L182] EXPR var_131_arg_0 | var_131_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L182] SORT_1 var_131 = var_131_arg_0 | var_131_arg_1; [L183] SORT_1 var_132_arg_0 = var_109; [L184] SORT_1 var_132 = ~var_132_arg_0; [L185] SORT_1 var_133_arg_0 = var_131; [L186] SORT_1 var_133_arg_1 = var_132; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_133_arg_0=255, var_133_arg_1=-2, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L187] EXPR var_133_arg_0 | var_133_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L187] SORT_1 var_133 = var_133_arg_0 | var_133_arg_1; [L188] EXPR var_133 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L188] var_133 = var_133 & mask_SORT_1 [L189] SORT_1 constr_134_arg_0 = var_133; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L190] CALL assume_abort_if_not(constr_134_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L190] RET assume_abort_if_not(constr_134_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L191] SORT_15 var_20_arg_0 = state_19; [L192] SORT_12 var_20 = var_20_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L193] EXPR var_20 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L193] var_20 = var_20 & mask_SORT_12 [L194] SORT_15 var_17_arg_0 = state_16; [L195] SORT_12 var_17 = var_17_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L196] EXPR var_17 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L196] var_17 = var_17 & mask_SORT_12 [L197] SORT_12 var_78_arg_0 = var_20; [L198] SORT_12 var_78_arg_1 = var_17; [L199] SORT_1 var_78 = var_78_arg_0 == var_78_arg_1; [L200] SORT_15 var_79_arg_0 = state_19; [L201] SORT_1 var_79 = var_79_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_92=0, var_99=0] [L202] EXPR var_79 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_92=0, var_99=0] [L202] var_79 = var_79 & mask_SORT_1 [L203] SORT_15 var_80_arg_0 = state_16; [L204] SORT_1 var_80 = var_80_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_80=0, var_92=0, var_99=0] [L205] EXPR var_80 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_92=0, var_99=0] [L205] var_80 = var_80 & mask_SORT_1 [L206] SORT_1 var_81_arg_0 = var_79; [L207] SORT_1 var_81_arg_1 = var_80; [L208] SORT_1 var_81 = var_81_arg_0 != var_81_arg_1; [L209] SORT_1 var_82_arg_0 = var_78; [L210] SORT_1 var_82_arg_1 = var_81; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_82_arg_0=1, var_82_arg_1=0, var_92=0, var_99=0] [L211] EXPR var_82_arg_0 & var_82_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L211] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L212] SORT_1 var_135_arg_0 = var_82; [L213] SORT_1 var_135 = ~var_135_arg_0; [L214] SORT_5 var_136_arg_0 = input_6; [L215] SORT_1 var_136 = var_136_arg_0 >> 1; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_135=-1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L216] EXPR var_136 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_135=-1, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L216] var_136 = var_136 & mask_SORT_1 [L217] SORT_1 var_137_arg_0 = var_136; [L218] SORT_1 var_137 = ~var_137_arg_0; [L219] SORT_1 var_138_arg_0 = var_135; [L220] SORT_1 var_138_arg_1 = var_137; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_138_arg_0=-1, var_138_arg_1=-1, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L221] EXPR var_138_arg_0 | var_138_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L221] SORT_1 var_138 = var_138_arg_0 | var_138_arg_1; [L222] SORT_1 var_139_arg_0 = var_109; [L223] SORT_1 var_139 = ~var_139_arg_0; [L224] SORT_1 var_140_arg_0 = var_138; [L225] SORT_1 var_140_arg_1 = var_139; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_140_arg_0=255, var_140_arg_1=-2, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L226] EXPR var_140_arg_0 | var_140_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L226] SORT_1 var_140 = var_140_arg_0 | var_140_arg_1; [L227] EXPR var_140 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L227] var_140 = var_140 & mask_SORT_1 [L228] SORT_1 constr_141_arg_0 = var_140; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L229] CALL assume_abort_if_not(constr_141_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L229] RET assume_abort_if_not(constr_141_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L230] SORT_1 var_142_arg_0 = state_111; [L231] SORT_1 var_142_arg_1 = input_9; [L232] SORT_1 var_142 = var_142_arg_0 == var_142_arg_1; [L233] SORT_1 var_143_arg_0 = var_109; [L234] SORT_1 var_143 = ~var_143_arg_0; [L235] SORT_1 var_144_arg_0 = var_142; [L236] SORT_1 var_144_arg_1 = var_143; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_144_arg_0=0, var_144_arg_1=-2, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L237] EXPR var_144_arg_0 | var_144_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L237] SORT_1 var_144 = var_144_arg_0 | var_144_arg_1; [L238] EXPR var_144 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L238] var_144 = var_144 & mask_SORT_1 [L239] SORT_1 constr_145_arg_0 = var_144; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L240] CALL assume_abort_if_not(constr_145_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L240] RET assume_abort_if_not(constr_145_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L242] SORT_1 var_113_arg_0 = state_111; [L243] SORT_1 var_113_arg_1 = var_110; [L244] SORT_1 var_113_arg_2 = var_109; [L245] SORT_1 var_113 = var_113_arg_0 ? var_113_arg_1 : var_113_arg_2; [L246] SORT_1 var_87_arg_0 = state_86; [L247] SORT_1 var_87 = ~var_87_arg_0; [L248] SORT_1 var_88_arg_0 = state_85; [L249] SORT_1 var_88_arg_1 = var_87; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_88_arg_0=0, var_88_arg_1=-1, var_92=0, var_99=0] [L250] EXPR var_88_arg_0 & var_88_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L250] SORT_1 var_88 = var_88_arg_0 & var_88_arg_1; [L251] SORT_15 var_90_arg_0 = state_89; [L252] SORT_1 var_90 = var_90_arg_0 != 0; [L253] SORT_1 var_91_arg_0 = var_88; [L254] SORT_1 var_91_arg_1 = var_90; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91_arg_0=0, var_91_arg_1=0, var_92=0, var_99=0] [L255] EXPR var_91_arg_0 & var_91_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L255] SORT_1 var_91 = var_91_arg_0 & var_91_arg_1; [L256] SORT_1 var_93_arg_0 = state_85; [L257] SORT_1 var_93 = ~var_93_arg_0; [L258] SORT_1 var_94_arg_0 = var_92; [L259] SORT_1 var_94_arg_1 = var_93; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_94_arg_0=0, var_94_arg_1=-1, var_99=0] [L260] EXPR var_94_arg_0 & var_94_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_99=0] [L260] SORT_1 var_94 = var_94_arg_0 & var_94_arg_1; [L261] SORT_1 var_95_arg_0 = var_94; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_95_arg_0=0, var_99=0] [L262] EXPR var_95_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_99=0] [L262] var_95_arg_0 = var_95_arg_0 & mask_SORT_1 [L263] SORT_15 var_95 = var_95_arg_0; [L264] SORT_15 var_96_arg_0 = state_89; [L265] SORT_15 var_96_arg_1 = var_95; [L266] SORT_15 var_96 = var_96_arg_0 + var_96_arg_1; [L267] SORT_1 var_53_arg_0 = var_52; [L268] SORT_1 var_53 = ~var_53_arg_0; [L269] SORT_1 var_54_arg_0 = var_51; [L270] SORT_1 var_54_arg_1 = var_53; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54_arg_0=1, var_54_arg_1=-2, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L271] EXPR var_54_arg_0 & var_54_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L271] SORT_1 var_54 = var_54_arg_0 & var_54_arg_1; [L272] EXPR var_54 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L272] var_54 = var_54 & mask_SORT_1 [L273] SORT_15 var_56_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_56_arg_0=8, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L274] EXPR var_56_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L274] var_56_arg_0 = var_56_arg_0 & mask_SORT_15 [L275] SORT_11 var_56 = var_56_arg_0; [L276] SORT_11 var_57_arg_0 = state_55; [L277] SORT_11 var_57_arg_1 = var_56; [L278] SORT_1 var_57 = var_57_arg_0 >= var_57_arg_1; [L279] SORT_1 var_58_arg_0 = var_54; [L280] SORT_1 var_58_arg_1 = var_57; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58_arg_0=0, var_58_arg_1=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L281] EXPR var_58_arg_0 & var_58_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L281] SORT_1 var_58 = var_58_arg_0 & var_58_arg_1; [L282] SORT_1 var_59_arg_0 = state_31; [L283] SORT_1 var_59 = ~var_59_arg_0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58=0, var_59=-1, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L284] EXPR var_59 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L284] var_59 = var_59 & mask_SORT_1 [L285] SORT_1 var_60_arg_0 = var_58; [L286] SORT_1 var_60_arg_1 = var_59; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60_arg_0=0, var_60_arg_1=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L287] EXPR var_60_arg_0 & var_60_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L287] SORT_1 var_60 = var_60_arg_0 & var_60_arg_1; [L288] EXPR var_60 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L288] var_60 = var_60 & mask_SORT_1 [L289] SORT_1 var_97_arg_0 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_97_arg_0=0, var_99=0] [L290] EXPR var_97_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L290] var_97_arg_0 = var_97_arg_0 & mask_SORT_1 [L291] SORT_15 var_97 = var_97_arg_0; [L292] SORT_15 var_98_arg_0 = var_96; [L293] SORT_15 var_98_arg_1 = var_97; [L294] SORT_15 var_98 = var_98_arg_0 - var_98_arg_1; [L295] SORT_1 var_100_arg_0 = input_9; [L296] SORT_15 var_100_arg_1 = var_99; [L297] SORT_15 var_100_arg_2 = var_98; [L298] SORT_15 var_100 = var_100_arg_0 ? var_100_arg_1 : var_100_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_99=0] [L299] EXPR var_100 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_99=0] [L299] var_100 = var_100 & mask_SORT_15 [L300] SORT_15 var_101_arg_0 = var_100; [L301] SORT_1 var_101 = var_101_arg_0 != 0; [L302] SORT_1 var_102_arg_0 = var_101; [L303] SORT_1 var_102 = ~var_102_arg_0; [L304] SORT_1 var_103_arg_0 = var_91; [L305] SORT_1 var_103_arg_1 = var_102; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103_arg_0=0, var_103_arg_1=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L306] EXPR var_103_arg_0 & var_103_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L306] SORT_1 var_103 = var_103_arg_0 & var_103_arg_1; [L307] SORT_1 var_104_arg_0 = var_103; [L308] SORT_1 var_104 = ~var_104_arg_0; [L309] SORT_11* var_21_arg_0 = state_14; [L310] SORT_12 var_21_arg_1 = var_20; [L311] EXPR var_21_arg_0[(unsigned char) var_21_arg_1] [L311] SORT_11 var_21 = var_21_arg_0[(unsigned char) var_21_arg_1]; [L312] SORT_1 var_24_arg_0 = var_23; [L313] SORT_1 var_24 = ~var_24_arg_0; [L314] SORT_1 var_25_arg_0 = var_22; [L315] SORT_1 var_25_arg_1 = var_24; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25_arg_0=0, var_25_arg_1=-2, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L316] EXPR var_25_arg_0 & var_25_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L316] SORT_1 var_25 = var_25_arg_0 & var_25_arg_1; [L317] SORT_15 var_28_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_28_arg_0=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L318] EXPR var_28_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L318] var_28_arg_0 = var_28_arg_0 & mask_SORT_15 [L319] SORT_11 var_28 = var_28_arg_0; [L320] SORT_11 var_29_arg_0 = state_26; [L321] SORT_11 var_29_arg_1 = var_28; [L322] SORT_1 var_29 = var_29_arg_0 >= var_29_arg_1; [L323] SORT_1 var_30_arg_0 = var_25; [L324] SORT_1 var_30_arg_1 = var_29; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_30_arg_0=0, var_30_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L325] EXPR var_30_arg_0 & var_30_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L325] SORT_1 var_30 = var_30_arg_0 & var_30_arg_1; [L326] SORT_1 var_32_arg_0 = var_30; [L327] SORT_1 var_32_arg_1 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32_arg_0=0, var_32_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L328] EXPR var_32_arg_0 & var_32_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L328] SORT_1 var_32 = var_32_arg_0 & var_32_arg_1; [L329] EXPR var_32 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L329] var_32 = var_32 & mask_SORT_1 [L330] SORT_1 var_33_arg_0 = var_32; [L331] SORT_1 var_33_arg_1 = var_32; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_33_arg_0=0, var_33_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L332] EXPR ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L332] SORT_5 var_33 = ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1; [L333] EXPR var_33 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L333] var_33 = var_33 & mask_SORT_5 [L334] SORT_1 var_34_arg_0 = var_32; [L335] SORT_5 var_34_arg_1 = var_33; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_34_arg_0=0, var_34_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L336] EXPR ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L336] SORT_12 var_34 = ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1; [L337] EXPR var_34 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L337] var_34 = var_34 & mask_SORT_12 [L338] SORT_1 var_35_arg_0 = var_32; [L339] SORT_12 var_35_arg_1 = var_34; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_35_arg_0=0, var_35_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L340] EXPR ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L340] SORT_15 var_35 = ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1; [L341] EXPR var_35 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L341] var_35 = var_35 & mask_SORT_15 [L342] SORT_1 var_37_arg_0 = var_32; [L343] SORT_15 var_37_arg_1 = var_35; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_37_arg_0=0, var_37_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L344] EXPR ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L344] SORT_36 var_37 = ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1; [L345] EXPR var_37 & mask_SORT_36 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L345] var_37 = var_37 & mask_SORT_36 [L346] SORT_1 var_39_arg_0 = var_32; [L347] SORT_36 var_39_arg_1 = var_37; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_39_arg_0=0, var_39_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L348] EXPR ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L348] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1; [L349] EXPR var_39 & mask_SORT_38 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L349] var_39 = var_39 & mask_SORT_38 [L350] SORT_1 var_41_arg_0 = var_32; [L351] SORT_38 var_41_arg_1 = var_39; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_41_arg_0=0, var_41_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L352] EXPR ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L352] SORT_40 var_41 = ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1; [L353] EXPR var_41 & mask_SORT_40 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L353] var_41 = var_41 & mask_SORT_40 [L354] SORT_1 var_42_arg_0 = var_32; [L355] SORT_40 var_42_arg_1 = var_41; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_42_arg_0=0, var_42_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L356] EXPR ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L356] SORT_11 var_42 = ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1; [L357] SORT_11 var_43_arg_0 = var_21; [L358] SORT_11 var_43_arg_1 = var_42; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43_arg_0=0, var_43_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L359] EXPR var_43_arg_0 & var_43_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L359] SORT_11 var_43 = var_43_arg_0 & var_43_arg_1; [L360] SORT_11* var_50_arg_0 = state_44; [L361] SORT_12 var_50_arg_1 = var_49; [L362] EXPR var_50_arg_0[(unsigned char) var_50_arg_1] [L362] SORT_11 var_50 = var_50_arg_0[(unsigned char) var_50_arg_1]; [L363] EXPR var_50 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L363] var_50 = var_50 & mask_SORT_11 [L364] SORT_1 var_61_arg_0 = var_60; [L365] SORT_1 var_61_arg_1 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_61_arg_0=0, var_61_arg_1=0, var_92=0, var_93=-1, var_99=0] [L366] EXPR ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L366] SORT_5 var_61 = ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1; [L367] EXPR var_61 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L367] var_61 = var_61 & mask_SORT_5 [L368] SORT_1 var_62_arg_0 = var_60; [L369] SORT_5 var_62_arg_1 = var_61; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_62_arg_0=0, var_62_arg_1=0, var_92=0, var_93=-1, var_99=0] [L370] EXPR ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L370] SORT_12 var_62 = ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1; [L371] EXPR var_62 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L371] var_62 = var_62 & mask_SORT_12 [L372] SORT_1 var_63_arg_0 = var_60; [L373] SORT_12 var_63_arg_1 = var_62; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_63_arg_0=0, var_63_arg_1=0, var_92=0, var_93=-1, var_99=0] [L374] EXPR ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L374] SORT_15 var_63 = ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1; [L375] EXPR var_63 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L375] var_63 = var_63 & mask_SORT_15 [L376] SORT_1 var_64_arg_0 = var_60; [L377] SORT_15 var_64_arg_1 = var_63; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_64_arg_0=0, var_64_arg_1=0, var_92=0, var_93=-1, var_99=0] [L378] EXPR ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L378] SORT_36 var_64 = ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1; [L379] EXPR var_64 & mask_SORT_36 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L379] var_64 = var_64 & mask_SORT_36 [L380] SORT_1 var_65_arg_0 = var_60; [L381] SORT_36 var_65_arg_1 = var_64; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_65_arg_0=0, var_65_arg_1=0, var_92=0, var_93=-1, var_99=0] [L382] EXPR ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L382] SORT_38 var_65 = ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1; [L383] EXPR var_65 & mask_SORT_38 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L383] var_65 = var_65 & mask_SORT_38 [L384] SORT_1 var_66_arg_0 = var_60; [L385] SORT_38 var_66_arg_1 = var_65; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_66_arg_0=0, var_66_arg_1=0, var_92=0, var_93=-1, var_99=0] [L386] EXPR ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L386] SORT_40 var_66 = ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1; [L387] EXPR var_66 & mask_SORT_40 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L387] var_66 = var_66 & mask_SORT_40 [L388] SORT_1 var_67_arg_0 = var_60; [L389] SORT_40 var_67_arg_1 = var_66; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_67_arg_0=0, var_67_arg_1=0, var_92=0, var_93=-1, var_99=0] [L390] EXPR ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L390] SORT_11 var_67 = ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1; [L391] SORT_11 var_68_arg_0 = var_50; [L392] SORT_11 var_68_arg_1 = var_67; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_68_arg_0=0, var_68_arg_1=0, var_92=0, var_93=-1, var_99=0] [L393] EXPR var_68_arg_0 & var_68_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L393] SORT_11 var_68 = var_68_arg_0 & var_68_arg_1; [L394] SORT_11 var_69_arg_0 = var_43; [L395] SORT_11 var_69_arg_1 = var_68; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_69_arg_0=0, var_69_arg_1=0, var_92=0, var_93=-1, var_99=0] [L396] EXPR var_69_arg_0 | var_69_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L396] SORT_11 var_69 = var_69_arg_0 | var_69_arg_1; [L397] EXPR var_69 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L397] var_69 = var_69 & mask_SORT_11 [L398] SORT_11 var_106_arg_0 = state_105; [L399] SORT_11 var_106_arg_1 = var_69; [L400] SORT_1 var_106 = var_106_arg_0 == var_106_arg_1; [L401] SORT_1 var_107_arg_0 = var_104; [L402] SORT_1 var_107_arg_1 = var_106; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_107_arg_0=-1, var_107_arg_1=1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L403] EXPR var_107_arg_0 | var_107_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L403] SORT_1 var_107 = var_107_arg_0 | var_107_arg_1; [L404] SORT_1 var_114_arg_0 = var_107; [L405] SORT_1 var_114 = ~var_114_arg_0; [L406] SORT_1 var_115_arg_0 = var_113; [L407] SORT_1 var_115_arg_1 = var_114; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_115_arg_0=0, var_115_arg_1=-256, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L408] EXPR var_115_arg_0 & var_115_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L408] SORT_1 var_115 = var_115_arg_0 & var_115_arg_1; [L409] EXPR var_115 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L409] var_115 = var_115 & mask_SORT_1 [L410] SORT_1 bad_116_arg_0 = var_115; [L411] CALL __VERIFIER_assert(!(bad_116_arg_0)) [L21] COND FALSE !(!(cond)) [L411] RET __VERIFIER_assert(!(bad_116_arg_0)) [L413] SORT_1 var_298_arg_0 = var_136; [L414] SORT_1 var_298_arg_1 = var_32; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_298_arg_0=0, var_298_arg_1=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L415] EXPR var_298_arg_0 | var_298_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L415] SORT_1 var_298 = var_298_arg_0 | var_298_arg_1; [L416] SORT_1 var_299_arg_0 = var_298; [L417] SORT_1 var_299_arg_1 = input_9; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299_arg_0=0, var_299_arg_1=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L418] EXPR var_299_arg_0 | var_299_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L418] SORT_1 var_299 = var_299_arg_0 | var_299_arg_1; [L419] EXPR var_299 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L419] var_299 = var_299 & mask_SORT_1 [L420] SORT_1 var_310_arg_0 = var_136; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_310_arg_0=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L421] EXPR var_310_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L421] var_310_arg_0 = var_310_arg_0 & mask_SORT_1 [L422] SORT_15 var_310 = var_310_arg_0; [L423] SORT_15 var_311_arg_0 = state_16; [L424] SORT_15 var_311_arg_1 = var_310; [L425] SORT_15 var_311 = var_311_arg_0 + var_311_arg_1; [L426] SORT_1 var_404_arg_0 = var_299; [L427] SORT_15 var_404_arg_1 = var_311; [L428] SORT_15 var_404_arg_2 = state_16; [L429] SORT_15 var_404 = var_404_arg_0 ? var_404_arg_1 : var_404_arg_2; [L430] SORT_1 var_405_arg_0 = input_9; [L431] SORT_15 var_405_arg_1 = var_99; [L432] SORT_15 var_405_arg_2 = var_404; [L433] SORT_15 var_405 = var_405_arg_0 ? var_405_arg_1 : var_405_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_32=0, var_405=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L434] EXPR var_405 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L434] var_405 = var_405 & mask_SORT_15 [L435] SORT_15 next_406_arg_1 = var_405; [L436] SORT_1 var_304_arg_0 = var_32; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, state_105=0, state_14={10:0}, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_304_arg_0=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L437] EXPR var_304_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, state_105=0, state_14={10:0}, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L437] var_304_arg_0 = var_304_arg_0 & mask_SORT_1 [L438] SORT_15 var_304 = var_304_arg_0; [L439] SORT_15 var_305_arg_0 = state_19; [L440] SORT_15 var_305_arg_1 = var_304; [L441] SORT_15 var_305 = var_305_arg_0 + var_305_arg_1; [L442] SORT_1 var_407_arg_0 = var_299; [L443] SORT_15 var_407_arg_1 = var_305; [L444] SORT_15 var_407_arg_2 = state_19; [L445] SORT_15 var_407 = var_407_arg_0 ? var_407_arg_1 : var_407_arg_2; [L446] SORT_1 var_408_arg_0 = input_9; [L447] SORT_15 var_408_arg_1 = var_99; [L448] SORT_15 var_408_arg_2 = var_407; [L449] SORT_15 var_408 = var_408_arg_0 ? var_408_arg_1 : var_408_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_408=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L450] EXPR var_408 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L450] var_408 = var_408 & mask_SORT_15 [L451] SORT_15 next_409_arg_1 = var_408; [L452] SORT_11 var_417_arg_0 = var_410; [L453] SORT_1 var_417 = var_417_arg_0 != 0; [L454] SORT_3 var_258_arg_0 = input_4; [L455] SORT_11 var_258 = var_258_arg_0 >> 8; [L456] SORT_11* var_18_arg_0 = state_14; [L457] SORT_12 var_18_arg_1 = var_17; [L458] EXPR var_18_arg_0[(unsigned char) var_18_arg_1] [L458] SORT_11 var_18 = var_18_arg_0[(unsigned char) var_18_arg_1]; [L459] SORT_1 var_317_arg_0 = var_136; [L460] SORT_11 var_317_arg_1 = var_258; [L461] SORT_11 var_317_arg_2 = var_18; [L462] SORT_11 var_317 = var_317_arg_0 ? var_317_arg_1 : var_317_arg_2; [L463] SORT_11 var_414_arg_0 = var_317; [L464] SORT_11 var_414_arg_1 = var_410; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_414_arg_0=0, var_414_arg_1=255, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L465] EXPR var_414_arg_0 & var_414_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L465] SORT_11 var_414 = var_414_arg_0 & var_414_arg_1; [L466] SORT_11* var_411_arg_0 = state_14; [L467] SORT_12 var_411_arg_1 = var_17; [L468] EXPR var_411_arg_0[(unsigned char) var_411_arg_1] [L468] SORT_11 var_411 = var_411_arg_0[(unsigned char) var_411_arg_1]; [L469] SORT_11 var_412_arg_0 = var_410; [L470] SORT_11 var_412 = ~var_412_arg_0; [L471] SORT_11 var_413_arg_0 = var_411; [L472] SORT_11 var_413_arg_1 = var_412; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_413_arg_0=0, var_413_arg_1=-256, var_414=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L473] EXPR var_413_arg_0 & var_413_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_414=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L473] SORT_11 var_413 = var_413_arg_0 & var_413_arg_1; [L474] SORT_11 var_415_arg_0 = var_414; [L475] SORT_11 var_415_arg_1 = var_413; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_415_arg_0=0, var_415_arg_1=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L476] EXPR var_415_arg_0 | var_415_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L476] SORT_11 var_415 = var_415_arg_0 | var_415_arg_1; [L477] SORT_11* var_416_arg_0 = state_14; [L478] SORT_12 var_416_arg_1 = var_17; [L479] SORT_11 var_416_arg_2 = var_415; [L480] SORT_13 var_416; [L481] unsigned char i = 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=8, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND FALSE !(i < (1 << 3)) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L482] var_416[(unsigned char) var_416_arg_1] = var_416_arg_2 [L483] SORT_1 var_418_arg_0 = var_417; [L484] SORT_11* var_418_arg_1 = var_416; [L485] SORT_11* var_418_arg_2 = state_14; [L486] SORT_11* var_418 = var_418_arg_0 ? var_418_arg_1 : var_418_arg_2; [L487] SORT_11* next_419_arg_1 = var_418; [L488] SORT_1 var_157_arg_0 = var_25; [L489] SORT_1 var_157_arg_1 = var_54; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157_arg_0=0, var_157_arg_1=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L490] EXPR ((SORT_5)var_157_arg_0 << 1) | var_157_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L490] SORT_5 var_157 = ((SORT_5)var_157_arg_0 << 1) | var_157_arg_1; [L491] EXPR var_157 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L491] var_157 = var_157 & mask_SORT_5 [L492] SORT_1 var_162_arg_0 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_162_arg_0=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L493] EXPR var_162_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L493] var_162_arg_0 = var_162_arg_0 & mask_SORT_1 [L494] SORT_5 var_162 = var_162_arg_0; [L495] SORT_1 var_163_arg_0 = var_109; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_162=0, var_163_arg_0=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L496] EXPR var_163_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_162=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L496] var_163_arg_0 = var_163_arg_0 & mask_SORT_1 [L497] SORT_5 var_163 = var_163_arg_0; [L498] SORT_5 var_164_arg_0 = var_162; [L499] SORT_5 var_164_arg_1 = var_163; [L500] SORT_5 var_164 = var_164_arg_0 + var_164_arg_1; [L501] SORT_5 var_165_arg_0 = var_164; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_165_arg_0=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L502] EXPR var_165_arg_0 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L502] var_165_arg_0 = var_165_arg_0 & mask_SORT_5 [L503] SORT_12 var_165 = var_165_arg_0; [L504] SORT_1 var_166_arg_0 = var_109; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_165=0, var_166_arg_0=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L505] EXPR var_166_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_165=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L505] var_166_arg_0 = var_166_arg_0 & mask_SORT_1 [L506] SORT_12 var_166 = var_166_arg_0; [L507] SORT_12 var_167_arg_0 = var_165; [L508] SORT_12 var_167_arg_1 = var_166; [L509] SORT_12 var_167 = var_167_arg_0 + var_167_arg_1; [L510] SORT_12 var_168_arg_0 = var_167; [L511] SORT_1 var_168 = var_168_arg_0 >> 0; [L512] SORT_1 var_169_arg_0 = var_168; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_169_arg_0=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L513] EXPR var_169_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L513] var_169_arg_0 = var_169_arg_0 & mask_SORT_1 [L514] SORT_5 var_169 = var_169_arg_0; [L515] SORT_5 var_170_arg_0 = var_157; [L516] SORT_5 var_170_arg_1 = var_169; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_170_arg_0=0, var_170_arg_1=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L517] EXPR var_170_arg_0 >> var_170_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L517] SORT_5 var_170 = var_170_arg_0 >> var_170_arg_1; [L518] SORT_5 var_171_arg_0 = var_170; [L519] SORT_1 var_171 = var_171_arg_0 >> 0; [L520] SORT_1 var_152_arg_0 = var_110; [L521] SORT_1 var_152_arg_1 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_152_arg_0=0, var_152_arg_1=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L522] EXPR ((SORT_5)var_152_arg_0 << 1) | var_152_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L522] SORT_5 var_152 = ((SORT_5)var_152_arg_0 << 1) | var_152_arg_1; [L523] SORT_5 var_153_arg_0 = var_152; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_153_arg_0=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L524] EXPR var_153_arg_0 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L524] var_153_arg_0 = var_153_arg_0 & mask_SORT_5 [L525] SORT_12 var_153 = var_153_arg_0; [L526] SORT_1 var_154_arg_0 = var_109; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_153=0, var_154_arg_0=1, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L527] EXPR var_154_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_153=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L527] var_154_arg_0 = var_154_arg_0 & mask_SORT_1 [L528] SORT_12 var_154 = var_154_arg_0; [L529] SORT_12 var_155_arg_0 = var_153; [L530] SORT_12 var_155_arg_1 = var_154; [L531] SORT_12 var_155 = var_155_arg_0 + var_155_arg_1; [L532] SORT_12 var_156_arg_0 = var_155; [L533] SORT_1 var_156 = var_156_arg_0 >> 0; [L534] SORT_1 var_158_arg_0 = var_156; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_157=0, var_158_arg_0=1, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L535] EXPR var_158_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L535] var_158_arg_0 = var_158_arg_0 & mask_SORT_1 [L536] SORT_5 var_158 = var_158_arg_0; [L537] SORT_5 var_159_arg_0 = var_157; [L538] SORT_5 var_159_arg_1 = var_158; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_159_arg_0=0, var_159_arg_1=1, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L539] EXPR var_159_arg_0 >> var_159_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L539] SORT_5 var_159 = var_159_arg_0 >> var_159_arg_1; [L540] SORT_5 var_160_arg_0 = var_159; [L541] SORT_1 var_160 = var_160_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_160=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L542] EXPR var_160 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L542] var_160 = var_160 & mask_SORT_1 [L543] SORT_1 var_172_arg_0 = var_160; [L544] SORT_1 var_172 = ~var_172_arg_0; [L545] SORT_1 var_173_arg_0 = var_171; [L546] SORT_1 var_173_arg_1 = var_172; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_160=0, var_168=1, var_173_arg_0=0, var_173_arg_1=-1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L547] EXPR var_173_arg_0 & var_173_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_160=0, var_168=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L547] SORT_1 var_173 = var_173_arg_0 & var_173_arg_1; [L548] EXPR var_173 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_160=0, var_168=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L548] var_173 = var_173 & mask_SORT_1 [L549] SORT_1 var_161_arg_0 = var_160; [L550] SORT_1 var_161_arg_1 = var_156; [L551] SORT_1 var_161_arg_2 = state_31; [L552] SORT_1 var_161 = var_161_arg_0 ? var_161_arg_1 : var_161_arg_2; [L553] SORT_1 var_174_arg_0 = var_173; [L554] SORT_1 var_174_arg_1 = var_168; [L555] SORT_1 var_174_arg_2 = var_161; [L556] SORT_1 var_174 = var_174_arg_0 ? var_174_arg_1 : var_174_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L557] EXPR var_174 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L557] var_174 = var_174 & mask_SORT_1 [L558] SORT_1 var_204_arg_0 = var_174; [L559] SORT_1 var_204_arg_1 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_204_arg_0=0, var_204_arg_1=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L560] EXPR var_204_arg_0 | var_204_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L560] SORT_1 var_204 = var_204_arg_0 | var_204_arg_1; [L561] EXPR var_204 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L561] var_204 = var_204 & mask_SORT_1 [L562] SORT_1 var_198_arg_0 = var_25; [L563] SORT_1 var_198 = ~var_198_arg_0; [L564] SORT_1 var_199_arg_0 = state_31; [L565] SORT_1 var_199_arg_1 = var_198; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_199_arg_0=0, var_199_arg_1=-1, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L566] EXPR var_199_arg_0 & var_199_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L566] SORT_1 var_199 = var_199_arg_0 & var_199_arg_1; [L567] EXPR var_199 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L567] var_199 = var_199 & mask_SORT_1 [L568] SORT_3 var_191_arg_0 = input_7; [L569] SORT_11 var_191 = var_191_arg_0 >> 8; [L570] SORT_11 var_192_arg_0 = state_26; [L571] SORT_11 var_192_arg_1 = var_191; [L572] SORT_11 var_192 = var_192_arg_0 + var_192_arg_1; [L573] SORT_1 var_193_arg_0 = var_174; [L574] SORT_11 var_193_arg_1 = var_192; [L575] SORT_11 var_193_arg_2 = state_26; [L576] SORT_11 var_193 = var_193_arg_0 ? var_193_arg_1 : var_193_arg_2; [L577] SORT_15 var_195_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_193=0, var_195_arg_0=8, var_198=-1, var_199=0, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L578] EXPR var_195_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_193=0, var_198=-1, var_199=0, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L578] var_195_arg_0 = var_195_arg_0 & mask_SORT_15 [L579] SORT_11 var_195 = var_195_arg_0; [L580] SORT_11 var_196_arg_0 = var_193; [L581] SORT_11 var_196_arg_1 = var_195; [L582] SORT_11 var_196 = var_196_arg_0 - var_196_arg_1; [L583] SORT_1 var_197_arg_0 = var_32; [L584] SORT_11 var_197_arg_1 = var_196; [L585] SORT_11 var_197_arg_2 = var_193; [L586] SORT_11 var_197 = var_197_arg_0 ? var_197_arg_1 : var_197_arg_2; [L587] SORT_1 var_200_arg_0 = var_199; [L588] SORT_11 var_200_arg_1 = state_26; [L589] SORT_11 var_200_arg_2 = var_197; [L590] SORT_11 var_200 = var_200_arg_0 ? var_200_arg_1 : var_200_arg_2; [L591] SORT_1 var_201_arg_0 = input_9; [L592] SORT_11 var_201_arg_1 = var_183; [L593] SORT_11 var_201_arg_2 = var_200; [L594] SORT_11 var_201 = var_201_arg_0 ? var_201_arg_1 : var_201_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_201=0, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L595] EXPR var_201 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L595] var_201 = var_201 & mask_SORT_11 [L596] SORT_1 var_420_arg_0 = var_204; [L597] SORT_11 var_420_arg_1 = var_201; [L598] SORT_11 var_420_arg_2 = state_26; [L599] SORT_11 var_420 = var_420_arg_0 ? var_420_arg_1 : var_420_arg_2; [L600] SORT_1 var_421_arg_0 = input_9; [L601] SORT_11 var_421_arg_1 = var_183; [L602] SORT_11 var_421_arg_2 = var_420; [L603] SORT_11 var_421 = var_421_arg_0 ? var_421_arg_1 : var_421_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_421=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L604] EXPR var_421 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L604] var_421 = var_421 & mask_SORT_11 [L605] SORT_11 next_422_arg_1 = var_421; [L606] SORT_1 var_180_arg_0 = var_54; [L607] SORT_1 var_180 = ~var_180_arg_0; [L608] SORT_1 var_181_arg_0 = var_59; [L609] SORT_1 var_181_arg_1 = var_180; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_181_arg_0=0, var_181_arg_1=-1, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L610] EXPR var_181_arg_0 & var_181_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L610] SORT_1 var_181 = var_181_arg_0 & var_181_arg_1; [L611] EXPR var_181 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L611] var_181 = var_181 & mask_SORT_1 [L612] SORT_3 var_150_arg_0 = input_7; [L613] SORT_11 var_150 = var_150_arg_0 >> 0; [L614] SORT_11 var_151_arg_0 = state_55; [L615] SORT_11 var_151_arg_1 = var_150; [L616] SORT_11 var_151 = var_151_arg_0 + var_151_arg_1; [L617] SORT_1 var_175_arg_0 = var_174; [L618] SORT_11 var_175_arg_1 = state_55; [L619] SORT_11 var_175_arg_2 = var_151; [L620] SORT_11 var_175 = var_175_arg_0 ? var_175_arg_1 : var_175_arg_2; [L621] SORT_15 var_177_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_175=0, var_177_arg_0=8, var_180=-1, var_181=0, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L622] EXPR var_177_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_175=0, var_180=-1, var_181=0, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L622] var_177_arg_0 = var_177_arg_0 & mask_SORT_15 [L623] SORT_11 var_177 = var_177_arg_0; [L624] SORT_11 var_178_arg_0 = var_175; [L625] SORT_11 var_178_arg_1 = var_177; [L626] SORT_11 var_178 = var_178_arg_0 - var_178_arg_1; [L627] SORT_1 var_179_arg_0 = var_60; [L628] SORT_11 var_179_arg_1 = var_178; [L629] SORT_11 var_179_arg_2 = var_175; [L630] SORT_11 var_179 = var_179_arg_0 ? var_179_arg_1 : var_179_arg_2; [L631] SORT_1 var_182_arg_0 = var_181; [L632] SORT_11 var_182_arg_1 = state_55; [L633] SORT_11 var_182_arg_2 = var_179; [L634] SORT_11 var_182 = var_182_arg_0 ? var_182_arg_1 : var_182_arg_2; [L635] SORT_1 var_184_arg_0 = input_9; [L636] SORT_11 var_184_arg_1 = var_183; [L637] SORT_11 var_184_arg_2 = var_182; [L638] SORT_11 var_184 = var_184_arg_0 ? var_184_arg_1 : var_184_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L639] EXPR var_184 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L639] var_184 = var_184 & mask_SORT_11 [L640] SORT_15 var_212_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_184=0, var_198=-1, var_201=0, var_212_arg_0=8, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L641] EXPR var_212_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L641] var_212_arg_0 = var_212_arg_0 & mask_SORT_15 [L642] SORT_11 var_212 = var_212_arg_0; [L643] SORT_11 var_213_arg_0 = var_184; [L644] SORT_11 var_213_arg_1 = var_212; [L645] SORT_1 var_213 = var_213_arg_0 < var_213_arg_1; [L646] SORT_1 var_214_arg_0 = var_180; [L647] SORT_1 var_214_arg_1 = var_213; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_214_arg_0=-1, var_214_arg_1=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L648] EXPR var_214_arg_0 | var_214_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L648] SORT_1 var_214 = var_214_arg_0 | var_214_arg_1; [L649] SORT_1 var_215_arg_0 = var_59; [L650] SORT_1 var_215_arg_1 = var_214; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_215_arg_0=0, var_215_arg_1=255, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L651] EXPR var_215_arg_0 & var_215_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L651] SORT_1 var_215 = var_215_arg_0 & var_215_arg_1; [L652] SORT_1 var_216_arg_0 = var_60; [L653] SORT_1 var_216_arg_1 = var_215; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_216_arg_0=0, var_216_arg_1=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L654] EXPR var_216_arg_0 & var_216_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L654] SORT_1 var_216 = var_216_arg_0 & var_216_arg_1; [L655] EXPR var_216 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L655] var_216 = var_216 & mask_SORT_1 [L656] SORT_15 var_207_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_207_arg_0=8, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L657] EXPR var_207_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L657] var_207_arg_0 = var_207_arg_0 & mask_SORT_15 [L658] SORT_11 var_207 = var_207_arg_0; [L659] SORT_11 var_208_arg_0 = var_201; [L660] SORT_11 var_208_arg_1 = var_207; [L661] SORT_1 var_208 = var_208_arg_0 < var_208_arg_1; [L662] SORT_1 var_209_arg_0 = var_198; [L663] SORT_1 var_209_arg_1 = var_208; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_209_arg_0=-1, var_209_arg_1=0, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L664] EXPR var_209_arg_0 | var_209_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L664] SORT_1 var_209 = var_209_arg_0 | var_209_arg_1; [L665] SORT_1 var_210_arg_0 = state_31; [L666] SORT_1 var_210_arg_1 = var_209; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_210_arg_0=0, var_210_arg_1=255, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L667] EXPR var_210_arg_0 & var_210_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L667] SORT_1 var_210 = var_210_arg_0 & var_210_arg_1; [L668] SORT_1 var_211_arg_0 = var_32; [L669] SORT_1 var_211_arg_1 = var_210; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_211_arg_0=0, var_211_arg_1=0, var_216=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L670] EXPR var_211_arg_0 & var_211_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_216=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L670] SORT_1 var_211 = var_211_arg_0 & var_211_arg_1; [L671] EXPR var_211 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_216=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L671] var_211 = var_211 & mask_SORT_1 [L672] SORT_1 var_217_arg_0 = var_216; [L673] SORT_1 var_217_arg_1 = var_211; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_217_arg_0=0, var_217_arg_1=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L674] EXPR ((SORT_5)var_217_arg_0 << 1) | var_217_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L674] SORT_5 var_217 = ((SORT_5)var_217_arg_0 << 1) | var_217_arg_1; [L675] EXPR var_217 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L675] var_217 = var_217 & mask_SORT_5 [L676] SORT_5 var_218_arg_0 = var_217; [L677] SORT_1 var_218 = var_218_arg_0 != 0; [L678] SORT_1 var_423_arg_0 = var_218; [L679] SORT_1 var_423_arg_1 = var_174; [L680] SORT_1 var_423_arg_2 = state_31; [L681] SORT_1 var_423 = var_423_arg_0 ? var_423_arg_1 : var_423_arg_2; [L682] SORT_1 var_424_arg_0 = input_9; [L683] SORT_1 var_424_arg_1 = var_110; [L684] SORT_1 var_424_arg_2 = var_423; [L685] SORT_1 var_424 = var_424_arg_0 ? var_424_arg_1 : var_424_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_424=0, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L686] EXPR var_424 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L686] var_424 = var_424 & mask_SORT_1 [L687] SORT_1 next_425_arg_1 = var_424; [L688] SORT_1 var_269_arg_0 = var_92; [L689] SORT_1 var_269_arg_1 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_269_arg_0=0, var_269_arg_1=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L690] EXPR var_269_arg_0 | var_269_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L690] SORT_1 var_269 = var_269_arg_0 | var_269_arg_1; [L691] SORT_1 var_270_arg_0 = var_269; [L692] SORT_1 var_270_arg_1 = input_9; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270_arg_0=0, var_270_arg_1=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L693] EXPR var_270_arg_0 | var_270_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L693] SORT_1 var_270 = var_270_arg_0 | var_270_arg_1; [L694] EXPR var_270 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L694] var_270 = var_270 & mask_SORT_1 [L695] SORT_1 var_281_arg_0 = var_92; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_281_arg_0=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L696] EXPR var_281_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L696] var_281_arg_0 = var_281_arg_0 & mask_SORT_1 [L697] SORT_15 var_281 = var_281_arg_0; [L698] SORT_15 var_282_arg_0 = state_45; [L699] SORT_15 var_282_arg_1 = var_281; [L700] SORT_15 var_282 = var_282_arg_0 + var_282_arg_1; [L701] SORT_1 var_426_arg_0 = var_270; [L702] SORT_15 var_426_arg_1 = var_282; [L703] SORT_15 var_426_arg_2 = state_45; [L704] SORT_15 var_426 = var_426_arg_0 ? var_426_arg_1 : var_426_arg_2; [L705] SORT_1 var_427_arg_0 = input_9; [L706] SORT_15 var_427_arg_1 = var_99; [L707] SORT_15 var_427_arg_2 = var_426; [L708] SORT_15 var_427 = var_427_arg_0 ? var_427_arg_1 : var_427_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_427=0, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L709] EXPR var_427 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L709] var_427 = var_427 & mask_SORT_15 [L710] SORT_15 next_428_arg_1 = var_427; [L711] SORT_1 var_275_arg_0 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_275_arg_0=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L712] EXPR var_275_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L712] var_275_arg_0 = var_275_arg_0 & mask_SORT_1 [L713] SORT_15 var_275 = var_275_arg_0; [L714] SORT_15 var_276_arg_0 = state_48; [L715] SORT_15 var_276_arg_1 = var_275; [L716] SORT_15 var_276 = var_276_arg_0 + var_276_arg_1; [L717] SORT_1 var_429_arg_0 = var_270; [L718] SORT_15 var_429_arg_1 = var_276; [L719] SORT_15 var_429_arg_2 = state_48; [L720] SORT_15 var_429 = var_429_arg_0 ? var_429_arg_1 : var_429_arg_2; [L721] SORT_1 var_430_arg_0 = input_9; [L722] SORT_15 var_430_arg_1 = var_99; [L723] SORT_15 var_430_arg_2 = var_429; [L724] SORT_15 var_430 = var_430_arg_0 ? var_430_arg_1 : var_430_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_430=0, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L725] EXPR var_430 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L725] var_430 = var_430 & mask_SORT_15 [L726] SORT_15 next_431_arg_1 = var_430; [L727] SORT_11 var_438_arg_0 = var_410; [L728] SORT_1 var_438 = var_438_arg_0 != 0; [L729] SORT_3 var_256_arg_0 = input_4; [L730] SORT_11 var_256 = var_256_arg_0 >> 0; [L731] SORT_11* var_47_arg_0 = state_44; [L732] SORT_12 var_47_arg_1 = var_46; [L733] EXPR var_47_arg_0[(unsigned char) var_47_arg_1] [L733] SORT_11 var_47 = var_47_arg_0[(unsigned char) var_47_arg_1]; [L734] SORT_1 var_288_arg_0 = var_92; [L735] SORT_11 var_288_arg_1 = var_256; [L736] SORT_11 var_288_arg_2 = var_47; [L737] SORT_11 var_288 = var_288_arg_0 ? var_288_arg_1 : var_288_arg_2; [L738] SORT_11 var_435_arg_0 = var_288; [L739] SORT_11 var_435_arg_1 = var_410; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_435_arg_0=0, var_435_arg_1=255, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L740] EXPR var_435_arg_0 & var_435_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L740] SORT_11 var_435 = var_435_arg_0 & var_435_arg_1; [L741] SORT_11* var_432_arg_0 = state_44; [L742] SORT_12 var_432_arg_1 = var_46; [L743] EXPR var_432_arg_0[(unsigned char) var_432_arg_1] [L743] SORT_11 var_432 = var_432_arg_0[(unsigned char) var_432_arg_1]; [L744] SORT_11 var_433_arg_0 = var_410; [L745] SORT_11 var_433 = ~var_433_arg_0; [L746] SORT_11 var_434_arg_0 = var_432; [L747] SORT_11 var_434_arg_1 = var_433; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_434_arg_0=0, var_434_arg_1=-256, var_435=0, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L748] EXPR var_434_arg_0 & var_434_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_435=0, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L748] SORT_11 var_434 = var_434_arg_0 & var_434_arg_1; [L749] SORT_11 var_436_arg_0 = var_435; [L750] SORT_11 var_436_arg_1 = var_434; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_436_arg_0=0, var_436_arg_1=0, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L751] EXPR var_436_arg_0 | var_436_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L751] SORT_11 var_436 = var_436_arg_0 | var_436_arg_1; [L752] SORT_11* var_437_arg_0 = state_44; [L753] SORT_12 var_437_arg_1 = var_46; [L754] SORT_11 var_437_arg_2 = var_436; [L755] SORT_13 var_437; [L756] unsigned char i = 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=8, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND FALSE !(i < (1 << 3)) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L757] var_437[(unsigned char) var_437_arg_1] = var_437_arg_2 [L758] SORT_1 var_439_arg_0 = var_438; [L759] SORT_11* var_439_arg_1 = var_437; [L760] SORT_11* var_439_arg_2 = state_44; [L761] SORT_11* var_439 = var_439_arg_0 ? var_439_arg_1 : var_439_arg_2; [L762] SORT_11* next_440_arg_1 = var_439; [L763] SORT_1 var_187_arg_0 = var_174; [L764] SORT_1 var_187 = ~var_187_arg_0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_187=-1, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_59=0, var_92=0, var_93=-1, var_99=0] [L765] EXPR var_187 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_59=0, var_92=0, var_93=-1, var_99=0] [L765] var_187 = var_187 & mask_SORT_1 [L766] SORT_1 var_188_arg_0 = var_187; [L767] SORT_1 var_188_arg_1 = var_59; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_188_arg_0=0, var_188_arg_1=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_92=0, var_93=-1, var_99=0] [L768] EXPR var_188_arg_0 | var_188_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_92=0, var_93=-1, var_99=0] [L768] SORT_1 var_188 = var_188_arg_0 | var_188_arg_1; [L769] EXPR var_188 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_92=0, var_93=-1, var_99=0] [L769] var_188 = var_188 & mask_SORT_1 [L770] SORT_1 var_441_arg_0 = var_188; [L771] SORT_11 var_441_arg_1 = var_184; [L772] SORT_11 var_441_arg_2 = state_55; [L773] SORT_11 var_441 = var_441_arg_0 ? var_441_arg_1 : var_441_arg_2; [L774] SORT_1 var_442_arg_0 = input_9; [L775] SORT_11 var_442_arg_1 = var_183; [L776] SORT_11 var_442_arg_2 = var_441; [L777] SORT_11 var_442 = var_442_arg_0 ? var_442_arg_1 : var_442_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_442=0, var_92=0, var_93=-1, var_99=0] [L778] EXPR var_442 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_92=0, var_93=-1, var_99=0] [L778] var_442 = var_442 & mask_SORT_11 [L779] SORT_11 next_443_arg_1 = var_442; [L780] SORT_1 var_365_arg_0 = input_10; [L781] SORT_1 var_365_arg_1 = var_92; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365_arg_0=0, var_365_arg_1=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L782] EXPR var_365_arg_0 & var_365_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L782] SORT_1 var_365 = var_365_arg_0 & var_365_arg_1; [L783] SORT_1 var_366_arg_0 = state_85; [L784] SORT_1 var_366_arg_1 = var_365; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_366_arg_0=0, var_366_arg_1=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L785] EXPR var_366_arg_0 | var_366_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L785] SORT_1 var_366 = var_366_arg_0 | var_366_arg_1; [L786] SORT_1 var_444_arg_0 = state_85; [L787] SORT_1 var_444_arg_1 = var_109; [L788] SORT_1 var_444_arg_2 = var_366; [L789] SORT_1 var_444 = var_444_arg_0 ? var_444_arg_1 : var_444_arg_2; [L790] SORT_1 var_445_arg_0 = input_9; [L791] SORT_1 var_445_arg_1 = var_110; [L792] SORT_1 var_445_arg_2 = var_444; [L793] SORT_1 var_445 = var_445_arg_0 ? var_445_arg_1 : var_445_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_445=0, var_93=-1, var_99=0] [L794] EXPR var_445 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L794] var_445 = var_445 & mask_SORT_1 [L795] SORT_1 next_446_arg_1 = var_445; [L796] SORT_1 var_376_arg_0 = var_103; [L797] SORT_1 var_376_arg_1 = state_86; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_376_arg_0=0, var_376_arg_1=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L798] EXPR var_376_arg_0 | var_376_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L798] SORT_1 var_376 = var_376_arg_0 | var_376_arg_1; [L799] SORT_1 var_447_arg_0 = input_9; [L800] SORT_1 var_447_arg_1 = var_110; [L801] SORT_1 var_447_arg_2 = var_376; [L802] SORT_1 var_447 = var_447_arg_0 ? var_447_arg_1 : var_447_arg_2; [L803] SORT_1 next_448_arg_1 = var_447; [L804] SORT_1 var_388_arg_0 = var_270; [L805] SORT_1 var_388_arg_1 = state_85; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_388_arg_0=0, var_388_arg_1=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L806] EXPR var_388_arg_0 | var_388_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L806] SORT_1 var_388 = var_388_arg_0 | var_388_arg_1; [L807] EXPR var_388 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L807] var_388 = var_388 & mask_SORT_1 [L808] SORT_1 var_449_arg_0 = var_388; [L809] SORT_15 var_449_arg_1 = var_100; [L810] SORT_15 var_449_arg_2 = state_89; [L811] SORT_15 var_449 = var_449_arg_0 ? var_449_arg_1 : var_449_arg_2; [L812] SORT_1 var_450_arg_0 = input_9; [L813] SORT_15 var_450_arg_1 = var_99; [L814] SORT_15 var_450_arg_2 = var_449; [L815] SORT_15 var_450 = var_450_arg_0 ? var_450_arg_1 : var_450_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_450=0, var_93=-1, var_99=0] [L816] EXPR var_450 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L816] var_450 = var_450 & mask_SORT_15 [L817] SORT_15 next_451_arg_1 = var_450; [L818] SORT_1 var_373_arg_0 = var_365; [L819] SORT_1 var_373_arg_1 = var_93; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_373_arg_0=0, var_373_arg_1=-1, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L820] EXPR var_373_arg_0 & var_373_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L820] SORT_1 var_373 = var_373_arg_0 & var_373_arg_1; [L821] EXPR var_373 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L821] var_373 = var_373 & mask_SORT_1 [L822] SORT_1 var_452_arg_0 = var_373; [L823] SORT_11 var_452_arg_1 = var_256; [L824] SORT_11 var_452_arg_2 = state_105; [L825] SORT_11 var_452 = var_452_arg_0 ? var_452_arg_1 : var_452_arg_2; [L826] SORT_1 var_453_arg_0 = input_9; [L827] SORT_11 var_453_arg_1 = var_183; [L828] SORT_11 var_453_arg_2 = var_452; [L829] SORT_11 var_453 = var_453_arg_0 ? var_453_arg_1 : var_453_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_453=0, var_99=0] [L830] EXPR var_453 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L830] var_453 = var_453 & mask_SORT_11 [L831] SORT_11 next_454_arg_1 = var_453; [L832] SORT_1 next_455_arg_1 = var_110; [L834] state_16 = next_406_arg_1 [L835] state_19 = next_409_arg_1 [L836] unsigned char i = 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND FALSE !(i < (1 << 3)) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L837] state_26 = next_422_arg_1 [L838] state_31 = next_425_arg_1 [L839] state_45 = next_428_arg_1 [L840] state_48 = next_431_arg_1 [L841] unsigned char i = 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND FALSE !(i < (1 << 3)) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L842] state_55 = next_443_arg_1 [L843] state_85 = next_446_arg_1 [L844] state_86 = next_448_arg_1 [L845] state_89 = next_451_arg_1 [L846] state_105 = next_454_arg_1 [L847] state_111 = next_455_arg_1 [L102] input_2 = __VERIFIER_nondet_uchar() [L103] input_4 = __VERIFIER_nondet_ushort() [L104] input_6 = __VERIFIER_nondet_uchar() [L105] input_7 = __VERIFIER_nondet_ushort() [L106] input_8 = __VERIFIER_nondet_uchar() [L107] input_9 = __VERIFIER_nondet_uchar() [L108] EXPR input_9 & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L108] input_9 = input_9 & mask_SORT_1 [L109] input_10 = __VERIFIER_nondet_uchar() [L111] SORT_15 var_52_arg_0 = state_48; [L112] SORT_15 var_52_arg_1 = state_45; [L113] SORT_1 var_52 = var_52_arg_0 == var_52_arg_1; [L114] SORT_1 var_117_arg_0 = var_52; [L115] SORT_1 var_117 = ~var_117_arg_0; [L116] SORT_5 var_51_arg_0 = input_8; [L117] SORT_1 var_51 = var_51_arg_0 >> 0; [L118] SORT_1 var_118_arg_0 = var_51; [L119] SORT_1 var_118 = ~var_118_arg_0; [L120] SORT_1 var_119_arg_0 = var_117; [L121] SORT_1 var_119_arg_1 = var_118; VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_119_arg_0=-2, var_119_arg_1=-2, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L122] EXPR var_119_arg_0 | var_119_arg_1 VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L122] SORT_1 var_119 = var_119_arg_0 | var_119_arg_1; [L123] SORT_1 var_120_arg_0 = var_109; [L124] SORT_1 var_120 = ~var_120_arg_0; [L125] SORT_1 var_121_arg_0 = var_119; [L126] SORT_1 var_121_arg_1 = var_120; VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_121_arg_0=254, var_121_arg_1=-2, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L127] EXPR var_121_arg_0 | var_121_arg_1 VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L127] SORT_1 var_121 = var_121_arg_0 | var_121_arg_1; [L128] EXPR var_121 & mask_SORT_1 VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L128] var_121 = var_121 & mask_SORT_1 [L129] SORT_1 constr_122_arg_0 = var_121; VAL [constr_122_arg_0=1, input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L130] CALL assume_abort_if_not(constr_122_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L130] RET assume_abort_if_not(constr_122_arg_0) VAL [constr_122_arg_0=1, input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L131] SORT_15 var_23_arg_0 = state_19; [L132] SORT_15 var_23_arg_1 = state_16; [L133] SORT_1 var_23 = var_23_arg_0 == var_23_arg_1; [L134] SORT_1 var_123_arg_0 = var_23; [L135] SORT_1 var_123 = ~var_123_arg_0; [L136] SORT_5 var_22_arg_0 = input_8; [L137] SORT_1 var_22 = var_22_arg_0 >> 1; [L138] SORT_1 var_124_arg_0 = var_22; [L139] SORT_1 var_124 = ~var_124_arg_0; [L140] SORT_1 var_125_arg_0 = var_123; [L141] SORT_1 var_125_arg_1 = var_124; VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_125_arg_0=-2, var_125_arg_1=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L142] EXPR var_125_arg_0 | var_125_arg_1 VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L142] SORT_1 var_125 = var_125_arg_0 | var_125_arg_1; [L143] SORT_1 var_126_arg_0 = var_109; [L144] SORT_1 var_126 = ~var_126_arg_0; [L145] SORT_1 var_127_arg_0 = var_125; [L146] SORT_1 var_127_arg_1 = var_126; VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_127_arg_0=256, var_127_arg_1=-2, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L147] EXPR var_127_arg_0 | var_127_arg_1 VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L147] SORT_1 var_127 = var_127_arg_0 | var_127_arg_1; [L148] EXPR var_127 & mask_SORT_1 VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L148] var_127 = var_127 & mask_SORT_1 [L149] SORT_1 constr_128_arg_0 = var_127; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L150] CALL assume_abort_if_not(constr_128_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L150] RET assume_abort_if_not(constr_128_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L151] SORT_15 var_49_arg_0 = state_48; [L152] SORT_12 var_49 = var_49_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_49=0, var_51=1, var_52=1, var_99=0] [L153] EXPR var_49 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L153] var_49 = var_49 & mask_SORT_12 [L154] SORT_15 var_46_arg_0 = state_45; [L155] SORT_12 var_46 = var_46_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L156] EXPR var_46 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_49=0, var_51=1, var_52=1, var_99=0] [L156] var_46 = var_46 & mask_SORT_12 [L157] SORT_12 var_73_arg_0 = var_49; [L158] SORT_12 var_73_arg_1 = var_46; [L159] SORT_1 var_73 = var_73_arg_0 == var_73_arg_1; [L160] SORT_15 var_74_arg_0 = state_48; [L161] SORT_1 var_74 = var_74_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_99=0] [L162] EXPR var_74 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_99=0] [L162] var_74 = var_74 & mask_SORT_1 [L163] SORT_15 var_75_arg_0 = state_45; [L164] SORT_1 var_75 = var_75_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_75=0, var_99=0] [L165] EXPR var_75 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_99=0] [L165] var_75 = var_75 & mask_SORT_1 [L166] SORT_1 var_76_arg_0 = var_74; [L167] SORT_1 var_76_arg_1 = var_75; [L168] SORT_1 var_76 = var_76_arg_0 != var_76_arg_1; [L169] SORT_1 var_77_arg_0 = var_73; [L170] SORT_1 var_77_arg_1 = var_76; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_77_arg_0=1, var_77_arg_1=0, var_99=0] [L171] EXPR var_77_arg_0 & var_77_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L171] SORT_1 var_77 = var_77_arg_0 & var_77_arg_1; [L172] EXPR var_77 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L172] var_77 = var_77 & mask_SORT_1 [L173] SORT_1 var_129_arg_0 = var_77; [L174] SORT_1 var_129 = ~var_129_arg_0; [L175] SORT_5 var_92_arg_0 = input_6; [L176] SORT_1 var_92 = var_92_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_129=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L177] EXPR var_92 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_129=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L177] var_92 = var_92 & mask_SORT_1 [L178] SORT_1 var_130_arg_0 = var_92; [L179] SORT_1 var_130 = ~var_130_arg_0; [L180] SORT_1 var_131_arg_0 = var_129; [L181] SORT_1 var_131_arg_1 = var_130; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_131_arg_0=-1, var_131_arg_1=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L182] EXPR var_131_arg_0 | var_131_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L182] SORT_1 var_131 = var_131_arg_0 | var_131_arg_1; [L183] SORT_1 var_132_arg_0 = var_109; [L184] SORT_1 var_132 = ~var_132_arg_0; [L185] SORT_1 var_133_arg_0 = var_131; [L186] SORT_1 var_133_arg_1 = var_132; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_133_arg_0=255, var_133_arg_1=-2, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L187] EXPR var_133_arg_0 | var_133_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L187] SORT_1 var_133 = var_133_arg_0 | var_133_arg_1; [L188] EXPR var_133 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L188] var_133 = var_133 & mask_SORT_1 [L189] SORT_1 constr_134_arg_0 = var_133; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L190] CALL assume_abort_if_not(constr_134_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L190] RET assume_abort_if_not(constr_134_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L191] SORT_15 var_20_arg_0 = state_19; [L192] SORT_12 var_20 = var_20_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L193] EXPR var_20 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L193] var_20 = var_20 & mask_SORT_12 [L194] SORT_15 var_17_arg_0 = state_16; [L195] SORT_12 var_17 = var_17_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L196] EXPR var_17 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L196] var_17 = var_17 & mask_SORT_12 [L197] SORT_12 var_78_arg_0 = var_20; [L198] SORT_12 var_78_arg_1 = var_17; [L199] SORT_1 var_78 = var_78_arg_0 == var_78_arg_1; [L200] SORT_15 var_79_arg_0 = state_19; [L201] SORT_1 var_79 = var_79_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_92=0, var_99=0] [L202] EXPR var_79 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_92=0, var_99=0] [L202] var_79 = var_79 & mask_SORT_1 [L203] SORT_15 var_80_arg_0 = state_16; [L204] SORT_1 var_80 = var_80_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_80=0, var_92=0, var_99=0] [L205] EXPR var_80 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_92=0, var_99=0] [L205] var_80 = var_80 & mask_SORT_1 [L206] SORT_1 var_81_arg_0 = var_79; [L207] SORT_1 var_81_arg_1 = var_80; [L208] SORT_1 var_81 = var_81_arg_0 != var_81_arg_1; [L209] SORT_1 var_82_arg_0 = var_78; [L210] SORT_1 var_82_arg_1 = var_81; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_82_arg_0=1, var_82_arg_1=0, var_92=0, var_99=0] [L211] EXPR var_82_arg_0 & var_82_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L211] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L212] SORT_1 var_135_arg_0 = var_82; [L213] SORT_1 var_135 = ~var_135_arg_0; [L214] SORT_5 var_136_arg_0 = input_6; [L215] SORT_1 var_136 = var_136_arg_0 >> 1; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_135=-1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L216] EXPR var_136 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_135=-1, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L216] var_136 = var_136 & mask_SORT_1 [L217] SORT_1 var_137_arg_0 = var_136; [L218] SORT_1 var_137 = ~var_137_arg_0; [L219] SORT_1 var_138_arg_0 = var_135; [L220] SORT_1 var_138_arg_1 = var_137; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_138_arg_0=-1, var_138_arg_1=-1, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L221] EXPR var_138_arg_0 | var_138_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L221] SORT_1 var_138 = var_138_arg_0 | var_138_arg_1; [L222] SORT_1 var_139_arg_0 = var_109; [L223] SORT_1 var_139 = ~var_139_arg_0; [L224] SORT_1 var_140_arg_0 = var_138; [L225] SORT_1 var_140_arg_1 = var_139; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_140_arg_0=255, var_140_arg_1=-2, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L226] EXPR var_140_arg_0 | var_140_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L226] SORT_1 var_140 = var_140_arg_0 | var_140_arg_1; [L227] EXPR var_140 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L227] var_140 = var_140 & mask_SORT_1 [L228] SORT_1 constr_141_arg_0 = var_140; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L229] CALL assume_abort_if_not(constr_141_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L229] RET assume_abort_if_not(constr_141_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L230] SORT_1 var_142_arg_0 = state_111; [L231] SORT_1 var_142_arg_1 = input_9; [L232] SORT_1 var_142 = var_142_arg_0 == var_142_arg_1; [L233] SORT_1 var_143_arg_0 = var_109; [L234] SORT_1 var_143 = ~var_143_arg_0; [L235] SORT_1 var_144_arg_0 = var_142; [L236] SORT_1 var_144_arg_1 = var_143; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_144_arg_0=0, var_144_arg_1=-2, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L237] EXPR var_144_arg_0 | var_144_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L237] SORT_1 var_144 = var_144_arg_0 | var_144_arg_1; [L238] EXPR var_144 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L238] var_144 = var_144 & mask_SORT_1 [L239] SORT_1 constr_145_arg_0 = var_144; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L240] CALL assume_abort_if_not(constr_145_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L240] RET assume_abort_if_not(constr_145_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L242] SORT_1 var_113_arg_0 = state_111; [L243] SORT_1 var_113_arg_1 = var_110; [L244] SORT_1 var_113_arg_2 = var_109; [L245] SORT_1 var_113 = var_113_arg_0 ? var_113_arg_1 : var_113_arg_2; [L246] SORT_1 var_87_arg_0 = state_86; [L247] SORT_1 var_87 = ~var_87_arg_0; [L248] SORT_1 var_88_arg_0 = state_85; [L249] SORT_1 var_88_arg_1 = var_87; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_88_arg_0=0, var_88_arg_1=-1, var_92=0, var_99=0] [L250] EXPR var_88_arg_0 & var_88_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L250] SORT_1 var_88 = var_88_arg_0 & var_88_arg_1; [L251] SORT_15 var_90_arg_0 = state_89; [L252] SORT_1 var_90 = var_90_arg_0 != 0; [L253] SORT_1 var_91_arg_0 = var_88; [L254] SORT_1 var_91_arg_1 = var_90; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91_arg_0=0, var_91_arg_1=0, var_92=0, var_99=0] [L255] EXPR var_91_arg_0 & var_91_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L255] SORT_1 var_91 = var_91_arg_0 & var_91_arg_1; [L256] SORT_1 var_93_arg_0 = state_85; [L257] SORT_1 var_93 = ~var_93_arg_0; [L258] SORT_1 var_94_arg_0 = var_92; [L259] SORT_1 var_94_arg_1 = var_93; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_94_arg_0=0, var_94_arg_1=-1, var_99=0] [L260] EXPR var_94_arg_0 & var_94_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_99=0] [L260] SORT_1 var_94 = var_94_arg_0 & var_94_arg_1; [L261] SORT_1 var_95_arg_0 = var_94; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_95_arg_0=0, var_99=0] [L262] EXPR var_95_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_99=0] [L262] var_95_arg_0 = var_95_arg_0 & mask_SORT_1 [L263] SORT_15 var_95 = var_95_arg_0; [L264] SORT_15 var_96_arg_0 = state_89; [L265] SORT_15 var_96_arg_1 = var_95; [L266] SORT_15 var_96 = var_96_arg_0 + var_96_arg_1; [L267] SORT_1 var_53_arg_0 = var_52; [L268] SORT_1 var_53 = ~var_53_arg_0; [L269] SORT_1 var_54_arg_0 = var_51; [L270] SORT_1 var_54_arg_1 = var_53; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54_arg_0=1, var_54_arg_1=-2, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L271] EXPR var_54_arg_0 & var_54_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L271] SORT_1 var_54 = var_54_arg_0 & var_54_arg_1; [L272] EXPR var_54 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L272] var_54 = var_54 & mask_SORT_1 [L273] SORT_15 var_56_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_56_arg_0=8, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L274] EXPR var_56_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L274] var_56_arg_0 = var_56_arg_0 & mask_SORT_15 [L275] SORT_11 var_56 = var_56_arg_0; [L276] SORT_11 var_57_arg_0 = state_55; [L277] SORT_11 var_57_arg_1 = var_56; [L278] SORT_1 var_57 = var_57_arg_0 >= var_57_arg_1; [L279] SORT_1 var_58_arg_0 = var_54; [L280] SORT_1 var_58_arg_1 = var_57; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58_arg_0=0, var_58_arg_1=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L281] EXPR var_58_arg_0 & var_58_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L281] SORT_1 var_58 = var_58_arg_0 & var_58_arg_1; [L282] SORT_1 var_59_arg_0 = state_31; [L283] SORT_1 var_59 = ~var_59_arg_0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58=0, var_59=-1, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L284] EXPR var_59 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L284] var_59 = var_59 & mask_SORT_1 [L285] SORT_1 var_60_arg_0 = var_58; [L286] SORT_1 var_60_arg_1 = var_59; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60_arg_0=0, var_60_arg_1=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L287] EXPR var_60_arg_0 & var_60_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L287] SORT_1 var_60 = var_60_arg_0 & var_60_arg_1; [L288] EXPR var_60 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L288] var_60 = var_60 & mask_SORT_1 [L289] SORT_1 var_97_arg_0 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_97_arg_0=0, var_99=0] [L290] EXPR var_97_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L290] var_97_arg_0 = var_97_arg_0 & mask_SORT_1 [L291] SORT_15 var_97 = var_97_arg_0; [L292] SORT_15 var_98_arg_0 = var_96; [L293] SORT_15 var_98_arg_1 = var_97; [L294] SORT_15 var_98 = var_98_arg_0 - var_98_arg_1; [L295] SORT_1 var_100_arg_0 = input_9; [L296] SORT_15 var_100_arg_1 = var_99; [L297] SORT_15 var_100_arg_2 = var_98; [L298] SORT_15 var_100 = var_100_arg_0 ? var_100_arg_1 : var_100_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_99=0] [L299] EXPR var_100 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_99=0] [L299] var_100 = var_100 & mask_SORT_15 [L300] SORT_15 var_101_arg_0 = var_100; [L301] SORT_1 var_101 = var_101_arg_0 != 0; [L302] SORT_1 var_102_arg_0 = var_101; [L303] SORT_1 var_102 = ~var_102_arg_0; [L304] SORT_1 var_103_arg_0 = var_91; [L305] SORT_1 var_103_arg_1 = var_102; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103_arg_0=0, var_103_arg_1=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L306] EXPR var_103_arg_0 & var_103_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L306] SORT_1 var_103 = var_103_arg_0 & var_103_arg_1; [L307] SORT_1 var_104_arg_0 = var_103; [L308] SORT_1 var_104 = ~var_104_arg_0; [L309] SORT_11* var_21_arg_0 = state_14; [L310] SORT_12 var_21_arg_1 = var_20; [L311] EXPR var_21_arg_0[(unsigned char) var_21_arg_1] [L311] SORT_11 var_21 = var_21_arg_0[(unsigned char) var_21_arg_1]; [L312] SORT_1 var_24_arg_0 = var_23; [L313] SORT_1 var_24 = ~var_24_arg_0; [L314] SORT_1 var_25_arg_0 = var_22; [L315] SORT_1 var_25_arg_1 = var_24; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25_arg_0=0, var_25_arg_1=-2, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L316] EXPR var_25_arg_0 & var_25_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L316] SORT_1 var_25 = var_25_arg_0 & var_25_arg_1; [L317] SORT_15 var_28_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_28_arg_0=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L318] EXPR var_28_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L318] var_28_arg_0 = var_28_arg_0 & mask_SORT_15 [L319] SORT_11 var_28 = var_28_arg_0; [L320] SORT_11 var_29_arg_0 = state_26; [L321] SORT_11 var_29_arg_1 = var_28; [L322] SORT_1 var_29 = var_29_arg_0 >= var_29_arg_1; [L323] SORT_1 var_30_arg_0 = var_25; [L324] SORT_1 var_30_arg_1 = var_29; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_30_arg_0=0, var_30_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L325] EXPR var_30_arg_0 & var_30_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L325] SORT_1 var_30 = var_30_arg_0 & var_30_arg_1; [L326] SORT_1 var_32_arg_0 = var_30; [L327] SORT_1 var_32_arg_1 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32_arg_0=0, var_32_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L328] EXPR var_32_arg_0 & var_32_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L328] SORT_1 var_32 = var_32_arg_0 & var_32_arg_1; [L329] EXPR var_32 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L329] var_32 = var_32 & mask_SORT_1 [L330] SORT_1 var_33_arg_0 = var_32; [L331] SORT_1 var_33_arg_1 = var_32; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_33_arg_0=0, var_33_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L332] EXPR ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L332] SORT_5 var_33 = ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1; [L333] EXPR var_33 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L333] var_33 = var_33 & mask_SORT_5 [L334] SORT_1 var_34_arg_0 = var_32; [L335] SORT_5 var_34_arg_1 = var_33; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_34_arg_0=0, var_34_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L336] EXPR ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L336] SORT_12 var_34 = ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1; [L337] EXPR var_34 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L337] var_34 = var_34 & mask_SORT_12 [L338] SORT_1 var_35_arg_0 = var_32; [L339] SORT_12 var_35_arg_1 = var_34; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_35_arg_0=0, var_35_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L340] EXPR ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L340] SORT_15 var_35 = ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1; [L341] EXPR var_35 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L341] var_35 = var_35 & mask_SORT_15 [L342] SORT_1 var_37_arg_0 = var_32; [L343] SORT_15 var_37_arg_1 = var_35; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_37_arg_0=0, var_37_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L344] EXPR ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L344] SORT_36 var_37 = ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1; [L345] EXPR var_37 & mask_SORT_36 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L345] var_37 = var_37 & mask_SORT_36 [L346] SORT_1 var_39_arg_0 = var_32; [L347] SORT_36 var_39_arg_1 = var_37; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_39_arg_0=0, var_39_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L348] EXPR ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L348] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1; [L349] EXPR var_39 & mask_SORT_38 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L349] var_39 = var_39 & mask_SORT_38 [L350] SORT_1 var_41_arg_0 = var_32; [L351] SORT_38 var_41_arg_1 = var_39; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_41_arg_0=0, var_41_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L352] EXPR ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L352] SORT_40 var_41 = ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1; [L353] EXPR var_41 & mask_SORT_40 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L353] var_41 = var_41 & mask_SORT_40 [L354] SORT_1 var_42_arg_0 = var_32; [L355] SORT_40 var_42_arg_1 = var_41; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_42_arg_0=0, var_42_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L356] EXPR ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L356] SORT_11 var_42 = ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1; [L357] SORT_11 var_43_arg_0 = var_21; [L358] SORT_11 var_43_arg_1 = var_42; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43_arg_0=0, var_43_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L359] EXPR var_43_arg_0 & var_43_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L359] SORT_11 var_43 = var_43_arg_0 & var_43_arg_1; [L360] SORT_11* var_50_arg_0 = state_44; [L361] SORT_12 var_50_arg_1 = var_49; [L362] EXPR var_50_arg_0[(unsigned char) var_50_arg_1] [L362] SORT_11 var_50 = var_50_arg_0[(unsigned char) var_50_arg_1]; [L363] EXPR var_50 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L363] var_50 = var_50 & mask_SORT_11 [L364] SORT_1 var_61_arg_0 = var_60; [L365] SORT_1 var_61_arg_1 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_61_arg_0=0, var_61_arg_1=0, var_92=0, var_93=-1, var_99=0] [L366] EXPR ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L366] SORT_5 var_61 = ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1; [L367] EXPR var_61 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L367] var_61 = var_61 & mask_SORT_5 [L368] SORT_1 var_62_arg_0 = var_60; [L369] SORT_5 var_62_arg_1 = var_61; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_62_arg_0=0, var_62_arg_1=0, var_92=0, var_93=-1, var_99=0] [L370] EXPR ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L370] SORT_12 var_62 = ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1; [L371] EXPR var_62 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L371] var_62 = var_62 & mask_SORT_12 [L372] SORT_1 var_63_arg_0 = var_60; [L373] SORT_12 var_63_arg_1 = var_62; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_63_arg_0=0, var_63_arg_1=0, var_92=0, var_93=-1, var_99=0] [L374] EXPR ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L374] SORT_15 var_63 = ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1; [L375] EXPR var_63 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L375] var_63 = var_63 & mask_SORT_15 [L376] SORT_1 var_64_arg_0 = var_60; [L377] SORT_15 var_64_arg_1 = var_63; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_64_arg_0=0, var_64_arg_1=0, var_92=0, var_93=-1, var_99=0] [L378] EXPR ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L378] SORT_36 var_64 = ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1; [L379] EXPR var_64 & mask_SORT_36 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L379] var_64 = var_64 & mask_SORT_36 [L380] SORT_1 var_65_arg_0 = var_60; [L381] SORT_36 var_65_arg_1 = var_64; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_65_arg_0=0, var_65_arg_1=0, var_92=0, var_93=-1, var_99=0] [L382] EXPR ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L382] SORT_38 var_65 = ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1; [L383] EXPR var_65 & mask_SORT_38 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L383] var_65 = var_65 & mask_SORT_38 [L384] SORT_1 var_66_arg_0 = var_60; [L385] SORT_38 var_66_arg_1 = var_65; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_66_arg_0=0, var_66_arg_1=0, var_92=0, var_93=-1, var_99=0] [L386] EXPR ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L386] SORT_40 var_66 = ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1; [L387] EXPR var_66 & mask_SORT_40 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L387] var_66 = var_66 & mask_SORT_40 [L388] SORT_1 var_67_arg_0 = var_60; [L389] SORT_40 var_67_arg_1 = var_66; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_67_arg_0=0, var_67_arg_1=0, var_92=0, var_93=-1, var_99=0] [L390] EXPR ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L390] SORT_11 var_67 = ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1; [L391] SORT_11 var_68_arg_0 = var_50; [L392] SORT_11 var_68_arg_1 = var_67; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_68_arg_0=0, var_68_arg_1=0, var_92=0, var_93=-1, var_99=0] [L393] EXPR var_68_arg_0 & var_68_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L393] SORT_11 var_68 = var_68_arg_0 & var_68_arg_1; [L394] SORT_11 var_69_arg_0 = var_43; [L395] SORT_11 var_69_arg_1 = var_68; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_69_arg_0=0, var_69_arg_1=0, var_92=0, var_93=-1, var_99=0] [L396] EXPR var_69_arg_0 | var_69_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L396] SORT_11 var_69 = var_69_arg_0 | var_69_arg_1; [L397] EXPR var_69 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L397] var_69 = var_69 & mask_SORT_11 [L398] SORT_11 var_106_arg_0 = state_105; [L399] SORT_11 var_106_arg_1 = var_69; [L400] SORT_1 var_106 = var_106_arg_0 == var_106_arg_1; [L401] SORT_1 var_107_arg_0 = var_104; [L402] SORT_1 var_107_arg_1 = var_106; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_107_arg_0=-1, var_107_arg_1=1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L403] EXPR var_107_arg_0 | var_107_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L403] SORT_1 var_107 = var_107_arg_0 | var_107_arg_1; [L404] SORT_1 var_114_arg_0 = var_107; [L405] SORT_1 var_114 = ~var_114_arg_0; [L406] SORT_1 var_115_arg_0 = var_113; [L407] SORT_1 var_115_arg_1 = var_114; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_115_arg_0=1, var_115_arg_1=-1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L408] EXPR var_115_arg_0 & var_115_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L408] SORT_1 var_115 = var_115_arg_0 & var_115_arg_1; [L409] EXPR var_115 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L409] var_115 = var_115 & mask_SORT_1 [L410] SORT_1 bad_116_arg_0 = var_115; [L411] CALL __VERIFIER_assert(!(bad_116_arg_0)) [L21] COND TRUE !(cond) [L21] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 752 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 479.9s, OverallIterations: 96, TraceHistogramMax: 10, PathProgramHistogramMax: 2, EmptinessCheckTime: 0.6s, AutomataDifference: 65.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 101041 SdHoareTripleChecker+Valid, 47.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 100908 mSDsluCounter, 584091 SdHoareTripleChecker+Invalid, 40.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 480476 mSDsCounter, 289 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 94408 IncrementalHoareTripleChecker+Invalid, 94697 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 289 mSolverCounterUnsat, 103615 mSDtfsCounter, 94408 mSolverCounterSat, 1.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 42665 GetRequests, 41622 SyntacticMatches, 2 SemanticMatches, 1041 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11643 ImplicationChecksByTransitivity, 15.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=27865occurred in iteration=95, InterpolantAutomatonStates: 798, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 9.7s AutomataMinimizationTime, 95 MinimizatonAttempts, 85294 StatesRemovedByMinimization, 47 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 7.7s SsaConstructionTime, 172.4s SatisfiabilityAnalysisTime, 157.3s InterpolantComputationTime, 85496 NumberOfCodeBlocks, 79685 NumberOfCodeBlocksAsserted, 135 NumberOfCheckSat, 102378 ConstructedInterpolants, 0 QuantifiedInterpolants, 358350 SizeOfPredicates, 94 NumberOfNonLiveVariables, 105539 ConjunctsInSsa, 1064 ConjunctsInUnsatCore, 160 InterpolantComputations, 78 PerfectInterpolantSequences, 97658/100452 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2024-12-02 06:11:19,958 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1 --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 1d054f79132e175b09d8c50472a4c24ca52f401c76e1d0704dd5609a369827e2 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-12-02 06:11:22,011 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-12-02 06:11:22,092 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Bitvector.epf [2024-12-02 06:11:22,099 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-12-02 06:11:22,099 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-12-02 06:11:22,121 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-12-02 06:11:22,122 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-12-02 06:11:22,122 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-12-02 06:11:22,123 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-12-02 06:11:22,123 INFO L153 SettingsManager]: * Use memory slicer=true [2024-12-02 06:11:22,123 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-12-02 06:11:22,123 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-12-02 06:11:22,123 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-12-02 06:11:22,123 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-12-02 06:11:22,124 INFO L153 SettingsManager]: * Use SBE=true [2024-12-02 06:11:22,124 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-12-02 06:11:22,124 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-12-02 06:11:22,124 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-12-02 06:11:22,124 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-12-02 06:11:22,124 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-12-02 06:11:22,124 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-12-02 06:11:22,124 INFO L153 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2024-12-02 06:11:22,124 INFO L153 SettingsManager]: * Use bitvectors instead of ints=true [2024-12-02 06:11:22,124 INFO L153 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2024-12-02 06:11:22,125 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-12-02 06:11:22,125 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-12-02 06:11:22,125 INFO L153 SettingsManager]: * Use constant arrays=true [2024-12-02 06:11:22,125 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-12-02 06:11:22,125 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 06:11:22,125 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 06:11:22,125 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 06:11:22,125 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:11:22,125 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-12-02 06:11:22,125 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 06:11:22,125 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 06:11:22,126 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 06:11:22,126 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:11:22,126 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-12-02 06:11:22,126 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-12-02 06:11:22,126 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-12-02 06:11:22,126 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-12-02 06:11:22,126 INFO L153 SettingsManager]: * Trace refinement strategy=FOX [2024-12-02 06:11:22,126 INFO L153 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2024-12-02 06:11:22,126 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-12-02 06:11:22,126 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-12-02 06:11:22,127 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-12-02 06:11:22,127 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-12-02 06:11:22,127 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1d054f79132e175b09d8c50472a4c24ca52f401c76e1d0704dd5609a369827e2 [2024-12-02 06:11:22,349 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-12-02 06:11:22,357 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-12-02 06:11:22,360 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-12-02 06:11:22,361 INFO L270 PluginConnector]: Initializing CDTParser... [2024-12-02 06:11:22,361 INFO L274 PluginConnector]: CDTParser initialized [2024-12-02 06:11:22,363 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-12-02 06:11:25,040 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/data/5b062ba91/e32d3b4a1a0b4ea0a0eb6fbb6c10e576/FLAGcd3d6c025 [2024-12-02 06:11:25,298 INFO L384 CDTParser]: Found 1 translation units. [2024-12-02 06:11:25,299 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-12-02 06:11:25,312 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/data/5b062ba91/e32d3b4a1a0b4ea0a0eb6fbb6c10e576/FLAGcd3d6c025 [2024-12-02 06:11:25,326 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/data/5b062ba91/e32d3b4a1a0b4ea0a0eb6fbb6c10e576 [2024-12-02 06:11:25,328 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-12-02 06:11:25,330 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-12-02 06:11:25,331 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-12-02 06:11:25,331 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-12-02 06:11:25,335 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-12-02 06:11:25,335 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,336 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@340b540a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25, skipping insertion in model container [2024-12-02 06:11:25,336 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,368 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-12-02 06:11:25,500 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c[1268,1281] [2024-12-02 06:11:25,686 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 06:11:25,698 INFO L200 MainTranslator]: Completed pre-run [2024-12-02 06:11:25,709 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c[1268,1281] [2024-12-02 06:11:25,803 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 06:11:25,818 INFO L204 MainTranslator]: Completed translation [2024-12-02 06:11:25,818 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25 WrapperNode [2024-12-02 06:11:25,818 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-12-02 06:11:25,819 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-12-02 06:11:25,820 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-12-02 06:11:25,820 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-12-02 06:11:25,826 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,846 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,893 INFO L138 Inliner]: procedures = 18, calls = 41, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 952 [2024-12-02 06:11:25,893 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-12-02 06:11:25,894 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-12-02 06:11:25,894 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-12-02 06:11:25,894 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-12-02 06:11:25,903 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,903 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,910 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,940 INFO L175 MemorySlicer]: Split 20 memory accesses to 3 slices as follows [2, 9, 9]. 45 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0, 0]. The 8 writes are split as follows [0, 4, 4]. [2024-12-02 06:11:25,941 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,941 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,965 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,967 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,972 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,977 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,981 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,989 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-12-02 06:11:25,990 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-12-02 06:11:25,990 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-12-02 06:11:25,990 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-12-02 06:11:25,991 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25" (1/1) ... [2024-12-02 06:11:25,997 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:11:26,011 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:26,023 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-12-02 06:11:26,026 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-12-02 06:11:26,050 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-12-02 06:11:26,050 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1#0 [2024-12-02 06:11:26,050 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1#1 [2024-12-02 06:11:26,050 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1#2 [2024-12-02 06:11:26,050 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#0 [2024-12-02 06:11:26,051 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#1 [2024-12-02 06:11:26,051 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#2 [2024-12-02 06:11:26,051 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-12-02 06:11:26,051 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-12-02 06:11:26,051 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-12-02 06:11:26,051 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-12-02 06:11:26,051 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-12-02 06:11:26,051 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1#0 [2024-12-02 06:11:26,051 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1#1 [2024-12-02 06:11:26,052 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1#2 [2024-12-02 06:11:26,052 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-12-02 06:11:26,246 INFO L234 CfgBuilder]: Building ICFG [2024-12-02 06:11:26,248 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-12-02 06:11:27,069 INFO L? ?]: Removed 681 outVars from TransFormulas that were not future-live. [2024-12-02 06:11:27,069 INFO L283 CfgBuilder]: Performing block encoding [2024-12-02 06:11:27,079 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-12-02 06:11:27,079 INFO L312 CfgBuilder]: Removed 7 assume(true) statements. [2024-12-02 06:11:27,080 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:11:27 BoogieIcfgContainer [2024-12-02 06:11:27,080 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-12-02 06:11:27,083 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-12-02 06:11:27,083 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-12-02 06:11:27,089 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-12-02 06:11:27,089 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 06:11:25" (1/3) ... [2024-12-02 06:11:27,089 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@43992703 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 06:11:27, skipping insertion in model container [2024-12-02 06:11:27,089 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:11:25" (2/3) ... [2024-12-02 06:11:27,090 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@43992703 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 06:11:27, skipping insertion in model container [2024-12-02 06:11:27,090 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:11:27" (3/3) ... [2024-12-02 06:11:27,091 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-12-02 06:11:27,105 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-12-02 06:11:27,106 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c that has 2 procedures, 42 locations, 1 initial locations, 7 loop locations, and 1 error locations. [2024-12-02 06:11:27,149 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-12-02 06:11:27,160 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@6d1c9d2c, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-12-02 06:11:27,160 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-12-02 06:11:27,164 INFO L276 IsEmpty]: Start isEmpty. Operand has 42 states, 34 states have (on average 1.4705882352941178) internal successors, (50), 35 states have internal predecessors, (50), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:11:27,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2024-12-02 06:11:27,171 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:27,172 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:27,172 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:27,177 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:27,177 INFO L85 PathProgramCache]: Analyzing trace with hash -172425956, now seen corresponding path program 1 times [2024-12-02 06:11:27,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:27,189 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2121152762] [2024-12-02 06:11:27,189 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:11:27,190 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:27,190 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:27,192 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:27,195 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-12-02 06:11:27,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:11:27,639 INFO L256 TraceCheckSpWp]: Trace formula consists of 376 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-12-02 06:11:27,645 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:27,665 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-12-02 06:11:27,665 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:11:27,665 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:27,665 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2121152762] [2024-12-02 06:11:27,666 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2121152762] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:11:27,666 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:11:27,666 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-12-02 06:11:27,668 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1902491860] [2024-12-02 06:11:27,668 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:11:27,671 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-12-02 06:11:27,671 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:27,685 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-12-02 06:11:27,685 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 06:11:27,686 INFO L87 Difference]: Start difference. First operand has 42 states, 34 states have (on average 1.4705882352941178) internal successors, (50), 35 states have internal predecessors, (50), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) Second operand has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:11:27,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:27,701 INFO L93 Difference]: Finished difference Result 77 states and 117 transitions. [2024-12-02 06:11:27,702 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-12-02 06:11:27,703 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) Word has length 39 [2024-12-02 06:11:27,703 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:27,707 INFO L225 Difference]: With dead ends: 77 [2024-12-02 06:11:27,707 INFO L226 Difference]: Without dead ends: 39 [2024-12-02 06:11:27,709 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 38 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 06:11:27,711 INFO L435 NwaCegarLoop]: 49 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 49 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:27,712 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:11:27,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2024-12-02 06:11:27,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2024-12-02 06:11:27,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 32 states have (on average 1.21875) internal successors, (39), 32 states have internal predecessors, (39), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:11:27,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 49 transitions. [2024-12-02 06:11:27,738 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 49 transitions. Word has length 39 [2024-12-02 06:11:27,739 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:27,739 INFO L471 AbstractCegarLoop]: Abstraction has 39 states and 49 transitions. [2024-12-02 06:11:27,739 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:11:27,739 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 49 transitions. [2024-12-02 06:11:27,740 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2024-12-02 06:11:27,741 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:27,741 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:27,752 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-12-02 06:11:27,941 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:27,941 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:27,942 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:27,942 INFO L85 PathProgramCache]: Analyzing trace with hash -1962528174, now seen corresponding path program 1 times [2024-12-02 06:11:27,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:27,943 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1947919425] [2024-12-02 06:11:27,943 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:11:27,943 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:27,943 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:27,945 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:27,946 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-12-02 06:11:28,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:11:28,310 INFO L256 TraceCheckSpWp]: Trace formula consists of 376 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-12-02 06:11:28,314 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:28,339 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:11:28,340 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:11:28,340 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:28,340 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1947919425] [2024-12-02 06:11:28,340 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1947919425] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:11:28,340 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:11:28,340 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:11:28,340 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [858325635] [2024-12-02 06:11:28,340 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:11:28,341 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:11:28,341 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:28,342 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:11:28,342 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:11:28,342 INFO L87 Difference]: Start difference. First operand 39 states and 49 transitions. Second operand has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 3 states have internal predecessors, (17), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:11:28,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:28,364 INFO L93 Difference]: Finished difference Result 76 states and 96 transitions. [2024-12-02 06:11:28,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:11:28,365 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 3 states have internal predecessors, (17), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 39 [2024-12-02 06:11:28,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:28,366 INFO L225 Difference]: With dead ends: 76 [2024-12-02 06:11:28,366 INFO L226 Difference]: Without dead ends: 41 [2024-12-02 06:11:28,366 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:11:28,367 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 44 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 91 SdHoareTripleChecker+Invalid, 6 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:28,367 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 91 Invalid, 6 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:11:28,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2024-12-02 06:11:28,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 40. [2024-12-02 06:11:28,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 33 states have (on average 1.2121212121212122) internal successors, (40), 33 states have internal predecessors, (40), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:11:28,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 50 transitions. [2024-12-02 06:11:28,373 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 50 transitions. Word has length 39 [2024-12-02 06:11:28,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:28,374 INFO L471 AbstractCegarLoop]: Abstraction has 40 states and 50 transitions. [2024-12-02 06:11:28,374 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 3 states have internal predecessors, (17), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:11:28,374 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 50 transitions. [2024-12-02 06:11:28,375 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2024-12-02 06:11:28,375 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:28,375 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:28,385 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-12-02 06:11:28,575 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:28,575 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:28,576 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:28,576 INFO L85 PathProgramCache]: Analyzing trace with hash 482086798, now seen corresponding path program 1 times [2024-12-02 06:11:28,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:28,577 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [522615188] [2024-12-02 06:11:28,577 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:11:28,577 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:28,577 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:28,579 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:28,580 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-12-02 06:11:28,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:11:28,939 INFO L256 TraceCheckSpWp]: Trace formula consists of 381 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-12-02 06:11:28,942 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:28,953 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:11:28,953 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:11:28,954 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:28,954 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [522615188] [2024-12-02 06:11:28,954 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [522615188] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:11:28,954 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:11:28,954 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:11:28,954 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [830474826] [2024-12-02 06:11:28,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:11:28,954 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:11:28,954 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:28,955 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:11:28,955 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:11:28,955 INFO L87 Difference]: Start difference. First operand 40 states and 50 transitions. Second operand has 3 states, 3 states have (on average 6.333333333333333) internal successors, (19), 3 states have internal predecessors, (19), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:11:28,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:28,981 INFO L93 Difference]: Finished difference Result 74 states and 93 transitions. [2024-12-02 06:11:28,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:11:28,982 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 6.333333333333333) internal successors, (19), 3 states have internal predecessors, (19), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 41 [2024-12-02 06:11:28,982 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:28,983 INFO L225 Difference]: With dead ends: 74 [2024-12-02 06:11:28,983 INFO L226 Difference]: Without dead ends: 42 [2024-12-02 06:11:28,983 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:11:28,984 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:28,984 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:11:28,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2024-12-02 06:11:28,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 41. [2024-12-02 06:11:28,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 34 states have (on average 1.2058823529411764) internal successors, (41), 34 states have internal predecessors, (41), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:11:28,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 51 transitions. [2024-12-02 06:11:28,990 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 51 transitions. Word has length 41 [2024-12-02 06:11:28,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:28,990 INFO L471 AbstractCegarLoop]: Abstraction has 41 states and 51 transitions. [2024-12-02 06:11:28,990 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 6.333333333333333) internal successors, (19), 3 states have internal predecessors, (19), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:11:28,991 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 51 transitions. [2024-12-02 06:11:28,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2024-12-02 06:11:28,991 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:28,991 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:29,002 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2024-12-02 06:11:29,192 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:29,192 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:29,192 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:29,193 INFO L85 PathProgramCache]: Analyzing trace with hash -1508766582, now seen corresponding path program 1 times [2024-12-02 06:11:29,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:29,193 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1430845281] [2024-12-02 06:11:29,193 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:11:29,193 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:29,193 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:29,195 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:29,195 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-12-02 06:11:29,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:11:29,543 INFO L256 TraceCheckSpWp]: Trace formula consists of 386 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-12-02 06:11:29,546 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:29,571 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:11:29,571 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:11:29,650 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:11:29,651 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:29,651 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1430845281] [2024-12-02 06:11:29,651 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1430845281] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:11:29,651 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:11:29,651 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-12-02 06:11:29,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [666366351] [2024-12-02 06:11:29,651 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:11:29,651 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:11:29,652 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:29,652 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:11:29,652 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:11:29,652 INFO L87 Difference]: Start difference. First operand 41 states and 51 transitions. Second operand has 7 states, 7 states have (on average 4.0) internal successors, (28), 7 states have internal predecessors, (28), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:11:29,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:29,718 INFO L93 Difference]: Finished difference Result 83 states and 105 transitions. [2024-12-02 06:11:29,719 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:11:29,719 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 4.0) internal successors, (28), 7 states have internal predecessors, (28), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 43 [2024-12-02 06:11:29,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:29,720 INFO L225 Difference]: With dead ends: 83 [2024-12-02 06:11:29,720 INFO L226 Difference]: Without dead ends: 47 [2024-12-02 06:11:29,720 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:11:29,721 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 132 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 179 SdHoareTripleChecker+Invalid, 23 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:29,721 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 179 Invalid, 23 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:11:29,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2024-12-02 06:11:29,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2024-12-02 06:11:29,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 40 states have (on average 1.175) internal successors, (47), 40 states have internal predecessors, (47), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:11:29,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 57 transitions. [2024-12-02 06:11:29,727 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 57 transitions. Word has length 43 [2024-12-02 06:11:29,727 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:29,727 INFO L471 AbstractCegarLoop]: Abstraction has 47 states and 57 transitions. [2024-12-02 06:11:29,728 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 4.0) internal successors, (28), 7 states have internal predecessors, (28), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:11:29,728 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 57 transitions. [2024-12-02 06:11:29,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2024-12-02 06:11:29,728 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:29,729 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:29,740 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-12-02 06:11:29,929 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:29,929 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:29,930 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:29,930 INFO L85 PathProgramCache]: Analyzing trace with hash 1082379582, now seen corresponding path program 2 times [2024-12-02 06:11:29,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:29,930 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [628417043] [2024-12-02 06:11:29,930 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:11:29,930 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:29,930 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:29,932 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:29,933 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-12-02 06:11:30,261 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:11:30,261 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:11:30,264 INFO L256 TraceCheckSpWp]: Trace formula consists of 257 conjuncts, 14 conjuncts are in the unsatisfiable core [2024-12-02 06:11:30,270 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:30,541 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 57 trivial. 0 not checked. [2024-12-02 06:11:30,541 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:11:30,541 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:30,541 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [628417043] [2024-12-02 06:11:30,541 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [628417043] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:11:30,541 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:11:30,541 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:11:30,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021188420] [2024-12-02 06:11:30,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:11:30,542 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:11:30,542 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:30,542 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:11:30,542 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:11:30,543 INFO L87 Difference]: Start difference. First operand 47 states and 57 transitions. Second operand has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:11:30,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:30,730 INFO L93 Difference]: Finished difference Result 61 states and 76 transitions. [2024-12-02 06:11:30,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:11:30,731 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 49 [2024-12-02 06:11:30,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:30,732 INFO L225 Difference]: With dead ends: 61 [2024-12-02 06:11:30,732 INFO L226 Difference]: Without dead ends: 59 [2024-12-02 06:11:30,732 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:11:30,733 INFO L435 NwaCegarLoop]: 37 mSDtfsCounter, 34 mSDsluCounter, 75 mSDsCounter, 0 mSdLazyCounter, 43 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 39 SdHoareTripleChecker+Valid, 112 SdHoareTripleChecker+Invalid, 48 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 43 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:30,733 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [39 Valid, 112 Invalid, 48 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 43 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:11:30,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2024-12-02 06:11:30,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2024-12-02 06:11:30,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 47 states have (on average 1.148936170212766) internal successors, (54), 47 states have internal predecessors, (54), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:11:30,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 74 transitions. [2024-12-02 06:11:30,744 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 74 transitions. Word has length 49 [2024-12-02 06:11:30,745 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:30,745 INFO L471 AbstractCegarLoop]: Abstraction has 59 states and 74 transitions. [2024-12-02 06:11:30,745 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:11:30,745 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 74 transitions. [2024-12-02 06:11:30,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2024-12-02 06:11:30,746 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:30,746 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:30,756 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-12-02 06:11:30,946 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:30,947 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:30,947 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:30,947 INFO L85 PathProgramCache]: Analyzing trace with hash -1262899509, now seen corresponding path program 1 times [2024-12-02 06:11:30,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:30,948 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [718224687] [2024-12-02 06:11:30,948 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:11:30,948 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:30,948 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:30,949 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:30,950 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-12-02 06:11:31,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:11:31,502 INFO L256 TraceCheckSpWp]: Trace formula consists of 1125 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-12-02 06:11:31,517 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:31,529 INFO L134 CoverageAnalysis]: Checked inductivity of 209 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:11:31,529 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:11:31,529 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:31,529 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [718224687] [2024-12-02 06:11:31,529 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [718224687] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:11:31,529 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:11:31,529 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:11:31,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1724153052] [2024-12-02 06:11:31,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:11:31,530 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:11:31,530 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:31,530 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:11:31,530 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:11:31,530 INFO L87 Difference]: Start difference. First operand 59 states and 74 transitions. Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:11:31,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:31,581 INFO L93 Difference]: Finished difference Result 92 states and 116 transitions. [2024-12-02 06:11:31,584 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:11:31,585 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 90 [2024-12-02 06:11:31,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:31,586 INFO L225 Difference]: With dead ends: 92 [2024-12-02 06:11:31,586 INFO L226 Difference]: Without dead ends: 61 [2024-12-02 06:11:31,586 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 89 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:11:31,587 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:31,587 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:11:31,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2024-12-02 06:11:31,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 60. [2024-12-02 06:11:31,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 48 states have (on average 1.1458333333333333) internal successors, (55), 48 states have internal predecessors, (55), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:11:31,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 75 transitions. [2024-12-02 06:11:31,597 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 75 transitions. Word has length 90 [2024-12-02 06:11:31,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:31,598 INFO L471 AbstractCegarLoop]: Abstraction has 60 states and 75 transitions. [2024-12-02 06:11:31,598 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:11:31,598 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 75 transitions. [2024-12-02 06:11:31,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2024-12-02 06:11:31,599 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:31,599 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:31,612 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-12-02 06:11:31,800 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:31,800 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:31,800 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:31,800 INFO L85 PathProgramCache]: Analyzing trace with hash 1332255303, now seen corresponding path program 1 times [2024-12-02 06:11:31,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:31,801 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [837051635] [2024-12-02 06:11:31,801 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:11:31,801 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:31,801 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:31,802 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:31,803 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-12-02 06:11:32,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:11:32,371 INFO L256 TraceCheckSpWp]: Trace formula consists of 1131 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-12-02 06:11:32,374 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:32,391 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2024-12-02 06:11:32,391 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:11:32,391 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:32,391 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [837051635] [2024-12-02 06:11:32,391 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [837051635] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:11:32,391 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:11:32,391 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:11:32,391 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258613270] [2024-12-02 06:11:32,392 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:11:32,392 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:11:32,392 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:32,392 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:11:32,393 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:11:32,393 INFO L87 Difference]: Start difference. First operand 60 states and 75 transitions. Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:11:32,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:32,425 INFO L93 Difference]: Finished difference Result 94 states and 118 transitions. [2024-12-02 06:11:32,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:11:32,427 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 92 [2024-12-02 06:11:32,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:32,428 INFO L225 Difference]: With dead ends: 94 [2024-12-02 06:11:32,428 INFO L226 Difference]: Without dead ends: 62 [2024-12-02 06:11:32,428 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:11:32,429 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:32,429 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:11:32,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2024-12-02 06:11:32,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 61. [2024-12-02 06:11:32,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 49 states have (on average 1.1428571428571428) internal successors, (56), 49 states have internal predecessors, (56), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:11:32,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 76 transitions. [2024-12-02 06:11:32,438 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 76 transitions. Word has length 92 [2024-12-02 06:11:32,438 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:32,438 INFO L471 AbstractCegarLoop]: Abstraction has 61 states and 76 transitions. [2024-12-02 06:11:32,438 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:11:32,438 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 76 transitions. [2024-12-02 06:11:32,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2024-12-02 06:11:32,439 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:32,440 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:32,453 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-12-02 06:11:32,644 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:32,644 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:32,644 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:32,644 INFO L85 PathProgramCache]: Analyzing trace with hash -523258493, now seen corresponding path program 1 times [2024-12-02 06:11:32,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:32,645 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [325923482] [2024-12-02 06:11:32,645 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:11:32,645 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:32,645 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:32,647 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:32,647 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-12-02 06:11:33,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:11:33,203 INFO L256 TraceCheckSpWp]: Trace formula consists of 1137 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-12-02 06:11:33,207 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:33,219 INFO L134 CoverageAnalysis]: Checked inductivity of 211 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 99 trivial. 0 not checked. [2024-12-02 06:11:33,219 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:11:33,219 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:33,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [325923482] [2024-12-02 06:11:33,219 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [325923482] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:11:33,219 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:11:33,219 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:11:33,219 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [116754926] [2024-12-02 06:11:33,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:11:33,220 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:11:33,220 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:33,221 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:11:33,221 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:11:33,221 INFO L87 Difference]: Start difference. First operand 61 states and 76 transitions. Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:11:33,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:33,243 INFO L93 Difference]: Finished difference Result 96 states and 120 transitions. [2024-12-02 06:11:33,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:11:33,243 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 94 [2024-12-02 06:11:33,244 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:33,244 INFO L225 Difference]: With dead ends: 96 [2024-12-02 06:11:33,244 INFO L226 Difference]: Without dead ends: 63 [2024-12-02 06:11:33,244 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 92 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:11:33,245 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:33,245 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:11:33,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2024-12-02 06:11:33,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 62. [2024-12-02 06:11:33,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 50 states have (on average 1.14) internal successors, (57), 50 states have internal predecessors, (57), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:11:33,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 77 transitions. [2024-12-02 06:11:33,257 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 77 transitions. Word has length 94 [2024-12-02 06:11:33,258 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:33,258 INFO L471 AbstractCegarLoop]: Abstraction has 62 states and 77 transitions. [2024-12-02 06:11:33,258 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:11:33,258 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 77 transitions. [2024-12-02 06:11:33,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2024-12-02 06:11:33,259 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:33,259 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:33,267 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2024-12-02 06:11:33,460 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:33,460 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:33,460 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:33,460 INFO L85 PathProgramCache]: Analyzing trace with hash 1675280511, now seen corresponding path program 1 times [2024-12-02 06:11:33,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:33,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [248060261] [2024-12-02 06:11:33,461 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:11:33,461 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:33,461 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:33,463 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:33,463 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-12-02 06:11:34,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:11:34,116 INFO L256 TraceCheckSpWp]: Trace formula consists of 1143 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-12-02 06:11:34,119 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:34,128 INFO L134 CoverageAnalysis]: Checked inductivity of 212 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2024-12-02 06:11:34,128 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:11:34,128 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:34,128 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [248060261] [2024-12-02 06:11:34,128 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [248060261] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:11:34,128 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:11:34,128 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:11:34,128 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84152372] [2024-12-02 06:11:34,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:11:34,129 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:11:34,129 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:34,130 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:11:34,130 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:11:34,130 INFO L87 Difference]: Start difference. First operand 62 states and 77 transitions. Second operand has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:11:34,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:34,151 INFO L93 Difference]: Finished difference Result 98 states and 122 transitions. [2024-12-02 06:11:34,151 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:11:34,151 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 96 [2024-12-02 06:11:34,151 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:34,152 INFO L225 Difference]: With dead ends: 98 [2024-12-02 06:11:34,152 INFO L226 Difference]: Without dead ends: 64 [2024-12-02 06:11:34,152 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:11:34,153 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:34,153 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:11:34,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2024-12-02 06:11:34,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 63. [2024-12-02 06:11:34,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 51 states have (on average 1.1372549019607843) internal successors, (58), 51 states have internal predecessors, (58), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:11:34,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 78 transitions. [2024-12-02 06:11:34,158 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 78 transitions. Word has length 96 [2024-12-02 06:11:34,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:34,158 INFO L471 AbstractCegarLoop]: Abstraction has 63 states and 78 transitions. [2024-12-02 06:11:34,159 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:11:34,159 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 78 transitions. [2024-12-02 06:11:34,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2024-12-02 06:11:34,159 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:34,159 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:34,169 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-12-02 06:11:34,360 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:34,360 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:34,360 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:34,360 INFO L85 PathProgramCache]: Analyzing trace with hash -571376837, now seen corresponding path program 1 times [2024-12-02 06:11:34,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:34,361 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1295094352] [2024-12-02 06:11:34,361 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:11:34,362 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:34,362 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:34,363 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:34,364 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-12-02 06:11:35,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:11:35,017 INFO L256 TraceCheckSpWp]: Trace formula consists of 1149 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-12-02 06:11:35,020 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:35,035 INFO L134 CoverageAnalysis]: Checked inductivity of 213 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 212 trivial. 0 not checked. [2024-12-02 06:11:35,035 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:11:35,106 INFO L134 CoverageAnalysis]: Checked inductivity of 213 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 212 trivial. 0 not checked. [2024-12-02 06:11:35,106 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:35,106 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1295094352] [2024-12-02 06:11:35,106 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1295094352] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:11:35,107 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:11:35,107 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-12-02 06:11:35,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1998102628] [2024-12-02 06:11:35,107 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:11:35,107 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:11:35,107 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:35,108 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:11:35,108 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:11:35,108 INFO L87 Difference]: Start difference. First operand 63 states and 78 transitions. Second operand has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 7 states have internal predecessors, (46), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:11:35,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:35,176 INFO L93 Difference]: Finished difference Result 117 states and 148 transitions. [2024-12-02 06:11:35,176 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:11:35,177 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 7 states have internal predecessors, (46), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 98 [2024-12-02 06:11:35,177 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:35,177 INFO L225 Difference]: With dead ends: 117 [2024-12-02 06:11:35,177 INFO L226 Difference]: Without dead ends: 69 [2024-12-02 06:11:35,177 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 195 GetRequests, 189 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:11:35,178 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 3 mSDsluCounter, 215 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 262 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:35,178 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 262 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:11:35,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2024-12-02 06:11:35,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2024-12-02 06:11:35,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 57 states have (on average 1.1228070175438596) internal successors, (64), 57 states have internal predecessors, (64), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:11:35,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 84 transitions. [2024-12-02 06:11:35,187 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 84 transitions. Word has length 98 [2024-12-02 06:11:35,188 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:35,188 INFO L471 AbstractCegarLoop]: Abstraction has 69 states and 84 transitions. [2024-12-02 06:11:35,188 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 7 states have internal predecessors, (46), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:11:35,188 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 84 transitions. [2024-12-02 06:11:35,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2024-12-02 06:11:35,189 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:35,189 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:35,198 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-12-02 06:11:35,389 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:35,389 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:35,390 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:35,390 INFO L85 PathProgramCache]: Analyzing trace with hash -327439417, now seen corresponding path program 2 times [2024-12-02 06:11:35,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:35,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [999730976] [2024-12-02 06:11:35,390 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:11:35,391 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:35,391 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:35,392 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:35,393 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-12-02 06:11:36,106 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:11:36,106 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:11:36,116 INFO L256 TraceCheckSpWp]: Trace formula consists of 1164 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-12-02 06:11:36,119 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:36,135 INFO L134 CoverageAnalysis]: Checked inductivity of 228 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 115 trivial. 0 not checked. [2024-12-02 06:11:36,135 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:11:36,195 INFO L134 CoverageAnalysis]: Checked inductivity of 228 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 215 trivial. 0 not checked. [2024-12-02 06:11:36,195 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:36,195 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [999730976] [2024-12-02 06:11:36,195 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [999730976] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:11:36,195 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:11:36,195 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-12-02 06:11:36,195 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527058389] [2024-12-02 06:11:36,195 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:11:36,196 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:11:36,196 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:36,196 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:11:36,196 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:11:36,197 INFO L87 Difference]: Start difference. First operand 69 states and 84 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:11:36,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:36,273 INFO L93 Difference]: Finished difference Result 110 states and 136 transitions. [2024-12-02 06:11:36,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:11:36,276 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 104 [2024-12-02 06:11:36,276 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:36,276 INFO L225 Difference]: With dead ends: 110 [2024-12-02 06:11:36,276 INFO L226 Difference]: Without dead ends: 75 [2024-12-02 06:11:36,276 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 207 GetRequests, 201 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:11:36,277 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 86 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 133 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:36,277 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 133 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:11:36,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2024-12-02 06:11:36,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2024-12-02 06:11:36,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 63 states have (on average 1.1111111111111112) internal successors, (70), 63 states have internal predecessors, (70), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:11:36,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 90 transitions. [2024-12-02 06:11:36,283 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 90 transitions. Word has length 104 [2024-12-02 06:11:36,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:36,284 INFO L471 AbstractCegarLoop]: Abstraction has 75 states and 90 transitions. [2024-12-02 06:11:36,284 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:11:36,284 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 90 transitions. [2024-12-02 06:11:36,285 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2024-12-02 06:11:36,285 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:36,285 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:36,295 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-12-02 06:11:36,485 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:36,485 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:36,486 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:36,486 INFO L85 PathProgramCache]: Analyzing trace with hash -1578953669, now seen corresponding path program 3 times [2024-12-02 06:11:36,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:36,487 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [689216107] [2024-12-02 06:11:36,487 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-12-02 06:11:36,487 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:36,487 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:36,488 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:36,489 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-12-02 06:11:37,271 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2024-12-02 06:11:37,272 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:11:37,280 INFO L256 TraceCheckSpWp]: Trace formula consists of 977 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-12-02 06:11:37,284 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:37,297 INFO L134 CoverageAnalysis]: Checked inductivity of 243 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 130 trivial. 0 not checked. [2024-12-02 06:11:37,298 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:11:37,365 INFO L134 CoverageAnalysis]: Checked inductivity of 243 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 230 trivial. 0 not checked. [2024-12-02 06:11:37,365 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:37,365 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [689216107] [2024-12-02 06:11:37,365 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [689216107] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:11:37,366 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:11:37,366 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-12-02 06:11:37,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2059224297] [2024-12-02 06:11:37,366 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:11:37,366 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:11:37,366 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:37,367 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:11:37,367 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:11:37,367 INFO L87 Difference]: Start difference. First operand 75 states and 90 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:11:37,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:37,429 INFO L93 Difference]: Finished difference Result 122 states and 148 transitions. [2024-12-02 06:11:37,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:11:37,430 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 110 [2024-12-02 06:11:37,430 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:37,431 INFO L225 Difference]: With dead ends: 122 [2024-12-02 06:11:37,431 INFO L226 Difference]: Without dead ends: 81 [2024-12-02 06:11:37,431 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 219 GetRequests, 213 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:11:37,431 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 86 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 133 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:37,431 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 133 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:11:37,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2024-12-02 06:11:37,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2024-12-02 06:11:37,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81 states, 69 states have (on average 1.1014492753623188) internal successors, (76), 69 states have internal predecessors, (76), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:11:37,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 96 transitions. [2024-12-02 06:11:37,440 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 96 transitions. Word has length 110 [2024-12-02 06:11:37,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:37,440 INFO L471 AbstractCegarLoop]: Abstraction has 81 states and 96 transitions. [2024-12-02 06:11:37,441 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:11:37,441 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 96 transitions. [2024-12-02 06:11:37,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2024-12-02 06:11:37,442 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:37,442 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:37,456 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-12-02 06:11:37,642 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:37,642 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:37,643 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:37,643 INFO L85 PathProgramCache]: Analyzing trace with hash 710782511, now seen corresponding path program 4 times [2024-12-02 06:11:37,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:37,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2054374702] [2024-12-02 06:11:37,643 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-12-02 06:11:37,643 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:37,643 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:37,645 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:37,646 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-12-02 06:11:38,367 INFO L229 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-12-02 06:11:38,368 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:11:38,377 INFO L256 TraceCheckSpWp]: Trace formula consists of 1154 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-12-02 06:11:38,380 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:38,393 INFO L134 CoverageAnalysis]: Checked inductivity of 258 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2024-12-02 06:11:38,394 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:11:38,449 INFO L134 CoverageAnalysis]: Checked inductivity of 258 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2024-12-02 06:11:38,450 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:38,450 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2054374702] [2024-12-02 06:11:38,450 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2054374702] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:11:38,450 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:11:38,450 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-12-02 06:11:38,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015272692] [2024-12-02 06:11:38,450 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:11:38,450 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:11:38,450 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:38,451 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:11:38,451 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:11:38,451 INFO L87 Difference]: Start difference. First operand 81 states and 96 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:11:38,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:38,515 INFO L93 Difference]: Finished difference Result 134 states and 160 transitions. [2024-12-02 06:11:38,516 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:11:38,516 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 116 [2024-12-02 06:11:38,516 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:38,517 INFO L225 Difference]: With dead ends: 134 [2024-12-02 06:11:38,517 INFO L226 Difference]: Without dead ends: 87 [2024-12-02 06:11:38,517 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 231 GetRequests, 225 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:11:38,518 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 129 mSDsCounter, 0 mSdLazyCounter, 24 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 176 SdHoareTripleChecker+Invalid, 26 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 24 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:38,518 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 176 Invalid, 26 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 24 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:11:38,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2024-12-02 06:11:38,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2024-12-02 06:11:38,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 75 states have (on average 1.0933333333333333) internal successors, (82), 75 states have internal predecessors, (82), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:11:38,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 102 transitions. [2024-12-02 06:11:38,529 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 102 transitions. Word has length 116 [2024-12-02 06:11:38,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:38,530 INFO L471 AbstractCegarLoop]: Abstraction has 87 states and 102 transitions. [2024-12-02 06:11:38,530 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:11:38,530 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 102 transitions. [2024-12-02 06:11:38,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2024-12-02 06:11:38,532 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:38,532 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:38,544 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2024-12-02 06:11:38,732 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:38,732 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:38,733 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:38,733 INFO L85 PathProgramCache]: Analyzing trace with hash -739418781, now seen corresponding path program 5 times [2024-12-02 06:11:38,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:38,734 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1222934127] [2024-12-02 06:11:38,734 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-12-02 06:11:38,734 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:38,734 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:38,735 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:38,736 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-12-02 06:11:51,004 INFO L229 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2024-12-02 06:11:51,004 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:11:51,021 INFO L256 TraceCheckSpWp]: Trace formula consists of 963 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-12-02 06:11:51,026 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:51,044 INFO L134 CoverageAnalysis]: Checked inductivity of 273 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2024-12-02 06:11:51,044 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:11:51,112 INFO L134 CoverageAnalysis]: Checked inductivity of 273 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2024-12-02 06:11:51,112 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:51,112 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1222934127] [2024-12-02 06:11:51,112 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1222934127] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:11:51,112 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:11:51,112 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-12-02 06:11:51,112 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838817139] [2024-12-02 06:11:51,112 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:11:51,113 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:11:51,113 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:51,113 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:11:51,114 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:11:51,114 INFO L87 Difference]: Start difference. First operand 87 states and 102 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:11:51,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:51,231 INFO L93 Difference]: Finished difference Result 146 states and 172 transitions. [2024-12-02 06:11:51,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:11:51,232 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 122 [2024-12-02 06:11:51,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:51,233 INFO L225 Difference]: With dead ends: 146 [2024-12-02 06:11:51,233 INFO L226 Difference]: Without dead ends: 93 [2024-12-02 06:11:51,233 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 243 GetRequests, 237 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:11:51,234 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 3 mSDsluCounter, 215 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 262 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:51,234 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 262 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:11:51,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2024-12-02 06:11:51,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2024-12-02 06:11:51,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93 states, 81 states have (on average 1.0864197530864197) internal successors, (88), 81 states have internal predecessors, (88), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:11:51,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 108 transitions. [2024-12-02 06:11:51,256 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 108 transitions. Word has length 122 [2024-12-02 06:11:51,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:51,257 INFO L471 AbstractCegarLoop]: Abstraction has 93 states and 108 transitions. [2024-12-02 06:11:51,257 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:11:51,257 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 108 transitions. [2024-12-02 06:11:51,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2024-12-02 06:11:51,258 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:51,258 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:51,279 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2024-12-02 06:11:51,459 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:51,459 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:51,459 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:51,459 INFO L85 PathProgramCache]: Analyzing trace with hash -651047657, now seen corresponding path program 6 times [2024-12-02 06:11:51,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:51,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1999693987] [2024-12-02 06:11:51,461 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-12-02 06:11:51,461 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:51,461 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:51,462 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:51,463 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-12-02 06:11:53,840 INFO L229 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2024-12-02 06:11:53,840 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:11:53,859 INFO L256 TraceCheckSpWp]: Trace formula consists of 1124 conjuncts, 44 conjuncts are in the unsatisfiable core [2024-12-02 06:11:53,866 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:54,737 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 12 proven. 34 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2024-12-02 06:11:54,738 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:11:54,845 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:11:54,845 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1999693987] [2024-12-02 06:11:54,845 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1999693987] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:11:54,845 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1112954399] [2024-12-02 06:11:54,845 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-12-02 06:11:54,845 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-12-02 06:11:54,845 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/cvc4 [2024-12-02 06:11:54,847 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-12-02 06:11:54,849 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (17)] Waiting until timeout for monitored process [2024-12-02 06:11:57,225 INFO L229 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2024-12-02 06:11:57,225 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:11:57,248 INFO L256 TraceCheckSpWp]: Trace formula consists of 1124 conjuncts, 44 conjuncts are in the unsatisfiable core [2024-12-02 06:11:57,256 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:11:58,141 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 12 proven. 27 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2024-12-02 06:11:58,141 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:11:58,245 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1112954399] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:11:58,245 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:11:58,245 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 11] total 17 [2024-12-02 06:11:58,245 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1883030532] [2024-12-02 06:11:58,245 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:11:58,245 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2024-12-02 06:11:58,245 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:11:58,246 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2024-12-02 06:11:58,246 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:11:58,246 INFO L87 Difference]: Start difference. First operand 93 states and 108 transitions. Second operand has 17 states, 15 states have (on average 5.133333333333334) internal successors, (77), 16 states have internal predecessors, (77), 5 states have call successors, (16), 1 states have call predecessors, (16), 2 states have return successors, (16), 5 states have call predecessors, (16), 5 states have call successors, (16) [2024-12-02 06:11:59,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:11:59,108 INFO L93 Difference]: Finished difference Result 169 states and 195 transitions. [2024-12-02 06:11:59,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2024-12-02 06:11:59,108 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 15 states have (on average 5.133333333333334) internal successors, (77), 16 states have internal predecessors, (77), 5 states have call successors, (16), 1 states have call predecessors, (16), 2 states have return successors, (16), 5 states have call predecessors, (16), 5 states have call successors, (16) Word has length 128 [2024-12-02 06:11:59,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:11:59,109 INFO L225 Difference]: With dead ends: 169 [2024-12-02 06:11:59,109 INFO L226 Difference]: Without dead ends: 167 [2024-12-02 06:11:59,110 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 244 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=94, Invalid=506, Unknown=0, NotChecked=0, Total=600 [2024-12-02 06:11:59,110 INFO L435 NwaCegarLoop]: 39 mSDtfsCounter, 58 mSDsluCounter, 423 mSDsCounter, 0 mSdLazyCounter, 453 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 63 SdHoareTripleChecker+Valid, 462 SdHoareTripleChecker+Invalid, 457 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 453 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-12-02 06:11:59,110 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [63 Valid, 462 Invalid, 457 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 453 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-12-02 06:11:59,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2024-12-02 06:11:59,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 146. [2024-12-02 06:11:59,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146 states, 129 states have (on average 1.0852713178294573) internal successors, (140), 129 states have internal predecessors, (140), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:11:59,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 170 transitions. [2024-12-02 06:11:59,119 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 170 transitions. Word has length 128 [2024-12-02 06:11:59,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:11:59,120 INFO L471 AbstractCegarLoop]: Abstraction has 146 states and 170 transitions. [2024-12-02 06:11:59,120 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 15 states have (on average 5.133333333333334) internal successors, (77), 16 states have internal predecessors, (77), 5 states have call successors, (16), 1 states have call predecessors, (16), 2 states have return successors, (16), 5 states have call predecessors, (16), 5 states have call successors, (16) [2024-12-02 06:11:59,120 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 170 transitions. [2024-12-02 06:11:59,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 202 [2024-12-02 06:11:59,121 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:11:59,121 INFO L218 NwaCegarLoop]: trace histogram [15, 15, 15, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:11:59,135 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0 [2024-12-02 06:11:59,341 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (17)] Ended with exit code 0 [2024-12-02 06:11:59,522 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt [2024-12-02 06:11:59,522 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:11:59,522 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:11:59,523 INFO L85 PathProgramCache]: Analyzing trace with hash -1549169454, now seen corresponding path program 7 times [2024-12-02 06:11:59,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:11:59,524 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1282276535] [2024-12-02 06:11:59,524 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-12-02 06:11:59,524 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:11:59,524 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:11:59,526 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:11:59,526 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-12-02 06:12:00,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:12:00,707 INFO L256 TraceCheckSpWp]: Trace formula consists of 2056 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-12-02 06:12:00,712 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:12:00,759 INFO L134 CoverageAnalysis]: Checked inductivity of 785 backedges. 308 proven. 16 refuted. 0 times theorem prover too weak. 461 trivial. 0 not checked. [2024-12-02 06:12:00,760 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:12:00,951 INFO L134 CoverageAnalysis]: Checked inductivity of 785 backedges. 108 proven. 16 refuted. 0 times theorem prover too weak. 661 trivial. 0 not checked. [2024-12-02 06:12:00,951 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:12:00,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1282276535] [2024-12-02 06:12:00,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1282276535] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:12:00,951 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:12:00,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 13 [2024-12-02 06:12:00,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [652636968] [2024-12-02 06:12:00,951 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:12:00,952 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2024-12-02 06:12:00,952 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:12:00,953 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-12-02 06:12:00,953 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=103, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:12:00,953 INFO L87 Difference]: Start difference. First operand 146 states and 170 transitions. Second operand has 13 states, 13 states have (on average 5.615384615384615) internal successors, (73), 13 states have internal predecessors, (73), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:12:01,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:12:01,234 INFO L93 Difference]: Finished difference Result 262 states and 313 transitions. [2024-12-02 06:12:01,234 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-12-02 06:12:01,234 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 5.615384615384615) internal successors, (73), 13 states have internal predecessors, (73), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 201 [2024-12-02 06:12:01,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:12:01,236 INFO L225 Difference]: With dead ends: 262 [2024-12-02 06:12:01,236 INFO L226 Difference]: Without dead ends: 170 [2024-12-02 06:12:01,237 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 404 GetRequests, 389 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=97, Invalid=175, Unknown=0, NotChecked=0, Total=272 [2024-12-02 06:12:01,237 INFO L435 NwaCegarLoop]: 46 mSDtfsCounter, 5 mSDsluCounter, 301 mSDsCounter, 0 mSdLazyCounter, 77 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5 SdHoareTripleChecker+Valid, 347 SdHoareTripleChecker+Invalid, 82 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 77 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:12:01,238 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [5 Valid, 347 Invalid, 82 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 77 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:12:01,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2024-12-02 06:12:01,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 170. [2024-12-02 06:12:01,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 170 states, 153 states have (on average 1.0849673202614378) internal successors, (166), 153 states have internal predecessors, (166), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:12:01,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 196 transitions. [2024-12-02 06:12:01,262 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 196 transitions. Word has length 201 [2024-12-02 06:12:01,262 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:12:01,262 INFO L471 AbstractCegarLoop]: Abstraction has 170 states and 196 transitions. [2024-12-02 06:12:01,262 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 5.615384615384615) internal successors, (73), 13 states have internal predecessors, (73), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:12:01,262 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 196 transitions. [2024-12-02 06:12:01,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 218 [2024-12-02 06:12:01,265 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:12:01,266 INFO L218 NwaCegarLoop]: trace histogram [16, 16, 15, 15, 15, 8, 8, 8, 8, 8, 8, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:12:01,290 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Ended with exit code 0 [2024-12-02 06:12:01,466 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:12:01,466 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:12:01,466 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:12:01,467 INFO L85 PathProgramCache]: Analyzing trace with hash 831217618, now seen corresponding path program 8 times [2024-12-02 06:12:01,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:12:01,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [540476828] [2024-12-02 06:12:01,468 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:12:01,468 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:12:01,468 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:12:01,469 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:12:01,470 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-12-02 06:12:02,751 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:12:02,751 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:12:02,774 INFO L256 TraceCheckSpWp]: Trace formula consists of 2104 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-12-02 06:12:02,779 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:12:02,819 INFO L134 CoverageAnalysis]: Checked inductivity of 985 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 969 trivial. 0 not checked. [2024-12-02 06:12:02,819 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:12:02,966 INFO L134 CoverageAnalysis]: Checked inductivity of 985 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 969 trivial. 0 not checked. [2024-12-02 06:12:02,966 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:12:02,966 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [540476828] [2024-12-02 06:12:02,966 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [540476828] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:12:02,966 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:12:02,966 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 13 [2024-12-02 06:12:02,966 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [929827006] [2024-12-02 06:12:02,966 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:12:02,967 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2024-12-02 06:12:02,967 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:12:02,967 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-12-02 06:12:02,968 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=103, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:12:02,968 INFO L87 Difference]: Start difference. First operand 170 states and 196 transitions. Second operand has 13 states, 13 states have (on average 4.461538461538462) internal successors, (58), 13 states have internal predecessors, (58), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:12:03,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:12:03,109 INFO L93 Difference]: Finished difference Result 341 states and 398 transitions. [2024-12-02 06:12:03,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-12-02 06:12:03,109 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 4.461538461538462) internal successors, (58), 13 states have internal predecessors, (58), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 217 [2024-12-02 06:12:03,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:12:03,110 INFO L225 Difference]: With dead ends: 341 [2024-12-02 06:12:03,111 INFO L226 Difference]: Without dead ends: 182 [2024-12-02 06:12:03,111 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 436 GetRequests, 421 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=97, Invalid=175, Unknown=0, NotChecked=0, Total=272 [2024-12-02 06:12:03,112 INFO L435 NwaCegarLoop]: 46 mSDtfsCounter, 6 mSDsluCounter, 264 mSDsCounter, 0 mSdLazyCounter, 69 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 6 SdHoareTripleChecker+Valid, 310 SdHoareTripleChecker+Invalid, 74 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 69 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:12:03,112 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [6 Valid, 310 Invalid, 74 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 69 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:12:03,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2024-12-02 06:12:03,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 182. [2024-12-02 06:12:03,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 182 states, 165 states have (on average 1.084848484848485) internal successors, (179), 165 states have internal predecessors, (179), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:12:03,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 209 transitions. [2024-12-02 06:12:03,125 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 209 transitions. Word has length 217 [2024-12-02 06:12:03,125 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:12:03,125 INFO L471 AbstractCegarLoop]: Abstraction has 182 states and 209 transitions. [2024-12-02 06:12:03,125 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 4.461538461538462) internal successors, (58), 13 states have internal predecessors, (58), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:12:03,125 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 209 transitions. [2024-12-02 06:12:03,126 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 226 [2024-12-02 06:12:03,126 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:12:03,127 INFO L218 NwaCegarLoop]: trace histogram [16, 16, 15, 15, 15, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:12:03,142 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Ended with exit code 0 [2024-12-02 06:12:03,327 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:12:03,327 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:12:03,327 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:12:03,328 INFO L85 PathProgramCache]: Analyzing trace with hash 958267074, now seen corresponding path program 9 times [2024-12-02 06:12:03,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:12:03,329 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [419546215] [2024-12-02 06:12:03,329 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-12-02 06:12:03,329 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:12:03,329 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:12:03,330 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:12:03,331 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-12-02 06:12:05,606 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2024-12-02 06:12:05,607 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:12:05,626 INFO L256 TraceCheckSpWp]: Trace formula consists of 1734 conjuncts, 146 conjuncts are in the unsatisfiable core [2024-12-02 06:12:05,644 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:12:11,431 INFO L134 CoverageAnalysis]: Checked inductivity of 1033 backedges. 51 proven. 344 refuted. 0 times theorem prover too weak. 638 trivial. 0 not checked. [2024-12-02 06:12:11,431 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:12:12,245 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:12:12,245 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [419546215] [2024-12-02 06:12:12,245 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [419546215] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:12:12,245 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [2144365236] [2024-12-02 06:12:12,245 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-12-02 06:12:12,245 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-12-02 06:12:12,246 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/cvc4 [2024-12-02 06:12:12,247 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-12-02 06:12:12,249 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (21)] Waiting until timeout for monitored process [2024-12-02 06:12:15,956 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2024-12-02 06:12:15,956 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:12:16,033 INFO L256 TraceCheckSpWp]: Trace formula consists of 1734 conjuncts, 198 conjuncts are in the unsatisfiable core [2024-12-02 06:12:16,058 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:12:47,131 INFO L134 CoverageAnalysis]: Checked inductivity of 1033 backedges. 51 proven. 336 refuted. 0 times theorem prover too weak. 646 trivial. 0 not checked. [2024-12-02 06:12:47,131 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:12:51,643 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 101 [2024-12-02 06:12:51,643 WARN L249 Executor]: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) stderr output: (error "out of memory") [2024-12-02 06:12:51,644 WARN L320 FreeRefinementEngine]: Global settings require throwing the following exception [2024-12-02 06:12:51,674 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (21)] Ended with exit code 0 [2024-12-02 06:12:51,860 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Ended with exit code 0 [2024-12-02 06:12:52,045 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt,20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:12:52,045 FATAL L? ?]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:262) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parseCheckSatResult(Executor.java:281) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Scriptor.checkSat(Scriptor.java:155) at de.uni_freiburg.informatik.ultimate.logic.WrapperScript.checkSat(WrapperScript.java:163) at de.uni_freiburg.informatik.ultimate.logic.WrapperScript.checkSat(WrapperScript.java:163) at de.uni_freiburg.informatik.ultimate.lib.smtlibutils.ManagedScript.checkSat(ManagedScript.java:148) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.MonolithicImplicationChecker.checkImplication(MonolithicImplicationChecker.java:85) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier$PredicateComparison.compare(PredicateUnifier.java:842) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier$PredicateComparison.(PredicateUnifier.java:786) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:374) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:323) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp$UnifyPostprocessor.postprocess(TraceCheckSpWp.java:555) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.predicates.IterativePredicateTransformer.applyPostprocessors(IterativePredicateTransformer.java:416) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.predicates.IterativePredicateTransformer.computeBackwardSequence(IterativePredicateTransformer.java:395) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.predicates.IterativePredicateTransformer.computeWeakestPreconditionSequence(IterativePredicateTransformer.java:267) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp.computeInterpolantsUsingUnsatCore(TraceCheckSpWp.java:325) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp.computeInterpolants(TraceCheckSpWp.java:181) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp.(TraceCheckSpWp.java:160) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleSpWp.construct(IpTcStrategyModuleSpWp.java:106) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleSpWp.construct(IpTcStrategyModuleSpWp.java:1) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleBase.getOrConstruct(IpTcStrategyModuleBase.java:101) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleBase.getInterpolantComputationStatus(IpTcStrategyModuleBase.java:77) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.tryExecuteInterpolantGenerator(AutomatonFreeRefinementEngine.java:267) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.generateProof(AutomatonFreeRefinementEngine.java:148) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.executeStrategy(AutomatonFreeRefinementEngine.java:137) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.(AutomatonFreeRefinementEngine.java:85) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:82) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:317) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:407) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.startCegar(AbstractCegarLoop.java:342) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.runCegar(AbstractCegarLoop.java:324) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.executeCegarLoop(TraceAbstractionStarter.java:428) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.analyseProgram(TraceAbstractionStarter.java:314) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.analyseSequentialProgram(TraceAbstractionStarter.java:275) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:167) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:140) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:132) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:167) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:150) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:127) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:233) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:227) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:144) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:106) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:319) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) Caused by: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: EOF at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1518) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser.do_action(Parser.java:701) at com.github.jhoenicke.javacup.runtime.LRParser.parse(LRParser.java:383) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:258) ... 46 more [2024-12-02 06:12:52,049 INFO L158 Benchmark]: Toolchain (without parser) took 86719.47ms. Allocated memory was 92.3MB in the beginning and 830.5MB in the end (delta: 738.2MB). Free memory was 68.7MB in the beginning and 704.5MB in the end (delta: -635.9MB). Peak memory consumption was 102.9MB. Max. memory is 16.1GB. [2024-12-02 06:12:52,049 INFO L158 Benchmark]: CDTParser took 0.41ms. Allocated memory is still 83.9MB. Free memory is still 47.7MB. There was no memory consumed. Max. memory is 16.1GB. [2024-12-02 06:12:52,049 INFO L158 Benchmark]: CACSL2BoogieTranslator took 487.78ms. Allocated memory is still 92.3MB. Free memory was 68.5MB in the beginning and 62.7MB in the end (delta: 5.7MB). Peak memory consumption was 39.6MB. Max. memory is 16.1GB. [2024-12-02 06:12:52,050 INFO L158 Benchmark]: Boogie Procedure Inliner took 74.18ms. Allocated memory is still 92.3MB. Free memory was 62.7MB in the beginning and 55.5MB in the end (delta: 7.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-12-02 06:12:52,050 INFO L158 Benchmark]: Boogie Preprocessor took 94.94ms. Allocated memory is still 92.3MB. Free memory was 55.5MB in the beginning and 46.8MB in the end (delta: 8.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-12-02 06:12:52,050 INFO L158 Benchmark]: RCFGBuilder took 1090.42ms. Allocated memory was 92.3MB in the beginning and 151.0MB in the end (delta: 58.7MB). Free memory was 46.8MB in the beginning and 71.2MB in the end (delta: -24.4MB). Peak memory consumption was 36.2MB. Max. memory is 16.1GB. [2024-12-02 06:12:52,050 INFO L158 Benchmark]: TraceAbstraction took 84966.05ms. Allocated memory was 151.0MB in the beginning and 830.5MB in the end (delta: 679.5MB). Free memory was 70.7MB in the beginning and 704.5MB in the end (delta: -633.8MB). Peak memory consumption was 48.8MB. Max. memory is 16.1GB. [2024-12-02 06:12:52,051 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.41ms. Allocated memory is still 83.9MB. Free memory is still 47.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 487.78ms. Allocated memory is still 92.3MB. Free memory was 68.5MB in the beginning and 62.7MB in the end (delta: 5.7MB). Peak memory consumption was 39.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 74.18ms. Allocated memory is still 92.3MB. Free memory was 62.7MB in the beginning and 55.5MB in the end (delta: 7.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 94.94ms. Allocated memory is still 92.3MB. Free memory was 55.5MB in the beginning and 46.8MB in the end (delta: 8.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 1090.42ms. Allocated memory was 92.3MB in the beginning and 151.0MB in the end (delta: 58.7MB). Free memory was 46.8MB in the beginning and 71.2MB in the end (delta: -24.4MB). Peak memory consumption was 36.2MB. Max. memory is 16.1GB. * TraceAbstraction took 84966.05ms. Allocated memory was 151.0MB in the beginning and 830.5MB in the end (delta: 679.5MB). Free memory was 70.7MB in the beginning and 704.5MB in the end (delta: -633.8MB). Peak memory consumption was 48.8MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") : de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:262) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_abaae24d-7e37-40a9-8185-081e824b683f/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory")