./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1 --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 37235873cdbfb4a92a6d9a366e7d975c617138dc8eee2f80d6fd06796710e280 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-12-02 06:04:43,023 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-12-02 06:04:43,078 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Default.epf [2024-12-02 06:04:43,084 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-12-02 06:04:43,084 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-12-02 06:04:43,105 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-12-02 06:04:43,106 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-12-02 06:04:43,106 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-12-02 06:04:43,106 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-12-02 06:04:43,107 INFO L153 SettingsManager]: * Use memory slicer=true [2024-12-02 06:04:43,110 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-12-02 06:04:43,110 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-12-02 06:04:43,110 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-12-02 06:04:43,111 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-12-02 06:04:43,111 INFO L153 SettingsManager]: * Use SBE=true [2024-12-02 06:04:43,111 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-12-02 06:04:43,111 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-12-02 06:04:43,111 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-12-02 06:04:43,111 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-12-02 06:04:43,111 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-12-02 06:04:43,111 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-12-02 06:04:43,111 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-12-02 06:04:43,111 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-12-02 06:04:43,111 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-12-02 06:04:43,112 INFO L153 SettingsManager]: * Use constant arrays=true [2024-12-02 06:04:43,112 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-12-02 06:04:43,112 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 06:04:43,112 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 06:04:43,112 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 06:04:43,112 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:04:43,112 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-12-02 06:04:43,112 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 06:04:43,112 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 06:04:43,112 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 06:04:43,112 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:04:43,113 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-12-02 06:04:43,113 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-12-02 06:04:43,113 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-12-02 06:04:43,113 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-12-02 06:04:43,113 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-12-02 06:04:43,113 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-12-02 06:04:43,113 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-12-02 06:04:43,113 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-12-02 06:04:43,113 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-12-02 06:04:43,113 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-12-02 06:04:43,113 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 37235873cdbfb4a92a6d9a366e7d975c617138dc8eee2f80d6fd06796710e280 [2024-12-02 06:04:43,319 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-12-02 06:04:43,326 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-12-02 06:04:43,328 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-12-02 06:04:43,329 INFO L270 PluginConnector]: Initializing CDTParser... [2024-12-02 06:04:43,329 INFO L274 PluginConnector]: CDTParser initialized [2024-12-02 06:04:43,330 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c [2024-12-02 06:04:45,980 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/data/842eaed4f/a3150cf2ea8546bf8f3671c1eda18fb3/FLAG1cf16b732 [2024-12-02 06:04:46,237 INFO L384 CDTParser]: Found 1 translation units. [2024-12-02 06:04:46,238 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c [2024-12-02 06:04:46,249 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/data/842eaed4f/a3150cf2ea8546bf8f3671c1eda18fb3/FLAG1cf16b732 [2024-12-02 06:04:46,550 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/data/842eaed4f/a3150cf2ea8546bf8f3671c1eda18fb3 [2024-12-02 06:04:46,552 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-12-02 06:04:46,553 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-12-02 06:04:46,554 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-12-02 06:04:46,554 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-12-02 06:04:46,557 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-12-02 06:04:46,557 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:46,558 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6ebd1f4a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46, skipping insertion in model container [2024-12-02 06:04:46,558 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:46,575 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-12-02 06:04:46,691 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c[1289,1302] [2024-12-02 06:04:46,800 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 06:04:46,810 INFO L200 MainTranslator]: Completed pre-run [2024-12-02 06:04:46,817 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c[1289,1302] [2024-12-02 06:04:46,891 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 06:04:46,902 INFO L204 MainTranslator]: Completed translation [2024-12-02 06:04:46,903 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46 WrapperNode [2024-12-02 06:04:46,903 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-12-02 06:04:46,903 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-12-02 06:04:46,904 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-12-02 06:04:46,904 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-12-02 06:04:46,908 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:46,922 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:46,994 INFO L138 Inliner]: procedures = 17, calls = 10, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 898 [2024-12-02 06:04:46,994 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-12-02 06:04:46,995 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-12-02 06:04:46,995 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-12-02 06:04:46,995 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-12-02 06:04:47,001 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:47,002 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:47,011 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:47,033 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-12-02 06:04:47,033 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:47,033 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:47,053 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:47,056 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:47,063 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:47,069 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:47,075 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:47,085 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-12-02 06:04:47,086 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-12-02 06:04:47,086 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-12-02 06:04:47,086 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-12-02 06:04:47,087 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46" (1/1) ... [2024-12-02 06:04:47,092 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:04:47,100 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:47,110 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-12-02 06:04:47,112 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-12-02 06:04:47,130 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-12-02 06:04:47,130 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-12-02 06:04:47,130 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-12-02 06:04:47,130 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-12-02 06:04:47,130 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-12-02 06:04:47,130 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-12-02 06:04:47,257 INFO L234 CfgBuilder]: Building ICFG [2024-12-02 06:04:47,259 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-12-02 06:04:48,325 INFO L? ?]: Removed 480 outVars from TransFormulas that were not future-live. [2024-12-02 06:04:48,325 INFO L283 CfgBuilder]: Performing block encoding [2024-12-02 06:04:48,339 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-12-02 06:04:48,339 INFO L312 CfgBuilder]: Removed 1 assume(true) statements. [2024-12-02 06:04:48,340 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:04:48 BoogieIcfgContainer [2024-12-02 06:04:48,340 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-12-02 06:04:48,341 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-12-02 06:04:48,342 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-12-02 06:04:48,345 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-12-02 06:04:48,345 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 06:04:46" (1/3) ... [2024-12-02 06:04:48,346 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@359e1639 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 06:04:48, skipping insertion in model container [2024-12-02 06:04:48,346 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:04:46" (2/3) ... [2024-12-02 06:04:48,346 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@359e1639 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 06:04:48, skipping insertion in model container [2024-12-02 06:04:48,346 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:04:48" (3/3) ... [2024-12-02 06:04:48,347 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.unsafe_analog_estimation_convergence.c [2024-12-02 06:04:48,358 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-12-02 06:04:48,359 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.unsafe_analog_estimation_convergence.c that has 2 procedures, 280 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2024-12-02 06:04:48,403 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-12-02 06:04:48,413 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@27914e46, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-12-02 06:04:48,413 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-12-02 06:04:48,417 INFO L276 IsEmpty]: Start isEmpty. Operand has 280 states, 275 states have (on average 1.4945454545454546) internal successors, (411), 276 states have internal predecessors, (411), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:48,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2024-12-02 06:04:48,430 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:48,431 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:48,431 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:48,435 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:48,436 INFO L85 PathProgramCache]: Analyzing trace with hash -851723277, now seen corresponding path program 1 times [2024-12-02 06:04:48,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:48,441 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [90445458] [2024-12-02 06:04:48,441 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:48,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:48,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:48,744 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-12-02 06:04:48,745 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:48,745 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [90445458] [2024-12-02 06:04:48,746 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [90445458] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:48,746 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1857918276] [2024-12-02 06:04:48,746 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:48,746 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:48,746 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:48,749 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:48,753 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-12-02 06:04:49,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:49,057 INFO L256 TraceCheckSpWp]: Trace formula consists of 678 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-12-02 06:04:49,064 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:49,085 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-12-02 06:04:49,085 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:04:49,085 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1857918276] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:49,085 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:04:49,086 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 2 [2024-12-02 06:04:49,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [530510075] [2024-12-02 06:04:49,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:49,092 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-12-02 06:04:49,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:49,110 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-12-02 06:04:49,110 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 06:04:49,113 INFO L87 Difference]: Start difference. First operand has 280 states, 275 states have (on average 1.4945454545454546) internal successors, (411), 276 states have internal predecessors, (411), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand has 2 states, 2 states have (on average 59.0) internal successors, (118), 2 states have internal predecessors, (118), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:49,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:49,154 INFO L93 Difference]: Finished difference Result 535 states and 798 transitions. [2024-12-02 06:04:49,155 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-12-02 06:04:49,156 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 59.0) internal successors, (118), 2 states have internal predecessors, (118), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) Word has length 123 [2024-12-02 06:04:49,157 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:49,164 INFO L225 Difference]: With dead ends: 535 [2024-12-02 06:04:49,164 INFO L226 Difference]: Without dead ends: 277 [2024-12-02 06:04:49,168 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 124 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 06:04:49,170 INFO L435 NwaCegarLoop]: 410 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 410 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:49,171 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 410 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:49,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277 states. [2024-12-02 06:04:49,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277 to 277. [2024-12-02 06:04:49,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 277 states, 273 states have (on average 1.4871794871794872) internal successors, (406), 273 states have internal predecessors, (406), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:49,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277 states to 277 states and 410 transitions. [2024-12-02 06:04:49,220 INFO L78 Accepts]: Start accepts. Automaton has 277 states and 410 transitions. Word has length 123 [2024-12-02 06:04:49,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:49,221 INFO L471 AbstractCegarLoop]: Abstraction has 277 states and 410 transitions. [2024-12-02 06:04:49,221 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 59.0) internal successors, (118), 2 states have internal predecessors, (118), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:49,221 INFO L276 IsEmpty]: Start isEmpty. Operand 277 states and 410 transitions. [2024-12-02 06:04:49,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2024-12-02 06:04:49,224 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:49,225 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:49,235 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-12-02 06:04:49,425 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable0 [2024-12-02 06:04:49,425 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:49,426 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:49,426 INFO L85 PathProgramCache]: Analyzing trace with hash -912801297, now seen corresponding path program 1 times [2024-12-02 06:04:49,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:49,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [615368924] [2024-12-02 06:04:49,426 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:49,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:49,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:50,381 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-12-02 06:04:50,381 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:50,381 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [615368924] [2024-12-02 06:04:50,381 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [615368924] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:50,381 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:04:50,381 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:04:50,381 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [63413708] [2024-12-02 06:04:50,382 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:50,382 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:04:50,383 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:50,383 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:04:50,383 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:04:50,384 INFO L87 Difference]: Start difference. First operand 277 states and 410 transitions. Second operand has 4 states, 4 states have (on average 29.0) internal successors, (116), 4 states have internal predecessors, (116), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:50,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:50,577 INFO L93 Difference]: Finished difference Result 531 states and 787 transitions. [2024-12-02 06:04:50,578 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:04:50,578 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 29.0) internal successors, (116), 4 states have internal predecessors, (116), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 123 [2024-12-02 06:04:50,578 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:50,580 INFO L225 Difference]: With dead ends: 531 [2024-12-02 06:04:50,580 INFO L226 Difference]: Without dead ends: 276 [2024-12-02 06:04:50,581 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:04:50,581 INFO L435 NwaCegarLoop]: 338 mSDtfsCounter, 380 mSDsluCounter, 340 mSDsCounter, 0 mSdLazyCounter, 140 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 381 SdHoareTripleChecker+Valid, 678 SdHoareTripleChecker+Invalid, 141 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 140 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:50,582 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [381 Valid, 678 Invalid, 141 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 140 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:04:50,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states. [2024-12-02 06:04:50,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 276. [2024-12-02 06:04:50,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 276 states, 272 states have (on average 1.4816176470588236) internal successors, (403), 272 states have internal predecessors, (403), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:50,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 276 states to 276 states and 407 transitions. [2024-12-02 06:04:50,595 INFO L78 Accepts]: Start accepts. Automaton has 276 states and 407 transitions. Word has length 123 [2024-12-02 06:04:50,596 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:50,597 INFO L471 AbstractCegarLoop]: Abstraction has 276 states and 407 transitions. [2024-12-02 06:04:50,597 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 29.0) internal successors, (116), 4 states have internal predecessors, (116), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:50,597 INFO L276 IsEmpty]: Start isEmpty. Operand 276 states and 407 transitions. [2024-12-02 06:04:50,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2024-12-02 06:04:50,599 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:50,599 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:50,599 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-12-02 06:04:50,600 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:50,600 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:50,600 INFO L85 PathProgramCache]: Analyzing trace with hash 355896318, now seen corresponding path program 1 times [2024-12-02 06:04:50,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:50,601 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081146767] [2024-12-02 06:04:50,601 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:50,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:50,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:51,124 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-12-02 06:04:51,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:51,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2081146767] [2024-12-02 06:04:51,124 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2081146767] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:51,124 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:04:51,124 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:04:51,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [809317480] [2024-12-02 06:04:51,124 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:51,125 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:04:51,125 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:51,126 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:04:51,126 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:04:51,127 INFO L87 Difference]: Start difference. First operand 276 states and 407 transitions. Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 4 states have internal predecessors, (117), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:04:51,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:51,195 INFO L93 Difference]: Finished difference Result 530 states and 782 transitions. [2024-12-02 06:04:51,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:04:51,195 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 29.25) internal successors, (117), 4 states have internal predecessors, (117), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 124 [2024-12-02 06:04:51,196 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:51,197 INFO L225 Difference]: With dead ends: 530 [2024-12-02 06:04:51,197 INFO L226 Difference]: Without dead ends: 276 [2024-12-02 06:04:51,198 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:04:51,199 INFO L435 NwaCegarLoop]: 391 mSDtfsCounter, 370 mSDsluCounter, 393 mSDsCounter, 0 mSdLazyCounter, 31 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 370 SdHoareTripleChecker+Valid, 784 SdHoareTripleChecker+Invalid, 31 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 31 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:51,199 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [370 Valid, 784 Invalid, 31 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 31 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:51,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states. [2024-12-02 06:04:51,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 276. [2024-12-02 06:04:51,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 276 states, 272 states have (on average 1.4779411764705883) internal successors, (402), 272 states have internal predecessors, (402), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:51,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 276 states to 276 states and 406 transitions. [2024-12-02 06:04:51,211 INFO L78 Accepts]: Start accepts. Automaton has 276 states and 406 transitions. Word has length 124 [2024-12-02 06:04:51,211 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:51,211 INFO L471 AbstractCegarLoop]: Abstraction has 276 states and 406 transitions. [2024-12-02 06:04:51,212 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 29.25) internal successors, (117), 4 states have internal predecessors, (117), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:04:51,212 INFO L276 IsEmpty]: Start isEmpty. Operand 276 states and 406 transitions. [2024-12-02 06:04:51,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2024-12-02 06:04:51,213 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:51,213 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:51,214 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2024-12-02 06:04:51,214 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:51,214 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:51,214 INFO L85 PathProgramCache]: Analyzing trace with hash 1060880424, now seen corresponding path program 1 times [2024-12-02 06:04:51,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:51,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [393530038] [2024-12-02 06:04:51,215 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:51,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:51,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:51,626 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-12-02 06:04:51,626 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:51,626 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [393530038] [2024-12-02 06:04:51,626 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [393530038] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:51,626 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:04:51,626 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:04:51,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109628565] [2024-12-02 06:04:51,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:51,627 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:04:51,627 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:51,628 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:04:51,628 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:04:51,628 INFO L87 Difference]: Start difference. First operand 276 states and 406 transitions. Second operand has 4 states, 4 states have (on average 29.5) internal successors, (118), 4 states have internal predecessors, (118), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:04:51,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:51,652 INFO L93 Difference]: Finished difference Result 280 states and 410 transitions. [2024-12-02 06:04:51,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:04:51,652 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 29.5) internal successors, (118), 4 states have internal predecessors, (118), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 125 [2024-12-02 06:04:51,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:51,654 INFO L225 Difference]: With dead ends: 280 [2024-12-02 06:04:51,654 INFO L226 Difference]: Without dead ends: 278 [2024-12-02 06:04:51,655 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:04:51,655 INFO L435 NwaCegarLoop]: 404 mSDtfsCounter, 0 mSDsluCounter, 802 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1206 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:51,656 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1206 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:51,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278 states. [2024-12-02 06:04:51,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278 to 278. [2024-12-02 06:04:51,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 278 states, 274 states have (on average 1.4744525547445255) internal successors, (404), 274 states have internal predecessors, (404), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:51,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 278 states to 278 states and 408 transitions. [2024-12-02 06:04:51,665 INFO L78 Accepts]: Start accepts. Automaton has 278 states and 408 transitions. Word has length 125 [2024-12-02 06:04:51,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:51,666 INFO L471 AbstractCegarLoop]: Abstraction has 278 states and 408 transitions. [2024-12-02 06:04:51,666 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 29.5) internal successors, (118), 4 states have internal predecessors, (118), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:04:51,666 INFO L276 IsEmpty]: Start isEmpty. Operand 278 states and 408 transitions. [2024-12-02 06:04:51,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2024-12-02 06:04:51,667 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:51,667 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:51,667 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2024-12-02 06:04:51,668 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:51,668 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:51,668 INFO L85 PathProgramCache]: Analyzing trace with hash -1470749368, now seen corresponding path program 1 times [2024-12-02 06:04:51,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:51,668 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70876759] [2024-12-02 06:04:51,668 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:51,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:51,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:51,916 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-12-02 06:04:51,916 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:51,916 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [70876759] [2024-12-02 06:04:51,916 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [70876759] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:51,916 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:04:51,916 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:04:51,916 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1341266177] [2024-12-02 06:04:51,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:51,917 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:04:51,917 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:51,918 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:04:51,918 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:04:51,918 INFO L87 Difference]: Start difference. First operand 278 states and 408 transitions. Second operand has 4 states, 4 states have (on average 29.75) internal successors, (119), 4 states have internal predecessors, (119), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:04:51,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:51,953 INFO L93 Difference]: Finished difference Result 536 states and 787 transitions. [2024-12-02 06:04:51,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:04:51,954 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 29.75) internal successors, (119), 4 states have internal predecessors, (119), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 126 [2024-12-02 06:04:51,954 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:51,955 INFO L225 Difference]: With dead ends: 536 [2024-12-02 06:04:51,955 INFO L226 Difference]: Without dead ends: 280 [2024-12-02 06:04:51,956 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:04:51,957 INFO L435 NwaCegarLoop]: 404 mSDtfsCounter, 0 mSDsluCounter, 798 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1202 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:51,957 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1202 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:51,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 280 states. [2024-12-02 06:04:51,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 280 to 280. [2024-12-02 06:04:51,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 280 states, 276 states have (on average 1.4710144927536233) internal successors, (406), 276 states have internal predecessors, (406), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:51,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 410 transitions. [2024-12-02 06:04:51,965 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 410 transitions. Word has length 126 [2024-12-02 06:04:51,966 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:51,966 INFO L471 AbstractCegarLoop]: Abstraction has 280 states and 410 transitions. [2024-12-02 06:04:51,966 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 29.75) internal successors, (119), 4 states have internal predecessors, (119), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:04:51,966 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 410 transitions. [2024-12-02 06:04:51,967 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2024-12-02 06:04:51,967 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:51,968 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:51,968 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2024-12-02 06:04:51,968 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:51,968 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:51,968 INFO L85 PathProgramCache]: Analyzing trace with hash 553444609, now seen corresponding path program 1 times [2024-12-02 06:04:51,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:51,968 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339191089] [2024-12-02 06:04:51,969 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:51,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:52,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:52,340 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-12-02 06:04:52,340 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:52,340 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [339191089] [2024-12-02 06:04:52,340 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [339191089] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:52,340 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:04:52,341 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:04:52,341 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [228306384] [2024-12-02 06:04:52,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:52,341 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:04:52,341 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:52,342 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:04:52,342 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:04:52,342 INFO L87 Difference]: Start difference. First operand 280 states and 410 transitions. Second operand has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:04:52,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:52,415 INFO L93 Difference]: Finished difference Result 538 states and 788 transitions. [2024-12-02 06:04:52,415 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:04:52,415 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 127 [2024-12-02 06:04:52,416 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:52,417 INFO L225 Difference]: With dead ends: 538 [2024-12-02 06:04:52,417 INFO L226 Difference]: Without dead ends: 280 [2024-12-02 06:04:52,417 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:04:52,418 INFO L435 NwaCegarLoop]: 391 mSDtfsCounter, 368 mSDsluCounter, 393 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 368 SdHoareTripleChecker+Valid, 784 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:52,418 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [368 Valid, 784 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:52,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 280 states. [2024-12-02 06:04:52,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 280 to 280. [2024-12-02 06:04:52,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 280 states, 276 states have (on average 1.4673913043478262) internal successors, (405), 276 states have internal predecessors, (405), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:52,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 280 states to 280 states and 409 transitions. [2024-12-02 06:04:52,427 INFO L78 Accepts]: Start accepts. Automaton has 280 states and 409 transitions. Word has length 127 [2024-12-02 06:04:52,428 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:52,428 INFO L471 AbstractCegarLoop]: Abstraction has 280 states and 409 transitions. [2024-12-02 06:04:52,428 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:04:52,428 INFO L276 IsEmpty]: Start isEmpty. Operand 280 states and 409 transitions. [2024-12-02 06:04:52,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2024-12-02 06:04:52,429 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:52,429 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:52,429 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2024-12-02 06:04:52,430 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:52,430 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:52,430 INFO L85 PathProgramCache]: Analyzing trace with hash -326343756, now seen corresponding path program 1 times [2024-12-02 06:04:52,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:52,430 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995321142] [2024-12-02 06:04:52,430 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:52,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:52,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:53,501 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-12-02 06:04:53,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:53,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1995321142] [2024-12-02 06:04:53,501 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1995321142] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:53,501 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:04:53,501 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:04:53,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1521506968] [2024-12-02 06:04:53,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:53,502 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:04:53,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:53,502 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:04:53,502 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:04:53,503 INFO L87 Difference]: Start difference. First operand 280 states and 409 transitions. Second operand has 8 states, 8 states have (on average 15.125) internal successors, (121), 8 states have internal predecessors, (121), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:53,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:53,783 INFO L93 Difference]: Finished difference Result 661 states and 970 transitions. [2024-12-02 06:04:53,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:04:53,784 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.125) internal successors, (121), 8 states have internal predecessors, (121), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 128 [2024-12-02 06:04:53,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:53,786 INFO L225 Difference]: With dead ends: 661 [2024-12-02 06:04:53,786 INFO L226 Difference]: Without dead ends: 403 [2024-12-02 06:04:53,787 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:04:53,787 INFO L435 NwaCegarLoop]: 335 mSDtfsCounter, 974 mSDsluCounter, 1154 mSDsCounter, 0 mSdLazyCounter, 301 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 975 SdHoareTripleChecker+Valid, 1489 SdHoareTripleChecker+Invalid, 304 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 301 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:53,787 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [975 Valid, 1489 Invalid, 304 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 301 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:04:53,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 403 states. [2024-12-02 06:04:53,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 403 to 402. [2024-12-02 06:04:53,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 402 states, 398 states have (on average 1.4748743718592965) internal successors, (587), 398 states have internal predecessors, (587), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:53,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 402 states to 402 states and 591 transitions. [2024-12-02 06:04:53,800 INFO L78 Accepts]: Start accepts. Automaton has 402 states and 591 transitions. Word has length 128 [2024-12-02 06:04:53,801 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:53,801 INFO L471 AbstractCegarLoop]: Abstraction has 402 states and 591 transitions. [2024-12-02 06:04:53,801 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.125) internal successors, (121), 8 states have internal predecessors, (121), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:53,801 INFO L276 IsEmpty]: Start isEmpty. Operand 402 states and 591 transitions. [2024-12-02 06:04:53,802 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2024-12-02 06:04:53,802 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:53,803 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:53,803 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2024-12-02 06:04:53,803 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:53,803 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:53,803 INFO L85 PathProgramCache]: Analyzing trace with hash 509903304, now seen corresponding path program 1 times [2024-12-02 06:04:53,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:53,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364134143] [2024-12-02 06:04:53,803 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:53,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:54,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:54,820 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-12-02 06:04:54,820 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:54,820 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364134143] [2024-12-02 06:04:54,820 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364134143] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:54,820 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:04:54,821 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:04:54,821 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369379222] [2024-12-02 06:04:54,821 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:54,821 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:04:54,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:54,822 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:04:54,822 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:04:54,822 INFO L87 Difference]: Start difference. First operand 402 states and 591 transitions. Second operand has 8 states, 8 states have (on average 15.25) internal successors, (122), 8 states have internal predecessors, (122), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:55,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:55,139 INFO L93 Difference]: Finished difference Result 790 states and 1162 transitions. [2024-12-02 06:04:55,139 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:04:55,139 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.25) internal successors, (122), 8 states have internal predecessors, (122), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 129 [2024-12-02 06:04:55,140 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:55,141 INFO L225 Difference]: With dead ends: 790 [2024-12-02 06:04:55,141 INFO L226 Difference]: Without dead ends: 410 [2024-12-02 06:04:55,142 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:04:55,142 INFO L435 NwaCegarLoop]: 331 mSDtfsCounter, 403 mSDsluCounter, 1623 mSDsCounter, 0 mSdLazyCounter, 458 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 405 SdHoareTripleChecker+Valid, 1954 SdHoareTripleChecker+Invalid, 461 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 458 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:55,143 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [405 Valid, 1954 Invalid, 461 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 458 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-12-02 06:04:55,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 410 states. [2024-12-02 06:04:55,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 410 to 407. [2024-12-02 06:04:55,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 407 states, 403 states have (on average 1.4739454094292803) internal successors, (594), 403 states have internal predecessors, (594), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:55,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 407 states to 407 states and 598 transitions. [2024-12-02 06:04:55,156 INFO L78 Accepts]: Start accepts. Automaton has 407 states and 598 transitions. Word has length 129 [2024-12-02 06:04:55,157 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:55,157 INFO L471 AbstractCegarLoop]: Abstraction has 407 states and 598 transitions. [2024-12-02 06:04:55,157 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.25) internal successors, (122), 8 states have internal predecessors, (122), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:55,157 INFO L276 IsEmpty]: Start isEmpty. Operand 407 states and 598 transitions. [2024-12-02 06:04:55,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2024-12-02 06:04:55,159 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:55,159 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:55,159 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2024-12-02 06:04:55,159 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:55,159 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:55,159 INFO L85 PathProgramCache]: Analyzing trace with hash 23793489, now seen corresponding path program 1 times [2024-12-02 06:04:55,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:55,160 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [802351837] [2024-12-02 06:04:55,160 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:55,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:55,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:56,183 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-12-02 06:04:56,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:56,183 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [802351837] [2024-12-02 06:04:56,184 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [802351837] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:56,184 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:04:56,184 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:04:56,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [651070570] [2024-12-02 06:04:56,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:56,184 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:04:56,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:56,185 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:04:56,185 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:04:56,185 INFO L87 Difference]: Start difference. First operand 407 states and 598 transitions. Second operand has 8 states, 8 states have (on average 15.375) internal successors, (123), 8 states have internal predecessors, (123), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:04:56,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:56,653 INFO L93 Difference]: Finished difference Result 1153 states and 1697 transitions. [2024-12-02 06:04:56,653 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:04:56,653 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.375) internal successors, (123), 8 states have internal predecessors, (123), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 130 [2024-12-02 06:04:56,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:56,656 INFO L225 Difference]: With dead ends: 1153 [2024-12-02 06:04:56,656 INFO L226 Difference]: Without dead ends: 768 [2024-12-02 06:04:56,657 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:04:56,657 INFO L435 NwaCegarLoop]: 327 mSDtfsCounter, 1179 mSDsluCounter, 1625 mSDsCounter, 0 mSdLazyCounter, 487 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1181 SdHoareTripleChecker+Valid, 1952 SdHoareTripleChecker+Invalid, 490 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 487 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:56,657 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1181 Valid, 1952 Invalid, 490 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 487 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 06:04:56,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states. [2024-12-02 06:04:56,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 729. [2024-12-02 06:04:56,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 729 states, 723 states have (on average 1.4771784232365146) internal successors, (1068), 723 states have internal predecessors, (1068), 4 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2024-12-02 06:04:56,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 729 states to 729 states and 1076 transitions. [2024-12-02 06:04:56,678 INFO L78 Accepts]: Start accepts. Automaton has 729 states and 1076 transitions. Word has length 130 [2024-12-02 06:04:56,678 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:56,678 INFO L471 AbstractCegarLoop]: Abstraction has 729 states and 1076 transitions. [2024-12-02 06:04:56,678 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.375) internal successors, (123), 8 states have internal predecessors, (123), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:04:56,678 INFO L276 IsEmpty]: Start isEmpty. Operand 729 states and 1076 transitions. [2024-12-02 06:04:56,679 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2024-12-02 06:04:56,679 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:56,679 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:56,679 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2024-12-02 06:04:56,680 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:56,680 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:56,680 INFO L85 PathProgramCache]: Analyzing trace with hash 739383388, now seen corresponding path program 1 times [2024-12-02 06:04:56,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:56,680 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960142960] [2024-12-02 06:04:56,680 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:56,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:56,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:57,550 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-12-02 06:04:57,550 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:57,550 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [960142960] [2024-12-02 06:04:57,550 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [960142960] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:57,550 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:04:57,550 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-12-02 06:04:57,550 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170353548] [2024-12-02 06:04:57,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:57,551 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:04:57,551 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:57,552 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:04:57,552 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:04:57,552 INFO L87 Difference]: Start difference. First operand 729 states and 1076 transitions. Second operand has 9 states, 9 states have (on average 13.777777777777779) internal successors, (124), 9 states have internal predecessors, (124), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:58,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:58,113 INFO L93 Difference]: Finished difference Result 1453 states and 2140 transitions. [2024-12-02 06:04:58,113 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:04:58,114 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 13.777777777777779) internal successors, (124), 9 states have internal predecessors, (124), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 131 [2024-12-02 06:04:58,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:58,117 INFO L225 Difference]: With dead ends: 1453 [2024-12-02 06:04:58,117 INFO L226 Difference]: Without dead ends: 775 [2024-12-02 06:04:58,118 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=161, Unknown=0, NotChecked=0, Total=210 [2024-12-02 06:04:58,119 INFO L435 NwaCegarLoop]: 327 mSDtfsCounter, 1056 mSDsluCounter, 1953 mSDsCounter, 0 mSdLazyCounter, 560 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1058 SdHoareTripleChecker+Valid, 2280 SdHoareTripleChecker+Invalid, 565 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 560 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:58,119 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1058 Valid, 2280 Invalid, 565 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 560 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 06:04:58,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 775 states. [2024-12-02 06:04:58,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 775 to 735. [2024-12-02 06:04:58,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 735 states, 729 states have (on average 1.4732510288065843) internal successors, (1074), 729 states have internal predecessors, (1074), 4 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2024-12-02 06:04:58,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 735 states to 735 states and 1082 transitions. [2024-12-02 06:04:58,148 INFO L78 Accepts]: Start accepts. Automaton has 735 states and 1082 transitions. Word has length 131 [2024-12-02 06:04:58,149 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:58,149 INFO L471 AbstractCegarLoop]: Abstraction has 735 states and 1082 transitions. [2024-12-02 06:04:58,149 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 13.777777777777779) internal successors, (124), 9 states have internal predecessors, (124), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:58,149 INFO L276 IsEmpty]: Start isEmpty. Operand 735 states and 1082 transitions. [2024-12-02 06:04:58,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2024-12-02 06:04:58,151 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:58,151 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:58,151 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2024-12-02 06:04:58,151 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:58,152 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:58,152 INFO L85 PathProgramCache]: Analyzing trace with hash -895861534, now seen corresponding path program 1 times [2024-12-02 06:04:58,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:58,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437153114] [2024-12-02 06:04:58,152 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:58,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:58,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:58,593 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-12-02 06:04:58,593 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:58,593 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437153114] [2024-12-02 06:04:58,594 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437153114] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:04:58,594 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [19947806] [2024-12-02 06:04:58,594 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:58,594 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:58,594 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:04:58,595 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:04:58,597 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-12-02 06:04:58,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:58,924 INFO L256 TraceCheckSpWp]: Trace formula consists of 699 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 06:04:58,928 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:04:58,959 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-02 06:04:58,960 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:04:58,960 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [19947806] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:58,960 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:04:58,960 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 7 [2024-12-02 06:04:58,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [284872271] [2024-12-02 06:04:58,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:58,961 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:04:58,961 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:58,961 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:04:58,961 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:04:58,962 INFO L87 Difference]: Start difference. First operand 735 states and 1082 transitions. Second operand has 6 states, 5 states have (on average 25.6) internal successors, (128), 6 states have internal predecessors, (128), 2 states have call successors, (2), 2 states have call predecessors, (2), 2 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:59,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:59,008 INFO L93 Difference]: Finished difference Result 1434 states and 2111 transitions. [2024-12-02 06:04:59,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:04:59,008 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 25.6) internal successors, (128), 6 states have internal predecessors, (128), 2 states have call successors, (2), 2 states have call predecessors, (2), 2 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) Word has length 132 [2024-12-02 06:04:59,008 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:59,010 INFO L225 Difference]: With dead ends: 1434 [2024-12-02 06:04:59,010 INFO L226 Difference]: Without dead ends: 735 [2024-12-02 06:04:59,011 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 132 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:04:59,012 INFO L435 NwaCegarLoop]: 401 mSDtfsCounter, 0 mSDsluCounter, 1591 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1992 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:59,012 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1992 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:04:59,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 735 states. [2024-12-02 06:04:59,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 735 to 735. [2024-12-02 06:04:59,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 735 states, 729 states have (on average 1.4705075445816187) internal successors, (1072), 729 states have internal predecessors, (1072), 4 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2024-12-02 06:04:59,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 735 states to 735 states and 1080 transitions. [2024-12-02 06:04:59,026 INFO L78 Accepts]: Start accepts. Automaton has 735 states and 1080 transitions. Word has length 132 [2024-12-02 06:04:59,026 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:59,026 INFO L471 AbstractCegarLoop]: Abstraction has 735 states and 1080 transitions. [2024-12-02 06:04:59,026 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 25.6) internal successors, (128), 6 states have internal predecessors, (128), 2 states have call successors, (2), 2 states have call predecessors, (2), 2 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:04:59,026 INFO L276 IsEmpty]: Start isEmpty. Operand 735 states and 1080 transitions. [2024-12-02 06:04:59,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2024-12-02 06:04:59,027 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:59,027 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:59,038 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2024-12-02 06:04:59,228 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:04:59,228 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:59,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:59,229 INFO L85 PathProgramCache]: Analyzing trace with hash 1436739828, now seen corresponding path program 1 times [2024-12-02 06:04:59,229 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:59,229 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [770995240] [2024-12-02 06:04:59,229 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:59,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:59,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:04:59,581 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-12-02 06:04:59,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:04:59,582 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [770995240] [2024-12-02 06:04:59,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [770995240] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:04:59,582 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:04:59,582 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:04:59,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [796725887] [2024-12-02 06:04:59,582 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:04:59,582 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:04:59,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:04:59,583 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:04:59,583 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:04:59,583 INFO L87 Difference]: Start difference. First operand 735 states and 1080 transitions. Second operand has 8 states, 8 states have (on average 15.75) internal successors, (126), 8 states have internal predecessors, (126), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:04:59,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:04:59,859 INFO L93 Difference]: Finished difference Result 1467 states and 2155 transitions. [2024-12-02 06:04:59,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:04:59,859 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.75) internal successors, (126), 8 states have internal predecessors, (126), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 133 [2024-12-02 06:04:59,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:04:59,862 INFO L225 Difference]: With dead ends: 1467 [2024-12-02 06:04:59,862 INFO L226 Difference]: Without dead ends: 763 [2024-12-02 06:04:59,862 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:04:59,863 INFO L435 NwaCegarLoop]: 337 mSDtfsCounter, 445 mSDsluCounter, 1646 mSDsCounter, 0 mSdLazyCounter, 422 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 447 SdHoareTripleChecker+Valid, 1983 SdHoareTripleChecker+Invalid, 424 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 422 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:04:59,863 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [447 Valid, 1983 Invalid, 424 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 422 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:04:59,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 763 states. [2024-12-02 06:04:59,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 763 to 763. [2024-12-02 06:04:59,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 763 states, 757 states have (on average 1.4689564068692207) internal successors, (1112), 757 states have internal predecessors, (1112), 4 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2024-12-02 06:04:59,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 763 states to 763 states and 1120 transitions. [2024-12-02 06:04:59,877 INFO L78 Accepts]: Start accepts. Automaton has 763 states and 1120 transitions. Word has length 133 [2024-12-02 06:04:59,877 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:04:59,877 INFO L471 AbstractCegarLoop]: Abstraction has 763 states and 1120 transitions. [2024-12-02 06:04:59,877 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.75) internal successors, (126), 8 states have internal predecessors, (126), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:04:59,877 INFO L276 IsEmpty]: Start isEmpty. Operand 763 states and 1120 transitions. [2024-12-02 06:04:59,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2024-12-02 06:04:59,880 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:04:59,881 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:04:59,881 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2024-12-02 06:04:59,881 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:04:59,881 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:04:59,881 INFO L85 PathProgramCache]: Analyzing trace with hash 752915177, now seen corresponding path program 1 times [2024-12-02 06:04:59,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:04:59,881 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789979657] [2024-12-02 06:04:59,882 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:04:59,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:04:59,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:00,060 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-12-02 06:05:00,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:00,060 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [789979657] [2024-12-02 06:05:00,060 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [789979657] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:05:00,060 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:05:00,060 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:05:00,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [907591674] [2024-12-02 06:05:00,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:05:00,061 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:05:00,061 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:00,061 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:05:00,061 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:05:00,062 INFO L87 Difference]: Start difference. First operand 763 states and 1120 transitions. Second operand has 5 states, 5 states have (on average 25.4) internal successors, (127), 5 states have internal predecessors, (127), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:05:00,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:00,093 INFO L93 Difference]: Finished difference Result 1464 states and 2150 transitions. [2024-12-02 06:05:00,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:05:00,093 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 25.4) internal successors, (127), 5 states have internal predecessors, (127), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 134 [2024-12-02 06:05:00,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:00,095 INFO L225 Difference]: With dead ends: 1464 [2024-12-02 06:05:00,095 INFO L226 Difference]: Without dead ends: 735 [2024-12-02 06:05:00,096 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:05:00,096 INFO L435 NwaCegarLoop]: 402 mSDtfsCounter, 24 mSDsluCounter, 1194 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 24 SdHoareTripleChecker+Valid, 1596 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:00,097 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [24 Valid, 1596 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:05:00,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 735 states. [2024-12-02 06:05:00,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 735 to 735. [2024-12-02 06:05:00,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 735 states, 729 states have (on average 1.4691358024691359) internal successors, (1071), 729 states have internal predecessors, (1071), 4 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2024-12-02 06:05:00,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 735 states to 735 states and 1079 transitions. [2024-12-02 06:05:00,111 INFO L78 Accepts]: Start accepts. Automaton has 735 states and 1079 transitions. Word has length 134 [2024-12-02 06:05:00,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:00,111 INFO L471 AbstractCegarLoop]: Abstraction has 735 states and 1079 transitions. [2024-12-02 06:05:00,111 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 25.4) internal successors, (127), 5 states have internal predecessors, (127), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:05:00,111 INFO L276 IsEmpty]: Start isEmpty. Operand 735 states and 1079 transitions. [2024-12-02 06:05:00,113 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2024-12-02 06:05:00,113 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:00,113 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:00,113 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2024-12-02 06:05:00,113 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:00,113 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:00,114 INFO L85 PathProgramCache]: Analyzing trace with hash -1626696904, now seen corresponding path program 1 times [2024-12-02 06:05:00,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:00,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510004351] [2024-12-02 06:05:00,114 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:00,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:00,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:00,396 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-12-02 06:05:00,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:05:00,396 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510004351] [2024-12-02 06:05:00,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510004351] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:05:00,397 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:05:00,397 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:05:00,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1314969298] [2024-12-02 06:05:00,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:05:00,397 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:05:00,397 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:05:00,398 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:05:00,398 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:05:00,398 INFO L87 Difference]: Start difference. First operand 735 states and 1079 transitions. Second operand has 6 states, 5 states have (on average 26.0) internal successors, (130), 6 states have internal predecessors, (130), 2 states have call successors, (2), 1 states have call predecessors, (2), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:05:00,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:00,437 INFO L93 Difference]: Finished difference Result 1405 states and 2068 transitions. [2024-12-02 06:05:00,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:05:00,437 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 26.0) internal successors, (130), 6 states have internal predecessors, (130), 2 states have call successors, (2), 1 states have call predecessors, (2), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 134 [2024-12-02 06:05:00,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:00,440 INFO L225 Difference]: With dead ends: 1405 [2024-12-02 06:05:00,440 INFO L226 Difference]: Without dead ends: 735 [2024-12-02 06:05:00,441 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:05:00,441 INFO L435 NwaCegarLoop]: 399 mSDtfsCounter, 0 mSDsluCounter, 1583 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1982 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:00,441 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1982 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:05:00,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 735 states. [2024-12-02 06:05:00,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 735 to 725. [2024-12-02 06:05:00,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 725 states, 719 states have (on average 1.467315716272601) internal successors, (1055), 719 states have internal predecessors, (1055), 4 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2024-12-02 06:05:00,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 725 states to 725 states and 1063 transitions. [2024-12-02 06:05:00,454 INFO L78 Accepts]: Start accepts. Automaton has 725 states and 1063 transitions. Word has length 134 [2024-12-02 06:05:00,454 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:00,454 INFO L471 AbstractCegarLoop]: Abstraction has 725 states and 1063 transitions. [2024-12-02 06:05:00,454 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 26.0) internal successors, (130), 6 states have internal predecessors, (130), 2 states have call successors, (2), 1 states have call predecessors, (2), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:05:00,454 INFO L276 IsEmpty]: Start isEmpty. Operand 725 states and 1063 transitions. [2024-12-02 06:05:00,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2024-12-02 06:05:00,455 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:00,455 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:00,455 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2024-12-02 06:05:00,455 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:00,455 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:00,456 INFO L85 PathProgramCache]: Analyzing trace with hash -576645736, now seen corresponding path program 1 times [2024-12-02 06:05:00,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:05:00,456 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039571142] [2024-12-02 06:05:00,456 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:00,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:05:00,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 06:05:00,572 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 06:05:00,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 06:05:00,769 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-12-02 06:05:00,769 INFO L340 BasicCegarLoop]: Counterexample is feasible [2024-12-02 06:05:00,769 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-12-02 06:05:00,771 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2024-12-02 06:05:00,773 INFO L422 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:00,866 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-12-02 06:05:00,869 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.12 06:05:00 BoogieIcfgContainer [2024-12-02 06:05:00,869 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-12-02 06:05:00,870 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-12-02 06:05:00,870 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-12-02 06:05:00,870 INFO L274 PluginConnector]: Witness Printer initialized [2024-12-02 06:05:00,871 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:04:48" (3/4) ... [2024-12-02 06:05:00,873 INFO L149 WitnessPrinter]: No result that supports witness generation found [2024-12-02 06:05:00,873 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-12-02 06:05:00,874 INFO L158 Benchmark]: Toolchain (without parser) took 14321.07ms. Allocated memory was 142.6MB in the beginning and 578.8MB in the end (delta: 436.2MB). Free memory was 118.3MB in the beginning and 479.8MB in the end (delta: -361.5MB). Peak memory consumption was 73.6MB. Max. memory is 16.1GB. [2024-12-02 06:05:00,874 INFO L158 Benchmark]: CDTParser took 0.30ms. Allocated memory is still 142.6MB. Free memory is still 83.0MB. There was no memory consumed. Max. memory is 16.1GB. [2024-12-02 06:05:00,874 INFO L158 Benchmark]: CACSL2BoogieTranslator took 349.27ms. Allocated memory is still 142.6MB. Free memory was 118.1MB in the beginning and 95.5MB in the end (delta: 22.6MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-12-02 06:05:00,875 INFO L158 Benchmark]: Boogie Procedure Inliner took 91.05ms. Allocated memory is still 142.6MB. Free memory was 95.5MB in the beginning and 81.0MB in the end (delta: 14.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-12-02 06:05:00,875 INFO L158 Benchmark]: Boogie Preprocessor took 90.28ms. Allocated memory is still 142.6MB. Free memory was 81.0MB in the beginning and 72.0MB in the end (delta: 9.0MB). There was no memory consumed. Max. memory is 16.1GB. [2024-12-02 06:05:00,875 INFO L158 Benchmark]: RCFGBuilder took 1254.00ms. Allocated memory is still 142.6MB. Free memory was 72.0MB in the beginning and 56.0MB in the end (delta: 16.0MB). Peak memory consumption was 45.2MB. Max. memory is 16.1GB. [2024-12-02 06:05:00,875 INFO L158 Benchmark]: TraceAbstraction took 12527.96ms. Allocated memory was 142.6MB in the beginning and 578.8MB in the end (delta: 436.2MB). Free memory was 55.2MB in the beginning and 479.8MB in the end (delta: -424.7MB). Peak memory consumption was 285.7MB. Max. memory is 16.1GB. [2024-12-02 06:05:00,876 INFO L158 Benchmark]: Witness Printer took 3.60ms. Allocated memory is still 578.8MB. Free memory was 479.8MB in the beginning and 479.8MB in the end (delta: 32.4kB). There was no memory consumed. Max. memory is 16.1GB. [2024-12-02 06:05:00,877 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.30ms. Allocated memory is still 142.6MB. Free memory is still 83.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 349.27ms. Allocated memory is still 142.6MB. Free memory was 118.1MB in the beginning and 95.5MB in the end (delta: 22.6MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 91.05ms. Allocated memory is still 142.6MB. Free memory was 95.5MB in the beginning and 81.0MB in the end (delta: 14.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 90.28ms. Allocated memory is still 142.6MB. Free memory was 81.0MB in the beginning and 72.0MB in the end (delta: 9.0MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 1254.00ms. Allocated memory is still 142.6MB. Free memory was 72.0MB in the beginning and 56.0MB in the end (delta: 16.0MB). Peak memory consumption was 45.2MB. Max. memory is 16.1GB. * TraceAbstraction took 12527.96ms. Allocated memory was 142.6MB in the beginning and 578.8MB in the end (delta: 436.2MB). Free memory was 55.2MB in the beginning and 479.8MB in the end (delta: -424.7MB). Peak memory consumption was 285.7MB. Max. memory is 16.1GB. * Witness Printer took 3.60ms. Allocated memory is still 578.8MB. Free memory was 479.8MB in the beginning and 479.8MB in the end (delta: 32.4kB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 21]: Unable to prove that a call to reach_error is unreachable Unable to prove that a call to reach_error is unreachable Reason: overapproximation of bitwiseAnd at line 296, overapproximation of bitwiseAnd at line 152, overapproximation of bitwiseAnd at line 157. Possible FailurePath: [L26] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L27] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L29] const SORT_9 mask_SORT_9 = (SORT_9)-1 >> (sizeof(SORT_9) * 8 - 31); [L30] const SORT_9 msb_SORT_9 = (SORT_9)1 << (31 - 1); [L32] const SORT_11 mask_SORT_11 = (SORT_11)-1 >> (sizeof(SORT_11) * 8 - 16); [L33] const SORT_11 msb_SORT_11 = (SORT_11)1 << (16 - 1); [L35] const SORT_12 mask_SORT_12 = (SORT_12)-1 >> (sizeof(SORT_12) * 8 - 8); [L36] const SORT_12 msb_SORT_12 = (SORT_12)1 << (8 - 1); [L38] const SORT_20 mask_SORT_20 = (SORT_20)-1 >> (sizeof(SORT_20) * 8 - 32); [L39] const SORT_20 msb_SORT_20 = (SORT_20)1 << (32 - 1); [L41] const SORT_23 mask_SORT_23 = (SORT_23)-1 >> (sizeof(SORT_23) * 8 - 17); [L42] const SORT_23 msb_SORT_23 = (SORT_23)1 << (17 - 1); [L44] const SORT_26 mask_SORT_26 = (SORT_26)-1 >> (sizeof(SORT_26) * 8 - 18); [L45] const SORT_26 msb_SORT_26 = (SORT_26)1 << (18 - 1); [L47] const SORT_29 mask_SORT_29 = (SORT_29)-1 >> (sizeof(SORT_29) * 8 - 19); [L48] const SORT_29 msb_SORT_29 = (SORT_29)1 << (19 - 1); [L50] const SORT_32 mask_SORT_32 = (SORT_32)-1 >> (sizeof(SORT_32) * 8 - 20); [L51] const SORT_32 msb_SORT_32 = (SORT_32)1 << (20 - 1); [L53] const SORT_35 mask_SORT_35 = (SORT_35)-1 >> (sizeof(SORT_35) * 8 - 21); [L54] const SORT_35 msb_SORT_35 = (SORT_35)1 << (21 - 1); [L56] const SORT_38 mask_SORT_38 = (SORT_38)-1 >> (sizeof(SORT_38) * 8 - 22); [L57] const SORT_38 msb_SORT_38 = (SORT_38)1 << (22 - 1); [L59] const SORT_41 mask_SORT_41 = (SORT_41)-1 >> (sizeof(SORT_41) * 8 - 23); [L60] const SORT_41 msb_SORT_41 = (SORT_41)1 << (23 - 1); [L62] const SORT_44 mask_SORT_44 = (SORT_44)-1 >> (sizeof(SORT_44) * 8 - 24); [L63] const SORT_44 msb_SORT_44 = (SORT_44)1 << (24 - 1); [L65] const SORT_47 mask_SORT_47 = (SORT_47)-1 >> (sizeof(SORT_47) * 8 - 25); [L66] const SORT_47 msb_SORT_47 = (SORT_47)1 << (25 - 1); [L68] const SORT_50 mask_SORT_50 = (SORT_50)-1 >> (sizeof(SORT_50) * 8 - 26); [L69] const SORT_50 msb_SORT_50 = (SORT_50)1 << (26 - 1); [L71] const SORT_53 mask_SORT_53 = (SORT_53)-1 >> (sizeof(SORT_53) * 8 - 27); [L72] const SORT_53 msb_SORT_53 = (SORT_53)1 << (27 - 1); [L74] const SORT_56 mask_SORT_56 = (SORT_56)-1 >> (sizeof(SORT_56) * 8 - 28); [L75] const SORT_56 msb_SORT_56 = (SORT_56)1 << (28 - 1); [L77] const SORT_59 mask_SORT_59 = (SORT_59)-1 >> (sizeof(SORT_59) * 8 - 29); [L78] const SORT_59 msb_SORT_59 = (SORT_59)1 << (29 - 1); [L80] const SORT_62 mask_SORT_62 = (SORT_62)-1 >> (sizeof(SORT_62) * 8 - 30); [L81] const SORT_62 msb_SORT_62 = (SORT_62)1 << (30 - 1); [L83] const SORT_72 mask_SORT_72 = (SORT_72)-1 >> (sizeof(SORT_72) * 8 - 3); [L84] const SORT_72 msb_SORT_72 = (SORT_72)1 << (3 - 1); [L86] const SORT_96 mask_SORT_96 = (SORT_96)-1 >> (sizeof(SORT_96) * 8 - 4); [L87] const SORT_96 msb_SORT_96 = (SORT_96)1 << (4 - 1); [L89] const SORT_101 mask_SORT_101 = (SORT_101)-1 >> (sizeof(SORT_101) * 8 - 6); [L90] const SORT_101 msb_SORT_101 = (SORT_101)1 << (6 - 1); [L92] const SORT_1 var_7 = 0; [L93] const SORT_1 var_8 = 1; [L94] const SORT_9 var_10 = 0; [L95] const SORT_12 var_13 = 0; [L96] const SORT_12 var_14 = 200; [L97] const SORT_72 var_73 = 5; [L98] const SORT_11 var_75 = 0; [L99] const SORT_11 var_108 = 200; [L100] const SORT_72 var_113 = 4; [L101] const SORT_72 var_116 = 6; [L102] const SORT_96 var_120 = 9; [L103] const SORT_72 var_137 = 0; [L104] const SORT_96 var_140 = 0; [L106] SORT_1 input_2; [L107] SORT_1 input_3; [L108] SORT_1 input_4; [L110] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L110] SORT_1 state_5 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L111] EXPR __VERIFIER_nondet_ushort() & mask_SORT_11 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_5=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L111] SORT_11 state_17 = __VERIFIER_nondet_ushort() & mask_SORT_11; [L112] EXPR __VERIFIER_nondet_ushort() & mask_SORT_11 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_17=0, state_5=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L112] SORT_11 state_76 = __VERIFIER_nondet_ushort() & mask_SORT_11; [L113] EXPR __VERIFIER_nondet_uchar() & mask_SORT_96 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_17=0, state_5=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L113] SORT_96 state_97 = __VERIFIER_nondet_uchar() & mask_SORT_96; [L114] EXPR __VERIFIER_nondet_uchar() & mask_SORT_96 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_17=0, state_5=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L114] SORT_96 state_100 = __VERIFIER_nondet_uchar() & mask_SORT_96; [L116] SORT_11 init_77_arg_1 = var_75; [L117] state_76 = init_77_arg_1 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_5=1, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] EXPR input_3 & mask_SORT_1 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_5=1, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] EXPR input_4 & mask_SORT_1 VAL [input_3=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_5=1, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; VAL [input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_86_arg_0=1, var_86_arg_1=-255, var_8=1] [L132] EXPR var_86_arg_0 | var_86_arg_1 VAL [input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] EXPR var_86 & mask_SORT_1 VAL [input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_88_arg_0=1, var_8=1] [L137] EXPR var_88_arg_0 & mask_SORT_1 VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1, var_90_arg_0=0, var_90_arg_1=1] [L144] EXPR var_90_arg_0 ^ var_90_arg_1 VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1, var_93_arg_0=-2, var_93_arg_1=-2] [L151] EXPR var_93_arg_0 | var_93_arg_1 VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] EXPR var_93 & mask_SORT_1 VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_74_arg_0=5, var_75=0, var_7=0, var_8=1] [L157] EXPR var_74_arg_0 & mask_SORT_72 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_15=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L166] EXPR var_15 & mask_SORT_12 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_16_arg_0=0, var_16_arg_1=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L169] EXPR ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_18=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L173] EXPR var_18 & mask_SORT_11 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_18=0, var_21_arg_0=0, var_21_arg_1=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L178] EXPR ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_18=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] EXPR var_21 & mask_SORT_20 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_18=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_24_arg_0=0, var_24_arg_1=0, var_25=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L212] EXPR ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_25=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] EXPR var_24 & mask_SORT_23 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_25=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_27_arg_0=0, var_27_arg_1=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L216] EXPR ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] EXPR var_27 & mask_SORT_26 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_30_arg_0=0, var_30_arg_1=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L220] EXPR ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] EXPR var_30 & mask_SORT_29 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_33_arg_0=0, var_33_arg_1=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L224] EXPR ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] EXPR var_33 & mask_SORT_32 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_36_arg_0=0, var_36_arg_1=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L228] EXPR ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] EXPR var_36 & mask_SORT_35 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_39_arg_0=0, var_39_arg_1=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L232] EXPR ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] EXPR var_39 & mask_SORT_38 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_42_arg_0=0, var_42_arg_1=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L236] EXPR ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] EXPR var_42 & mask_SORT_41 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_45_arg_0=0, var_45_arg_1=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L240] EXPR ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] EXPR var_45 & mask_SORT_44 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_48_arg_0=0, var_48_arg_1=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L244] EXPR ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] EXPR var_48 & mask_SORT_47 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_51_arg_0=0, var_51_arg_1=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L248] EXPR ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] EXPR var_51 & mask_SORT_50 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_54_arg_0=0, var_54_arg_1=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L252] EXPR ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] EXPR var_54 & mask_SORT_53 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_57_arg_0=0, var_57_arg_1=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L256] EXPR ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] EXPR var_57 & mask_SORT_56 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_60_arg_0=0, var_60_arg_1=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L260] EXPR ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] EXPR var_60 & mask_SORT_59 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_63_arg_0=0, var_63_arg_1=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L264] EXPR ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] EXPR var_63 & mask_SORT_62 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_65_arg_0=0, var_65_arg_1=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L268] EXPR ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_66_arg_0=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L270] EXPR var_66_arg_0 & mask_SORT_9 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L279] EXPR var_68 & mask_SORT_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_69_arg_0=0, var_69_arg_1=1, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L282] EXPR var_69_arg_0 ^ var_69_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_7=0, var_82_arg_0=-2, var_82_arg_1=-2, var_8=1] [L295] EXPR var_82_arg_0 & var_82_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_7=0, var_8=1] [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] EXPR var_82 & mask_SORT_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_7=0, var_8=1] [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND TRUE !(cond) [L21] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 280 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 12.4s, OverallIterations: 15, TraceHistogramMax: 2, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 2.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 5209 SdHoareTripleChecker+Valid, 1.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 5199 mSDsluCounter, 20292 SdHoareTripleChecker+Invalid, 1.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 15095 mSDsCounter, 17 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 2531 IncrementalHoareTripleChecker+Invalid, 2548 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 17 mSolverCounterUnsat, 5197 mSDtfsCounter, 2531 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 354 GetRequests, 286 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=763occurred in iteration=12, InterpolantAutomatonStates: 79, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 14 MinimizatonAttempts, 93 StatesRemovedByMinimization, 5 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.2s SsaConstructionTime, 1.6s SatisfiabilityAnalysisTime, 6.3s InterpolantComputationTime, 2188 NumberOfCodeBlocks, 2188 NumberOfCodeBlocksAsserted, 17 NumberOfCheckSat, 2038 ConstructedInterpolants, 0 QuantifiedInterpolants, 5276 SizeOfPredicates, 0 NumberOfNonLiveVariables, 1377 ConjunctsInSsa, 12 ConjunctsInUnsatCore, 16 InterpolantComputations, 14 PerfectInterpolantSequences, 59/64 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2024-12-02 06:05:00,892 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1 --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 37235873cdbfb4a92a6d9a366e7d975c617138dc8eee2f80d6fd06796710e280 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-12-02 06:05:02,823 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-12-02 06:05:02,906 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Bitvector.epf [2024-12-02 06:05:02,912 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-12-02 06:05:02,912 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-12-02 06:05:02,933 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-12-02 06:05:02,934 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-12-02 06:05:02,934 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-12-02 06:05:02,934 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-12-02 06:05:02,934 INFO L153 SettingsManager]: * Use memory slicer=true [2024-12-02 06:05:02,934 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-12-02 06:05:02,935 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-12-02 06:05:02,935 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-12-02 06:05:02,935 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-12-02 06:05:02,935 INFO L153 SettingsManager]: * Use SBE=true [2024-12-02 06:05:02,935 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-12-02 06:05:02,935 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-12-02 06:05:02,935 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-12-02 06:05:02,935 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-12-02 06:05:02,935 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-12-02 06:05:02,936 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-12-02 06:05:02,936 INFO L153 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2024-12-02 06:05:02,936 INFO L153 SettingsManager]: * Use bitvectors instead of ints=true [2024-12-02 06:05:02,936 INFO L153 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2024-12-02 06:05:02,936 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-12-02 06:05:02,936 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-12-02 06:05:02,936 INFO L153 SettingsManager]: * Use constant arrays=true [2024-12-02 06:05:02,936 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-12-02 06:05:02,936 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 06:05:02,936 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 06:05:02,936 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 06:05:02,936 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:05:02,936 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-12-02 06:05:02,936 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 06:05:02,937 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 06:05:02,937 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 06:05:02,937 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:05:02,937 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-12-02 06:05:02,937 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-12-02 06:05:02,938 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-12-02 06:05:02,938 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-12-02 06:05:02,938 INFO L153 SettingsManager]: * Trace refinement strategy=FOX [2024-12-02 06:05:02,938 INFO L153 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2024-12-02 06:05:02,938 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-12-02 06:05:02,938 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-12-02 06:05:02,938 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-12-02 06:05:02,938 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-12-02 06:05:02,938 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 37235873cdbfb4a92a6d9a366e7d975c617138dc8eee2f80d6fd06796710e280 [2024-12-02 06:05:03,148 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-12-02 06:05:03,155 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-12-02 06:05:03,158 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-12-02 06:05:03,159 INFO L270 PluginConnector]: Initializing CDTParser... [2024-12-02 06:05:03,159 INFO L274 PluginConnector]: CDTParser initialized [2024-12-02 06:05:03,160 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c [2024-12-02 06:05:05,787 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/data/16404ecb1/ec546ff59e104fbda5ed9303a7b82d61/FLAGffa4c15b7 [2024-12-02 06:05:06,015 INFO L384 CDTParser]: Found 1 translation units. [2024-12-02 06:05:06,016 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c [2024-12-02 06:05:06,026 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/data/16404ecb1/ec546ff59e104fbda5ed9303a7b82d61/FLAGffa4c15b7 [2024-12-02 06:05:06,353 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/data/16404ecb1/ec546ff59e104fbda5ed9303a7b82d61 [2024-12-02 06:05:06,355 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-12-02 06:05:06,356 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-12-02 06:05:06,356 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-12-02 06:05:06,357 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-12-02 06:05:06,359 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-12-02 06:05:06,360 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,360 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2e743079 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06, skipping insertion in model container [2024-12-02 06:05:06,360 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,379 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-12-02 06:05:06,484 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c[1289,1302] [2024-12-02 06:05:06,576 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 06:05:06,586 INFO L200 MainTranslator]: Completed pre-run [2024-12-02 06:05:06,594 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c[1289,1302] [2024-12-02 06:05:06,653 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 06:05:06,665 INFO L204 MainTranslator]: Completed translation [2024-12-02 06:05:06,665 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06 WrapperNode [2024-12-02 06:05:06,665 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-12-02 06:05:06,666 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-12-02 06:05:06,666 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-12-02 06:05:06,666 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-12-02 06:05:06,671 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,682 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,704 INFO L138 Inliner]: procedures = 17, calls = 10, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 374 [2024-12-02 06:05:06,704 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-12-02 06:05:06,704 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-12-02 06:05:06,704 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-12-02 06:05:06,705 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-12-02 06:05:06,711 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,711 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,715 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,730 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-12-02 06:05:06,730 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,730 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,741 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,742 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,745 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,747 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,749 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,753 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-12-02 06:05:06,753 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-12-02 06:05:06,754 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-12-02 06:05:06,754 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-12-02 06:05:06,755 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06" (1/1) ... [2024-12-02 06:05:06,760 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:05:06,779 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:05:06,790 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-12-02 06:05:06,792 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-12-02 06:05:06,816 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-12-02 06:05:06,817 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#0 [2024-12-02 06:05:06,817 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-12-02 06:05:06,817 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-12-02 06:05:06,817 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-12-02 06:05:06,817 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-12-02 06:05:06,938 INFO L234 CfgBuilder]: Building ICFG [2024-12-02 06:05:06,939 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-12-02 06:05:07,266 INFO L? ?]: Removed 176 outVars from TransFormulas that were not future-live. [2024-12-02 06:05:07,267 INFO L283 CfgBuilder]: Performing block encoding [2024-12-02 06:05:07,275 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-12-02 06:05:07,275 INFO L312 CfgBuilder]: Removed 1 assume(true) statements. [2024-12-02 06:05:07,275 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:05:07 BoogieIcfgContainer [2024-12-02 06:05:07,276 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-12-02 06:05:07,278 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-12-02 06:05:07,278 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-12-02 06:05:07,283 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-12-02 06:05:07,283 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 06:05:06" (1/3) ... [2024-12-02 06:05:07,283 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2bf4494e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 06:05:07, skipping insertion in model container [2024-12-02 06:05:07,283 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:05:06" (2/3) ... [2024-12-02 06:05:07,284 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2bf4494e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 06:05:07, skipping insertion in model container [2024-12-02 06:05:07,284 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:05:07" (3/3) ... [2024-12-02 06:05:07,285 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.unsafe_analog_estimation_convergence.c [2024-12-02 06:05:07,299 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-12-02 06:05:07,301 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.unsafe_analog_estimation_convergence.c that has 2 procedures, 18 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2024-12-02 06:05:07,338 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-12-02 06:05:07,347 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@75425f68, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-12-02 06:05:07,347 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-12-02 06:05:07,351 INFO L276 IsEmpty]: Start isEmpty. Operand has 18 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 14 states have internal predecessors, (17), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:05:07,356 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2024-12-02 06:05:07,356 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:07,356 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:07,357 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:07,360 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:07,360 INFO L85 PathProgramCache]: Analyzing trace with hash 584130565, now seen corresponding path program 1 times [2024-12-02 06:05:07,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:05:07,369 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [573441212] [2024-12-02 06:05:07,369 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:07,370 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:07,370 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:05:07,372 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:05:07,373 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-12-02 06:05:07,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:07,587 INFO L256 TraceCheckSpWp]: Trace formula consists of 240 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-12-02 06:05:07,591 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:07,608 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-12-02 06:05:07,608 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:05:07,608 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:05:07,609 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [573441212] [2024-12-02 06:05:07,609 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [573441212] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:05:07,609 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:05:07,609 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-12-02 06:05:07,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1760377597] [2024-12-02 06:05:07,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:05:07,614 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-12-02 06:05:07,614 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:05:07,628 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-12-02 06:05:07,628 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 06:05:07,629 INFO L87 Difference]: Start difference. First operand has 18 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 14 states have internal predecessors, (17), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:05:07,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:07,640 INFO L93 Difference]: Finished difference Result 31 states and 40 transitions. [2024-12-02 06:05:07,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-12-02 06:05:07,642 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) Word has length 17 [2024-12-02 06:05:07,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:07,646 INFO L225 Difference]: With dead ends: 31 [2024-12-02 06:05:07,647 INFO L226 Difference]: Without dead ends: 15 [2024-12-02 06:05:07,649 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 06:05:07,651 INFO L435 NwaCegarLoop]: 16 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 16 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:07,652 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:05:07,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2024-12-02 06:05:07,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2024-12-02 06:05:07,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 11 states have internal predecessors, (12), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:05:07,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions. [2024-12-02 06:05:07,680 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 16 transitions. Word has length 17 [2024-12-02 06:05:07,680 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:07,680 INFO L471 AbstractCegarLoop]: Abstraction has 15 states and 16 transitions. [2024-12-02 06:05:07,680 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-12-02 06:05:07,681 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 16 transitions. [2024-12-02 06:05:07,681 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2024-12-02 06:05:07,682 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:07,682 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:07,688 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-12-02 06:05:07,882 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:07,883 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:07,883 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:07,883 INFO L85 PathProgramCache]: Analyzing trace with hash 899554305, now seen corresponding path program 1 times [2024-12-02 06:05:07,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:05:07,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2144676620] [2024-12-02 06:05:07,884 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:07,884 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:07,884 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:05:07,886 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:05:07,887 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-12-02 06:05:08,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:08,098 INFO L256 TraceCheckSpWp]: Trace formula consists of 240 conjuncts, 23 conjuncts are in the unsatisfiable core [2024-12-02 06:05:08,103 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:08,379 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-12-02 06:05:08,379 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:08,605 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:05:08,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2144676620] [2024-12-02 06:05:08,605 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2144676620] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:08,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [373823118] [2024-12-02 06:05:08,606 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:08,606 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-12-02 06:05:08,606 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 [2024-12-02 06:05:08,608 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-12-02 06:05:08,609 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (4)] Waiting until timeout for monitored process [2024-12-02 06:05:08,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:08,959 INFO L256 TraceCheckSpWp]: Trace formula consists of 240 conjuncts, 18 conjuncts are in the unsatisfiable core [2024-12-02 06:05:08,964 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:09,105 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-12-02 06:05:09,105 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:05:09,106 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [373823118] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:05:09,106 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:05:09,106 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [7] total 7 [2024-12-02 06:05:09,106 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435793112] [2024-12-02 06:05:09,106 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:05:09,107 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:05:09,107 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:05:09,108 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:05:09,108 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:05:09,108 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. Second operand has 4 states, 4 states have (on average 2.5) internal successors, (10), 4 states have internal predecessors, (10), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:05:09,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:09,205 INFO L93 Difference]: Finished difference Result 24 states and 27 transitions. [2024-12-02 06:05:09,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:05:09,206 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.5) internal successors, (10), 4 states have internal predecessors, (10), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 17 [2024-12-02 06:05:09,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:09,207 INFO L225 Difference]: With dead ends: 24 [2024-12-02 06:05:09,207 INFO L226 Difference]: Without dead ends: 22 [2024-12-02 06:05:09,207 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:05:09,208 INFO L435 NwaCegarLoop]: 11 mSDtfsCounter, 2 mSDsluCounter, 21 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 32 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:09,208 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 32 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:05:09,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2024-12-02 06:05:09,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2024-12-02 06:05:09,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 15 states have internal predecessors, (16), 4 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2024-12-02 06:05:09,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 24 transitions. [2024-12-02 06:05:09,213 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 24 transitions. Word has length 17 [2024-12-02 06:05:09,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:09,214 INFO L471 AbstractCegarLoop]: Abstraction has 21 states and 24 transitions. [2024-12-02 06:05:09,214 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.5) internal successors, (10), 4 states have internal predecessors, (10), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-12-02 06:05:09,214 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 24 transitions. [2024-12-02 06:05:09,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2024-12-02 06:05:09,215 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:09,215 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2024-12-02 06:05:09,219 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (4)] Ended with exit code 0 [2024-12-02 06:05:09,421 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-12-02 06:05:09,615 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:09,616 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:09,616 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:09,616 INFO L85 PathProgramCache]: Analyzing trace with hash -1718916253, now seen corresponding path program 1 times [2024-12-02 06:05:09,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:05:09,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [71023575] [2024-12-02 06:05:09,617 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:09,617 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:09,618 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:05:09,619 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:05:09,620 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-12-02 06:05:09,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:09,893 INFO L256 TraceCheckSpWp]: Trace formula consists of 409 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-12-02 06:05:09,898 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:10,213 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2024-12-02 06:05:10,214 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:10,345 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:05:10,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [71023575] [2024-12-02 06:05:10,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [71023575] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:10,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1963944471] [2024-12-02 06:05:10,345 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:05:10,346 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-12-02 06:05:10,346 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 [2024-12-02 06:05:10,347 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-12-02 06:05:10,349 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (6)] Waiting until timeout for monitored process [2024-12-02 06:05:10,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:05:10,834 INFO L256 TraceCheckSpWp]: Trace formula consists of 409 conjuncts, 26 conjuncts are in the unsatisfiable core [2024-12-02 06:05:10,840 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:11,062 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2024-12-02 06:05:11,062 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:11,175 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1963944471] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:11,175 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:05:11,175 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5] total 6 [2024-12-02 06:05:11,175 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [524446063] [2024-12-02 06:05:11,175 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:05:11,176 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:05:11,176 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:05:11,176 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:05:11,176 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:05:11,176 INFO L87 Difference]: Start difference. First operand 21 states and 24 transitions. Second operand has 6 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 6 states have internal predecessors, (17), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) [2024-12-02 06:05:11,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:11,327 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2024-12-02 06:05:11,327 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:05:11,327 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 6 states have internal predecessors, (17), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) Word has length 32 [2024-12-02 06:05:11,327 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:11,328 INFO L225 Difference]: With dead ends: 31 [2024-12-02 06:05:11,328 INFO L226 Difference]: Without dead ends: 29 [2024-12-02 06:05:11,328 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 63 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=35, Invalid=55, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:05:11,329 INFO L435 NwaCegarLoop]: 11 mSDtfsCounter, 2 mSDsluCounter, 21 mSDsCounter, 0 mSdLazyCounter, 28 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 32 SdHoareTripleChecker+Invalid, 28 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 28 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:11,330 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 32 Invalid, 28 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 28 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:05:11,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2024-12-02 06:05:11,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 28. [2024-12-02 06:05:11,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 20 states have (on average 1.05) internal successors, (21), 20 states have internal predecessors, (21), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 06:05:11,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2024-12-02 06:05:11,336 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 33 transitions. Word has length 32 [2024-12-02 06:05:11,336 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:11,336 INFO L471 AbstractCegarLoop]: Abstraction has 28 states and 33 transitions. [2024-12-02 06:05:11,336 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 6 states have internal predecessors, (17), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) [2024-12-02 06:05:11,336 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 33 transitions. [2024-12-02 06:05:11,337 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2024-12-02 06:05:11,337 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:11,337 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1] [2024-12-02 06:05:11,340 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (6)] Ended with exit code 0 [2024-12-02 06:05:11,544 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2024-12-02 06:05:11,738 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:11,738 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:11,738 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:11,738 INFO L85 PathProgramCache]: Analyzing trace with hash -1689441343, now seen corresponding path program 2 times [2024-12-02 06:05:11,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:05:11,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [205448551] [2024-12-02 06:05:11,739 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:05:11,740 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:11,740 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:05:11,741 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:05:11,742 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-12-02 06:05:12,083 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:05:12,083 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:05:12,089 INFO L256 TraceCheckSpWp]: Trace formula consists of 578 conjuncts, 25 conjuncts are in the unsatisfiable core [2024-12-02 06:05:12,095 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:12,471 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 0 proven. 19 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 06:05:12,471 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:12,593 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:05:12,593 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [205448551] [2024-12-02 06:05:12,593 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [205448551] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:12,593 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [495786586] [2024-12-02 06:05:12,594 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:05:12,594 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-12-02 06:05:12,594 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 [2024-12-02 06:05:12,595 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-12-02 06:05:12,596 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (8)] Waiting until timeout for monitored process [2024-12-02 06:05:13,219 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:05:13,219 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:05:13,226 INFO L256 TraceCheckSpWp]: Trace formula consists of 578 conjuncts, 28 conjuncts are in the unsatisfiable core [2024-12-02 06:05:13,231 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:13,526 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 0 proven. 19 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 06:05:13,526 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:13,635 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [495786586] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:13,635 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:05:13,635 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2024-12-02 06:05:13,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1545674462] [2024-12-02 06:05:13,635 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:05:13,636 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:05:13,636 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:05:13,636 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:05:13,637 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:05:13,637 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. Second operand has 6 states, 6 states have (on average 3.3333333333333335) internal successors, (20), 6 states have internal predecessors, (20), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 06:05:13,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:13,831 INFO L93 Difference]: Finished difference Result 38 states and 45 transitions. [2024-12-02 06:05:13,831 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:05:13,831 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 3.3333333333333335) internal successors, (20), 6 states have internal predecessors, (20), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 47 [2024-12-02 06:05:13,832 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:13,832 INFO L225 Difference]: With dead ends: 38 [2024-12-02 06:05:13,832 INFO L226 Difference]: Without dead ends: 36 [2024-12-02 06:05:13,832 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 93 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=38, Invalid=72, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:05:13,833 INFO L435 NwaCegarLoop]: 15 mSDtfsCounter, 2 mSDsluCounter, 44 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 59 SdHoareTripleChecker+Invalid, 51 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:13,833 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 59 Invalid, 51 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:05:13,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2024-12-02 06:05:13,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 35. [2024-12-02 06:05:13,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 25 states have (on average 1.04) internal successors, (26), 25 states have internal predecessors, (26), 8 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 8 states have call predecessors, (8), 8 states have call successors, (8) [2024-12-02 06:05:13,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 42 transitions. [2024-12-02 06:05:13,838 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 42 transitions. Word has length 47 [2024-12-02 06:05:13,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:13,838 INFO L471 AbstractCegarLoop]: Abstraction has 35 states and 42 transitions. [2024-12-02 06:05:13,838 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 3.3333333333333335) internal successors, (20), 6 states have internal predecessors, (20), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 06:05:13,838 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 42 transitions. [2024-12-02 06:05:13,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2024-12-02 06:05:13,839 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:13,839 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 4, 4, 4, 4, 4, 4, 4, 3, 3, 1, 1, 1, 1] [2024-12-02 06:05:13,848 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-12-02 06:05:14,044 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (8)] Ended with exit code 0 [2024-12-02 06:05:14,240 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt [2024-12-02 06:05:14,240 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:14,240 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:14,241 INFO L85 PathProgramCache]: Analyzing trace with hash -110959709, now seen corresponding path program 3 times [2024-12-02 06:05:14,241 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:05:14,241 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [22385683] [2024-12-02 06:05:14,241 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-12-02 06:05:14,241 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:14,241 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:05:14,243 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:05:14,244 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-12-02 06:05:14,648 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2024-12-02 06:05:14,648 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:05:14,656 INFO L256 TraceCheckSpWp]: Trace formula consists of 724 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-12-02 06:05:14,660 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:15,116 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2024-12-02 06:05:15,116 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:15,211 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:05:15,211 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [22385683] [2024-12-02 06:05:15,211 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [22385683] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:15,211 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1826520665] [2024-12-02 06:05:15,212 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-12-02 06:05:15,212 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-12-02 06:05:15,212 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 [2024-12-02 06:05:15,213 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-12-02 06:05:15,214 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (10)] Waiting until timeout for monitored process [2024-12-02 06:05:16,054 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2024-12-02 06:05:16,055 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:05:16,081 INFO L256 TraceCheckSpWp]: Trace formula consists of 724 conjuncts, 37 conjuncts are in the unsatisfiable core [2024-12-02 06:05:16,088 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:16,459 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2024-12-02 06:05:16,459 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:16,548 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1826520665] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:16,548 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:05:16,548 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2024-12-02 06:05:16,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1525154686] [2024-12-02 06:05:16,549 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:05:16,549 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:05:16,549 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:05:16,550 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:05:16,550 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:05:16,550 INFO L87 Difference]: Start difference. First operand 35 states and 42 transitions. Second operand has 7 states, 7 states have (on average 3.5714285714285716) internal successors, (25), 7 states have internal predecessors, (25), 4 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) [2024-12-02 06:05:16,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:16,852 INFO L93 Difference]: Finished difference Result 45 states and 54 transitions. [2024-12-02 06:05:16,853 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:05:16,853 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 3.5714285714285716) internal successors, (25), 7 states have internal predecessors, (25), 4 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) Word has length 62 [2024-12-02 06:05:16,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:16,854 INFO L225 Difference]: With dead ends: 45 [2024-12-02 06:05:16,854 INFO L226 Difference]: Without dead ends: 43 [2024-12-02 06:05:16,854 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 122 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=44, Invalid=112, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:05:16,855 INFO L435 NwaCegarLoop]: 23 mSDtfsCounter, 2 mSDsluCounter, 78 mSDsCounter, 0 mSdLazyCounter, 126 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 101 SdHoareTripleChecker+Invalid, 129 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 126 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:16,855 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 101 Invalid, 129 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 126 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:05:16,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2024-12-02 06:05:16,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 42. [2024-12-02 06:05:16,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 30 states have (on average 1.0333333333333334) internal successors, (31), 30 states have internal predecessors, (31), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:05:16,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 51 transitions. [2024-12-02 06:05:16,860 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 51 transitions. Word has length 62 [2024-12-02 06:05:16,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:16,861 INFO L471 AbstractCegarLoop]: Abstraction has 42 states and 51 transitions. [2024-12-02 06:05:16,861 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 3.5714285714285716) internal successors, (25), 7 states have internal predecessors, (25), 4 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) [2024-12-02 06:05:16,861 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 51 transitions. [2024-12-02 06:05:16,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2024-12-02 06:05:16,862 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:16,862 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 5, 5, 5, 5, 5, 5, 5, 4, 4, 1, 1, 1, 1] [2024-12-02 06:05:16,870 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2024-12-02 06:05:17,068 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (10)] Ended with exit code 0 [2024-12-02 06:05:17,263 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt [2024-12-02 06:05:17,263 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:17,263 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:17,263 INFO L85 PathProgramCache]: Analyzing trace with hash 1997417345, now seen corresponding path program 4 times [2024-12-02 06:05:17,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:05:17,264 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [22318039] [2024-12-02 06:05:17,264 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-12-02 06:05:17,264 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:17,264 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:05:17,266 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:05:17,267 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-12-02 06:05:17,742 INFO L229 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-12-02 06:05:17,742 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:05:17,751 INFO L256 TraceCheckSpWp]: Trace formula consists of 916 conjuncts, 31 conjuncts are in the unsatisfiable core [2024-12-02 06:05:17,759 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:18,337 INFO L134 CoverageAnalysis]: Checked inductivity of 246 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2024-12-02 06:05:18,338 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:18,445 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:05:18,445 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [22318039] [2024-12-02 06:05:18,445 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [22318039] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:18,446 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [741276144] [2024-12-02 06:05:18,446 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-12-02 06:05:18,446 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-12-02 06:05:18,446 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 [2024-12-02 06:05:18,447 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-12-02 06:05:18,448 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (12)] Waiting until timeout for monitored process [2024-12-02 06:05:19,596 INFO L229 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-12-02 06:05:19,596 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:05:19,629 INFO L256 TraceCheckSpWp]: Trace formula consists of 916 conjuncts, 33 conjuncts are in the unsatisfiable core [2024-12-02 06:05:19,636 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:20,075 INFO L134 CoverageAnalysis]: Checked inductivity of 246 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2024-12-02 06:05:20,075 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:20,148 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [741276144] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:20,148 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:05:20,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8] total 9 [2024-12-02 06:05:20,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [317311442] [2024-12-02 06:05:20,148 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:05:20,149 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:05:20,149 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:05:20,149 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:05:20,149 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:05:20,150 INFO L87 Difference]: Start difference. First operand 42 states and 51 transitions. Second operand has 9 states, 9 states have (on average 3.5555555555555554) internal successors, (32), 9 states have internal predecessors, (32), 5 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 5 states have call predecessors, (10), 5 states have call successors, (10) [2024-12-02 06:05:20,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:20,575 INFO L93 Difference]: Finished difference Result 52 states and 63 transitions. [2024-12-02 06:05:20,575 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-12-02 06:05:20,576 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 3.5555555555555554) internal successors, (32), 9 states have internal predecessors, (32), 5 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 5 states have call predecessors, (10), 5 states have call successors, (10) Word has length 77 [2024-12-02 06:05:20,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:20,576 INFO L225 Difference]: With dead ends: 52 [2024-12-02 06:05:20,576 INFO L226 Difference]: Without dead ends: 50 [2024-12-02 06:05:20,577 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 150 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=58, Invalid=182, Unknown=0, NotChecked=0, Total=240 [2024-12-02 06:05:20,577 INFO L435 NwaCegarLoop]: 27 mSDtfsCounter, 2 mSDsluCounter, 106 mSDsCounter, 0 mSdLazyCounter, 198 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 133 SdHoareTripleChecker+Invalid, 202 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 198 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:20,577 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 133 Invalid, 202 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 198 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-12-02 06:05:20,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2024-12-02 06:05:20,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 49. [2024-12-02 06:05:20,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 35 states have (on average 1.0285714285714285) internal successors, (36), 35 states have internal predecessors, (36), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-12-02 06:05:20,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 60 transitions. [2024-12-02 06:05:20,583 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 60 transitions. Word has length 77 [2024-12-02 06:05:20,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:20,583 INFO L471 AbstractCegarLoop]: Abstraction has 49 states and 60 transitions. [2024-12-02 06:05:20,584 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 3.5555555555555554) internal successors, (32), 9 states have internal predecessors, (32), 5 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 5 states have call predecessors, (10), 5 states have call successors, (10) [2024-12-02 06:05:20,584 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 60 transitions. [2024-12-02 06:05:20,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2024-12-02 06:05:20,584 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:20,585 INFO L218 NwaCegarLoop]: trace histogram [12, 12, 12, 6, 6, 6, 6, 6, 6, 6, 5, 5, 1, 1, 1, 1] [2024-12-02 06:05:20,594 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-12-02 06:05:20,792 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (12)] Ended with exit code 0 [2024-12-02 06:05:20,985 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt [2024-12-02 06:05:20,985 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:20,985 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:20,985 INFO L85 PathProgramCache]: Analyzing trace with hash -1626706973, now seen corresponding path program 5 times [2024-12-02 06:05:20,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:05:20,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1892452056] [2024-12-02 06:05:20,986 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-12-02 06:05:20,986 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:20,986 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:05:20,988 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:05:20,988 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-12-02 06:05:21,906 INFO L229 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2024-12-02 06:05:21,906 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:05:21,917 INFO L256 TraceCheckSpWp]: Trace formula consists of 1085 conjuncts, 32 conjuncts are in the unsatisfiable core [2024-12-02 06:05:21,923 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:22,568 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2024-12-02 06:05:22,569 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:22,667 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:05:22,667 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1892452056] [2024-12-02 06:05:22,667 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1892452056] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:22,667 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1759882826] [2024-12-02 06:05:22,667 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-12-02 06:05:22,667 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-12-02 06:05:22,667 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 [2024-12-02 06:05:22,669 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-12-02 06:05:22,670 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (14)] Waiting until timeout for monitored process [2024-12-02 06:05:24,078 INFO L229 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2024-12-02 06:05:24,078 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:05:24,116 INFO L256 TraceCheckSpWp]: Trace formula consists of 1085 conjuncts, 34 conjuncts are in the unsatisfiable core [2024-12-02 06:05:24,125 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:05:24,701 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2024-12-02 06:05:24,701 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:05:24,792 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1759882826] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:05:24,792 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:05:24,792 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 10 [2024-12-02 06:05:24,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1011438394] [2024-12-02 06:05:24,792 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:05:24,792 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 06:05:24,792 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:05:24,793 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 06:05:24,793 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=102, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:05:24,793 INFO L87 Difference]: Start difference. First operand 49 states and 60 transitions. Second operand has 10 states, 10 states have (on average 3.7) internal successors, (37), 10 states have internal predecessors, (37), 6 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 6 states have call predecessors, (12), 6 states have call successors, (12) [2024-12-02 06:05:25,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:05:25,364 INFO L93 Difference]: Finished difference Result 59 states and 72 transitions. [2024-12-02 06:05:25,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2024-12-02 06:05:25,365 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 3.7) internal successors, (37), 10 states have internal predecessors, (37), 6 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 6 states have call predecessors, (12), 6 states have call successors, (12) Word has length 92 [2024-12-02 06:05:25,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:05:25,366 INFO L225 Difference]: With dead ends: 59 [2024-12-02 06:05:25,366 INFO L226 Difference]: Without dead ends: 57 [2024-12-02 06:05:25,367 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 179 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=67, Invalid=239, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:05:25,367 INFO L435 NwaCegarLoop]: 31 mSDtfsCounter, 2 mSDsluCounter, 155 mSDsCounter, 0 mSdLazyCounter, 315 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 186 SdHoareTripleChecker+Invalid, 320 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 315 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:05:25,367 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 186 Invalid, 320 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 315 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 06:05:25,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2024-12-02 06:05:25,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 56. [2024-12-02 06:05:25,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 40 states have (on average 1.025) internal successors, (41), 40 states have internal predecessors, (41), 14 states have call successors, (14), 1 states have call predecessors, (14), 1 states have return successors, (14), 14 states have call predecessors, (14), 14 states have call successors, (14) [2024-12-02 06:05:25,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 69 transitions. [2024-12-02 06:05:25,376 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 69 transitions. Word has length 92 [2024-12-02 06:05:25,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:05:25,376 INFO L471 AbstractCegarLoop]: Abstraction has 56 states and 69 transitions. [2024-12-02 06:05:25,377 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 3.7) internal successors, (37), 10 states have internal predecessors, (37), 6 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 6 states have call predecessors, (12), 6 states have call successors, (12) [2024-12-02 06:05:25,377 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 69 transitions. [2024-12-02 06:05:25,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2024-12-02 06:05:25,377 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:05:25,378 INFO L218 NwaCegarLoop]: trace histogram [14, 14, 14, 7, 7, 7, 7, 7, 7, 7, 6, 6, 1, 1, 1, 1] [2024-12-02 06:05:25,387 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (14)] Ended with exit code 0 [2024-12-02 06:05:25,587 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-12-02 06:05:25,778 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt,13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:25,778 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:05:25,778 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:05:25,778 INFO L85 PathProgramCache]: Analyzing trace with hash -790815935, now seen corresponding path program 6 times [2024-12-02 06:05:25,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:05:25,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2084631541] [2024-12-02 06:05:25,779 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-12-02 06:05:25,779 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:25,779 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:05:25,781 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:05:25,781 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-12-02 06:05:26,724 INFO L229 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2024-12-02 06:05:26,724 INFO L230 tOrderPrioritization]: Conjunction of SSA is sat [2024-12-02 06:05:26,724 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 06:05:27,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 06:05:27,267 INFO L130 FreeRefinementEngine]: Strategy FOX found a feasible trace [2024-12-02 06:05:27,267 INFO L340 BasicCegarLoop]: Counterexample is feasible [2024-12-02 06:05:27,268 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-12-02 06:05:27,288 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2024-12-02 06:05:27,470 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:05:27,472 INFO L422 BasicCegarLoop]: Path program histogram: [6, 1, 1] [2024-12-02 06:05:27,581 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-12-02 06:05:27,584 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.12 06:05:27 BoogieIcfgContainer [2024-12-02 06:05:27,584 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-12-02 06:05:27,585 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-12-02 06:05:27,585 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-12-02 06:05:27,585 INFO L274 PluginConnector]: Witness Printer initialized [2024-12-02 06:05:27,586 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:05:07" (3/4) ... [2024-12-02 06:05:27,586 INFO L140 WitnessPrinter]: Generating witness for reachability counterexample [2024-12-02 06:05:27,798 INFO L129 tionWitnessGenerator]: Generated YAML witness of length 63. [2024-12-02 06:05:27,868 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/witness.graphml [2024-12-02 06:05:27,869 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/witness.yml [2024-12-02 06:05:27,869 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-12-02 06:05:27,870 INFO L158 Benchmark]: Toolchain (without parser) took 21513.82ms. Allocated memory was 92.3MB in the beginning and 352.3MB in the end (delta: 260.0MB). Free memory was 68.7MB in the beginning and 286.2MB in the end (delta: -217.4MB). Peak memory consumption was 222.5MB. Max. memory is 16.1GB. [2024-12-02 06:05:27,870 INFO L158 Benchmark]: CDTParser took 0.30ms. Allocated memory is still 83.9MB. Free memory is still 48.2MB. There was no memory consumed. Max. memory is 16.1GB. [2024-12-02 06:05:27,870 INFO L158 Benchmark]: CACSL2BoogieTranslator took 309.02ms. Allocated memory is still 92.3MB. Free memory was 68.5MB in the beginning and 47.3MB in the end (delta: 21.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-12-02 06:05:27,870 INFO L158 Benchmark]: Boogie Procedure Inliner took 38.27ms. Allocated memory is still 92.3MB. Free memory was 47.2MB in the beginning and 44.0MB in the end (delta: 3.2MB). There was no memory consumed. Max. memory is 16.1GB. [2024-12-02 06:05:27,871 INFO L158 Benchmark]: Boogie Preprocessor took 48.45ms. Allocated memory is still 92.3MB. Free memory was 43.9MB in the beginning and 40.2MB in the end (delta: 3.7MB). There was no memory consumed. Max. memory is 16.1GB. [2024-12-02 06:05:27,871 INFO L158 Benchmark]: RCFGBuilder took 522.36ms. Allocated memory is still 92.3MB. Free memory was 40.1MB in the beginning and 62.2MB in the end (delta: -22.1MB). Peak memory consumption was 14.4MB. Max. memory is 16.1GB. [2024-12-02 06:05:27,871 INFO L158 Benchmark]: TraceAbstraction took 20306.29ms. Allocated memory was 92.3MB in the beginning and 352.3MB in the end (delta: 260.0MB). Free memory was 61.8MB in the beginning and 127.1MB in the end (delta: -65.3MB). Peak memory consumption was 191.5MB. Max. memory is 16.1GB. [2024-12-02 06:05:27,871 INFO L158 Benchmark]: Witness Printer took 284.26ms. Allocated memory is still 352.3MB. Free memory was 127.1MB in the beginning and 286.2MB in the end (delta: -159.1MB). Peak memory consumption was 25.0MB. Max. memory is 16.1GB. [2024-12-02 06:05:27,873 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.30ms. Allocated memory is still 83.9MB. Free memory is still 48.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 309.02ms. Allocated memory is still 92.3MB. Free memory was 68.5MB in the beginning and 47.3MB in the end (delta: 21.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 38.27ms. Allocated memory is still 92.3MB. Free memory was 47.2MB in the beginning and 44.0MB in the end (delta: 3.2MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 48.45ms. Allocated memory is still 92.3MB. Free memory was 43.9MB in the beginning and 40.2MB in the end (delta: 3.7MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 522.36ms. Allocated memory is still 92.3MB. Free memory was 40.1MB in the beginning and 62.2MB in the end (delta: -22.1MB). Peak memory consumption was 14.4MB. Max. memory is 16.1GB. * TraceAbstraction took 20306.29ms. Allocated memory was 92.3MB in the beginning and 352.3MB in the end (delta: 260.0MB). Free memory was 61.8MB in the beginning and 127.1MB in the end (delta: -65.3MB). Peak memory consumption was 191.5MB. Max. memory is 16.1GB. * Witness Printer took 284.26ms. Allocated memory is still 352.3MB. Free memory was 127.1MB in the beginning and 286.2MB in the end (delta: -159.1MB). Peak memory consumption was 25.0MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L26] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L27] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L29] const SORT_9 mask_SORT_9 = (SORT_9)-1 >> (sizeof(SORT_9) * 8 - 31); [L30] const SORT_9 msb_SORT_9 = (SORT_9)1 << (31 - 1); [L32] const SORT_11 mask_SORT_11 = (SORT_11)-1 >> (sizeof(SORT_11) * 8 - 16); [L33] const SORT_11 msb_SORT_11 = (SORT_11)1 << (16 - 1); [L35] const SORT_12 mask_SORT_12 = (SORT_12)-1 >> (sizeof(SORT_12) * 8 - 8); [L36] const SORT_12 msb_SORT_12 = (SORT_12)1 << (8 - 1); [L38] const SORT_20 mask_SORT_20 = (SORT_20)-1 >> (sizeof(SORT_20) * 8 - 32); [L39] const SORT_20 msb_SORT_20 = (SORT_20)1 << (32 - 1); [L41] const SORT_23 mask_SORT_23 = (SORT_23)-1 >> (sizeof(SORT_23) * 8 - 17); [L42] const SORT_23 msb_SORT_23 = (SORT_23)1 << (17 - 1); [L44] const SORT_26 mask_SORT_26 = (SORT_26)-1 >> (sizeof(SORT_26) * 8 - 18); [L45] const SORT_26 msb_SORT_26 = (SORT_26)1 << (18 - 1); [L47] const SORT_29 mask_SORT_29 = (SORT_29)-1 >> (sizeof(SORT_29) * 8 - 19); [L48] const SORT_29 msb_SORT_29 = (SORT_29)1 << (19 - 1); [L50] const SORT_32 mask_SORT_32 = (SORT_32)-1 >> (sizeof(SORT_32) * 8 - 20); [L51] const SORT_32 msb_SORT_32 = (SORT_32)1 << (20 - 1); [L53] const SORT_35 mask_SORT_35 = (SORT_35)-1 >> (sizeof(SORT_35) * 8 - 21); [L54] const SORT_35 msb_SORT_35 = (SORT_35)1 << (21 - 1); [L56] const SORT_38 mask_SORT_38 = (SORT_38)-1 >> (sizeof(SORT_38) * 8 - 22); [L57] const SORT_38 msb_SORT_38 = (SORT_38)1 << (22 - 1); [L59] const SORT_41 mask_SORT_41 = (SORT_41)-1 >> (sizeof(SORT_41) * 8 - 23); [L60] const SORT_41 msb_SORT_41 = (SORT_41)1 << (23 - 1); [L62] const SORT_44 mask_SORT_44 = (SORT_44)-1 >> (sizeof(SORT_44) * 8 - 24); [L63] const SORT_44 msb_SORT_44 = (SORT_44)1 << (24 - 1); [L65] const SORT_47 mask_SORT_47 = (SORT_47)-1 >> (sizeof(SORT_47) * 8 - 25); [L66] const SORT_47 msb_SORT_47 = (SORT_47)1 << (25 - 1); [L68] const SORT_50 mask_SORT_50 = (SORT_50)-1 >> (sizeof(SORT_50) * 8 - 26); [L69] const SORT_50 msb_SORT_50 = (SORT_50)1 << (26 - 1); [L71] const SORT_53 mask_SORT_53 = (SORT_53)-1 >> (sizeof(SORT_53) * 8 - 27); [L72] const SORT_53 msb_SORT_53 = (SORT_53)1 << (27 - 1); [L74] const SORT_56 mask_SORT_56 = (SORT_56)-1 >> (sizeof(SORT_56) * 8 - 28); [L75] const SORT_56 msb_SORT_56 = (SORT_56)1 << (28 - 1); [L77] const SORT_59 mask_SORT_59 = (SORT_59)-1 >> (sizeof(SORT_59) * 8 - 29); [L78] const SORT_59 msb_SORT_59 = (SORT_59)1 << (29 - 1); [L80] const SORT_62 mask_SORT_62 = (SORT_62)-1 >> (sizeof(SORT_62) * 8 - 30); [L81] const SORT_62 msb_SORT_62 = (SORT_62)1 << (30 - 1); [L83] const SORT_72 mask_SORT_72 = (SORT_72)-1 >> (sizeof(SORT_72) * 8 - 3); [L84] const SORT_72 msb_SORT_72 = (SORT_72)1 << (3 - 1); [L86] const SORT_96 mask_SORT_96 = (SORT_96)-1 >> (sizeof(SORT_96) * 8 - 4); [L87] const SORT_96 msb_SORT_96 = (SORT_96)1 << (4 - 1); [L89] const SORT_101 mask_SORT_101 = (SORT_101)-1 >> (sizeof(SORT_101) * 8 - 6); [L90] const SORT_101 msb_SORT_101 = (SORT_101)1 << (6 - 1); [L92] const SORT_1 var_7 = 0; [L93] const SORT_1 var_8 = 1; [L94] const SORT_9 var_10 = 0; [L95] const SORT_12 var_13 = 0; [L96] const SORT_12 var_14 = 200; [L97] const SORT_72 var_73 = 5; [L98] const SORT_11 var_75 = 0; [L99] const SORT_11 var_108 = 200; [L100] const SORT_72 var_113 = 4; [L101] const SORT_72 var_116 = 6; [L102] const SORT_96 var_120 = 9; [L103] const SORT_72 var_137 = 0; [L104] const SORT_96 var_140 = 0; [L106] SORT_1 input_2; [L107] SORT_1 input_3; [L108] SORT_1 input_4; [L110] SORT_1 state_5 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L111] SORT_11 state_17 = __VERIFIER_nondet_ushort() & mask_SORT_11; [L112] SORT_11 state_76 = __VERIFIER_nondet_ushort() & mask_SORT_11; [L113] SORT_96 state_97 = __VERIFIER_nondet_uchar() & mask_SORT_96; [L114] SORT_96 state_100 = __VERIFIER_nondet_uchar() & mask_SORT_96; [L116] SORT_11 init_77_arg_1 = var_75; [L117] state_76 = init_77_arg_1 VAL [mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=13, state_17=-4096, state_5=1, state_76=0, state_97=6, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=13, state_17=-4096, state_76=0, state_97=6, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=13, state_17=-4096, state_76=0, state_97=6, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=13, state_17=-4096, state_76=0, state_97=6, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=13, state_17=-4096, state_76=0, state_97=6, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=1, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=2, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=1, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=2, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=1, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=2, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=1, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=2, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=1, state_17=1, state_76=3, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=1, state_17=1, state_76=3, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=1, state_17=1, state_76=3, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=1, state_17=1, state_76=3, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=2, state_17=0, state_76=4, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=2, state_17=0, state_76=4, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=2, state_17=0, state_76=4, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=2, state_17=0, state_76=4, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=3, state_17=1, state_76=5, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=3, state_17=1, state_76=5, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=3, state_17=1, state_76=5, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=3, state_17=1, state_76=5, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=4, state_17=0, state_76=6, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=4, state_17=0, state_76=6, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=4, state_17=0, state_76=6, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=4, state_17=0, state_76=6, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND TRUE !(cond) [L21] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 18 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 20.1s, OverallIterations: 8, TraceHistogramMax: 14, PathProgramHistogramMax: 6, EmptinessCheckTime: 0.0s, AutomataDifference: 1.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 12 SdHoareTripleChecker+Valid, 1.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 12 mSDsluCounter, 559 SdHoareTripleChecker+Invalid, 1.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 425 mSDsCounter, 13 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 732 IncrementalHoareTripleChecker+Invalid, 745 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 13 mSolverCounterUnsat, 134 mSDtfsCounter, 732 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 723 GetRequests, 652 SyntacticMatches, 5 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92 ImplicationChecksByTransitivity, 1.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=56occurred in iteration=7, InterpolantAutomatonStates: 56, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 7 MinimizatonAttempts, 6 StatesRemovedByMinimization, 6 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 1.4s SsaConstructionTime, 3.8s SatisfiabilityAnalysisTime, 6.2s InterpolantComputationTime, 778 NumberOfCodeBlocks, 766 NumberOfCodeBlocksAsserted, 51 NumberOfCheckSat, 658 ConstructedInterpolants, 21 QuantifiedInterpolants, 5800 SizeOfPredicates, 81 NumberOfNonLiveVariables, 8144 ConjunctsInSsa, 342 ConjunctsInUnsatCore, 13 InterpolantComputations, 2 PerfectInterpolantSequences, 1289/1752 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2024-12-02 06:05:27,908 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b9a65120-dc1a-4ff3-a180-6741f6575e96/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE