./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1 --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 77ae88daffb8285870a38f38e30db5571fe2930110ef63da660dc306a4cb95e3 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-12-02 06:22:52,174 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-12-02 06:22:52,230 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Default.epf [2024-12-02 06:22:52,236 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-12-02 06:22:52,236 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-12-02 06:22:52,258 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-12-02 06:22:52,258 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-12-02 06:22:52,258 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-12-02 06:22:52,259 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-12-02 06:22:52,259 INFO L153 SettingsManager]: * Use memory slicer=true [2024-12-02 06:22:52,259 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-12-02 06:22:52,259 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-12-02 06:22:52,259 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-12-02 06:22:52,260 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-12-02 06:22:52,260 INFO L153 SettingsManager]: * Use SBE=true [2024-12-02 06:22:52,260 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-12-02 06:22:52,260 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-12-02 06:22:52,260 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-12-02 06:22:52,260 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-12-02 06:22:52,260 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-12-02 06:22:52,260 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-12-02 06:22:52,260 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-12-02 06:22:52,261 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-12-02 06:22:52,261 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-12-02 06:22:52,261 INFO L153 SettingsManager]: * Use constant arrays=true [2024-12-02 06:22:52,261 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-12-02 06:22:52,261 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 06:22:52,261 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 06:22:52,261 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 06:22:52,261 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:22:52,261 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-12-02 06:22:52,261 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 06:22:52,262 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 06:22:52,262 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 06:22:52,262 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:22:52,262 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-12-02 06:22:52,262 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-12-02 06:22:52,262 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-12-02 06:22:52,262 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-12-02 06:22:52,262 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-12-02 06:22:52,262 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-12-02 06:22:52,262 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-12-02 06:22:52,263 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-12-02 06:22:52,263 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-12-02 06:22:52,263 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-12-02 06:22:52,263 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 77ae88daffb8285870a38f38e30db5571fe2930110ef63da660dc306a4cb95e3 [2024-12-02 06:22:52,478 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-12-02 06:22:52,485 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-12-02 06:22:52,487 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-12-02 06:22:52,488 INFO L270 PluginConnector]: Initializing CDTParser... [2024-12-02 06:22:52,489 INFO L274 PluginConnector]: CDTParser initialized [2024-12-02 06:22:52,490 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c [2024-12-02 06:22:55,130 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/data/5b9f7e692/d4e1fa9ef21d4acd85471203c68d979b/FLAG8cf6cf978 [2024-12-02 06:22:55,397 INFO L384 CDTParser]: Found 1 translation units. [2024-12-02 06:22:55,398 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c [2024-12-02 06:22:55,408 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/data/5b9f7e692/d4e1fa9ef21d4acd85471203c68d979b/FLAG8cf6cf978 [2024-12-02 06:22:55,707 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/data/5b9f7e692/d4e1fa9ef21d4acd85471203c68d979b [2024-12-02 06:22:55,708 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-12-02 06:22:55,709 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-12-02 06:22:55,710 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-12-02 06:22:55,710 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-12-02 06:22:55,714 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-12-02 06:22:55,714 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:22:55" (1/1) ... [2024-12-02 06:22:55,715 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1046f2ec and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:55, skipping insertion in model container [2024-12-02 06:22:55,715 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:22:55" (1/1) ... [2024-12-02 06:22:55,743 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-12-02 06:22:55,888 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c[1270,1283] [2024-12-02 06:22:56,068 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 06:22:56,077 INFO L200 MainTranslator]: Completed pre-run [2024-12-02 06:22:56,084 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c[1270,1283] [2024-12-02 06:22:56,178 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 06:22:56,189 INFO L204 MainTranslator]: Completed translation [2024-12-02 06:22:56,189 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56 WrapperNode [2024-12-02 06:22:56,189 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-12-02 06:22:56,190 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-12-02 06:22:56,190 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-12-02 06:22:56,190 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-12-02 06:22:56,194 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56" (1/1) ... [2024-12-02 06:22:56,217 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56" (1/1) ... [2024-12-02 06:22:56,430 INFO L138 Inliner]: procedures = 18, calls = 41, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 2364 [2024-12-02 06:22:56,431 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-12-02 06:22:56,431 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-12-02 06:22:56,432 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-12-02 06:22:56,432 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-12-02 06:22:56,441 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56" (1/1) ... [2024-12-02 06:22:56,441 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56" (1/1) ... [2024-12-02 06:22:56,476 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56" (1/1) ... [2024-12-02 06:22:56,541 INFO L175 MemorySlicer]: Split 20 memory accesses to 3 slices as follows [2, 9, 9]. 45 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0, 0]. The 8 writes are split as follows [0, 4, 4]. [2024-12-02 06:22:56,541 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56" (1/1) ... [2024-12-02 06:22:56,541 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56" (1/1) ... [2024-12-02 06:22:56,649 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56" (1/1) ... [2024-12-02 06:22:56,655 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56" (1/1) ... [2024-12-02 06:22:56,666 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56" (1/1) ... [2024-12-02 06:22:56,700 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56" (1/1) ... [2024-12-02 06:22:56,710 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56" (1/1) ... [2024-12-02 06:22:56,735 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-12-02 06:22:56,736 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-12-02 06:22:56,736 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-12-02 06:22:56,736 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-12-02 06:22:56,737 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56" (1/1) ... [2024-12-02 06:22:56,742 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:22:56,754 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:22:56,765 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-12-02 06:22:56,767 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-12-02 06:22:56,785 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-12-02 06:22:56,785 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-12-02 06:22:56,785 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-12-02 06:22:56,785 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-12-02 06:22:56,785 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2024-12-02 06:22:56,785 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#2 [2024-12-02 06:22:56,785 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-12-02 06:22:56,786 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2024-12-02 06:22:56,786 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2024-12-02 06:22:56,786 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#2 [2024-12-02 06:22:56,786 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-12-02 06:22:56,786 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-12-02 06:22:56,786 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2024-12-02 06:22:56,786 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2024-12-02 06:22:56,786 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#2 [2024-12-02 06:22:56,786 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-12-02 06:22:56,994 INFO L234 CfgBuilder]: Building ICFG [2024-12-02 06:22:56,996 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-12-02 06:22:59,703 INFO L? ?]: Removed 1277 outVars from TransFormulas that were not future-live. [2024-12-02 06:22:59,703 INFO L283 CfgBuilder]: Performing block encoding [2024-12-02 06:22:59,725 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-12-02 06:22:59,726 INFO L312 CfgBuilder]: Removed 7 assume(true) statements. [2024-12-02 06:22:59,726 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:22:59 BoogieIcfgContainer [2024-12-02 06:22:59,726 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-12-02 06:22:59,728 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-12-02 06:22:59,728 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-12-02 06:22:59,733 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-12-02 06:22:59,733 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 06:22:55" (1/3) ... [2024-12-02 06:22:59,734 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@33096d11 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 06:22:59, skipping insertion in model container [2024-12-02 06:22:59,734 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:22:56" (2/3) ... [2024-12-02 06:22:59,734 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@33096d11 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 06:22:59, skipping insertion in model container [2024-12-02 06:22:59,734 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:22:59" (3/3) ... [2024-12-02 06:22:59,735 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c [2024-12-02 06:22:59,746 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-12-02 06:22:59,747 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c that has 2 procedures, 752 locations, 1 initial locations, 7 loop locations, and 1 error locations. [2024-12-02 06:22:59,806 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-12-02 06:22:59,816 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@770d379, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-12-02 06:22:59,816 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-12-02 06:22:59,822 INFO L276 IsEmpty]: Start isEmpty. Operand has 752 states, 744 states have (on average 1.4973118279569892) internal successors, (1114), 745 states have internal predecessors, (1114), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:22:59,836 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 238 [2024-12-02 06:22:59,836 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:22:59,837 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:22:59,837 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:22:59,842 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:22:59,842 INFO L85 PathProgramCache]: Analyzing trace with hash 1495465516, now seen corresponding path program 1 times [2024-12-02 06:22:59,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:22:59,848 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678128795] [2024-12-02 06:22:59,848 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:22:59,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:00,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:00,251 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-12-02 06:23:00,251 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:00,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [678128795] [2024-12-02 06:23:00,252 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [678128795] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:00,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [698172308] [2024-12-02 06:23:00,253 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:00,253 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:00,253 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:00,255 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:00,256 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-12-02 06:23:00,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:00,736 INFO L256 TraceCheckSpWp]: Trace formula consists of 1071 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-12-02 06:23:00,747 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:00,772 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-12-02 06:23:00,772 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:23:00,772 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [698172308] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:00,772 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:23:00,773 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 2 [2024-12-02 06:23:00,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [637026883] [2024-12-02 06:23:00,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:00,779 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-12-02 06:23:00,780 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:00,799 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-12-02 06:23:00,800 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 06:23:00,803 INFO L87 Difference]: Start difference. First operand has 752 states, 744 states have (on average 1.4973118279569892) internal successors, (1114), 745 states have internal predecessors, (1114), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) Second operand has 2 states, 2 states have (on average 108.5) internal successors, (217), 2 states have internal predecessors, (217), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:23:00,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:00,868 INFO L93 Difference]: Finished difference Result 1493 states and 2239 transitions. [2024-12-02 06:23:00,869 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-12-02 06:23:00,870 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 108.5) internal successors, (217), 2 states have internal predecessors, (217), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) Word has length 237 [2024-12-02 06:23:00,871 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:00,880 INFO L225 Difference]: With dead ends: 1493 [2024-12-02 06:23:00,880 INFO L226 Difference]: Without dead ends: 749 [2024-12-02 06:23:00,884 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 238 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 06:23:00,886 INFO L435 NwaCegarLoop]: 1113 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1113 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:00,887 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1113 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:23:00,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 749 states. [2024-12-02 06:23:00,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 749 to 749. [2024-12-02 06:23:00,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 749 states, 742 states have (on average 1.486522911051213) internal successors, (1103), 742 states have internal predecessors, (1103), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:23:00,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 749 states to 749 states and 1113 transitions. [2024-12-02 06:23:00,944 INFO L78 Accepts]: Start accepts. Automaton has 749 states and 1113 transitions. Word has length 237 [2024-12-02 06:23:00,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:00,944 INFO L471 AbstractCegarLoop]: Abstraction has 749 states and 1113 transitions. [2024-12-02 06:23:00,945 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 108.5) internal successors, (217), 2 states have internal predecessors, (217), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:23:00,945 INFO L276 IsEmpty]: Start isEmpty. Operand 749 states and 1113 transitions. [2024-12-02 06:23:00,949 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 238 [2024-12-02 06:23:00,949 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:00,949 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:00,961 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-12-02 06:23:01,153 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable0 [2024-12-02 06:23:01,153 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:01,154 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:01,154 INFO L85 PathProgramCache]: Analyzing trace with hash -807506718, now seen corresponding path program 1 times [2024-12-02 06:23:01,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:01,154 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [758489878] [2024-12-02 06:23:01,155 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:01,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:01,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:01,807 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:23:01,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:01,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [758489878] [2024-12-02 06:23:01,807 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [758489878] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:01,807 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:01,807 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:23:01,807 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [957929077] [2024-12-02 06:23:01,807 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:01,808 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:23:01,809 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:01,809 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:23:01,810 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:23:01,810 INFO L87 Difference]: Start difference. First operand 749 states and 1113 transitions. Second operand has 3 states, 3 states have (on average 71.66666666666667) internal successors, (215), 3 states have internal predecessors, (215), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:01,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:01,852 INFO L93 Difference]: Finished difference Result 1496 states and 2224 transitions. [2024-12-02 06:23:01,853 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:23:01,853 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 71.66666666666667) internal successors, (215), 3 states have internal predecessors, (215), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 237 [2024-12-02 06:23:01,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:01,856 INFO L225 Difference]: With dead ends: 1496 [2024-12-02 06:23:01,857 INFO L226 Difference]: Without dead ends: 755 [2024-12-02 06:23:01,858 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:23:01,859 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 7 mSDsluCounter, 1108 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 2219 SdHoareTripleChecker+Invalid, 6 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:01,859 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 2219 Invalid, 6 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:23:01,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 755 states. [2024-12-02 06:23:01,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 755 to 750. [2024-12-02 06:23:01,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 750 states, 743 states have (on average 1.4858681022880216) internal successors, (1104), 743 states have internal predecessors, (1104), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:23:01,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 750 states to 750 states and 1114 transitions. [2024-12-02 06:23:01,881 INFO L78 Accepts]: Start accepts. Automaton has 750 states and 1114 transitions. Word has length 237 [2024-12-02 06:23:01,881 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:01,881 INFO L471 AbstractCegarLoop]: Abstraction has 750 states and 1114 transitions. [2024-12-02 06:23:01,881 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 71.66666666666667) internal successors, (215), 3 states have internal predecessors, (215), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:01,881 INFO L276 IsEmpty]: Start isEmpty. Operand 750 states and 1114 transitions. [2024-12-02 06:23:01,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 242 [2024-12-02 06:23:01,885 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:01,885 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:01,885 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-12-02 06:23:01,886 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:01,886 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:01,886 INFO L85 PathProgramCache]: Analyzing trace with hash 1769687476, now seen corresponding path program 1 times [2024-12-02 06:23:01,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:01,886 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079004161] [2024-12-02 06:23:01,887 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:01,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:02,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:02,519 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:23:02,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:02,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079004161] [2024-12-02 06:23:02,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2079004161] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:02,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1451277566] [2024-12-02 06:23:02,520 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:02,520 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:02,521 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:02,522 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:02,524 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-12-02 06:23:02,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:02,961 INFO L256 TraceCheckSpWp]: Trace formula consists of 1082 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:23:02,969 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:02,999 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:23:03,000 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:23:03,050 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:23:03,050 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1451277566] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:03,050 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:23:03,050 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 6 [2024-12-02 06:23:03,050 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [52328827] [2024-12-02 06:23:03,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:03,051 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:23:03,051 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:03,052 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:23:03,052 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:23:03,052 INFO L87 Difference]: Start difference. First operand 750 states and 1114 transitions. Second operand has 3 states, 3 states have (on average 73.0) internal successors, (219), 3 states have internal predecessors, (219), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:03,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:03,093 INFO L93 Difference]: Finished difference Result 1469 states and 2184 transitions. [2024-12-02 06:23:03,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:23:03,094 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 73.0) internal successors, (219), 3 states have internal predecessors, (219), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 241 [2024-12-02 06:23:03,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:03,096 INFO L225 Difference]: With dead ends: 1469 [2024-12-02 06:23:03,096 INFO L226 Difference]: Without dead ends: 751 [2024-12-02 06:23:03,097 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 484 GetRequests, 480 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:23:03,098 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 7 mSDsluCounter, 1101 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 2212 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:03,098 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 2212 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:23:03,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 751 states. [2024-12-02 06:23:03,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 751 to 751. [2024-12-02 06:23:03,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 751 states, 744 states have (on average 1.4852150537634408) internal successors, (1105), 744 states have internal predecessors, (1105), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:23:03,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 751 states to 751 states and 1115 transitions. [2024-12-02 06:23:03,118 INFO L78 Accepts]: Start accepts. Automaton has 751 states and 1115 transitions. Word has length 241 [2024-12-02 06:23:03,118 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:03,118 INFO L471 AbstractCegarLoop]: Abstraction has 751 states and 1115 transitions. [2024-12-02 06:23:03,118 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 73.0) internal successors, (219), 3 states have internal predecessors, (219), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:03,119 INFO L276 IsEmpty]: Start isEmpty. Operand 751 states and 1115 transitions. [2024-12-02 06:23:03,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 246 [2024-12-02 06:23:03,122 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:03,122 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:03,132 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-12-02 06:23:03,322 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:03,322 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:03,323 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:03,323 INFO L85 PathProgramCache]: Analyzing trace with hash 650268102, now seen corresponding path program 1 times [2024-12-02 06:23:03,323 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:03,323 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831488430] [2024-12-02 06:23:03,323 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:03,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:03,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:03,747 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:23:03,747 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:03,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1831488430] [2024-12-02 06:23:03,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1831488430] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:03,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1504115884] [2024-12-02 06:23:03,747 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:03,748 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:03,748 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:03,750 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:03,752 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-12-02 06:23:04,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:04,232 INFO L256 TraceCheckSpWp]: Trace formula consists of 1093 conjuncts, 39 conjuncts are in the unsatisfiable core [2024-12-02 06:23:04,240 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:04,263 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:23:04,263 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:23:04,801 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2024-12-02 06:23:04,801 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1504115884] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:04,801 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:23:04,801 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 4] total 8 [2024-12-02 06:23:04,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [281792542] [2024-12-02 06:23:04,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:04,802 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:23:04,802 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:04,803 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:23:04,803 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:23:04,803 INFO L87 Difference]: Start difference. First operand 751 states and 1115 transitions. Second operand has 5 states, 5 states have (on average 44.6) internal successors, (223), 5 states have internal predecessors, (223), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:04,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:04,887 INFO L93 Difference]: Finished difference Result 1558 states and 2317 transitions. [2024-12-02 06:23:04,887 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:23:04,888 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 44.6) internal successors, (223), 5 states have internal predecessors, (223), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 245 [2024-12-02 06:23:04,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:04,892 INFO L225 Difference]: With dead ends: 1558 [2024-12-02 06:23:04,892 INFO L226 Difference]: Without dead ends: 905 [2024-12-02 06:23:04,893 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 492 GetRequests, 486 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:23:04,894 INFO L435 NwaCegarLoop]: 1107 mSDtfsCounter, 154 mSDsluCounter, 3312 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 154 SdHoareTripleChecker+Valid, 4419 SdHoareTripleChecker+Invalid, 31 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:04,894 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [154 Valid, 4419 Invalid, 31 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:23:04,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 905 states. [2024-12-02 06:23:04,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 905 to 905. [2024-12-02 06:23:04,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 905 states, 898 states have (on average 1.4866369710467706) internal successors, (1335), 898 states have internal predecessors, (1335), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:23:04,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 905 states to 905 states and 1345 transitions. [2024-12-02 06:23:04,919 INFO L78 Accepts]: Start accepts. Automaton has 905 states and 1345 transitions. Word has length 245 [2024-12-02 06:23:04,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:04,921 INFO L471 AbstractCegarLoop]: Abstraction has 905 states and 1345 transitions. [2024-12-02 06:23:04,921 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 44.6) internal successors, (223), 5 states have internal predecessors, (223), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:04,921 INFO L276 IsEmpty]: Start isEmpty. Operand 905 states and 1345 transitions. [2024-12-02 06:23:04,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 247 [2024-12-02 06:23:04,925 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:04,925 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:04,936 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2024-12-02 06:23:05,125 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2024-12-02 06:23:05,126 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:05,126 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:05,126 INFO L85 PathProgramCache]: Analyzing trace with hash 582510664, now seen corresponding path program 1 times [2024-12-02 06:23:05,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:05,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1848822553] [2024-12-02 06:23:05,127 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:05,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:05,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:05,509 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:23:05,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:05,510 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1848822553] [2024-12-02 06:23:05,510 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1848822553] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:05,510 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [502394374] [2024-12-02 06:23:05,510 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:05,510 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:05,510 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:05,513 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:05,516 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-12-02 06:23:06,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:06,036 INFO L256 TraceCheckSpWp]: Trace formula consists of 1096 conjuncts, 16 conjuncts are in the unsatisfiable core [2024-12-02 06:23:06,041 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:06,074 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:23:06,074 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:23:06,782 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:23:06,783 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [502394374] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:23:06,783 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:23:06,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 8] total 12 [2024-12-02 06:23:06,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [553171917] [2024-12-02 06:23:06,783 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:23:06,784 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2024-12-02 06:23:06,784 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:06,785 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2024-12-02 06:23:06,785 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:23:06,786 INFO L87 Difference]: Start difference. First operand 905 states and 1345 transitions. Second operand has 12 states, 12 states have (on average 29.75) internal successors, (357), 12 states have internal predecessors, (357), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:23:08,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:08,665 INFO L93 Difference]: Finished difference Result 2575 states and 3832 transitions. [2024-12-02 06:23:08,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:23:08,665 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 29.75) internal successors, (357), 12 states have internal predecessors, (357), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 246 [2024-12-02 06:23:08,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:08,672 INFO L225 Difference]: With dead ends: 2575 [2024-12-02 06:23:08,672 INFO L226 Difference]: Without dead ends: 1679 [2024-12-02 06:23:08,673 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 495 GetRequests, 484 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=53, Invalid=103, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:23:08,674 INFO L435 NwaCegarLoop]: 1365 mSDtfsCounter, 2973 mSDsluCounter, 7576 mSDsCounter, 0 mSdLazyCounter, 3037 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2978 SdHoareTripleChecker+Valid, 8941 SdHoareTripleChecker+Invalid, 3043 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 3037 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.7s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:08,674 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2978 Valid, 8941 Invalid, 3043 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 3037 Invalid, 0 Unknown, 0 Unchecked, 1.7s Time] [2024-12-02 06:23:08,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1679 states. [2024-12-02 06:23:08,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1679 to 1124. [2024-12-02 06:23:08,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1124 states, 1112 states have (on average 1.4838129496402879) internal successors, (1650), 1112 states have internal predecessors, (1650), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:23:08,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1124 states to 1124 states and 1670 transitions. [2024-12-02 06:23:08,717 INFO L78 Accepts]: Start accepts. Automaton has 1124 states and 1670 transitions. Word has length 246 [2024-12-02 06:23:08,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:08,718 INFO L471 AbstractCegarLoop]: Abstraction has 1124 states and 1670 transitions. [2024-12-02 06:23:08,718 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 29.75) internal successors, (357), 12 states have internal predecessors, (357), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:23:08,718 INFO L276 IsEmpty]: Start isEmpty. Operand 1124 states and 1670 transitions. [2024-12-02 06:23:08,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 252 [2024-12-02 06:23:08,723 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:08,723 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:08,735 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2024-12-02 06:23:08,923 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:08,923 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:08,924 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:08,924 INFO L85 PathProgramCache]: Analyzing trace with hash 658013442, now seen corresponding path program 1 times [2024-12-02 06:23:08,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:08,924 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028646586] [2024-12-02 06:23:08,924 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:08,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:09,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:09,377 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:23:09,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:09,377 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1028646586] [2024-12-02 06:23:09,377 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1028646586] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:09,377 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [683557852] [2024-12-02 06:23:09,377 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:09,377 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:09,378 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:09,379 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:09,381 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-12-02 06:23:09,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:09,839 INFO L256 TraceCheckSpWp]: Trace formula consists of 1110 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:23:09,845 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:09,874 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:23:09,874 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:23:09,926 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2024-12-02 06:23:09,926 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [683557852] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:23:09,926 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:23:09,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 6, 4] total 9 [2024-12-02 06:23:09,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [44138610] [2024-12-02 06:23:09,926 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:23:09,927 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:23:09,927 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:09,928 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:23:09,928 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:23:09,928 INFO L87 Difference]: Start difference. First operand 1124 states and 1670 transitions. Second operand has 9 states, 9 states have (on average 28.88888888888889) internal successors, (260), 9 states have internal predecessors, (260), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:23:10,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:10,012 INFO L93 Difference]: Finished difference Result 2280 states and 3390 transitions. [2024-12-02 06:23:10,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:23:10,013 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 28.88888888888889) internal successors, (260), 9 states have internal predecessors, (260), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 251 [2024-12-02 06:23:10,013 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:10,016 INFO L225 Difference]: With dead ends: 2280 [2024-12-02 06:23:10,016 INFO L226 Difference]: Without dead ends: 1171 [2024-12-02 06:23:10,018 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 506 GetRequests, 498 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:23:10,018 INFO L435 NwaCegarLoop]: 1121 mSDtfsCounter, 56 mSDsluCounter, 4457 mSDsCounter, 0 mSdLazyCounter, 52 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 56 SdHoareTripleChecker+Valid, 5578 SdHoareTripleChecker+Invalid, 54 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 52 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:10,019 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [56 Valid, 5578 Invalid, 54 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 52 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:23:10,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1171 states. [2024-12-02 06:23:10,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1171 to 1166. [2024-12-02 06:23:10,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1166 states, 1154 states have (on average 1.4783362218370883) internal successors, (1706), 1154 states have internal predecessors, (1706), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:23:10,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1166 states to 1166 states and 1726 transitions. [2024-12-02 06:23:10,050 INFO L78 Accepts]: Start accepts. Automaton has 1166 states and 1726 transitions. Word has length 251 [2024-12-02 06:23:10,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:10,050 INFO L471 AbstractCegarLoop]: Abstraction has 1166 states and 1726 transitions. [2024-12-02 06:23:10,050 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 28.88888888888889) internal successors, (260), 9 states have internal predecessors, (260), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:23:10,050 INFO L276 IsEmpty]: Start isEmpty. Operand 1166 states and 1726 transitions. [2024-12-02 06:23:10,054 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 268 [2024-12-02 06:23:10,054 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:10,054 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:10,066 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-12-02 06:23:10,255 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:10,255 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:10,255 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:10,256 INFO L85 PathProgramCache]: Analyzing trace with hash -771710754, now seen corresponding path program 2 times [2024-12-02 06:23:10,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:10,256 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1315256879] [2024-12-02 06:23:10,256 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:23:10,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:10,318 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:23:10,318 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:23:10,647 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2024-12-02 06:23:10,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:10,647 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1315256879] [2024-12-02 06:23:10,647 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1315256879] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:10,647 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:10,648 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:23:10,648 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1227989768] [2024-12-02 06:23:10,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:10,648 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:23:10,648 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:10,649 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:23:10,649 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:23:10,649 INFO L87 Difference]: Start difference. First operand 1166 states and 1726 transitions. Second operand has 4 states, 4 states have (on average 56.25) internal successors, (225), 4 states have internal predecessors, (225), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:10,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:10,675 INFO L93 Difference]: Finished difference Result 1170 states and 1730 transitions. [2024-12-02 06:23:10,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:23:10,676 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 56.25) internal successors, (225), 4 states have internal predecessors, (225), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 267 [2024-12-02 06:23:10,676 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:10,680 INFO L225 Difference]: With dead ends: 1170 [2024-12-02 06:23:10,680 INFO L226 Difference]: Without dead ends: 1168 [2024-12-02 06:23:10,681 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:23:10,682 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 0 mSDsluCounter, 2216 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3327 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:10,682 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3327 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:23:10,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1168 states. [2024-12-02 06:23:10,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1168 to 1168. [2024-12-02 06:23:10,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1168 states, 1156 states have (on average 1.4775086505190311) internal successors, (1708), 1156 states have internal predecessors, (1708), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:23:10,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1168 states to 1168 states and 1728 transitions. [2024-12-02 06:23:10,702 INFO L78 Accepts]: Start accepts. Automaton has 1168 states and 1728 transitions. Word has length 267 [2024-12-02 06:23:10,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:10,702 INFO L471 AbstractCegarLoop]: Abstraction has 1168 states and 1728 transitions. [2024-12-02 06:23:10,703 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 56.25) internal successors, (225), 4 states have internal predecessors, (225), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:10,703 INFO L276 IsEmpty]: Start isEmpty. Operand 1168 states and 1728 transitions. [2024-12-02 06:23:10,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 269 [2024-12-02 06:23:10,705 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:10,706 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:10,706 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2024-12-02 06:23:10,706 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:10,706 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:10,706 INFO L85 PathProgramCache]: Analyzing trace with hash 1848466914, now seen corresponding path program 1 times [2024-12-02 06:23:10,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:10,706 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271418957] [2024-12-02 06:23:10,706 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:10,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:10,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:11,020 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 68 trivial. 0 not checked. [2024-12-02 06:23:11,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:11,020 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1271418957] [2024-12-02 06:23:11,021 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1271418957] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:11,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1725153088] [2024-12-02 06:23:11,021 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:11,021 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:11,021 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:11,022 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:11,024 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-12-02 06:23:11,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:11,530 INFO L256 TraceCheckSpWp]: Trace formula consists of 1157 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-12-02 06:23:11,534 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:11,559 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 68 trivial. 0 not checked. [2024-12-02 06:23:11,559 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:23:11,721 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 13 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:23:11,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1725153088] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:23:11,721 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:23:11,721 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 10] total 15 [2024-12-02 06:23:11,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1812796451] [2024-12-02 06:23:11,721 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:23:11,723 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2024-12-02 06:23:11,723 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:11,723 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2024-12-02 06:23:11,724 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2024-12-02 06:23:11,724 INFO L87 Difference]: Start difference. First operand 1168 states and 1728 transitions. Second operand has 15 states, 15 states have (on average 17.8) internal successors, (267), 15 states have internal predecessors, (267), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:23:11,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:11,880 INFO L93 Difference]: Finished difference Result 2345 states and 3473 transitions. [2024-12-02 06:23:11,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:23:11,880 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 17.8) internal successors, (267), 15 states have internal predecessors, (267), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 268 [2024-12-02 06:23:11,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:11,884 INFO L225 Difference]: With dead ends: 2345 [2024-12-02 06:23:11,884 INFO L226 Difference]: Without dead ends: 1198 [2024-12-02 06:23:11,886 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 543 GetRequests, 527 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=84, Invalid=222, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:23:11,887 INFO L435 NwaCegarLoop]: 1129 mSDtfsCounter, 122 mSDsluCounter, 8996 mSDsCounter, 0 mSdLazyCounter, 108 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 122 SdHoareTripleChecker+Valid, 10125 SdHoareTripleChecker+Invalid, 110 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 108 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:11,887 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [122 Valid, 10125 Invalid, 110 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 108 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:23:11,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1198 states. [2024-12-02 06:23:11,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1198 to 1198. [2024-12-02 06:23:11,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1198 states, 1186 states have (on average 1.4738617200674535) internal successors, (1748), 1186 states have internal predecessors, (1748), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:23:11,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1198 states to 1198 states and 1768 transitions. [2024-12-02 06:23:11,919 INFO L78 Accepts]: Start accepts. Automaton has 1198 states and 1768 transitions. Word has length 268 [2024-12-02 06:23:11,919 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:11,919 INFO L471 AbstractCegarLoop]: Abstraction has 1198 states and 1768 transitions. [2024-12-02 06:23:11,919 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 17.8) internal successors, (267), 15 states have internal predecessors, (267), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:23:11,919 INFO L276 IsEmpty]: Start isEmpty. Operand 1198 states and 1768 transitions. [2024-12-02 06:23:11,924 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 289 [2024-12-02 06:23:11,924 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:11,924 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:11,935 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-12-02 06:23:12,124 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:12,125 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:12,125 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:12,125 INFO L85 PathProgramCache]: Analyzing trace with hash 1690764424, now seen corresponding path program 2 times [2024-12-02 06:23:12,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:12,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215764694] [2024-12-02 06:23:12,126 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:23:12,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:12,204 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:23:12,204 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:23:12,448 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 188 trivial. 0 not checked. [2024-12-02 06:23:12,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:12,449 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1215764694] [2024-12-02 06:23:12,449 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1215764694] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:12,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:12,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:23:12,449 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1543319388] [2024-12-02 06:23:12,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:12,450 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:23:12,450 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:12,450 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:23:12,450 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:23:12,450 INFO L87 Difference]: Start difference. First operand 1198 states and 1768 transitions. Second operand has 4 states, 4 states have (on average 56.5) internal successors, (226), 4 states have internal predecessors, (226), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:12,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:12,488 INFO L93 Difference]: Finished difference Result 2009 states and 2974 transitions. [2024-12-02 06:23:12,489 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:23:12,489 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 56.5) internal successors, (226), 4 states have internal predecessors, (226), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 288 [2024-12-02 06:23:12,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:12,493 INFO L225 Difference]: With dead ends: 2009 [2024-12-02 06:23:12,493 INFO L226 Difference]: Without dead ends: 1200 [2024-12-02 06:23:12,494 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:23:12,495 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 0 mSDsluCounter, 2212 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3323 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:12,495 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3323 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:23:12,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1200 states. [2024-12-02 06:23:12,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1200 to 1200. [2024-12-02 06:23:12,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1200 states, 1188 states have (on average 1.473063973063973) internal successors, (1750), 1188 states have internal predecessors, (1750), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:23:12,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1200 states to 1200 states and 1770 transitions. [2024-12-02 06:23:12,526 INFO L78 Accepts]: Start accepts. Automaton has 1200 states and 1770 transitions. Word has length 288 [2024-12-02 06:23:12,526 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:12,526 INFO L471 AbstractCegarLoop]: Abstraction has 1200 states and 1770 transitions. [2024-12-02 06:23:12,527 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 56.5) internal successors, (226), 4 states have internal predecessors, (226), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:12,527 INFO L276 IsEmpty]: Start isEmpty. Operand 1200 states and 1770 transitions. [2024-12-02 06:23:12,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 290 [2024-12-02 06:23:12,529 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:12,530 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:12,530 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2024-12-02 06:23:12,530 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:12,530 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:12,530 INFO L85 PathProgramCache]: Analyzing trace with hash -223874991, now seen corresponding path program 1 times [2024-12-02 06:23:12,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:12,531 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1646194230] [2024-12-02 06:23:12,531 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:12,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:12,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:13,030 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2024-12-02 06:23:13,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:13,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1646194230] [2024-12-02 06:23:13,030 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1646194230] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:13,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1482307944] [2024-12-02 06:23:13,030 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:13,030 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:13,030 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:13,032 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:13,033 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-12-02 06:23:13,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:13,450 INFO L256 TraceCheckSpWp]: Trace formula consists of 1215 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-12-02 06:23:13,453 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:13,520 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 124 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2024-12-02 06:23:13,520 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:23:13,631 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2024-12-02 06:23:13,631 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1482307944] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:23:13,631 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:23:13,632 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-12-02 06:23:13,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [554531620] [2024-12-02 06:23:13,632 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:23:13,632 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-12-02 06:23:13,632 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:13,633 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-12-02 06:23:13,633 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:23:13,633 INFO L87 Difference]: Start difference. First operand 1200 states and 1770 transitions. Second operand has 18 states, 18 states have (on average 15.555555555555555) internal successors, (280), 18 states have internal predecessors, (280), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:23:13,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:13,868 INFO L93 Difference]: Finished difference Result 2329 states and 3450 transitions. [2024-12-02 06:23:13,868 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-12-02 06:23:13,868 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 15.555555555555555) internal successors, (280), 18 states have internal predecessors, (280), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 289 [2024-12-02 06:23:13,869 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:13,873 INFO L225 Difference]: With dead ends: 2329 [2024-12-02 06:23:13,873 INFO L226 Difference]: Without dead ends: 1248 [2024-12-02 06:23:13,874 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 585 GetRequests, 567 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:23:13,875 INFO L435 NwaCegarLoop]: 1157 mSDtfsCounter, 107 mSDsluCounter, 14862 mSDsCounter, 0 mSdLazyCounter, 280 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 107 SdHoareTripleChecker+Valid, 16019 SdHoareTripleChecker+Invalid, 281 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 280 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:13,875 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [107 Valid, 16019 Invalid, 281 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 280 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:23:13,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1248 states. [2024-12-02 06:23:13,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1248 to 1248. [2024-12-02 06:23:13,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1248 states, 1236 states have (on average 1.4676375404530744) internal successors, (1814), 1236 states have internal predecessors, (1814), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:23:13,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1248 states to 1248 states and 1834 transitions. [2024-12-02 06:23:13,908 INFO L78 Accepts]: Start accepts. Automaton has 1248 states and 1834 transitions. Word has length 289 [2024-12-02 06:23:13,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:13,909 INFO L471 AbstractCegarLoop]: Abstraction has 1248 states and 1834 transitions. [2024-12-02 06:23:13,909 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 15.555555555555555) internal successors, (280), 18 states have internal predecessors, (280), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:23:13,909 INFO L276 IsEmpty]: Start isEmpty. Operand 1248 states and 1834 transitions. [2024-12-02 06:23:13,912 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 306 [2024-12-02 06:23:13,912 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:13,912 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:13,925 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-12-02 06:23:14,112 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9,8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:14,113 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:14,113 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:14,113 INFO L85 PathProgramCache]: Analyzing trace with hash 983758089, now seen corresponding path program 2 times [2024-12-02 06:23:14,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:14,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055422371] [2024-12-02 06:23:14,113 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:23:14,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:14,201 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:23:14,202 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:23:14,644 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:23:14,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:14,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1055422371] [2024-12-02 06:23:14,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1055422371] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:14,645 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:14,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:23:14,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1390852469] [2024-12-02 06:23:14,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:14,645 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:23:14,646 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:14,646 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:23:14,646 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:23:14,646 INFO L87 Difference]: Start difference. First operand 1248 states and 1834 transitions. Second operand has 4 states, 4 states have (on average 56.75) internal successors, (227), 4 states have internal predecessors, (227), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:14,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:14,838 INFO L93 Difference]: Finished difference Result 2059 states and 3039 transitions. [2024-12-02 06:23:14,838 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:23:14,839 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 56.75) internal successors, (227), 4 states have internal predecessors, (227), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 305 [2024-12-02 06:23:14,839 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:14,841 INFO L225 Difference]: With dead ends: 2059 [2024-12-02 06:23:14,841 INFO L226 Difference]: Without dead ends: 1248 [2024-12-02 06:23:14,842 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:23:14,843 INFO L435 NwaCegarLoop]: 1012 mSDtfsCounter, 961 mSDsluCounter, 1014 mSDsCounter, 0 mSdLazyCounter, 204 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 961 SdHoareTripleChecker+Valid, 2026 SdHoareTripleChecker+Invalid, 204 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 204 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:14,843 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [961 Valid, 2026 Invalid, 204 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 204 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:23:14,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1248 states. [2024-12-02 06:23:14,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1248 to 1248. [2024-12-02 06:23:14,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1248 states, 1236 states have (on average 1.4660194174757282) internal successors, (1812), 1236 states have internal predecessors, (1812), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:23:14,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1248 states to 1248 states and 1832 transitions. [2024-12-02 06:23:14,877 INFO L78 Accepts]: Start accepts. Automaton has 1248 states and 1832 transitions. Word has length 305 [2024-12-02 06:23:14,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:14,878 INFO L471 AbstractCegarLoop]: Abstraction has 1248 states and 1832 transitions. [2024-12-02 06:23:14,878 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 56.75) internal successors, (227), 4 states have internal predecessors, (227), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:14,878 INFO L276 IsEmpty]: Start isEmpty. Operand 1248 states and 1832 transitions. [2024-12-02 06:23:14,881 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 307 [2024-12-02 06:23:14,881 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:14,881 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:14,881 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2024-12-02 06:23:14,881 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:14,882 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:14,882 INFO L85 PathProgramCache]: Analyzing trace with hash 178411131, now seen corresponding path program 1 times [2024-12-02 06:23:14,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:14,882 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [906613108] [2024-12-02 06:23:14,882 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:14,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:14,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:15,217 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:23:15,217 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:15,217 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [906613108] [2024-12-02 06:23:15,217 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [906613108] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:15,217 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:15,217 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:23:15,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1084816240] [2024-12-02 06:23:15,217 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:15,218 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:23:15,218 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:15,218 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:23:15,218 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:23:15,218 INFO L87 Difference]: Start difference. First operand 1248 states and 1832 transitions. Second operand has 5 states, 5 states have (on average 45.6) internal successors, (228), 5 states have internal predecessors, (228), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:15,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:15,344 INFO L93 Difference]: Finished difference Result 2111 states and 3110 transitions. [2024-12-02 06:23:15,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:23:15,345 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 45.6) internal successors, (228), 5 states have internal predecessors, (228), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 306 [2024-12-02 06:23:15,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:15,348 INFO L225 Difference]: With dead ends: 2111 [2024-12-02 06:23:15,348 INFO L226 Difference]: Without dead ends: 1248 [2024-12-02 06:23:15,348 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:23:15,349 INFO L435 NwaCegarLoop]: 1100 mSDtfsCounter, 1064 mSDsluCounter, 2118 mSDsCounter, 0 mSdLazyCounter, 123 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1064 SdHoareTripleChecker+Valid, 3218 SdHoareTripleChecker+Invalid, 124 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 123 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:15,349 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1064 Valid, 3218 Invalid, 124 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 123 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:23:15,350 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1248 states. [2024-12-02 06:23:15,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1248 to 1248. [2024-12-02 06:23:15,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1248 states, 1236 states have (on average 1.464401294498382) internal successors, (1810), 1236 states have internal predecessors, (1810), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:23:15,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1248 states to 1248 states and 1830 transitions. [2024-12-02 06:23:15,369 INFO L78 Accepts]: Start accepts. Automaton has 1248 states and 1830 transitions. Word has length 306 [2024-12-02 06:23:15,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:15,369 INFO L471 AbstractCegarLoop]: Abstraction has 1248 states and 1830 transitions. [2024-12-02 06:23:15,369 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 45.6) internal successors, (228), 5 states have internal predecessors, (228), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:15,369 INFO L276 IsEmpty]: Start isEmpty. Operand 1248 states and 1830 transitions. [2024-12-02 06:23:15,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 308 [2024-12-02 06:23:15,372 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:15,372 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:15,372 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2024-12-02 06:23:15,372 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:15,372 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:15,373 INFO L85 PathProgramCache]: Analyzing trace with hash -990624561, now seen corresponding path program 1 times [2024-12-02 06:23:15,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:15,373 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1675374397] [2024-12-02 06:23:15,373 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:15,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:15,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:15,905 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:23:15,905 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:15,905 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1675374397] [2024-12-02 06:23:15,905 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1675374397] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:15,905 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:15,906 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:23:15,906 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [649160660] [2024-12-02 06:23:15,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:15,906 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:23:15,906 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:15,907 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:23:15,907 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:23:15,907 INFO L87 Difference]: Start difference. First operand 1248 states and 1830 transitions. Second operand has 4 states, 4 states have (on average 57.25) internal successors, (229), 4 states have internal predecessors, (229), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:16,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:16,102 INFO L93 Difference]: Finished difference Result 2065 states and 3040 transitions. [2024-12-02 06:23:16,102 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:23:16,103 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 57.25) internal successors, (229), 4 states have internal predecessors, (229), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 307 [2024-12-02 06:23:16,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:16,105 INFO L225 Difference]: With dead ends: 2065 [2024-12-02 06:23:16,105 INFO L226 Difference]: Without dead ends: 1248 [2024-12-02 06:23:16,106 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:23:16,106 INFO L435 NwaCegarLoop]: 1012 mSDtfsCounter, 978 mSDsluCounter, 1014 mSDsCounter, 0 mSdLazyCounter, 200 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 978 SdHoareTripleChecker+Valid, 2026 SdHoareTripleChecker+Invalid, 200 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 200 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:16,107 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [978 Valid, 2026 Invalid, 200 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 200 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:23:16,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1248 states. [2024-12-02 06:23:16,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1248 to 1248. [2024-12-02 06:23:16,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1248 states, 1236 states have (on average 1.4627831715210355) internal successors, (1808), 1236 states have internal predecessors, (1808), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:23:16,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1248 states to 1248 states and 1828 transitions. [2024-12-02 06:23:16,128 INFO L78 Accepts]: Start accepts. Automaton has 1248 states and 1828 transitions. Word has length 307 [2024-12-02 06:23:16,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:16,128 INFO L471 AbstractCegarLoop]: Abstraction has 1248 states and 1828 transitions. [2024-12-02 06:23:16,128 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 57.25) internal successors, (229), 4 states have internal predecessors, (229), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:16,128 INFO L276 IsEmpty]: Start isEmpty. Operand 1248 states and 1828 transitions. [2024-12-02 06:23:16,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 309 [2024-12-02 06:23:16,131 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:16,131 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:16,131 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2024-12-02 06:23:16,131 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:16,132 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:16,132 INFO L85 PathProgramCache]: Analyzing trace with hash -787051624, now seen corresponding path program 1 times [2024-12-02 06:23:16,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:16,132 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768865848] [2024-12-02 06:23:16,132 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:16,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:16,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:16,684 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:23:16,685 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:16,685 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1768865848] [2024-12-02 06:23:16,685 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1768865848] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:16,685 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:16,685 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:23:16,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342430310] [2024-12-02 06:23:16,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:16,686 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:23:16,686 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:16,686 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:23:16,686 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:23:16,687 INFO L87 Difference]: Start difference. First operand 1248 states and 1828 transitions. Second operand has 4 states, 4 states have (on average 57.5) internal successors, (230), 4 states have internal predecessors, (230), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:16,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:16,881 INFO L93 Difference]: Finished difference Result 2059 states and 3029 transitions. [2024-12-02 06:23:16,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:23:16,881 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 57.5) internal successors, (230), 4 states have internal predecessors, (230), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 308 [2024-12-02 06:23:16,882 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:16,884 INFO L225 Difference]: With dead ends: 2059 [2024-12-02 06:23:16,884 INFO L226 Difference]: Without dead ends: 1248 [2024-12-02 06:23:16,885 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:23:16,885 INFO L435 NwaCegarLoop]: 1012 mSDtfsCounter, 955 mSDsluCounter, 1014 mSDsCounter, 0 mSdLazyCounter, 198 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 955 SdHoareTripleChecker+Valid, 2026 SdHoareTripleChecker+Invalid, 198 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 198 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:16,885 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [955 Valid, 2026 Invalid, 198 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 198 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:23:16,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1248 states. [2024-12-02 06:23:16,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1248 to 1248. [2024-12-02 06:23:16,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1248 states, 1236 states have (on average 1.4611650485436893) internal successors, (1806), 1236 states have internal predecessors, (1806), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:23:16,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1248 states to 1248 states and 1826 transitions. [2024-12-02 06:23:16,904 INFO L78 Accepts]: Start accepts. Automaton has 1248 states and 1826 transitions. Word has length 308 [2024-12-02 06:23:16,905 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:16,905 INFO L471 AbstractCegarLoop]: Abstraction has 1248 states and 1826 transitions. [2024-12-02 06:23:16,905 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 57.5) internal successors, (230), 4 states have internal predecessors, (230), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:16,905 INFO L276 IsEmpty]: Start isEmpty. Operand 1248 states and 1826 transitions. [2024-12-02 06:23:16,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 310 [2024-12-02 06:23:16,907 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:16,907 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:16,907 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2024-12-02 06:23:16,907 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:16,908 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:16,908 INFO L85 PathProgramCache]: Analyzing trace with hash 957685519, now seen corresponding path program 1 times [2024-12-02 06:23:16,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:16,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2116508164] [2024-12-02 06:23:16,908 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:16,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:17,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:18,104 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:23:18,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:18,104 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2116508164] [2024-12-02 06:23:18,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2116508164] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:18,104 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:18,105 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-12-02 06:23:18,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [265177470] [2024-12-02 06:23:18,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:18,105 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:23:18,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:18,106 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:23:18,106 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:23:18,106 INFO L87 Difference]: Start difference. First operand 1248 states and 1826 transitions. Second operand has 9 states, 9 states have (on average 25.666666666666668) internal successors, (231), 9 states have internal predecessors, (231), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:23:19,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:19,171 INFO L93 Difference]: Finished difference Result 2167 states and 3184 transitions. [2024-12-02 06:23:19,171 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:23:19,171 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 25.666666666666668) internal successors, (231), 9 states have internal predecessors, (231), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 309 [2024-12-02 06:23:19,172 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:19,176 INFO L225 Difference]: With dead ends: 2167 [2024-12-02 06:23:19,176 INFO L226 Difference]: Without dead ends: 1272 [2024-12-02 06:23:19,177 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:23:19,178 INFO L435 NwaCegarLoop]: 808 mSDtfsCounter, 1038 mSDsluCounter, 4789 mSDsCounter, 0 mSdLazyCounter, 2147 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1041 SdHoareTripleChecker+Valid, 5597 SdHoareTripleChecker+Invalid, 2150 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 2147 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:19,178 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1041 Valid, 5597 Invalid, 2150 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 2147 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-12-02 06:23:19,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1272 states. [2024-12-02 06:23:19,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1272 to 1264. [2024-12-02 06:23:19,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1264 states, 1252 states have (on average 1.4600638977635783) internal successors, (1828), 1252 states have internal predecessors, (1828), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:23:19,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1264 states to 1264 states and 1848 transitions. [2024-12-02 06:23:19,209 INFO L78 Accepts]: Start accepts. Automaton has 1264 states and 1848 transitions. Word has length 309 [2024-12-02 06:23:19,209 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:19,209 INFO L471 AbstractCegarLoop]: Abstraction has 1264 states and 1848 transitions. [2024-12-02 06:23:19,210 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 25.666666666666668) internal successors, (231), 9 states have internal predecessors, (231), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:23:19,210 INFO L276 IsEmpty]: Start isEmpty. Operand 1264 states and 1848 transitions. [2024-12-02 06:23:19,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 311 [2024-12-02 06:23:19,220 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:19,221 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:19,221 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2024-12-02 06:23:19,221 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:19,222 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:19,222 INFO L85 PathProgramCache]: Analyzing trace with hash 239088988, now seen corresponding path program 1 times [2024-12-02 06:23:19,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:19,222 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493979933] [2024-12-02 06:23:19,222 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:19,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:19,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:20,317 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:23:20,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:20,317 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1493979933] [2024-12-02 06:23:20,317 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1493979933] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:20,317 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:20,318 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2024-12-02 06:23:20,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [201353555] [2024-12-02 06:23:20,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:20,318 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 06:23:20,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:20,319 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 06:23:20,319 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:23:20,319 INFO L87 Difference]: Start difference. First operand 1264 states and 1848 transitions. Second operand has 10 states, 10 states have (on average 23.2) internal successors, (232), 10 states have internal predecessors, (232), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:23:21,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:21,487 INFO L93 Difference]: Finished difference Result 2207 states and 3239 transitions. [2024-12-02 06:23:21,487 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:23:21,488 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 23.2) internal successors, (232), 10 states have internal predecessors, (232), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 310 [2024-12-02 06:23:21,488 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:21,490 INFO L225 Difference]: With dead ends: 2207 [2024-12-02 06:23:21,490 INFO L226 Difference]: Without dead ends: 1312 [2024-12-02 06:23:21,491 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:23:21,492 INFO L435 NwaCegarLoop]: 807 mSDtfsCounter, 1051 mSDsluCounter, 5567 mSDsCounter, 0 mSdLazyCounter, 2461 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1054 SdHoareTripleChecker+Valid, 6374 SdHoareTripleChecker+Invalid, 2464 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 2461 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:21,492 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1054 Valid, 6374 Invalid, 2464 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 2461 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-12-02 06:23:21,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1312 states. [2024-12-02 06:23:21,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1312 to 1278. [2024-12-02 06:23:21,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1266 states have (on average 1.4612954186413902) internal successors, (1850), 1266 states have internal predecessors, (1850), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:23:21,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1870 transitions. [2024-12-02 06:23:21,519 INFO L78 Accepts]: Start accepts. Automaton has 1278 states and 1870 transitions. Word has length 310 [2024-12-02 06:23:21,519 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:21,519 INFO L471 AbstractCegarLoop]: Abstraction has 1278 states and 1870 transitions. [2024-12-02 06:23:21,520 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 23.2) internal successors, (232), 10 states have internal predecessors, (232), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:23:21,520 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1870 transitions. [2024-12-02 06:23:21,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 311 [2024-12-02 06:23:21,524 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:21,524 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:21,524 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2024-12-02 06:23:21,524 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:21,525 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:21,525 INFO L85 PathProgramCache]: Analyzing trace with hash -2120664431, now seen corresponding path program 1 times [2024-12-02 06:23:21,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:21,525 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999992661] [2024-12-02 06:23:21,525 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:21,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:21,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:22,793 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-12-02 06:23:22,793 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:22,793 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1999992661] [2024-12-02 06:23:22,793 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1999992661] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:22,793 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:22,793 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:23:22,794 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1782319013] [2024-12-02 06:23:22,794 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:22,794 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:23:22,794 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:22,794 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:23:22,795 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:23:22,795 INFO L87 Difference]: Start difference. First operand 1278 states and 1870 transitions. Second operand has 7 states, 7 states have (on average 33.142857142857146) internal successors, (232), 7 states have internal predecessors, (232), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:22,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:22,957 INFO L93 Difference]: Finished difference Result 2593 states and 3817 transitions. [2024-12-02 06:23:22,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:23:22,958 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 33.142857142857146) internal successors, (232), 7 states have internal predecessors, (232), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 310 [2024-12-02 06:23:22,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:22,963 INFO L225 Difference]: With dead ends: 2593 [2024-12-02 06:23:22,964 INFO L226 Difference]: Without dead ends: 1767 [2024-12-02 06:23:22,965 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:23:22,965 INFO L435 NwaCegarLoop]: 1092 mSDtfsCounter, 1805 mSDsluCounter, 4356 mSDsCounter, 0 mSdLazyCounter, 105 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1810 SdHoareTripleChecker+Valid, 5448 SdHoareTripleChecker+Invalid, 111 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 105 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:22,965 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1810 Valid, 5448 Invalid, 111 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 105 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:23:22,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1767 states. [2024-12-02 06:23:22,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1767 to 1767. [2024-12-02 06:23:22,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1767 states, 1750 states have (on average 1.4657142857142857) internal successors, (2565), 1750 states have internal predecessors, (2565), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:23:23,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1767 states to 1767 states and 2595 transitions. [2024-12-02 06:23:23,000 INFO L78 Accepts]: Start accepts. Automaton has 1767 states and 2595 transitions. Word has length 310 [2024-12-02 06:23:23,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:23,001 INFO L471 AbstractCegarLoop]: Abstraction has 1767 states and 2595 transitions. [2024-12-02 06:23:23,001 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 33.142857142857146) internal successors, (232), 7 states have internal predecessors, (232), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:23,001 INFO L276 IsEmpty]: Start isEmpty. Operand 1767 states and 2595 transitions. [2024-12-02 06:23:23,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 670 [2024-12-02 06:23:23,007 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:23,007 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:23,007 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2024-12-02 06:23:23,007 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:23,008 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:23,008 INFO L85 PathProgramCache]: Analyzing trace with hash -392694466, now seen corresponding path program 1 times [2024-12-02 06:23:23,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:23,008 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007077468] [2024-12-02 06:23:23,008 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:23,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:23,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:24,012 INFO L134 CoverageAnalysis]: Checked inductivity of 596 backedges. 176 proven. 0 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:23:24,013 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:24,013 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1007077468] [2024-12-02 06:23:24,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1007077468] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:24,013 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:24,013 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:23:24,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613724761] [2024-12-02 06:23:24,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:24,014 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:23:24,014 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:24,015 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:23:24,015 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:23:24,016 INFO L87 Difference]: Start difference. First operand 1767 states and 2595 transitions. Second operand has 3 states, 3 states have (on average 188.66666666666666) internal successors, (566), 3 states have internal predecessors, (566), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:24,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:24,043 INFO L93 Difference]: Finished difference Result 2595 states and 3819 transitions. [2024-12-02 06:23:24,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:23:24,044 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 188.66666666666666) internal successors, (566), 3 states have internal predecessors, (566), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 669 [2024-12-02 06:23:24,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:24,048 INFO L225 Difference]: With dead ends: 2595 [2024-12-02 06:23:24,048 INFO L226 Difference]: Without dead ends: 1769 [2024-12-02 06:23:24,049 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:23:24,049 INFO L435 NwaCegarLoop]: 1107 mSDtfsCounter, 1 mSDsluCounter, 1103 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2210 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:24,049 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2210 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:23:24,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1769 states. [2024-12-02 06:23:24,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1769 to 1768. [2024-12-02 06:23:24,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1768 states, 1751 states have (on average 1.4654483152484294) internal successors, (2566), 1751 states have internal predecessors, (2566), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:23:24,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1768 states to 1768 states and 2596 transitions. [2024-12-02 06:23:24,074 INFO L78 Accepts]: Start accepts. Automaton has 1768 states and 2596 transitions. Word has length 669 [2024-12-02 06:23:24,075 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:24,075 INFO L471 AbstractCegarLoop]: Abstraction has 1768 states and 2596 transitions. [2024-12-02 06:23:24,075 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 188.66666666666666) internal successors, (566), 3 states have internal predecessors, (566), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:24,075 INFO L276 IsEmpty]: Start isEmpty. Operand 1768 states and 2596 transitions. [2024-12-02 06:23:24,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 672 [2024-12-02 06:23:24,079 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:24,079 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:24,079 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2024-12-02 06:23:24,080 INFO L396 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:24,080 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:24,080 INFO L85 PathProgramCache]: Analyzing trace with hash 1830801850, now seen corresponding path program 1 times [2024-12-02 06:23:24,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:24,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855701350] [2024-12-02 06:23:24,081 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:24,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:24,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:25,020 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 176 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:23:25,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:25,020 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1855701350] [2024-12-02 06:23:25,020 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1855701350] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:25,020 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1583246078] [2024-12-02 06:23:25,020 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:25,020 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:25,021 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:25,022 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:25,023 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-12-02 06:23:25,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:25,992 INFO L256 TraceCheckSpWp]: Trace formula consists of 3323 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-12-02 06:23:26,000 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:26,796 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 276 proven. 0 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2024-12-02 06:23:26,796 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:23:26,796 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1583246078] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:26,796 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:23:26,796 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2024-12-02 06:23:26,797 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1808139273] [2024-12-02 06:23:26,797 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:26,797 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:23:26,797 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:26,798 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:23:26,798 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:23:26,798 INFO L87 Difference]: Start difference. First operand 1768 states and 2596 transitions. Second operand has 4 states, 4 states have (on average 142.75) internal successors, (571), 4 states have internal predecessors, (571), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:27,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:27,172 INFO L93 Difference]: Finished difference Result 2594 states and 3817 transitions. [2024-12-02 06:23:27,173 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:23:27,173 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 142.75) internal successors, (571), 4 states have internal predecessors, (571), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 671 [2024-12-02 06:23:27,173 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:27,178 INFO L225 Difference]: With dead ends: 2594 [2024-12-02 06:23:27,178 INFO L226 Difference]: Without dead ends: 1767 [2024-12-02 06:23:27,179 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 675 GetRequests, 670 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:23:27,179 INFO L435 NwaCegarLoop]: 808 mSDtfsCounter, 836 mSDsluCounter, 810 mSDsCounter, 0 mSdLazyCounter, 601 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 836 SdHoareTripleChecker+Valid, 1618 SdHoareTripleChecker+Invalid, 602 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 601 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:27,179 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [836 Valid, 1618 Invalid, 602 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 601 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-12-02 06:23:27,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1767 states. [2024-12-02 06:23:27,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1767 to 1767. [2024-12-02 06:23:27,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1767 states, 1750 states have (on average 1.4645714285714286) internal successors, (2563), 1750 states have internal predecessors, (2563), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:23:27,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1767 states to 1767 states and 2593 transitions. [2024-12-02 06:23:27,212 INFO L78 Accepts]: Start accepts. Automaton has 1767 states and 2593 transitions. Word has length 671 [2024-12-02 06:23:27,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:27,212 INFO L471 AbstractCegarLoop]: Abstraction has 1767 states and 2593 transitions. [2024-12-02 06:23:27,212 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 142.75) internal successors, (571), 4 states have internal predecessors, (571), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:27,212 INFO L276 IsEmpty]: Start isEmpty. Operand 1767 states and 2593 transitions. [2024-12-02 06:23:27,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 673 [2024-12-02 06:23:27,218 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:27,218 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:27,228 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2024-12-02 06:23:27,418 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:27,419 INFO L396 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:27,419 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:27,420 INFO L85 PathProgramCache]: Analyzing trace with hash -466735181, now seen corresponding path program 1 times [2024-12-02 06:23:27,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:27,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122966470] [2024-12-02 06:23:27,420 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:27,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:27,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:28,224 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 176 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:23:28,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:28,224 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [122966470] [2024-12-02 06:23:28,224 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [122966470] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:28,224 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1050271653] [2024-12-02 06:23:28,224 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:28,224 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:28,224 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:28,226 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:28,227 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-12-02 06:23:29,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:29,118 INFO L256 TraceCheckSpWp]: Trace formula consists of 3326 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-12-02 06:23:29,126 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:29,814 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 276 proven. 0 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2024-12-02 06:23:29,814 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:23:29,814 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1050271653] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:29,814 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:23:29,815 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2024-12-02 06:23:29,815 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436301906] [2024-12-02 06:23:29,815 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:29,816 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:23:29,816 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:29,816 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:23:29,817 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:23:29,817 INFO L87 Difference]: Start difference. First operand 1767 states and 2593 transitions. Second operand has 4 states, 4 states have (on average 143.0) internal successors, (572), 4 states have internal predecessors, (572), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:30,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:30,208 INFO L93 Difference]: Finished difference Result 2592 states and 3811 transitions. [2024-12-02 06:23:30,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:23:30,208 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 143.0) internal successors, (572), 4 states have internal predecessors, (572), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 672 [2024-12-02 06:23:30,209 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:30,214 INFO L225 Difference]: With dead ends: 2592 [2024-12-02 06:23:30,214 INFO L226 Difference]: Without dead ends: 1766 [2024-12-02 06:23:30,215 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 676 GetRequests, 671 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:23:30,215 INFO L435 NwaCegarLoop]: 808 mSDtfsCounter, 828 mSDsluCounter, 810 mSDsCounter, 0 mSdLazyCounter, 595 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 828 SdHoareTripleChecker+Valid, 1618 SdHoareTripleChecker+Invalid, 596 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 595 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:30,215 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [828 Valid, 1618 Invalid, 596 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 595 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 06:23:30,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1766 states. [2024-12-02 06:23:30,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1766 to 1766. [2024-12-02 06:23:30,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1766 states, 1749 states have (on average 1.4636935391652373) internal successors, (2560), 1749 states have internal predecessors, (2560), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:23:30,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1766 states to 1766 states and 2590 transitions. [2024-12-02 06:23:30,235 INFO L78 Accepts]: Start accepts. Automaton has 1766 states and 2590 transitions. Word has length 672 [2024-12-02 06:23:30,235 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:30,235 INFO L471 AbstractCegarLoop]: Abstraction has 1766 states and 2590 transitions. [2024-12-02 06:23:30,235 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 143.0) internal successors, (572), 4 states have internal predecessors, (572), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:30,235 INFO L276 IsEmpty]: Start isEmpty. Operand 1766 states and 2590 transitions. [2024-12-02 06:23:30,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 674 [2024-12-02 06:23:30,250 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:30,250 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:30,260 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-12-02 06:23:30,451 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:30,451 INFO L396 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:30,452 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:30,452 INFO L85 PathProgramCache]: Analyzing trace with hash -595573272, now seen corresponding path program 1 times [2024-12-02 06:23:30,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:30,452 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [777580625] [2024-12-02 06:23:30,452 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:30,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:30,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:31,132 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 176 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:23:31,132 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:31,132 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [777580625] [2024-12-02 06:23:31,132 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [777580625] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:31,132 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1395143172] [2024-12-02 06:23:31,132 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:31,133 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:31,133 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:31,134 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:31,135 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-12-02 06:23:32,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:32,040 INFO L256 TraceCheckSpWp]: Trace formula consists of 3329 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-12-02 06:23:32,048 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:32,761 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 276 proven. 0 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2024-12-02 06:23:32,761 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:23:32,761 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1395143172] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:32,761 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:23:32,762 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2024-12-02 06:23:32,762 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1185218193] [2024-12-02 06:23:32,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:32,762 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:23:32,762 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:32,763 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:23:32,763 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:23:32,763 INFO L87 Difference]: Start difference. First operand 1766 states and 2590 transitions. Second operand has 4 states, 4 states have (on average 143.25) internal successors, (573), 4 states have internal predecessors, (573), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:33,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:33,170 INFO L93 Difference]: Finished difference Result 2590 states and 3805 transitions. [2024-12-02 06:23:33,170 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:23:33,170 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 143.25) internal successors, (573), 4 states have internal predecessors, (573), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 673 [2024-12-02 06:23:33,171 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:33,175 INFO L225 Difference]: With dead ends: 2590 [2024-12-02 06:23:33,175 INFO L226 Difference]: Without dead ends: 1765 [2024-12-02 06:23:33,177 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 677 GetRequests, 672 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:23:33,177 INFO L435 NwaCegarLoop]: 808 mSDtfsCounter, 814 mSDsluCounter, 810 mSDsCounter, 0 mSdLazyCounter, 589 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 814 SdHoareTripleChecker+Valid, 1618 SdHoareTripleChecker+Invalid, 590 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 589 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:33,177 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [814 Valid, 1618 Invalid, 590 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 589 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 06:23:33,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1765 states. [2024-12-02 06:23:33,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1765 to 1765. [2024-12-02 06:23:33,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1765 states, 1748 states have (on average 1.4628146453089246) internal successors, (2557), 1748 states have internal predecessors, (2557), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:23:33,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1765 states to 1765 states and 2587 transitions. [2024-12-02 06:23:33,214 INFO L78 Accepts]: Start accepts. Automaton has 1765 states and 2587 transitions. Word has length 673 [2024-12-02 06:23:33,215 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:33,215 INFO L471 AbstractCegarLoop]: Abstraction has 1765 states and 2587 transitions. [2024-12-02 06:23:33,215 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 143.25) internal successors, (573), 4 states have internal predecessors, (573), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:33,215 INFO L276 IsEmpty]: Start isEmpty. Operand 1765 states and 2587 transitions. [2024-12-02 06:23:33,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 675 [2024-12-02 06:23:33,222 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:33,222 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:33,238 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-12-02 06:23:33,423 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable20 [2024-12-02 06:23:33,423 INFO L396 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:33,423 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:33,424 INFO L85 PathProgramCache]: Analyzing trace with hash 1805138129, now seen corresponding path program 1 times [2024-12-02 06:23:33,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:33,424 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [994105598] [2024-12-02 06:23:33,424 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:33,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:33,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:34,264 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 176 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:23:34,264 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:34,264 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [994105598] [2024-12-02 06:23:34,264 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [994105598] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:34,264 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1657905488] [2024-12-02 06:23:34,264 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:34,265 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:34,265 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:34,266 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:34,267 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-12-02 06:23:35,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:35,278 INFO L256 TraceCheckSpWp]: Trace formula consists of 3332 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-12-02 06:23:35,283 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:36,051 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 276 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-12-02 06:23:36,051 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:23:36,717 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 176 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-12-02 06:23:36,717 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1657905488] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:36,717 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:23:36,717 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-12-02 06:23:36,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1580733727] [2024-12-02 06:23:36,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:36,718 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:23:36,718 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:36,718 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:23:36,719 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-12-02 06:23:36,719 INFO L87 Difference]: Start difference. First operand 1765 states and 2587 transitions. Second operand has 5 states, 5 states have (on average 114.2) internal successors, (571), 5 states have internal predecessors, (571), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:36,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:36,901 INFO L93 Difference]: Finished difference Result 2589 states and 3800 transitions. [2024-12-02 06:23:36,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:23:36,902 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 114.2) internal successors, (571), 5 states have internal predecessors, (571), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 674 [2024-12-02 06:23:36,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:36,905 INFO L225 Difference]: With dead ends: 2589 [2024-12-02 06:23:36,905 INFO L226 Difference]: Without dead ends: 1765 [2024-12-02 06:23:36,906 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1351 GetRequests, 1333 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:23:36,907 INFO L435 NwaCegarLoop]: 1003 mSDtfsCounter, 1819 mSDsluCounter, 1005 mSDsCounter, 0 mSdLazyCounter, 196 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1824 SdHoareTripleChecker+Valid, 2008 SdHoareTripleChecker+Invalid, 203 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 196 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:36,907 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1824 Valid, 2008 Invalid, 203 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 196 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:23:36,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1765 states. [2024-12-02 06:23:36,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1765 to 1765. [2024-12-02 06:23:36,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1765 states, 1748 states have (on average 1.4622425629290619) internal successors, (2556), 1748 states have internal predecessors, (2556), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:23:36,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1765 states to 1765 states and 2586 transitions. [2024-12-02 06:23:36,928 INFO L78 Accepts]: Start accepts. Automaton has 1765 states and 2586 transitions. Word has length 674 [2024-12-02 06:23:36,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:36,928 INFO L471 AbstractCegarLoop]: Abstraction has 1765 states and 2586 transitions. [2024-12-02 06:23:36,928 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 114.2) internal successors, (571), 5 states have internal predecessors, (571), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:36,928 INFO L276 IsEmpty]: Start isEmpty. Operand 1765 states and 2586 transitions. [2024-12-02 06:23:36,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 676 [2024-12-02 06:23:36,931 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:36,932 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:36,942 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-12-02 06:23:37,132 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable21 [2024-12-02 06:23:37,132 INFO L396 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:37,132 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:37,133 INFO L85 PathProgramCache]: Analyzing trace with hash -610374352, now seen corresponding path program 1 times [2024-12-02 06:23:37,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:37,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [734050910] [2024-12-02 06:23:37,133 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:37,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:37,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:37,876 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 176 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:23:37,876 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:37,876 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [734050910] [2024-12-02 06:23:37,876 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [734050910] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:37,876 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1829725375] [2024-12-02 06:23:37,876 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:37,876 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:37,876 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:37,878 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:37,879 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-12-02 06:23:38,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:38,923 INFO L256 TraceCheckSpWp]: Trace formula consists of 3335 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-12-02 06:23:38,929 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:39,725 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 276 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-12-02 06:23:39,725 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:23:40,486 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 176 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-12-02 06:23:40,486 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1829725375] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:40,486 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:23:40,487 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-12-02 06:23:40,487 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [134064706] [2024-12-02 06:23:40,487 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:40,487 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:23:40,487 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:40,488 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:23:40,488 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-12-02 06:23:40,488 INFO L87 Difference]: Start difference. First operand 1765 states and 2586 transitions. Second operand has 5 states, 5 states have (on average 114.4) internal successors, (572), 5 states have internal predecessors, (572), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:40,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:40,660 INFO L93 Difference]: Finished difference Result 2589 states and 3798 transitions. [2024-12-02 06:23:40,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:23:40,661 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 114.4) internal successors, (572), 5 states have internal predecessors, (572), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 675 [2024-12-02 06:23:40,661 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:40,664 INFO L225 Difference]: With dead ends: 2589 [2024-12-02 06:23:40,664 INFO L226 Difference]: Without dead ends: 1765 [2024-12-02 06:23:40,665 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1353 GetRequests, 1335 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:23:40,665 INFO L435 NwaCegarLoop]: 1003 mSDtfsCounter, 1795 mSDsluCounter, 1005 mSDsCounter, 0 mSdLazyCounter, 194 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1800 SdHoareTripleChecker+Valid, 2008 SdHoareTripleChecker+Invalid, 201 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 194 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:40,665 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1800 Valid, 2008 Invalid, 201 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 194 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:23:40,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1765 states. [2024-12-02 06:23:40,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1765 to 1765. [2024-12-02 06:23:40,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1765 states, 1748 states have (on average 1.4616704805491991) internal successors, (2555), 1748 states have internal predecessors, (2555), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:23:40,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1765 states to 1765 states and 2585 transitions. [2024-12-02 06:23:40,684 INFO L78 Accepts]: Start accepts. Automaton has 1765 states and 2585 transitions. Word has length 675 [2024-12-02 06:23:40,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:40,685 INFO L471 AbstractCegarLoop]: Abstraction has 1765 states and 2585 transitions. [2024-12-02 06:23:40,685 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 114.4) internal successors, (572), 5 states have internal predecessors, (572), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:40,685 INFO L276 IsEmpty]: Start isEmpty. Operand 1765 states and 2585 transitions. [2024-12-02 06:23:40,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 677 [2024-12-02 06:23:40,688 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:40,688 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:40,704 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-12-02 06:23:40,889 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22,13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:40,889 INFO L396 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:40,889 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:40,889 INFO L85 PathProgramCache]: Analyzing trace with hash -1307009548, now seen corresponding path program 1 times [2024-12-02 06:23:40,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:40,889 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907540757] [2024-12-02 06:23:40,890 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:40,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:41,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:41,568 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 176 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:23:41,568 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:41,568 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1907540757] [2024-12-02 06:23:41,568 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1907540757] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:41,568 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [577124725] [2024-12-02 06:23:41,569 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:41,569 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:41,569 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:41,570 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:41,571 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-12-02 06:23:42,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:42,631 INFO L256 TraceCheckSpWp]: Trace formula consists of 3338 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-12-02 06:23:42,638 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:43,541 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 276 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-12-02 06:23:43,541 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:23:44,258 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 176 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-12-02 06:23:44,258 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [577124725] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:44,258 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:23:44,258 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-12-02 06:23:44,258 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1447983651] [2024-12-02 06:23:44,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:44,259 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:23:44,259 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:44,259 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:23:44,259 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-12-02 06:23:44,259 INFO L87 Difference]: Start difference. First operand 1765 states and 2585 transitions. Second operand has 5 states, 5 states have (on average 114.6) internal successors, (573), 5 states have internal predecessors, (573), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:44,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:44,431 INFO L93 Difference]: Finished difference Result 2589 states and 3796 transitions. [2024-12-02 06:23:44,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:23:44,432 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 114.6) internal successors, (573), 5 states have internal predecessors, (573), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 676 [2024-12-02 06:23:44,432 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:44,435 INFO L225 Difference]: With dead ends: 2589 [2024-12-02 06:23:44,435 INFO L226 Difference]: Without dead ends: 1765 [2024-12-02 06:23:44,436 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1355 GetRequests, 1337 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:23:44,436 INFO L435 NwaCegarLoop]: 1003 mSDtfsCounter, 1783 mSDsluCounter, 1005 mSDsCounter, 0 mSdLazyCounter, 192 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1788 SdHoareTripleChecker+Valid, 2008 SdHoareTripleChecker+Invalid, 199 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 192 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:44,436 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1788 Valid, 2008 Invalid, 199 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 192 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:23:44,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1765 states. [2024-12-02 06:23:44,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1765 to 1765. [2024-12-02 06:23:44,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1765 states, 1748 states have (on average 1.4610983981693364) internal successors, (2554), 1748 states have internal predecessors, (2554), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:23:44,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1765 states to 1765 states and 2584 transitions. [2024-12-02 06:23:44,457 INFO L78 Accepts]: Start accepts. Automaton has 1765 states and 2584 transitions. Word has length 676 [2024-12-02 06:23:44,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:44,458 INFO L471 AbstractCegarLoop]: Abstraction has 1765 states and 2584 transitions. [2024-12-02 06:23:44,458 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 114.6) internal successors, (573), 5 states have internal predecessors, (573), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:44,458 INFO L276 IsEmpty]: Start isEmpty. Operand 1765 states and 2584 transitions. [2024-12-02 06:23:44,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 678 [2024-12-02 06:23:44,461 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:44,461 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:44,473 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2024-12-02 06:23:44,662 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23,14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:44,662 INFO L396 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:44,662 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:44,662 INFO L85 PathProgramCache]: Analyzing trace with hash 572179262, now seen corresponding path program 1 times [2024-12-02 06:23:44,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:44,662 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215223245] [2024-12-02 06:23:44,662 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:44,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:44,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:45,392 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 176 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:23:45,393 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:45,393 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215223245] [2024-12-02 06:23:45,393 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [215223245] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:45,393 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [343682187] [2024-12-02 06:23:45,393 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:45,393 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:45,393 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:45,395 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:45,396 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-12-02 06:23:46,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:46,511 INFO L256 TraceCheckSpWp]: Trace formula consists of 3341 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-12-02 06:23:46,517 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:47,341 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 276 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-12-02 06:23:47,341 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:23:48,098 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 176 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-12-02 06:23:48,098 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [343682187] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:48,099 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:23:48,099 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-12-02 06:23:48,099 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [972115946] [2024-12-02 06:23:48,099 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:48,099 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:23:48,099 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:48,100 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:23:48,100 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-12-02 06:23:48,100 INFO L87 Difference]: Start difference. First operand 1765 states and 2584 transitions. Second operand has 5 states, 5 states have (on average 114.8) internal successors, (574), 5 states have internal predecessors, (574), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:48,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:48,253 INFO L93 Difference]: Finished difference Result 2589 states and 3794 transitions. [2024-12-02 06:23:48,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:23:48,254 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 114.8) internal successors, (574), 5 states have internal predecessors, (574), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 677 [2024-12-02 06:23:48,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:48,256 INFO L225 Difference]: With dead ends: 2589 [2024-12-02 06:23:48,256 INFO L226 Difference]: Without dead ends: 1765 [2024-12-02 06:23:48,257 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1357 GetRequests, 1339 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:23:48,258 INFO L435 NwaCegarLoop]: 1003 mSDtfsCounter, 881 mSDsluCounter, 1014 mSDsCounter, 0 mSdLazyCounter, 190 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 886 SdHoareTripleChecker+Valid, 2017 SdHoareTripleChecker+Invalid, 191 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 190 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:48,258 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [886 Valid, 2017 Invalid, 191 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 190 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:23:48,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1765 states. [2024-12-02 06:23:48,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1765 to 1765. [2024-12-02 06:23:48,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1765 states, 1748 states have (on average 1.4605263157894737) internal successors, (2553), 1748 states have internal predecessors, (2553), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:23:48,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1765 states to 1765 states and 2583 transitions. [2024-12-02 06:23:48,277 INFO L78 Accepts]: Start accepts. Automaton has 1765 states and 2583 transitions. Word has length 677 [2024-12-02 06:23:48,277 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:48,277 INFO L471 AbstractCegarLoop]: Abstraction has 1765 states and 2583 transitions. [2024-12-02 06:23:48,277 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 114.8) internal successors, (574), 5 states have internal predecessors, (574), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:48,277 INFO L276 IsEmpty]: Start isEmpty. Operand 1765 states and 2583 transitions. [2024-12-02 06:23:48,281 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 679 [2024-12-02 06:23:48,281 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:48,281 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:48,292 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2024-12-02 06:23:48,481 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable24 [2024-12-02 06:23:48,481 INFO L396 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:48,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:48,482 INFO L85 PathProgramCache]: Analyzing trace with hash 88949175, now seen corresponding path program 1 times [2024-12-02 06:23:48,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:48,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1642116337] [2024-12-02 06:23:48,482 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:48,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:48,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:49,131 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 176 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-12-02 06:23:49,131 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:49,131 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1642116337] [2024-12-02 06:23:49,131 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1642116337] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:49,131 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [675183299] [2024-12-02 06:23:49,131 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:49,131 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:49,132 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:49,133 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:49,134 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-12-02 06:23:50,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:50,270 INFO L256 TraceCheckSpWp]: Trace formula consists of 3344 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:23:50,276 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:50,294 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 276 proven. 8 refuted. 0 times theorem prover too weak. 313 trivial. 0 not checked. [2024-12-02 06:23:50,294 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:23:50,333 INFO L134 CoverageAnalysis]: Checked inductivity of 597 backedges. 176 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-12-02 06:23:50,333 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [675183299] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:50,333 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:23:50,334 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:23:50,334 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2086149228] [2024-12-02 06:23:50,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:50,335 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:23:50,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:50,335 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:23:50,336 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:23:50,336 INFO L87 Difference]: Start difference. First operand 1765 states and 2583 transitions. Second operand has 3 states, 3 states have (on average 191.66666666666666) internal successors, (575), 3 states have internal predecessors, (575), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:50,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:50,358 INFO L93 Difference]: Finished difference Result 2590 states and 3794 transitions. [2024-12-02 06:23:50,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:23:50,359 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 191.66666666666666) internal successors, (575), 3 states have internal predecessors, (575), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 678 [2024-12-02 06:23:50,359 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:50,361 INFO L225 Difference]: With dead ends: 2590 [2024-12-02 06:23:50,362 INFO L226 Difference]: Without dead ends: 1766 [2024-12-02 06:23:50,362 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1358 GetRequests, 1353 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:23:50,363 INFO L435 NwaCegarLoop]: 1094 mSDtfsCounter, 1 mSDsluCounter, 1090 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2184 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:50,363 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2184 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:23:50,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1766 states. [2024-12-02 06:23:50,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1766 to 1766. [2024-12-02 06:23:50,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1766 states, 1749 states have (on average 1.4602630074328187) internal successors, (2554), 1749 states have internal predecessors, (2554), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:23:50,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1766 states to 1766 states and 2584 transitions. [2024-12-02 06:23:50,398 INFO L78 Accepts]: Start accepts. Automaton has 1766 states and 2584 transitions. Word has length 678 [2024-12-02 06:23:50,398 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:50,398 INFO L471 AbstractCegarLoop]: Abstraction has 1766 states and 2584 transitions. [2024-12-02 06:23:50,399 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 191.66666666666666) internal successors, (575), 3 states have internal predecessors, (575), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:50,399 INFO L276 IsEmpty]: Start isEmpty. Operand 1766 states and 2584 transitions. [2024-12-02 06:23:50,404 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 681 [2024-12-02 06:23:50,404 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:50,405 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:50,417 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0 [2024-12-02 06:23:50,605 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable25 [2024-12-02 06:23:50,605 INFO L396 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:50,606 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:50,606 INFO L85 PathProgramCache]: Analyzing trace with hash 1227461363, now seen corresponding path program 1 times [2024-12-02 06:23:50,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:50,606 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1591168624] [2024-12-02 06:23:50,606 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:50,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:50,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:51,422 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 176 proven. 1 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-12-02 06:23:51,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:51,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1591168624] [2024-12-02 06:23:51,422 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1591168624] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:51,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1900778018] [2024-12-02 06:23:51,422 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:51,422 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:51,423 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:51,424 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:51,425 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-12-02 06:23:52,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:52,578 INFO L256 TraceCheckSpWp]: Trace formula consists of 3353 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:23:52,583 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:52,600 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 276 proven. 8 refuted. 0 times theorem prover too weak. 314 trivial. 0 not checked. [2024-12-02 06:23:52,600 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:23:52,640 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 176 proven. 0 refuted. 0 times theorem prover too weak. 422 trivial. 0 not checked. [2024-12-02 06:23:52,641 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1900778018] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:52,641 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:23:52,641 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:23:52,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1025909172] [2024-12-02 06:23:52,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:52,642 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:23:52,642 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:52,642 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:23:52,642 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:23:52,643 INFO L87 Difference]: Start difference. First operand 1766 states and 2584 transitions. Second operand has 3 states, 3 states have (on average 192.33333333333334) internal successors, (577), 3 states have internal predecessors, (577), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:52,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:52,671 INFO L93 Difference]: Finished difference Result 2592 states and 3796 transitions. [2024-12-02 06:23:52,672 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:23:52,672 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 192.33333333333334) internal successors, (577), 3 states have internal predecessors, (577), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 680 [2024-12-02 06:23:52,673 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:52,675 INFO L225 Difference]: With dead ends: 2592 [2024-12-02 06:23:52,675 INFO L226 Difference]: Without dead ends: 1767 [2024-12-02 06:23:52,676 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1362 GetRequests, 1357 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:23:52,676 INFO L435 NwaCegarLoop]: 1094 mSDtfsCounter, 1 mSDsluCounter, 1090 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2184 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:52,677 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2184 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:23:52,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1767 states. [2024-12-02 06:23:52,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1767 to 1767. [2024-12-02 06:23:52,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1767 states, 1750 states have (on average 1.46) internal successors, (2555), 1750 states have internal predecessors, (2555), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:23:52,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1767 states to 1767 states and 2585 transitions. [2024-12-02 06:23:52,699 INFO L78 Accepts]: Start accepts. Automaton has 1767 states and 2585 transitions. Word has length 680 [2024-12-02 06:23:52,700 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:52,700 INFO L471 AbstractCegarLoop]: Abstraction has 1767 states and 2585 transitions. [2024-12-02 06:23:52,700 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 192.33333333333334) internal successors, (577), 3 states have internal predecessors, (577), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:52,700 INFO L276 IsEmpty]: Start isEmpty. Operand 1767 states and 2585 transitions. [2024-12-02 06:23:52,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 683 [2024-12-02 06:23:52,703 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:52,703 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:52,715 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Ended with exit code 0 [2024-12-02 06:23:52,903 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable26 [2024-12-02 06:23:52,904 INFO L396 AbstractCegarLoop]: === Iteration 28 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:52,904 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:52,904 INFO L85 PathProgramCache]: Analyzing trace with hash -1961115089, now seen corresponding path program 1 times [2024-12-02 06:23:52,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:52,904 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2034210180] [2024-12-02 06:23:52,904 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:52,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:53,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:53,580 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 176 proven. 1 refuted. 0 times theorem prover too weak. 422 trivial. 0 not checked. [2024-12-02 06:23:53,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:53,580 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2034210180] [2024-12-02 06:23:53,580 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2034210180] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:53,580 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1000607506] [2024-12-02 06:23:53,581 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:53,581 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:53,581 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:53,582 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:53,583 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-12-02 06:23:54,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:54,788 INFO L256 TraceCheckSpWp]: Trace formula consists of 3362 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:23:54,793 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:54,816 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 276 proven. 8 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2024-12-02 06:23:54,816 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:23:54,853 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 176 proven. 0 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-12-02 06:23:54,853 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1000607506] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:54,853 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:23:54,853 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:23:54,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [971433635] [2024-12-02 06:23:54,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:54,854 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:23:54,854 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:54,854 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:23:54,854 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:23:54,855 INFO L87 Difference]: Start difference. First operand 1767 states and 2585 transitions. Second operand has 3 states, 3 states have (on average 193.0) internal successors, (579), 3 states have internal predecessors, (579), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:54,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:54,876 INFO L93 Difference]: Finished difference Result 2594 states and 3798 transitions. [2024-12-02 06:23:54,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:23:54,877 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 193.0) internal successors, (579), 3 states have internal predecessors, (579), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 682 [2024-12-02 06:23:54,877 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:54,879 INFO L225 Difference]: With dead ends: 2594 [2024-12-02 06:23:54,879 INFO L226 Difference]: Without dead ends: 1768 [2024-12-02 06:23:54,880 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1366 GetRequests, 1361 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:23:54,881 INFO L435 NwaCegarLoop]: 1094 mSDtfsCounter, 1 mSDsluCounter, 1090 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2184 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:54,881 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2184 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:23:54,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1768 states. [2024-12-02 06:23:54,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1768 to 1768. [2024-12-02 06:23:54,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1768 states, 1751 states have (on average 1.4597372929754426) internal successors, (2556), 1751 states have internal predecessors, (2556), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:23:54,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1768 states to 1768 states and 2586 transitions. [2024-12-02 06:23:54,901 INFO L78 Accepts]: Start accepts. Automaton has 1768 states and 2586 transitions. Word has length 682 [2024-12-02 06:23:54,902 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:54,902 INFO L471 AbstractCegarLoop]: Abstraction has 1768 states and 2586 transitions. [2024-12-02 06:23:54,902 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 193.0) internal successors, (579), 3 states have internal predecessors, (579), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:54,902 INFO L276 IsEmpty]: Start isEmpty. Operand 1768 states and 2586 transitions. [2024-12-02 06:23:54,905 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 685 [2024-12-02 06:23:54,905 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:54,905 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:54,919 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Ended with exit code 0 [2024-12-02 06:23:55,106 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable27 [2024-12-02 06:23:55,106 INFO L396 AbstractCegarLoop]: === Iteration 29 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:55,106 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:55,107 INFO L85 PathProgramCache]: Analyzing trace with hash -1574928085, now seen corresponding path program 1 times [2024-12-02 06:23:55,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:55,107 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1264492395] [2024-12-02 06:23:55,107 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:55,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:55,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:55,791 INFO L134 CoverageAnalysis]: Checked inductivity of 600 backedges. 176 proven. 1 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-12-02 06:23:55,792 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:55,792 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1264492395] [2024-12-02 06:23:55,792 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1264492395] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:55,792 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1111190770] [2024-12-02 06:23:55,792 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:55,792 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:55,792 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:55,793 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:55,794 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-12-02 06:23:57,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:57,087 INFO L256 TraceCheckSpWp]: Trace formula consists of 3371 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:23:57,093 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:23:57,123 INFO L134 CoverageAnalysis]: Checked inductivity of 600 backedges. 276 proven. 37 refuted. 0 times theorem prover too weak. 287 trivial. 0 not checked. [2024-12-02 06:23:57,123 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:23:57,180 INFO L134 CoverageAnalysis]: Checked inductivity of 600 backedges. 176 proven. 1 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-12-02 06:23:57,180 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1111190770] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:23:57,180 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:23:57,181 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:23:57,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1985509861] [2024-12-02 06:23:57,181 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:23:57,183 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:23:57,183 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:57,184 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:23:57,184 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:23:57,184 INFO L87 Difference]: Start difference. First operand 1768 states and 2586 transitions. Second operand has 9 states, 9 states have (on average 66.22222222222223) internal successors, (596), 9 states have internal predecessors, (596), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:23:57,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:57,260 INFO L93 Difference]: Finished difference Result 2601 states and 3807 transitions. [2024-12-02 06:23:57,261 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:23:57,261 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 66.22222222222223) internal successors, (596), 9 states have internal predecessors, (596), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 684 [2024-12-02 06:23:57,261 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:57,265 INFO L225 Difference]: With dead ends: 2601 [2024-12-02 06:23:57,265 INFO L226 Difference]: Without dead ends: 1774 [2024-12-02 06:23:57,266 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1371 GetRequests, 1363 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:23:57,267 INFO L435 NwaCegarLoop]: 1098 mSDtfsCounter, 14 mSDsluCounter, 6554 mSDsCounter, 0 mSdLazyCounter, 65 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 14 SdHoareTripleChecker+Valid, 7652 SdHoareTripleChecker+Invalid, 67 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 65 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:57,267 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [14 Valid, 7652 Invalid, 67 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 65 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:23:57,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1774 states. [2024-12-02 06:23:57,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1774 to 1774. [2024-12-02 06:23:57,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1774 states, 1757 states have (on average 1.4581673306772909) internal successors, (2562), 1757 states have internal predecessors, (2562), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:23:57,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1774 states to 1774 states and 2592 transitions. [2024-12-02 06:23:57,307 INFO L78 Accepts]: Start accepts. Automaton has 1774 states and 2592 transitions. Word has length 684 [2024-12-02 06:23:57,307 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:57,307 INFO L471 AbstractCegarLoop]: Abstraction has 1774 states and 2592 transitions. [2024-12-02 06:23:57,307 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 66.22222222222223) internal successors, (596), 9 states have internal predecessors, (596), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:23:57,307 INFO L276 IsEmpty]: Start isEmpty. Operand 1774 states and 2592 transitions. [2024-12-02 06:23:57,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 691 [2024-12-02 06:23:57,311 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:57,312 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:57,333 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Ended with exit code 0 [2024-12-02 06:23:57,512 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable28 [2024-12-02 06:23:57,512 INFO L396 AbstractCegarLoop]: === Iteration 30 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:57,513 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:57,513 INFO L85 PathProgramCache]: Analyzing trace with hash 1511539255, now seen corresponding path program 2 times [2024-12-02 06:23:57,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:57,513 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [756197613] [2024-12-02 06:23:57,513 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:23:57,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:57,671 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:23:57,671 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:23:57,999 INFO L134 CoverageAnalysis]: Checked inductivity of 615 backedges. 87 proven. 0 refuted. 0 times theorem prover too weak. 528 trivial. 0 not checked. [2024-12-02 06:23:57,999 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:57,999 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [756197613] [2024-12-02 06:23:57,999 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [756197613] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:57,999 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:57,999 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:23:57,999 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1696605954] [2024-12-02 06:23:57,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:58,000 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:23:58,000 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:58,000 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:23:58,000 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:23:58,001 INFO L87 Difference]: Start difference. First operand 1774 states and 2592 transitions. Second operand has 7 states, 7 states have (on average 71.14285714285714) internal successors, (498), 7 states have internal predecessors, (498), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:58,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:58,064 INFO L93 Difference]: Finished difference Result 2615 states and 3821 transitions. [2024-12-02 06:23:58,064 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:23:58,064 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 71.14285714285714) internal successors, (498), 7 states have internal predecessors, (498), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 690 [2024-12-02 06:23:58,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:58,069 INFO L225 Difference]: With dead ends: 2615 [2024-12-02 06:23:58,069 INFO L226 Difference]: Without dead ends: 1782 [2024-12-02 06:23:58,070 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:23:58,071 INFO L435 NwaCegarLoop]: 1089 mSDtfsCounter, 149 mSDsluCounter, 5428 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 149 SdHoareTripleChecker+Valid, 6517 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:58,071 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [149 Valid, 6517 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:23:58,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1782 states. [2024-12-02 06:23:58,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1782 to 1775. [2024-12-02 06:23:58,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1775 states, 1758 states have (on average 1.4584755403868033) internal successors, (2564), 1758 states have internal predecessors, (2564), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:23:58,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1775 states to 1775 states and 2594 transitions. [2024-12-02 06:23:58,097 INFO L78 Accepts]: Start accepts. Automaton has 1775 states and 2594 transitions. Word has length 690 [2024-12-02 06:23:58,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:58,098 INFO L471 AbstractCegarLoop]: Abstraction has 1775 states and 2594 transitions. [2024-12-02 06:23:58,098 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 71.14285714285714) internal successors, (498), 7 states have internal predecessors, (498), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:58,098 INFO L276 IsEmpty]: Start isEmpty. Operand 1775 states and 2594 transitions. [2024-12-02 06:23:58,101 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 691 [2024-12-02 06:23:58,101 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:58,101 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:58,101 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29 [2024-12-02 06:23:58,101 INFO L396 AbstractCegarLoop]: === Iteration 31 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:58,101 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:58,101 INFO L85 PathProgramCache]: Analyzing trace with hash -1704047198, now seen corresponding path program 1 times [2024-12-02 06:23:58,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:58,101 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1231302128] [2024-12-02 06:23:58,102 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:58,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:58,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:58,952 INFO L134 CoverageAnalysis]: Checked inductivity of 614 backedges. 175 proven. 16 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-12-02 06:23:58,952 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:58,952 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1231302128] [2024-12-02 06:23:58,952 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1231302128] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:23:58,952 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [3118213] [2024-12-02 06:23:58,952 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:58,952 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:23:58,953 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:23:58,954 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:23:58,955 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-12-02 06:24:00,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:00,347 INFO L256 TraceCheckSpWp]: Trace formula consists of 3398 conjuncts, 15 conjuncts are in the unsatisfiable core [2024-12-02 06:24:00,352 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:24:00,547 INFO L134 CoverageAnalysis]: Checked inductivity of 614 backedges. 112 proven. 26 refuted. 0 times theorem prover too weak. 476 trivial. 0 not checked. [2024-12-02 06:24:00,547 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:24:00,630 INFO L134 CoverageAnalysis]: Checked inductivity of 614 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 502 trivial. 0 not checked. [2024-12-02 06:24:00,631 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [3118213] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:24:00,631 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:24:00,631 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7, 8] total 16 [2024-12-02 06:24:00,631 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2031428846] [2024-12-02 06:24:00,631 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:00,631 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:24:00,632 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:00,632 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:24:00,632 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=202, Unknown=0, NotChecked=0, Total=240 [2024-12-02 06:24:00,632 INFO L87 Difference]: Start difference. First operand 1775 states and 2594 transitions. Second operand has 5 states, 5 states have (on average 104.8) internal successors, (524), 5 states have internal predecessors, (524), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:24:00,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:00,671 INFO L93 Difference]: Finished difference Result 2887 states and 4221 transitions. [2024-12-02 06:24:00,671 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:24:00,671 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 104.8) internal successors, (524), 5 states have internal predecessors, (524), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 690 [2024-12-02 06:24:00,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:00,674 INFO L225 Difference]: With dead ends: 2887 [2024-12-02 06:24:00,674 INFO L226 Difference]: Without dead ends: 1893 [2024-12-02 06:24:00,675 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1385 GetRequests, 1371 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=38, Invalid=202, Unknown=0, NotChecked=0, Total=240 [2024-12-02 06:24:00,675 INFO L435 NwaCegarLoop]: 1093 mSDtfsCounter, 40 mSDsluCounter, 3267 mSDsCounter, 0 mSdLazyCounter, 23 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 4360 SdHoareTripleChecker+Invalid, 23 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 23 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:00,675 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [40 Valid, 4360 Invalid, 23 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 23 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:24:00,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1893 states. [2024-12-02 06:24:00,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1893 to 1893. [2024-12-02 06:24:00,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1893 states, 1876 states have (on average 1.4562899786780383) internal successors, (2732), 1876 states have internal predecessors, (2732), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:24:00,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1893 states to 1893 states and 2762 transitions. [2024-12-02 06:24:00,698 INFO L78 Accepts]: Start accepts. Automaton has 1893 states and 2762 transitions. Word has length 690 [2024-12-02 06:24:00,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:00,698 INFO L471 AbstractCegarLoop]: Abstraction has 1893 states and 2762 transitions. [2024-12-02 06:24:00,698 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 104.8) internal successors, (524), 5 states have internal predecessors, (524), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:24:00,698 INFO L276 IsEmpty]: Start isEmpty. Operand 1893 states and 2762 transitions. [2024-12-02 06:24:00,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 692 [2024-12-02 06:24:00,701 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:00,702 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:00,721 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Ended with exit code 0 [2024-12-02 06:24:00,902 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30,20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:24:00,902 INFO L396 AbstractCegarLoop]: === Iteration 32 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:00,903 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:00,903 INFO L85 PathProgramCache]: Analyzing trace with hash -67575706, now seen corresponding path program 1 times [2024-12-02 06:24:00,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:00,903 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328727753] [2024-12-02 06:24:00,903 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:00,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:01,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:01,733 INFO L134 CoverageAnalysis]: Checked inductivity of 615 backedges. 176 proven. 16 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-12-02 06:24:01,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:01,733 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328727753] [2024-12-02 06:24:01,733 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328727753] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:24:01,733 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1217805765] [2024-12-02 06:24:01,733 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:01,733 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:24:01,733 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:24:01,735 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:24:01,735 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2024-12-02 06:24:03,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:03,111 INFO L256 TraceCheckSpWp]: Trace formula consists of 3399 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-12-02 06:24:03,116 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:24:03,175 INFO L134 CoverageAnalysis]: Checked inductivity of 615 backedges. 276 proven. 112 refuted. 0 times theorem prover too weak. 227 trivial. 0 not checked. [2024-12-02 06:24:03,175 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:24:03,284 INFO L134 CoverageAnalysis]: Checked inductivity of 615 backedges. 176 proven. 16 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-12-02 06:24:03,284 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1217805765] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:24:03,284 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:24:03,284 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-12-02 06:24:03,285 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193998715] [2024-12-02 06:24:03,285 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:24:03,285 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-12-02 06:24:03,285 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:03,286 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-12-02 06:24:03,286 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:24:03,286 INFO L87 Difference]: Start difference. First operand 1893 states and 2762 transitions. Second operand has 18 states, 18 states have (on average 34.5) internal successors, (621), 18 states have internal predecessors, (621), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:24:03,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:03,484 INFO L93 Difference]: Finished difference Result 2783 states and 4062 transitions. [2024-12-02 06:24:03,484 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-12-02 06:24:03,484 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 34.5) internal successors, (621), 18 states have internal predecessors, (621), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 691 [2024-12-02 06:24:03,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:03,487 INFO L225 Difference]: With dead ends: 2783 [2024-12-02 06:24:03,487 INFO L226 Difference]: Without dead ends: 1901 [2024-12-02 06:24:03,489 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1389 GetRequests, 1371 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:24:03,489 INFO L435 NwaCegarLoop]: 1116 mSDtfsCounter, 27 mSDsluCounter, 13319 mSDsCounter, 0 mSdLazyCounter, 270 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 14435 SdHoareTripleChecker+Invalid, 271 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 270 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:03,489 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 14435 Invalid, 271 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 270 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:24:03,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1901 states. [2024-12-02 06:24:03,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1901 to 1901. [2024-12-02 06:24:03,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1901 states, 1884 states have (on average 1.454352441613588) internal successors, (2740), 1884 states have internal predecessors, (2740), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:24:03,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1901 states to 1901 states and 2770 transitions. [2024-12-02 06:24:03,520 INFO L78 Accepts]: Start accepts. Automaton has 1901 states and 2770 transitions. Word has length 691 [2024-12-02 06:24:03,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:03,521 INFO L471 AbstractCegarLoop]: Abstraction has 1901 states and 2770 transitions. [2024-12-02 06:24:03,521 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 34.5) internal successors, (621), 18 states have internal predecessors, (621), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:24:03,521 INFO L276 IsEmpty]: Start isEmpty. Operand 1901 states and 2770 transitions. [2024-12-02 06:24:03,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 700 [2024-12-02 06:24:03,524 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:03,524 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:03,537 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Ended with exit code 0 [2024-12-02 06:24:03,725 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable31 [2024-12-02 06:24:03,725 INFO L396 AbstractCegarLoop]: === Iteration 33 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:03,725 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:03,725 INFO L85 PathProgramCache]: Analyzing trace with hash 10265686, now seen corresponding path program 2 times [2024-12-02 06:24:03,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:03,726 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678606786] [2024-12-02 06:24:03,726 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:24:03,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:03,872 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:24:03,872 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:24:04,377 INFO L134 CoverageAnalysis]: Checked inductivity of 663 backedges. 173 proven. 0 refuted. 0 times theorem prover too weak. 490 trivial. 0 not checked. [2024-12-02 06:24:04,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:04,377 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [678606786] [2024-12-02 06:24:04,377 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [678606786] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:24:04,377 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:24:04,377 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:24:04,377 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [116625241] [2024-12-02 06:24:04,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:04,378 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:24:04,378 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:04,378 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:24:04,379 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:24:04,379 INFO L87 Difference]: Start difference. First operand 1901 states and 2770 transitions. Second operand has 8 states, 8 states have (on average 72.5) internal successors, (580), 8 states have internal predecessors, (580), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:05,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:05,216 INFO L93 Difference]: Finished difference Result 3497 states and 5108 transitions. [2024-12-02 06:24:05,216 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:24:05,216 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 72.5) internal successors, (580), 8 states have internal predecessors, (580), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 699 [2024-12-02 06:24:05,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:05,220 INFO L225 Difference]: With dead ends: 3497 [2024-12-02 06:24:05,220 INFO L226 Difference]: Without dead ends: 1925 [2024-12-02 06:24:05,222 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:24:05,222 INFO L435 NwaCegarLoop]: 805 mSDtfsCounter, 697 mSDsluCounter, 3999 mSDsCounter, 0 mSdLazyCounter, 1776 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 697 SdHoareTripleChecker+Valid, 4804 SdHoareTripleChecker+Invalid, 1779 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1776 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:05,222 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [697 Valid, 4804 Invalid, 1779 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1776 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2024-12-02 06:24:05,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1925 states. [2024-12-02 06:24:05,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1925 to 1916. [2024-12-02 06:24:05,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1916 states, 1899 states have (on average 1.4539231174302265) internal successors, (2761), 1899 states have internal predecessors, (2761), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:24:05,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1916 states to 1916 states and 2791 transitions. [2024-12-02 06:24:05,248 INFO L78 Accepts]: Start accepts. Automaton has 1916 states and 2791 transitions. Word has length 699 [2024-12-02 06:24:05,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:05,248 INFO L471 AbstractCegarLoop]: Abstraction has 1916 states and 2791 transitions. [2024-12-02 06:24:05,249 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 72.5) internal successors, (580), 8 states have internal predecessors, (580), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:05,249 INFO L276 IsEmpty]: Start isEmpty. Operand 1916 states and 2791 transitions. [2024-12-02 06:24:05,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 702 [2024-12-02 06:24:05,252 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:05,253 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:05,253 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable32 [2024-12-02 06:24:05,253 INFO L396 AbstractCegarLoop]: === Iteration 34 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:05,253 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:05,253 INFO L85 PathProgramCache]: Analyzing trace with hash -390338718, now seen corresponding path program 1 times [2024-12-02 06:24:05,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:05,253 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [521077617] [2024-12-02 06:24:05,254 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:05,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:05,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:06,540 INFO L134 CoverageAnalysis]: Checked inductivity of 664 backedges. 177 proven. 0 refuted. 0 times theorem prover too weak. 487 trivial. 0 not checked. [2024-12-02 06:24:06,540 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:06,540 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [521077617] [2024-12-02 06:24:06,540 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [521077617] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:24:06,540 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:24:06,540 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:24:06,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [804234778] [2024-12-02 06:24:06,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:06,541 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:24:06,541 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:06,542 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:24:06,542 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:24:06,542 INFO L87 Difference]: Start difference. First operand 1916 states and 2791 transitions. Second operand has 6 states, 6 states have (on average 97.33333333333333) internal successors, (584), 6 states have internal predecessors, (584), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:07,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:07,488 INFO L93 Difference]: Finished difference Result 3688 states and 5369 transitions. [2024-12-02 06:24:07,488 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:24:07,488 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 97.33333333333333) internal successors, (584), 6 states have internal predecessors, (584), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 701 [2024-12-02 06:24:07,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:07,491 INFO L225 Difference]: With dead ends: 3688 [2024-12-02 06:24:07,491 INFO L226 Difference]: Without dead ends: 2793 [2024-12-02 06:24:07,492 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:24:07,492 INFO L435 NwaCegarLoop]: 1096 mSDtfsCounter, 1978 mSDsluCounter, 2949 mSDsCounter, 0 mSdLazyCounter, 1671 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1983 SdHoareTripleChecker+Valid, 4045 SdHoareTripleChecker+Invalid, 1672 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1671 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:07,492 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1983 Valid, 4045 Invalid, 1672 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1671 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-12-02 06:24:07,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2793 states. [2024-12-02 06:24:07,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2793 to 2647. [2024-12-02 06:24:07,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2647 states, 2625 states have (on average 1.4537142857142857) internal successors, (3816), 2625 states have internal predecessors, (3816), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:24:07,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2647 states to 2647 states and 3856 transitions. [2024-12-02 06:24:07,551 INFO L78 Accepts]: Start accepts. Automaton has 2647 states and 3856 transitions. Word has length 701 [2024-12-02 06:24:07,552 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:07,552 INFO L471 AbstractCegarLoop]: Abstraction has 2647 states and 3856 transitions. [2024-12-02 06:24:07,552 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 97.33333333333333) internal successors, (584), 6 states have internal predecessors, (584), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:07,552 INFO L276 IsEmpty]: Start isEmpty. Operand 2647 states and 3856 transitions. [2024-12-02 06:24:07,560 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 702 [2024-12-02 06:24:07,560 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:07,560 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:07,560 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable33 [2024-12-02 06:24:07,561 INFO L396 AbstractCegarLoop]: === Iteration 35 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:07,561 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:07,561 INFO L85 PathProgramCache]: Analyzing trace with hash 847181788, now seen corresponding path program 1 times [2024-12-02 06:24:07,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:07,561 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844610104] [2024-12-02 06:24:07,561 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:07,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:07,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:08,407 INFO L134 CoverageAnalysis]: Checked inductivity of 664 backedges. 177 proven. 1 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-12-02 06:24:08,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:08,407 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844610104] [2024-12-02 06:24:08,407 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [844610104] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:24:08,407 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1069292966] [2024-12-02 06:24:08,407 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:08,408 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:24:08,408 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:24:08,409 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:24:08,410 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2024-12-02 06:24:09,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:09,924 INFO L256 TraceCheckSpWp]: Trace formula consists of 3441 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:24:09,929 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:24:09,957 INFO L134 CoverageAnalysis]: Checked inductivity of 664 backedges. 277 proven. 37 refuted. 0 times theorem prover too weak. 350 trivial. 0 not checked. [2024-12-02 06:24:09,957 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:24:10,006 INFO L134 CoverageAnalysis]: Checked inductivity of 664 backedges. 177 proven. 1 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-12-02 06:24:10,006 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1069292966] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:24:10,006 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:24:10,006 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:24:10,007 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1136159373] [2024-12-02 06:24:10,007 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:24:10,007 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:24:10,007 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:10,008 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:24:10,008 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:24:10,008 INFO L87 Difference]: Start difference. First operand 2647 states and 3856 transitions. Second operand has 9 states, 9 states have (on average 66.55555555555556) internal successors, (599), 9 states have internal predecessors, (599), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:24:10,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:10,078 INFO L93 Difference]: Finished difference Result 3548 states and 5168 transitions. [2024-12-02 06:24:10,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:24:10,079 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 66.55555555555556) internal successors, (599), 9 states have internal predecessors, (599), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 701 [2024-12-02 06:24:10,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:10,081 INFO L225 Difference]: With dead ends: 3548 [2024-12-02 06:24:10,081 INFO L226 Difference]: Without dead ends: 2653 [2024-12-02 06:24:10,082 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1405 GetRequests, 1397 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:24:10,083 INFO L435 NwaCegarLoop]: 1098 mSDtfsCounter, 15 mSDsluCounter, 4366 mSDsCounter, 0 mSdLazyCounter, 51 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 5464 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 51 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:10,083 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 5464 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 51 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:24:10,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2653 states. [2024-12-02 06:24:10,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2653 to 2653. [2024-12-02 06:24:10,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2653 states, 2631 states have (on average 1.4526795895096922) internal successors, (3822), 2631 states have internal predecessors, (3822), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:24:10,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2653 states to 2653 states and 3862 transitions. [2024-12-02 06:24:10,116 INFO L78 Accepts]: Start accepts. Automaton has 2653 states and 3862 transitions. Word has length 701 [2024-12-02 06:24:10,116 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:10,116 INFO L471 AbstractCegarLoop]: Abstraction has 2653 states and 3862 transitions. [2024-12-02 06:24:10,116 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 66.55555555555556) internal successors, (599), 9 states have internal predecessors, (599), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:24:10,116 INFO L276 IsEmpty]: Start isEmpty. Operand 2653 states and 3862 transitions. [2024-12-02 06:24:10,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 708 [2024-12-02 06:24:10,120 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:10,120 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:10,134 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Ended with exit code 0 [2024-12-02 06:24:10,321 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable34 [2024-12-02 06:24:10,321 INFO L396 AbstractCegarLoop]: === Iteration 36 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:10,321 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:10,321 INFO L85 PathProgramCache]: Analyzing trace with hash 725337168, now seen corresponding path program 2 times [2024-12-02 06:24:10,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:10,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936049315] [2024-12-02 06:24:10,321 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:24:10,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:10,488 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:24:10,488 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:24:10,704 INFO L134 CoverageAnalysis]: Checked inductivity of 679 backedges. 168 proven. 4 refuted. 0 times theorem prover too weak. 507 trivial. 0 not checked. [2024-12-02 06:24:10,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:10,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936049315] [2024-12-02 06:24:10,704 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936049315] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:24:10,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1950864012] [2024-12-02 06:24:10,704 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:24:10,704 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:24:10,704 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:24:10,706 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:24:10,707 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2024-12-02 06:24:12,053 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:24:12,054 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:24:12,059 INFO L256 TraceCheckSpWp]: Trace formula consists of 820 conjuncts, 16 conjuncts are in the unsatisfiable core [2024-12-02 06:24:12,066 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:24:13,148 INFO L134 CoverageAnalysis]: Checked inductivity of 679 backedges. 268 proven. 4 refuted. 0 times theorem prover too weak. 407 trivial. 0 not checked. [2024-12-02 06:24:13,148 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:24:14,423 INFO L134 CoverageAnalysis]: Checked inductivity of 679 backedges. 168 proven. 4 refuted. 0 times theorem prover too weak. 507 trivial. 0 not checked. [2024-12-02 06:24:14,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1950864012] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:24:14,424 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:24:14,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 13 [2024-12-02 06:24:14,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1593414082] [2024-12-02 06:24:14,424 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:24:14,425 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2024-12-02 06:24:14,425 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:14,425 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-12-02 06:24:14,426 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:24:14,426 INFO L87 Difference]: Start difference. First operand 2653 states and 3862 transitions. Second operand has 13 states, 13 states have (on average 76.6923076923077) internal successors, (997), 13 states have internal predecessors, (997), 3 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 3 states have call predecessors, (20), 3 states have call successors, (20) [2024-12-02 06:24:15,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:15,557 INFO L93 Difference]: Finished difference Result 4865 states and 7095 transitions. [2024-12-02 06:24:15,558 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:24:15,558 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 76.6923076923077) internal successors, (997), 13 states have internal predecessors, (997), 3 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 3 states have call predecessors, (20), 3 states have call successors, (20) Word has length 707 [2024-12-02 06:24:15,558 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:15,559 INFO L225 Difference]: With dead ends: 4865 [2024-12-02 06:24:15,559 INFO L226 Difference]: Without dead ends: 2669 [2024-12-02 06:24:15,560 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1423 GetRequests, 1408 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=212, Unknown=0, NotChecked=0, Total=272 [2024-12-02 06:24:15,561 INFO L435 NwaCegarLoop]: 798 mSDtfsCounter, 683 mSDsluCounter, 5558 mSDsCounter, 0 mSdLazyCounter, 2412 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 683 SdHoareTripleChecker+Valid, 6356 SdHoareTripleChecker+Invalid, 2415 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 2412 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:15,561 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [683 Valid, 6356 Invalid, 2415 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 2412 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-12-02 06:24:15,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2669 states. [2024-12-02 06:24:15,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2669 to 2645. [2024-12-02 06:24:15,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2645 states, 2623 states have (on average 1.4494853221502098) internal successors, (3802), 2623 states have internal predecessors, (3802), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:24:15,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2645 states to 2645 states and 3842 transitions. [2024-12-02 06:24:15,590 INFO L78 Accepts]: Start accepts. Automaton has 2645 states and 3842 transitions. Word has length 707 [2024-12-02 06:24:15,590 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:15,590 INFO L471 AbstractCegarLoop]: Abstraction has 2645 states and 3842 transitions. [2024-12-02 06:24:15,590 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 76.6923076923077) internal successors, (997), 13 states have internal predecessors, (997), 3 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 3 states have call predecessors, (20), 3 states have call successors, (20) [2024-12-02 06:24:15,590 INFO L276 IsEmpty]: Start isEmpty. Operand 2645 states and 3842 transitions. [2024-12-02 06:24:15,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 710 [2024-12-02 06:24:15,594 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:15,594 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:15,604 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Ended with exit code 0 [2024-12-02 06:24:15,794 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable35 [2024-12-02 06:24:15,795 INFO L396 AbstractCegarLoop]: === Iteration 37 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:15,795 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:15,795 INFO L85 PathProgramCache]: Analyzing trace with hash -500024490, now seen corresponding path program 1 times [2024-12-02 06:24:15,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:15,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1315597406] [2024-12-02 06:24:15,795 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:15,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:16,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:16,632 INFO L134 CoverageAnalysis]: Checked inductivity of 680 backedges. 178 proven. 16 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-12-02 06:24:16,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:16,632 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1315597406] [2024-12-02 06:24:16,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1315597406] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:24:16,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [687839231] [2024-12-02 06:24:16,633 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:16,633 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:24:16,633 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:24:16,634 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:24:16,635 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2024-12-02 06:24:18,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:18,271 INFO L256 TraceCheckSpWp]: Trace formula consists of 3470 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-12-02 06:24:18,276 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:24:18,349 INFO L134 CoverageAnalysis]: Checked inductivity of 680 backedges. 278 proven. 112 refuted. 0 times theorem prover too weak. 290 trivial. 0 not checked. [2024-12-02 06:24:18,349 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:24:18,456 INFO L134 CoverageAnalysis]: Checked inductivity of 680 backedges. 178 proven. 16 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-12-02 06:24:18,456 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [687839231] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:24:18,456 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:24:18,457 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-12-02 06:24:18,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1133413771] [2024-12-02 06:24:18,457 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:24:18,458 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-12-02 06:24:18,458 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:18,458 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-12-02 06:24:18,458 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:24:18,458 INFO L87 Difference]: Start difference. First operand 2645 states and 3842 transitions. Second operand has 18 states, 18 states have (on average 34.72222222222222) internal successors, (625), 18 states have internal predecessors, (625), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:24:18,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:18,665 INFO L93 Difference]: Finished difference Result 3552 states and 5158 transitions. [2024-12-02 06:24:18,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-12-02 06:24:18,665 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 34.72222222222222) internal successors, (625), 18 states have internal predecessors, (625), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 709 [2024-12-02 06:24:18,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:18,667 INFO L225 Difference]: With dead ends: 3552 [2024-12-02 06:24:18,668 INFO L226 Difference]: Without dead ends: 2653 [2024-12-02 06:24:18,669 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1425 GetRequests, 1407 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:24:18,669 INFO L435 NwaCegarLoop]: 1115 mSDtfsCounter, 28 mSDsluCounter, 13307 mSDsCounter, 0 mSdLazyCounter, 269 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 14422 SdHoareTripleChecker+Invalid, 270 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 269 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:18,669 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 14422 Invalid, 270 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 269 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:24:18,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2653 states. [2024-12-02 06:24:18,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2653 to 2653. [2024-12-02 06:24:18,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2653 states, 2631 states have (on average 1.4481185860889396) internal successors, (3810), 2631 states have internal predecessors, (3810), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-12-02 06:24:18,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2653 states to 2653 states and 3850 transitions. [2024-12-02 06:24:18,701 INFO L78 Accepts]: Start accepts. Automaton has 2653 states and 3850 transitions. Word has length 709 [2024-12-02 06:24:18,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:18,702 INFO L471 AbstractCegarLoop]: Abstraction has 2653 states and 3850 transitions. [2024-12-02 06:24:18,702 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 34.72222222222222) internal successors, (625), 18 states have internal predecessors, (625), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:24:18,702 INFO L276 IsEmpty]: Start isEmpty. Operand 2653 states and 3850 transitions. [2024-12-02 06:24:18,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 718 [2024-12-02 06:24:18,706 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:18,706 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:18,721 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Ended with exit code 0 [2024-12-02 06:24:18,907 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 24 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable36 [2024-12-02 06:24:18,907 INFO L396 AbstractCegarLoop]: === Iteration 38 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:18,907 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:18,907 INFO L85 PathProgramCache]: Analyzing trace with hash -678597274, now seen corresponding path program 2 times [2024-12-02 06:24:18,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:18,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [440464828] [2024-12-02 06:24:18,907 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:24:18,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:19,068 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:24:19,068 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:24:19,951 INFO L134 CoverageAnalysis]: Checked inductivity of 728 backedges. 4 proven. 112 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-12-02 06:24:19,952 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:19,952 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [440464828] [2024-12-02 06:24:19,952 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [440464828] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:24:19,952 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [970700803] [2024-12-02 06:24:19,952 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:24:19,952 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:24:19,952 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:24:19,953 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:24:19,954 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2024-12-02 06:24:21,398 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:24:21,398 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:24:21,404 INFO L256 TraceCheckSpWp]: Trace formula consists of 821 conjuncts, 68 conjuncts are in the unsatisfiable core [2024-12-02 06:24:21,411 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:24:23,308 INFO L134 CoverageAnalysis]: Checked inductivity of 728 backedges. 109 proven. 66 refuted. 0 times theorem prover too weak. 553 trivial. 0 not checked. [2024-12-02 06:24:23,308 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:24:26,168 INFO L134 CoverageAnalysis]: Checked inductivity of 728 backedges. 106 proven. 69 refuted. 0 times theorem prover too weak. 553 trivial. 0 not checked. [2024-12-02 06:24:26,168 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [970700803] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:24:26,168 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:24:26,168 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 11] total 28 [2024-12-02 06:24:26,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1476745058] [2024-12-02 06:24:26,168 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:24:26,169 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 28 states [2024-12-02 06:24:26,169 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:26,170 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2024-12-02 06:24:26,171 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=665, Unknown=0, NotChecked=0, Total=756 [2024-12-02 06:24:26,171 INFO L87 Difference]: Start difference. First operand 2653 states and 3850 transitions. Second operand has 28 states, 28 states have (on average 56.25) internal successors, (1575), 28 states have internal predecessors, (1575), 5 states have call successors, (25), 1 states have call predecessors, (25), 1 states have return successors, (25), 5 states have call predecessors, (25), 5 states have call successors, (25) [2024-12-02 06:24:31,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:31,230 INFO L93 Difference]: Finished difference Result 5595 states and 8148 transitions. [2024-12-02 06:24:31,230 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-12-02 06:24:31,230 INFO L78 Accepts]: Start accepts. Automaton has has 28 states, 28 states have (on average 56.25) internal successors, (1575), 28 states have internal predecessors, (1575), 5 states have call successors, (25), 1 states have call predecessors, (25), 1 states have return successors, (25), 5 states have call predecessors, (25), 5 states have call successors, (25) Word has length 717 [2024-12-02 06:24:31,231 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:31,233 INFO L225 Difference]: With dead ends: 5595 [2024-12-02 06:24:31,233 INFO L226 Difference]: Without dead ends: 3822 [2024-12-02 06:24:31,235 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1465 GetRequests, 1417 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 334 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=322, Invalid=2128, Unknown=0, NotChecked=0, Total=2450 [2024-12-02 06:24:31,236 INFO L435 NwaCegarLoop]: 867 mSDtfsCounter, 2416 mSDsluCounter, 15000 mSDsCounter, 0 mSdLazyCounter, 7470 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2416 SdHoareTripleChecker+Valid, 15867 SdHoareTripleChecker+Invalid, 7477 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 7470 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 4.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:31,236 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2416 Valid, 15867 Invalid, 7477 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 7470 Invalid, 0 Unknown, 0 Unchecked, 4.2s Time] [2024-12-02 06:24:31,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3822 states. [2024-12-02 06:24:31,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3822 to 3797. [2024-12-02 06:24:31,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3797 states, 3735 states have (on average 1.4465863453815262) internal successors, (5403), 3735 states have internal predecessors, (5403), 60 states have call successors, (60), 1 states have call predecessors, (60), 1 states have return successors, (60), 60 states have call predecessors, (60), 60 states have call successors, (60) [2024-12-02 06:24:31,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3797 states to 3797 states and 5523 transitions. [2024-12-02 06:24:31,283 INFO L78 Accepts]: Start accepts. Automaton has 3797 states and 5523 transitions. Word has length 717 [2024-12-02 06:24:31,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:31,283 INFO L471 AbstractCegarLoop]: Abstraction has 3797 states and 5523 transitions. [2024-12-02 06:24:31,283 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 28 states, 28 states have (on average 56.25) internal successors, (1575), 28 states have internal predecessors, (1575), 5 states have call successors, (25), 1 states have call predecessors, (25), 1 states have return successors, (25), 5 states have call predecessors, (25), 5 states have call successors, (25) [2024-12-02 06:24:31,283 INFO L276 IsEmpty]: Start isEmpty. Operand 3797 states and 5523 transitions. [2024-12-02 06:24:31,309 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 718 [2024-12-02 06:24:31,309 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:31,310 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:31,320 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Ended with exit code 0 [2024-12-02 06:24:31,510 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 25 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable37 [2024-12-02 06:24:31,510 INFO L396 AbstractCegarLoop]: === Iteration 39 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:31,512 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:31,512 INFO L85 PathProgramCache]: Analyzing trace with hash -1437563269, now seen corresponding path program 1 times [2024-12-02 06:24:31,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:31,512 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [474694771] [2024-12-02 06:24:31,512 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:31,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:31,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:32,227 INFO L134 CoverageAnalysis]: Checked inductivity of 727 backedges. 177 proven. 1 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-12-02 06:24:32,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:32,227 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [474694771] [2024-12-02 06:24:32,227 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [474694771] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:24:32,227 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1769906401] [2024-12-02 06:24:32,227 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:32,227 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:24:32,227 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:24:32,229 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:24:32,230 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2024-12-02 06:24:33,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:33,962 INFO L256 TraceCheckSpWp]: Trace formula consists of 3508 conjuncts, 15 conjuncts are in the unsatisfiable core [2024-12-02 06:24:33,967 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:24:33,993 INFO L134 CoverageAnalysis]: Checked inductivity of 727 backedges. 114 proven. 2 refuted. 0 times theorem prover too weak. 611 trivial. 0 not checked. [2024-12-02 06:24:33,993 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:24:34,034 INFO L134 CoverageAnalysis]: Checked inductivity of 727 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 613 trivial. 0 not checked. [2024-12-02 06:24:34,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1769906401] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:24:34,034 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:24:34,034 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 6] total 10 [2024-12-02 06:24:34,034 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139977947] [2024-12-02 06:24:34,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:34,035 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:24:34,035 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:34,035 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:24:34,035 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:24:34,035 INFO L87 Difference]: Start difference. First operand 3797 states and 5523 transitions. Second operand has 4 states, 4 states have (on average 132.25) internal successors, (529), 4 states have internal predecessors, (529), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:24:34,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:34,090 INFO L93 Difference]: Finished difference Result 5918 states and 8608 transitions. [2024-12-02 06:24:34,090 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:24:34,090 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 132.25) internal successors, (529), 4 states have internal predecessors, (529), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 717 [2024-12-02 06:24:34,091 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:34,095 INFO L225 Difference]: With dead ends: 5918 [2024-12-02 06:24:34,095 INFO L226 Difference]: Without dead ends: 3821 [2024-12-02 06:24:34,098 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1436 GetRequests, 1428 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:24:34,098 INFO L435 NwaCegarLoop]: 1093 mSDtfsCounter, 0 mSDsluCounter, 2176 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3269 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:34,098 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3269 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:24:34,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3821 states. [2024-12-02 06:24:34,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3821 to 3821. [2024-12-02 06:24:34,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3821 states, 3759 states have (on average 1.4437350359138068) internal successors, (5427), 3759 states have internal predecessors, (5427), 60 states have call successors, (60), 1 states have call predecessors, (60), 1 states have return successors, (60), 60 states have call predecessors, (60), 60 states have call successors, (60) [2024-12-02 06:24:34,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3821 states to 3821 states and 5547 transitions. [2024-12-02 06:24:34,202 INFO L78 Accepts]: Start accepts. Automaton has 3821 states and 5547 transitions. Word has length 717 [2024-12-02 06:24:34,203 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:34,203 INFO L471 AbstractCegarLoop]: Abstraction has 3821 states and 5547 transitions. [2024-12-02 06:24:34,203 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 132.25) internal successors, (529), 4 states have internal predecessors, (529), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:24:34,203 INFO L276 IsEmpty]: Start isEmpty. Operand 3821 states and 5547 transitions. [2024-12-02 06:24:34,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 719 [2024-12-02 06:24:34,211 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:34,211 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:34,226 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Ended with exit code 0 [2024-12-02 06:24:34,411 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 26 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable38 [2024-12-02 06:24:34,412 INFO L396 AbstractCegarLoop]: === Iteration 40 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:34,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:34,412 INFO L85 PathProgramCache]: Analyzing trace with hash 747837686, now seen corresponding path program 1 times [2024-12-02 06:24:34,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:34,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249060427] [2024-12-02 06:24:34,412 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:34,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:34,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:35,104 INFO L134 CoverageAnalysis]: Checked inductivity of 728 backedges. 178 proven. 1 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-12-02 06:24:35,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:35,104 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249060427] [2024-12-02 06:24:35,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1249060427] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:24:35,104 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [940603209] [2024-12-02 06:24:35,104 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:35,105 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:24:35,105 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:24:35,106 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:24:35,107 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2024-12-02 06:24:36,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:36,936 INFO L256 TraceCheckSpWp]: Trace formula consists of 3507 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:24:36,942 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:24:36,973 INFO L134 CoverageAnalysis]: Checked inductivity of 728 backedges. 278 proven. 37 refuted. 0 times theorem prover too weak. 413 trivial. 0 not checked. [2024-12-02 06:24:36,973 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:24:37,025 INFO L134 CoverageAnalysis]: Checked inductivity of 728 backedges. 178 proven. 1 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-12-02 06:24:37,025 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [940603209] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:24:37,025 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:24:37,026 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:24:37,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1535541131] [2024-12-02 06:24:37,026 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:24:37,027 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:24:37,027 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:37,027 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:24:37,027 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:24:37,027 INFO L87 Difference]: Start difference. First operand 3821 states and 5547 transitions. Second operand has 9 states, 9 states have (on average 66.88888888888889) internal successors, (602), 9 states have internal predecessors, (602), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:24:37,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:37,129 INFO L93 Difference]: Finished difference Result 5029 states and 7296 transitions. [2024-12-02 06:24:37,129 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:24:37,129 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 66.88888888888889) internal successors, (602), 9 states have internal predecessors, (602), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 718 [2024-12-02 06:24:37,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:37,133 INFO L225 Difference]: With dead ends: 5029 [2024-12-02 06:24:37,133 INFO L226 Difference]: Without dead ends: 3827 [2024-12-02 06:24:37,135 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1439 GetRequests, 1431 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:24:37,135 INFO L435 NwaCegarLoop]: 1097 mSDtfsCounter, 16 mSDsluCounter, 5455 mSDsCounter, 0 mSdLazyCounter, 57 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 16 SdHoareTripleChecker+Valid, 6552 SdHoareTripleChecker+Invalid, 59 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 57 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:37,135 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [16 Valid, 6552 Invalid, 59 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 57 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:24:37,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3827 states. [2024-12-02 06:24:37,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3827 to 3827. [2024-12-02 06:24:37,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3827 states, 3765 states have (on average 1.443027888446215) internal successors, (5433), 3765 states have internal predecessors, (5433), 60 states have call successors, (60), 1 states have call predecessors, (60), 1 states have return successors, (60), 60 states have call predecessors, (60), 60 states have call successors, (60) [2024-12-02 06:24:37,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3827 states to 3827 states and 5553 transitions. [2024-12-02 06:24:37,219 INFO L78 Accepts]: Start accepts. Automaton has 3827 states and 5553 transitions. Word has length 718 [2024-12-02 06:24:37,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:37,219 INFO L471 AbstractCegarLoop]: Abstraction has 3827 states and 5553 transitions. [2024-12-02 06:24:37,219 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 66.88888888888889) internal successors, (602), 9 states have internal predecessors, (602), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:24:37,219 INFO L276 IsEmpty]: Start isEmpty. Operand 3827 states and 5553 transitions. [2024-12-02 06:24:37,223 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 725 [2024-12-02 06:24:37,223 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:37,224 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:37,239 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Ended with exit code 0 [2024-12-02 06:24:37,424 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable39 [2024-12-02 06:24:37,424 INFO L396 AbstractCegarLoop]: === Iteration 41 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:37,424 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:37,425 INFO L85 PathProgramCache]: Analyzing trace with hash 677897834, now seen corresponding path program 2 times [2024-12-02 06:24:37,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:37,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624841558] [2024-12-02 06:24:37,425 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:24:37,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:37,752 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:24:37,752 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:24:38,999 INFO L134 CoverageAnalysis]: Checked inductivity of 743 backedges. 178 proven. 0 refuted. 0 times theorem prover too weak. 565 trivial. 0 not checked. [2024-12-02 06:24:38,999 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:38,999 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624841558] [2024-12-02 06:24:38,999 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [624841558] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:24:38,999 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:24:38,999 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-12-02 06:24:38,999 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1891089581] [2024-12-02 06:24:38,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:39,000 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:24:39,000 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:39,000 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:24:39,000 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:24:39,000 INFO L87 Difference]: Start difference. First operand 3827 states and 5553 transitions. Second operand has 9 states, 9 states have (on average 65.22222222222223) internal successors, (587), 9 states have internal predecessors, (587), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:39,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:39,528 INFO L93 Difference]: Finished difference Result 6653 states and 9644 transitions. [2024-12-02 06:24:39,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:24:39,528 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 65.22222222222223) internal successors, (587), 9 states have internal predecessors, (587), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 724 [2024-12-02 06:24:39,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:39,532 INFO L225 Difference]: With dead ends: 6653 [2024-12-02 06:24:39,532 INFO L226 Difference]: Without dead ends: 5028 [2024-12-02 06:24:39,534 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:24:39,534 INFO L435 NwaCegarLoop]: 1848 mSDtfsCounter, 1338 mSDsluCounter, 7252 mSDsCounter, 0 mSdLazyCounter, 602 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1338 SdHoareTripleChecker+Valid, 9100 SdHoareTripleChecker+Invalid, 611 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 602 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:39,534 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1338 Valid, 9100 Invalid, 611 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 602 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 06:24:39,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5028 states. [2024-12-02 06:24:39,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5028 to 4435. [2024-12-02 06:24:39,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4435 states, 4358 states have (on average 1.4407985314364387) internal successors, (6279), 4358 states have internal predecessors, (6279), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:24:39,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4435 states to 4435 states and 6429 transitions. [2024-12-02 06:24:39,598 INFO L78 Accepts]: Start accepts. Automaton has 4435 states and 6429 transitions. Word has length 724 [2024-12-02 06:24:39,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:39,598 INFO L471 AbstractCegarLoop]: Abstraction has 4435 states and 6429 transitions. [2024-12-02 06:24:39,598 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 65.22222222222223) internal successors, (587), 9 states have internal predecessors, (587), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:39,598 INFO L276 IsEmpty]: Start isEmpty. Operand 4435 states and 6429 transitions. [2024-12-02 06:24:39,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 726 [2024-12-02 06:24:39,603 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:39,603 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:39,603 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable40 [2024-12-02 06:24:39,603 INFO L396 AbstractCegarLoop]: === Iteration 42 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:39,604 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:39,604 INFO L85 PathProgramCache]: Analyzing trace with hash -363847226, now seen corresponding path program 1 times [2024-12-02 06:24:39,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:39,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815137322] [2024-12-02 06:24:39,604 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:39,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:39,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:40,586 INFO L134 CoverageAnalysis]: Checked inductivity of 744 backedges. 179 proven. 16 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-12-02 06:24:40,586 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:40,586 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815137322] [2024-12-02 06:24:40,586 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815137322] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:24:40,586 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [702521317] [2024-12-02 06:24:40,586 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:40,586 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:24:40,586 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:24:40,588 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:24:40,589 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2024-12-02 06:24:42,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:42,444 INFO L256 TraceCheckSpWp]: Trace formula consists of 3537 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-12-02 06:24:42,449 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:24:42,513 INFO L134 CoverageAnalysis]: Checked inductivity of 744 backedges. 279 proven. 112 refuted. 0 times theorem prover too weak. 353 trivial. 0 not checked. [2024-12-02 06:24:42,514 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:24:42,612 INFO L134 CoverageAnalysis]: Checked inductivity of 744 backedges. 179 proven. 16 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-12-02 06:24:42,612 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [702521317] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:24:42,612 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:24:42,613 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-12-02 06:24:42,613 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [286863686] [2024-12-02 06:24:42,613 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:24:42,613 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-12-02 06:24:42,613 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:42,614 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-12-02 06:24:42,614 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:24:42,614 INFO L87 Difference]: Start difference. First operand 4435 states and 6429 transitions. Second operand has 18 states, 18 states have (on average 34.833333333333336) internal successors, (627), 18 states have internal predecessors, (627), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:24:42,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:42,798 INFO L93 Difference]: Finished difference Result 6267 states and 9075 transitions. [2024-12-02 06:24:42,799 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-12-02 06:24:42,799 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 34.833333333333336) internal successors, (627), 18 states have internal predecessors, (627), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 725 [2024-12-02 06:24:42,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:42,803 INFO L225 Difference]: With dead ends: 6267 [2024-12-02 06:24:42,803 INFO L226 Difference]: Without dead ends: 4451 [2024-12-02 06:24:42,805 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1457 GetRequests, 1439 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:24:42,805 INFO L435 NwaCegarLoop]: 1115 mSDtfsCounter, 27 mSDsluCounter, 11085 mSDsCounter, 0 mSdLazyCounter, 235 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 12200 SdHoareTripleChecker+Invalid, 236 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 235 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:42,805 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 12200 Invalid, 236 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 235 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:24:42,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4451 states. [2024-12-02 06:24:42,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4451 to 4451. [2024-12-02 06:24:42,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4451 states, 4374 states have (on average 1.4391860996799268) internal successors, (6295), 4374 states have internal predecessors, (6295), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:24:42,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4451 states to 4451 states and 6445 transitions. [2024-12-02 06:24:42,860 INFO L78 Accepts]: Start accepts. Automaton has 4451 states and 6445 transitions. Word has length 725 [2024-12-02 06:24:42,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:42,861 INFO L471 AbstractCegarLoop]: Abstraction has 4451 states and 6445 transitions. [2024-12-02 06:24:42,861 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 34.833333333333336) internal successors, (627), 18 states have internal predecessors, (627), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:24:42,861 INFO L276 IsEmpty]: Start isEmpty. Operand 4451 states and 6445 transitions. [2024-12-02 06:24:42,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 734 [2024-12-02 06:24:42,865 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:42,866 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:42,881 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Ended with exit code 0 [2024-12-02 06:24:43,066 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 28 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable41 [2024-12-02 06:24:43,066 INFO L396 AbstractCegarLoop]: === Iteration 43 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:43,067 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:43,067 INFO L85 PathProgramCache]: Analyzing trace with hash -1074946090, now seen corresponding path program 2 times [2024-12-02 06:24:43,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:43,067 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904045071] [2024-12-02 06:24:43,067 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:24:43,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:43,428 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:24:43,428 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:24:44,250 INFO L134 CoverageAnalysis]: Checked inductivity of 792 backedges. 179 proven. 0 refuted. 0 times theorem prover too weak. 613 trivial. 0 not checked. [2024-12-02 06:24:44,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:44,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1904045071] [2024-12-02 06:24:44,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1904045071] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:24:44,250 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:24:44,250 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:24:44,250 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103904300] [2024-12-02 06:24:44,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:44,251 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:24:44,251 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:44,251 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:24:44,251 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:24:44,251 INFO L87 Difference]: Start difference. First operand 4451 states and 6445 transitions. Second operand has 7 states, 7 states have (on average 84.0) internal successors, (588), 7 states have internal predecessors, (588), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:45,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:45,083 INFO L93 Difference]: Finished difference Result 6876 states and 9943 transitions. [2024-12-02 06:24:45,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:24:45,084 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 84.0) internal successors, (588), 7 states have internal predecessors, (588), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 733 [2024-12-02 06:24:45,084 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:45,088 INFO L225 Difference]: With dead ends: 6876 [2024-12-02 06:24:45,088 INFO L226 Difference]: Without dead ends: 5044 [2024-12-02 06:24:45,089 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:24:45,090 INFO L435 NwaCegarLoop]: 1409 mSDtfsCounter, 1633 mSDsluCounter, 4183 mSDsCounter, 0 mSdLazyCounter, 1909 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1633 SdHoareTripleChecker+Valid, 5592 SdHoareTripleChecker+Invalid, 1909 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1909 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:45,090 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1633 Valid, 5592 Invalid, 1909 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1909 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-12-02 06:24:45,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5044 states. [2024-12-02 06:24:45,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5044 to 4453. [2024-12-02 06:24:45,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4453 states, 4376 states have (on average 1.4389853747714807) internal successors, (6297), 4376 states have internal predecessors, (6297), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:24:45,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4453 states to 4453 states and 6447 transitions. [2024-12-02 06:24:45,160 INFO L78 Accepts]: Start accepts. Automaton has 4453 states and 6447 transitions. Word has length 733 [2024-12-02 06:24:45,161 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:45,161 INFO L471 AbstractCegarLoop]: Abstraction has 4453 states and 6447 transitions. [2024-12-02 06:24:45,161 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 84.0) internal successors, (588), 7 states have internal predecessors, (588), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:45,161 INFO L276 IsEmpty]: Start isEmpty. Operand 4453 states and 6447 transitions. [2024-12-02 06:24:45,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 734 [2024-12-02 06:24:45,165 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:45,166 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:45,166 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable42 [2024-12-02 06:24:45,166 INFO L396 AbstractCegarLoop]: === Iteration 44 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:45,166 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:45,167 INFO L85 PathProgramCache]: Analyzing trace with hash 1656438812, now seen corresponding path program 1 times [2024-12-02 06:24:45,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:45,167 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095334823] [2024-12-02 06:24:45,167 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:45,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:45,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:45,889 INFO L134 CoverageAnalysis]: Checked inductivity of 791 backedges. 178 proven. 1 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-12-02 06:24:45,889 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:45,889 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095334823] [2024-12-02 06:24:45,889 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095334823] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:24:45,889 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [728943729] [2024-12-02 06:24:45,889 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:45,889 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:24:45,889 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:24:45,891 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:24:45,891 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2024-12-02 06:24:47,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:47,855 INFO L256 TraceCheckSpWp]: Trace formula consists of 3573 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:24:47,864 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:24:47,904 INFO L134 CoverageAnalysis]: Checked inductivity of 791 backedges. 278 proven. 37 refuted. 0 times theorem prover too weak. 476 trivial. 0 not checked. [2024-12-02 06:24:47,904 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:24:47,962 INFO L134 CoverageAnalysis]: Checked inductivity of 791 backedges. 178 proven. 1 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-12-02 06:24:47,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [728943729] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:24:47,963 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:24:47,963 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:24:47,963 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [168271582] [2024-12-02 06:24:47,963 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:24:47,964 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:24:47,964 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:47,965 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:24:47,965 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:24:47,965 INFO L87 Difference]: Start difference. First operand 4453 states and 6447 transitions. Second operand has 9 states, 9 states have (on average 67.0) internal successors, (603), 9 states have internal predecessors, (603), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:24:48,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:48,108 INFO L93 Difference]: Finished difference Result 6299 states and 9105 transitions. [2024-12-02 06:24:48,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:24:48,109 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 67.0) internal successors, (603), 9 states have internal predecessors, (603), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 733 [2024-12-02 06:24:48,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:48,113 INFO L225 Difference]: With dead ends: 6299 [2024-12-02 06:24:48,113 INFO L226 Difference]: Without dead ends: 4465 [2024-12-02 06:24:48,116 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1469 GetRequests, 1461 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:24:48,116 INFO L435 NwaCegarLoop]: 1097 mSDtfsCounter, 14 mSDsluCounter, 7641 mSDsCounter, 0 mSdLazyCounter, 72 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 14 SdHoareTripleChecker+Valid, 8738 SdHoareTripleChecker+Invalid, 74 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 72 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:48,116 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [14 Valid, 8738 Invalid, 74 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 72 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:24:48,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4465 states. [2024-12-02 06:24:48,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4465 to 4465. [2024-12-02 06:24:48,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4465 states, 4388 states have (on average 1.437784867821331) internal successors, (6309), 4388 states have internal predecessors, (6309), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:24:48,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4465 states to 4465 states and 6459 transitions. [2024-12-02 06:24:48,214 INFO L78 Accepts]: Start accepts. Automaton has 4465 states and 6459 transitions. Word has length 733 [2024-12-02 06:24:48,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:48,214 INFO L471 AbstractCegarLoop]: Abstraction has 4465 states and 6459 transitions. [2024-12-02 06:24:48,214 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 67.0) internal successors, (603), 9 states have internal predecessors, (603), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:24:48,214 INFO L276 IsEmpty]: Start isEmpty. Operand 4465 states and 6459 transitions. [2024-12-02 06:24:48,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 740 [2024-12-02 06:24:48,225 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:48,225 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:48,240 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Ended with exit code 0 [2024-12-02 06:24:48,425 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable43,29 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:24:48,425 INFO L396 AbstractCegarLoop]: === Iteration 45 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:48,426 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:48,426 INFO L85 PathProgramCache]: Analyzing trace with hash -1964792496, now seen corresponding path program 2 times [2024-12-02 06:24:48,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:48,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227306289] [2024-12-02 06:24:48,426 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:24:48,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:48,801 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:24:48,801 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:24:49,415 INFO L134 CoverageAnalysis]: Checked inductivity of 806 backedges. 178 proven. 16 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-12-02 06:24:49,415 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:49,415 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227306289] [2024-12-02 06:24:49,415 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1227306289] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:24:49,415 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [150027469] [2024-12-02 06:24:49,415 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:24:49,416 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:24:49,416 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:24:49,417 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:24:49,418 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2024-12-02 06:24:51,508 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:24:51,508 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:24:51,524 INFO L256 TraceCheckSpWp]: Trace formula consists of 3600 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-12-02 06:24:51,530 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:24:51,605 INFO L134 CoverageAnalysis]: Checked inductivity of 806 backedges. 278 proven. 112 refuted. 0 times theorem prover too weak. 416 trivial. 0 not checked. [2024-12-02 06:24:51,605 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:24:51,708 INFO L134 CoverageAnalysis]: Checked inductivity of 806 backedges. 178 proven. 16 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-12-02 06:24:51,708 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [150027469] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:24:51,708 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:24:51,709 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-12-02 06:24:51,709 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1138255649] [2024-12-02 06:24:51,709 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:24:51,710 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-12-02 06:24:51,710 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:51,711 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-12-02 06:24:51,711 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:24:51,711 INFO L87 Difference]: Start difference. First operand 4465 states and 6459 transitions. Second operand has 18 states, 18 states have (on average 34.833333333333336) internal successors, (627), 18 states have internal predecessors, (627), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:24:51,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:51,900 INFO L93 Difference]: Finished difference Result 6327 states and 9135 transitions. [2024-12-02 06:24:51,900 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-12-02 06:24:51,900 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 34.833333333333336) internal successors, (627), 18 states have internal predecessors, (627), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 739 [2024-12-02 06:24:51,901 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:51,904 INFO L225 Difference]: With dead ends: 6327 [2024-12-02 06:24:51,904 INFO L226 Difference]: Without dead ends: 4481 [2024-12-02 06:24:51,906 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1485 GetRequests, 1467 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:24:51,907 INFO L435 NwaCegarLoop]: 1115 mSDtfsCounter, 27 mSDsluCounter, 11085 mSDsCounter, 0 mSdLazyCounter, 240 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 12200 SdHoareTripleChecker+Invalid, 241 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 240 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:51,907 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 12200 Invalid, 241 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 240 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:24:51,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4481 states. [2024-12-02 06:24:51,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4481 to 4481. [2024-12-02 06:24:51,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4481 states, 4404 states have (on average 1.4361943687556766) internal successors, (6325), 4404 states have internal predecessors, (6325), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:24:51,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4481 states to 4481 states and 6475 transitions. [2024-12-02 06:24:51,966 INFO L78 Accepts]: Start accepts. Automaton has 4481 states and 6475 transitions. Word has length 739 [2024-12-02 06:24:51,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:51,967 INFO L471 AbstractCegarLoop]: Abstraction has 4481 states and 6475 transitions. [2024-12-02 06:24:51,967 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 34.833333333333336) internal successors, (627), 18 states have internal predecessors, (627), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:24:51,967 INFO L276 IsEmpty]: Start isEmpty. Operand 4481 states and 6475 transitions. [2024-12-02 06:24:51,972 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 748 [2024-12-02 06:24:51,972 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:51,973 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:51,993 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Ended with exit code 0 [2024-12-02 06:24:52,173 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable44,30 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:24:52,173 INFO L396 AbstractCegarLoop]: === Iteration 46 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:52,173 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:52,174 INFO L85 PathProgramCache]: Analyzing trace with hash 201669184, now seen corresponding path program 3 times [2024-12-02 06:24:52,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:52,174 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775812325] [2024-12-02 06:24:52,174 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-12-02 06:24:52,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:52,628 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2024-12-02 06:24:52,628 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:24:53,588 INFO L134 CoverageAnalysis]: Checked inductivity of 854 backedges. 178 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:24:53,588 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:53,588 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775812325] [2024-12-02 06:24:53,588 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775812325] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:24:53,588 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:24:53,589 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:24:53,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1857882231] [2024-12-02 06:24:53,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:53,589 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:24:53,589 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:53,590 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:24:53,590 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:24:53,590 INFO L87 Difference]: Start difference. First operand 4481 states and 6475 transitions. Second operand has 8 states, 8 states have (on average 73.5) internal successors, (588), 8 states have internal predecessors, (588), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:54,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:54,846 INFO L93 Difference]: Finished difference Result 7566 states and 10903 transitions. [2024-12-02 06:24:54,846 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:24:54,846 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 73.5) internal successors, (588), 8 states have internal predecessors, (588), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 747 [2024-12-02 06:24:54,847 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:54,851 INFO L225 Difference]: With dead ends: 7566 [2024-12-02 06:24:54,851 INFO L226 Difference]: Without dead ends: 5704 [2024-12-02 06:24:54,854 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:24:54,854 INFO L435 NwaCegarLoop]: 1532 mSDtfsCounter, 1608 mSDsluCounter, 6212 mSDsCounter, 0 mSdLazyCounter, 2708 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1613 SdHoareTripleChecker+Valid, 7744 SdHoareTripleChecker+Invalid, 2709 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 2708 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:54,854 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1613 Valid, 7744 Invalid, 2709 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 2708 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-12-02 06:24:54,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5704 states. [2024-12-02 06:24:54,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5704 to 4481. [2024-12-02 06:24:54,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4481 states, 4404 states have (on average 1.4361943687556766) internal successors, (6325), 4404 states have internal predecessors, (6325), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:24:54,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4481 states to 4481 states and 6475 transitions. [2024-12-02 06:24:54,927 INFO L78 Accepts]: Start accepts. Automaton has 4481 states and 6475 transitions. Word has length 747 [2024-12-02 06:24:54,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:54,928 INFO L471 AbstractCegarLoop]: Abstraction has 4481 states and 6475 transitions. [2024-12-02 06:24:54,928 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 73.5) internal successors, (588), 8 states have internal predecessors, (588), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:54,928 INFO L276 IsEmpty]: Start isEmpty. Operand 4481 states and 6475 transitions. [2024-12-02 06:24:54,934 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 749 [2024-12-02 06:24:54,934 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:54,934 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:54,934 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable45 [2024-12-02 06:24:54,934 INFO L396 AbstractCegarLoop]: === Iteration 47 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:54,935 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:54,935 INFO L85 PathProgramCache]: Analyzing trace with hash -911130559, now seen corresponding path program 1 times [2024-12-02 06:24:54,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:54,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716339558] [2024-12-02 06:24:54,935 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:54,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:55,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:56,643 INFO L134 CoverageAnalysis]: Checked inductivity of 855 backedges. 179 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:24:56,643 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:56,644 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1716339558] [2024-12-02 06:24:56,644 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1716339558] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:24:56,644 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:24:56,644 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:24:56,644 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1969021770] [2024-12-02 06:24:56,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:56,644 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:24:56,644 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:56,645 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:24:56,645 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:24:56,645 INFO L87 Difference]: Start difference. First operand 4481 states and 6475 transitions. Second operand has 4 states, 4 states have (on average 147.25) internal successors, (589), 4 states have internal predecessors, (589), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:56,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:56,830 INFO L93 Difference]: Finished difference Result 6343 states and 9143 transitions. [2024-12-02 06:24:56,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:24:56,830 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 147.25) internal successors, (589), 4 states have internal predecessors, (589), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 748 [2024-12-02 06:24:56,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:56,834 INFO L225 Difference]: With dead ends: 6343 [2024-12-02 06:24:56,834 INFO L226 Difference]: Without dead ends: 4481 [2024-12-02 06:24:56,836 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:24:56,837 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 783 mSDsluCounter, 1004 mSDsCounter, 0 mSdLazyCounter, 188 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 783 SdHoareTripleChecker+Valid, 2006 SdHoareTripleChecker+Invalid, 188 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 188 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:56,837 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [783 Valid, 2006 Invalid, 188 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 188 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:24:56,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4481 states. [2024-12-02 06:24:56,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4481 to 4481. [2024-12-02 06:24:56,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4481 states, 4404 states have (on average 1.435967302452316) internal successors, (6324), 4404 states have internal predecessors, (6324), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:24:56,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4481 states to 4481 states and 6474 transitions. [2024-12-02 06:24:56,902 INFO L78 Accepts]: Start accepts. Automaton has 4481 states and 6474 transitions. Word has length 748 [2024-12-02 06:24:56,902 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:56,903 INFO L471 AbstractCegarLoop]: Abstraction has 4481 states and 6474 transitions. [2024-12-02 06:24:56,903 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 147.25) internal successors, (589), 4 states have internal predecessors, (589), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:56,903 INFO L276 IsEmpty]: Start isEmpty. Operand 4481 states and 6474 transitions. [2024-12-02 06:24:56,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 750 [2024-12-02 06:24:56,909 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:56,909 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:56,909 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable46 [2024-12-02 06:24:56,909 INFO L396 AbstractCegarLoop]: === Iteration 48 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:56,909 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:56,910 INFO L85 PathProgramCache]: Analyzing trace with hash -1804583737, now seen corresponding path program 1 times [2024-12-02 06:24:56,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:56,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797091697] [2024-12-02 06:24:56,910 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:56,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:57,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:58,504 INFO L134 CoverageAnalysis]: Checked inductivity of 855 backedges. 179 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:24:58,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:58,505 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797091697] [2024-12-02 06:24:58,505 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1797091697] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:24:58,505 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:24:58,505 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:24:58,505 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071413256] [2024-12-02 06:24:58,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:58,505 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:24:58,505 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:58,506 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:24:58,506 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:24:58,506 INFO L87 Difference]: Start difference. First operand 4481 states and 6474 transitions. Second operand has 5 states, 5 states have (on average 118.0) internal successors, (590), 5 states have internal predecessors, (590), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:58,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:58,778 INFO L93 Difference]: Finished difference Result 6343 states and 9141 transitions. [2024-12-02 06:24:58,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:24:58,779 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 118.0) internal successors, (590), 5 states have internal predecessors, (590), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 749 [2024-12-02 06:24:58,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:58,783 INFO L225 Difference]: With dead ends: 6343 [2024-12-02 06:24:58,783 INFO L226 Difference]: Without dead ends: 4481 [2024-12-02 06:24:58,784 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:24:58,785 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 1073 mSDsluCounter, 1013 mSDsCounter, 0 mSdLazyCounter, 186 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1078 SdHoareTripleChecker+Valid, 2015 SdHoareTripleChecker+Invalid, 186 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 186 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:58,785 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1078 Valid, 2015 Invalid, 186 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 186 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:24:58,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4481 states. [2024-12-02 06:24:58,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4481 to 4481. [2024-12-02 06:24:58,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4481 states, 4404 states have (on average 1.4357402361489555) internal successors, (6323), 4404 states have internal predecessors, (6323), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:24:58,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4481 states to 4481 states and 6473 transitions. [2024-12-02 06:24:58,853 INFO L78 Accepts]: Start accepts. Automaton has 4481 states and 6473 transitions. Word has length 749 [2024-12-02 06:24:58,854 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:58,854 INFO L471 AbstractCegarLoop]: Abstraction has 4481 states and 6473 transitions. [2024-12-02 06:24:58,854 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 118.0) internal successors, (590), 5 states have internal predecessors, (590), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:58,854 INFO L276 IsEmpty]: Start isEmpty. Operand 4481 states and 6473 transitions. [2024-12-02 06:24:58,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 751 [2024-12-02 06:24:58,860 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:58,860 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:58,860 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable47 [2024-12-02 06:24:58,860 INFO L396 AbstractCegarLoop]: === Iteration 49 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:58,860 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:58,861 INFO L85 PathProgramCache]: Analyzing trace with hash -1779083772, now seen corresponding path program 1 times [2024-12-02 06:24:58,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:58,861 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56150313] [2024-12-02 06:24:58,861 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:58,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:59,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:00,486 INFO L134 CoverageAnalysis]: Checked inductivity of 855 backedges. 179 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:25:00,486 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:00,486 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [56150313] [2024-12-02 06:25:00,486 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [56150313] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:00,486 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:00,486 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:25:00,486 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2065813302] [2024-12-02 06:25:00,486 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:00,487 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:25:00,487 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:00,487 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:25:00,487 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:25:00,487 INFO L87 Difference]: Start difference. First operand 4481 states and 6473 transitions. Second operand has 5 states, 5 states have (on average 118.2) internal successors, (591), 5 states have internal predecessors, (591), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:00,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:00,703 INFO L93 Difference]: Finished difference Result 6343 states and 9139 transitions. [2024-12-02 06:25:00,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:25:00,704 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 118.2) internal successors, (591), 5 states have internal predecessors, (591), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 750 [2024-12-02 06:25:00,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:00,708 INFO L225 Difference]: With dead ends: 6343 [2024-12-02 06:25:00,708 INFO L226 Difference]: Without dead ends: 4481 [2024-12-02 06:25:00,710 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:25:00,711 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 1072 mSDsluCounter, 1013 mSDsCounter, 0 mSdLazyCounter, 184 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1077 SdHoareTripleChecker+Valid, 2015 SdHoareTripleChecker+Invalid, 184 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 184 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:00,711 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1077 Valid, 2015 Invalid, 184 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 184 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:25:00,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4481 states. [2024-12-02 06:25:00,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4481 to 4481. [2024-12-02 06:25:00,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4481 states, 4404 states have (on average 1.435513169845595) internal successors, (6322), 4404 states have internal predecessors, (6322), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:25:00,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4481 states to 4481 states and 6472 transitions. [2024-12-02 06:25:00,774 INFO L78 Accepts]: Start accepts. Automaton has 4481 states and 6472 transitions. Word has length 750 [2024-12-02 06:25:00,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:00,774 INFO L471 AbstractCegarLoop]: Abstraction has 4481 states and 6472 transitions. [2024-12-02 06:25:00,774 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 118.2) internal successors, (591), 5 states have internal predecessors, (591), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:00,774 INFO L276 IsEmpty]: Start isEmpty. Operand 4481 states and 6472 transitions. [2024-12-02 06:25:00,779 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 752 [2024-12-02 06:25:00,779 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:00,780 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:00,780 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable48 [2024-12-02 06:25:00,780 INFO L396 AbstractCegarLoop]: === Iteration 50 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:00,780 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:00,780 INFO L85 PathProgramCache]: Analyzing trace with hash 1615415567, now seen corresponding path program 1 times [2024-12-02 06:25:00,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:00,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289795542] [2024-12-02 06:25:00,781 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:00,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:01,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:02,243 INFO L134 CoverageAnalysis]: Checked inductivity of 855 backedges. 179 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:25:02,243 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:02,243 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289795542] [2024-12-02 06:25:02,243 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1289795542] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:02,243 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:02,243 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:25:02,243 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [313721126] [2024-12-02 06:25:02,243 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:02,244 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:25:02,244 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:02,245 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:25:02,245 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:25:02,245 INFO L87 Difference]: Start difference. First operand 4481 states and 6472 transitions. Second operand has 4 states, 4 states have (on average 148.0) internal successors, (592), 4 states have internal predecessors, (592), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:02,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:02,430 INFO L93 Difference]: Finished difference Result 6343 states and 9137 transitions. [2024-12-02 06:25:02,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:25:02,431 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 148.0) internal successors, (592), 4 states have internal predecessors, (592), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 751 [2024-12-02 06:25:02,431 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:02,435 INFO L225 Difference]: With dead ends: 6343 [2024-12-02 06:25:02,435 INFO L226 Difference]: Without dead ends: 4481 [2024-12-02 06:25:02,437 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:25:02,437 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 750 mSDsluCounter, 1004 mSDsCounter, 0 mSdLazyCounter, 182 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 750 SdHoareTripleChecker+Valid, 2006 SdHoareTripleChecker+Invalid, 182 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 182 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:02,437 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [750 Valid, 2006 Invalid, 182 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 182 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:25:02,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4481 states. [2024-12-02 06:25:02,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4481 to 4481. [2024-12-02 06:25:02,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4481 states, 4404 states have (on average 1.4352861035422344) internal successors, (6321), 4404 states have internal predecessors, (6321), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:25:02,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4481 states to 4481 states and 6471 transitions. [2024-12-02 06:25:02,500 INFO L78 Accepts]: Start accepts. Automaton has 4481 states and 6471 transitions. Word has length 751 [2024-12-02 06:25:02,500 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:02,500 INFO L471 AbstractCegarLoop]: Abstraction has 4481 states and 6471 transitions. [2024-12-02 06:25:02,501 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 148.0) internal successors, (592), 4 states have internal predecessors, (592), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:02,501 INFO L276 IsEmpty]: Start isEmpty. Operand 4481 states and 6471 transitions. [2024-12-02 06:25:02,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 753 [2024-12-02 06:25:02,505 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:02,506 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:02,506 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable49 [2024-12-02 06:25:02,506 INFO L396 AbstractCegarLoop]: === Iteration 51 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:02,506 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:02,506 INFO L85 PathProgramCache]: Analyzing trace with hash 739287655, now seen corresponding path program 1 times [2024-12-02 06:25:02,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:02,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1993713295] [2024-12-02 06:25:02,507 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:02,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:04,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:05,531 INFO L134 CoverageAnalysis]: Checked inductivity of 855 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 773 trivial. 0 not checked. [2024-12-02 06:25:05,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:05,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1993713295] [2024-12-02 06:25:05,532 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1993713295] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:05,532 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:05,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:25:05,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [736455610] [2024-12-02 06:25:05,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:05,533 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:25:05,533 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:05,533 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:25:05,533 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:25:05,533 INFO L87 Difference]: Start difference. First operand 4481 states and 6471 transitions. Second operand has 6 states, 6 states have (on average 83.33333333333333) internal successors, (500), 6 states have internal predecessors, (500), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:06,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:06,368 INFO L93 Difference]: Finished difference Result 7267 states and 10484 transitions. [2024-12-02 06:25:06,369 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:25:06,369 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 83.33333333333333) internal successors, (500), 6 states have internal predecessors, (500), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 752 [2024-12-02 06:25:06,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:06,374 INFO L225 Difference]: With dead ends: 7267 [2024-12-02 06:25:06,374 INFO L226 Difference]: Without dead ends: 5057 [2024-12-02 06:25:06,376 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:25:06,377 INFO L435 NwaCegarLoop]: 1346 mSDtfsCounter, 1931 mSDsluCounter, 3438 mSDsCounter, 0 mSdLazyCounter, 1597 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1936 SdHoareTripleChecker+Valid, 4784 SdHoareTripleChecker+Invalid, 1597 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1597 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:06,377 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1936 Valid, 4784 Invalid, 1597 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1597 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-12-02 06:25:06,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5057 states. [2024-12-02 06:25:06,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5057 to 4483. [2024-12-02 06:25:06,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4483 states, 4406 states have (on average 1.435088515660463) internal successors, (6323), 4406 states have internal predecessors, (6323), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:25:06,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4483 states to 4483 states and 6473 transitions. [2024-12-02 06:25:06,475 INFO L78 Accepts]: Start accepts. Automaton has 4483 states and 6473 transitions. Word has length 752 [2024-12-02 06:25:06,475 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:06,475 INFO L471 AbstractCegarLoop]: Abstraction has 4483 states and 6473 transitions. [2024-12-02 06:25:06,475 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 83.33333333333333) internal successors, (500), 6 states have internal predecessors, (500), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:06,475 INFO L276 IsEmpty]: Start isEmpty. Operand 4483 states and 6473 transitions. [2024-12-02 06:25:06,480 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 754 [2024-12-02 06:25:06,480 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:06,480 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:06,480 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable50 [2024-12-02 06:25:06,480 INFO L396 AbstractCegarLoop]: === Iteration 52 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:06,481 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:06,481 INFO L85 PathProgramCache]: Analyzing trace with hash -543702479, now seen corresponding path program 1 times [2024-12-02 06:25:06,481 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:06,481 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862775288] [2024-12-02 06:25:06,481 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:06,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:08,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:09,278 INFO L134 CoverageAnalysis]: Checked inductivity of 854 backedges. 178 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:25:09,279 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:09,279 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1862775288] [2024-12-02 06:25:09,279 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1862775288] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:09,279 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:09,279 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:25:09,279 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407243713] [2024-12-02 06:25:09,279 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:09,280 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:25:09,280 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:09,281 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:25:09,281 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:25:09,281 INFO L87 Difference]: Start difference. First operand 4483 states and 6473 transitions. Second operand has 6 states, 6 states have (on average 99.0) internal successors, (594), 6 states have internal predecessors, (594), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:09,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:09,951 INFO L93 Difference]: Finished difference Result 6573 states and 9455 transitions. [2024-12-02 06:25:09,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:25:09,951 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 99.0) internal successors, (594), 6 states have internal predecessors, (594), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 753 [2024-12-02 06:25:09,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:09,955 INFO L225 Difference]: With dead ends: 6573 [2024-12-02 06:25:09,955 INFO L226 Difference]: Without dead ends: 4711 [2024-12-02 06:25:09,957 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:25:09,958 INFO L435 NwaCegarLoop]: 805 mSDtfsCounter, 928 mSDsluCounter, 2385 mSDsCounter, 0 mSdLazyCounter, 1164 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 928 SdHoareTripleChecker+Valid, 3190 SdHoareTripleChecker+Invalid, 1165 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1164 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:09,958 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [928 Valid, 3190 Invalid, 1165 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1164 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-12-02 06:25:09,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4711 states. [2024-12-02 06:25:10,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4711 to 4707. [2024-12-02 06:25:10,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4707 states, 4630 states have (on average 1.4326133909287257) internal successors, (6633), 4630 states have internal predecessors, (6633), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:25:10,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4707 states to 4707 states and 6783 transitions. [2024-12-02 06:25:10,031 INFO L78 Accepts]: Start accepts. Automaton has 4707 states and 6783 transitions. Word has length 753 [2024-12-02 06:25:10,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:10,031 INFO L471 AbstractCegarLoop]: Abstraction has 4707 states and 6783 transitions. [2024-12-02 06:25:10,031 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 99.0) internal successors, (594), 6 states have internal predecessors, (594), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:10,032 INFO L276 IsEmpty]: Start isEmpty. Operand 4707 states and 6783 transitions. [2024-12-02 06:25:10,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 755 [2024-12-02 06:25:10,037 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:10,037 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:10,037 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable51 [2024-12-02 06:25:10,037 INFO L396 AbstractCegarLoop]: === Iteration 53 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:10,037 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:10,038 INFO L85 PathProgramCache]: Analyzing trace with hash 1141876773, now seen corresponding path program 1 times [2024-12-02 06:25:10,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:10,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254571173] [2024-12-02 06:25:10,038 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:10,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:12,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:13,102 INFO L134 CoverageAnalysis]: Checked inductivity of 854 backedges. 178 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:25:13,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:13,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254571173] [2024-12-02 06:25:13,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [254571173] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:13,102 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:13,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:25:13,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [510796050] [2024-12-02 06:25:13,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:13,102 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:25:13,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:13,103 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:25:13,103 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:25:13,103 INFO L87 Difference]: Start difference. First operand 4707 states and 6783 transitions. Second operand has 6 states, 6 states have (on average 99.16666666666667) internal successors, (595), 6 states have internal predecessors, (595), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:13,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:13,722 INFO L93 Difference]: Finished difference Result 6797 states and 9763 transitions. [2024-12-02 06:25:13,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:25:13,723 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 99.16666666666667) internal successors, (595), 6 states have internal predecessors, (595), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 754 [2024-12-02 06:25:13,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:13,727 INFO L225 Difference]: With dead ends: 6797 [2024-12-02 06:25:13,727 INFO L226 Difference]: Without dead ends: 4711 [2024-12-02 06:25:13,729 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:25:13,729 INFO L435 NwaCegarLoop]: 805 mSDtfsCounter, 1037 mSDsluCounter, 2376 mSDsCounter, 0 mSdLazyCounter, 1164 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1037 SdHoareTripleChecker+Valid, 3181 SdHoareTripleChecker+Invalid, 1164 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1164 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:13,729 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1037 Valid, 3181 Invalid, 1164 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1164 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-12-02 06:25:13,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4711 states. [2024-12-02 06:25:13,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4711 to 4709. [2024-12-02 06:25:13,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4709 states, 4632 states have (on average 1.432426597582038) internal successors, (6635), 4632 states have internal predecessors, (6635), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:25:13,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4709 states to 4709 states and 6785 transitions. [2024-12-02 06:25:13,796 INFO L78 Accepts]: Start accepts. Automaton has 4709 states and 6785 transitions. Word has length 754 [2024-12-02 06:25:13,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:13,797 INFO L471 AbstractCegarLoop]: Abstraction has 4709 states and 6785 transitions. [2024-12-02 06:25:13,797 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 99.16666666666667) internal successors, (595), 6 states have internal predecessors, (595), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:13,797 INFO L276 IsEmpty]: Start isEmpty. Operand 4709 states and 6785 transitions. [2024-12-02 06:25:13,801 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 755 [2024-12-02 06:25:13,801 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:13,802 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:13,802 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable52 [2024-12-02 06:25:13,802 INFO L396 AbstractCegarLoop]: === Iteration 54 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:13,802 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:13,802 INFO L85 PathProgramCache]: Analyzing trace with hash -230697469, now seen corresponding path program 1 times [2024-12-02 06:25:13,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:13,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665704166] [2024-12-02 06:25:13,802 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:13,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:15,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:17,122 INFO L134 CoverageAnalysis]: Checked inductivity of 854 backedges. 178 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:25:17,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:17,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665704166] [2024-12-02 06:25:17,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665704166] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:17,122 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:17,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:25:17,123 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408025392] [2024-12-02 06:25:17,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:17,123 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:25:17,123 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:17,123 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:25:17,123 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:25:17,123 INFO L87 Difference]: Start difference. First operand 4709 states and 6785 transitions. Second operand has 6 states, 6 states have (on average 99.16666666666667) internal successors, (595), 6 states have internal predecessors, (595), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:17,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:17,231 INFO L93 Difference]: Finished difference Result 8287 states and 11909 transitions. [2024-12-02 06:25:17,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:25:17,232 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 99.16666666666667) internal successors, (595), 6 states have internal predecessors, (595), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 754 [2024-12-02 06:25:17,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:17,236 INFO L225 Difference]: With dead ends: 8287 [2024-12-02 06:25:17,236 INFO L226 Difference]: Without dead ends: 6199 [2024-12-02 06:25:17,239 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:25:17,239 INFO L435 NwaCegarLoop]: 1082 mSDtfsCounter, 321 mSDsluCounter, 4311 mSDsCounter, 0 mSdLazyCounter, 61 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 321 SdHoareTripleChecker+Valid, 5393 SdHoareTripleChecker+Invalid, 61 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 61 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:17,239 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [321 Valid, 5393 Invalid, 61 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 61 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:25:17,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6199 states. [2024-12-02 06:25:17,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6199 to 6193. [2024-12-02 06:25:17,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6193 states, 6116 states have (on average 1.4345977763243951) internal successors, (8774), 6116 states have internal predecessors, (8774), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:25:17,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6193 states to 6193 states and 8924 transitions. [2024-12-02 06:25:17,323 INFO L78 Accepts]: Start accepts. Automaton has 6193 states and 8924 transitions. Word has length 754 [2024-12-02 06:25:17,323 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:17,324 INFO L471 AbstractCegarLoop]: Abstraction has 6193 states and 8924 transitions. [2024-12-02 06:25:17,324 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 99.16666666666667) internal successors, (595), 6 states have internal predecessors, (595), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:17,324 INFO L276 IsEmpty]: Start isEmpty. Operand 6193 states and 8924 transitions. [2024-12-02 06:25:17,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 756 [2024-12-02 06:25:17,329 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:17,330 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:17,330 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable53 [2024-12-02 06:25:17,330 INFO L396 AbstractCegarLoop]: === Iteration 55 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:17,330 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:17,330 INFO L85 PathProgramCache]: Analyzing trace with hash 517879210, now seen corresponding path program 1 times [2024-12-02 06:25:17,330 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:17,330 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1285291910] [2024-12-02 06:25:17,331 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:17,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:17,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:18,425 INFO L134 CoverageAnalysis]: Checked inductivity of 854 backedges. 73 proven. 0 refuted. 0 times theorem prover too weak. 781 trivial. 0 not checked. [2024-12-02 06:25:18,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:18,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1285291910] [2024-12-02 06:25:18,426 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1285291910] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:18,426 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:18,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:25:18,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1859408089] [2024-12-02 06:25:18,426 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:18,427 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:25:18,427 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:18,427 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:25:18,427 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:25:18,427 INFO L87 Difference]: Start difference. First operand 6193 states and 8924 transitions. Second operand has 5 states, 5 states have (on average 99.2) internal successors, (496), 5 states have internal predecessors, (496), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:18,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:18,949 INFO L93 Difference]: Finished difference Result 9797 states and 14087 transitions. [2024-12-02 06:25:18,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:25:18,949 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 99.2) internal successors, (496), 5 states have internal predecessors, (496), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 755 [2024-12-02 06:25:18,949 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:18,954 INFO L225 Difference]: With dead ends: 9797 [2024-12-02 06:25:18,954 INFO L226 Difference]: Without dead ends: 6213 [2024-12-02 06:25:18,957 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:25:18,957 INFO L435 NwaCegarLoop]: 809 mSDtfsCounter, 970 mSDsluCounter, 1607 mSDsCounter, 0 mSdLazyCounter, 865 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 970 SdHoareTripleChecker+Valid, 2416 SdHoareTripleChecker+Invalid, 867 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 865 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:18,957 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [970 Valid, 2416 Invalid, 867 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 865 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 06:25:18,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6213 states. [2024-12-02 06:25:19,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6213 to 6213. [2024-12-02 06:25:19,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6213 states, 6136 states have (on average 1.433181225554107) internal successors, (8794), 6136 states have internal predecessors, (8794), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:25:19,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6213 states to 6213 states and 8944 transitions. [2024-12-02 06:25:19,046 INFO L78 Accepts]: Start accepts. Automaton has 6213 states and 8944 transitions. Word has length 755 [2024-12-02 06:25:19,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:19,047 INFO L471 AbstractCegarLoop]: Abstraction has 6213 states and 8944 transitions. [2024-12-02 06:25:19,047 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 99.2) internal successors, (496), 5 states have internal predecessors, (496), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:19,047 INFO L276 IsEmpty]: Start isEmpty. Operand 6213 states and 8944 transitions. [2024-12-02 06:25:19,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 756 [2024-12-02 06:25:19,053 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:19,053 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:19,053 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable54 [2024-12-02 06:25:19,053 INFO L396 AbstractCegarLoop]: === Iteration 56 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:19,054 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:19,054 INFO L85 PathProgramCache]: Analyzing trace with hash 926154490, now seen corresponding path program 1 times [2024-12-02 06:25:19,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:19,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611406008] [2024-12-02 06:25:19,054 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:19,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:20,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:22,459 INFO L134 CoverageAnalysis]: Checked inductivity of 854 backedges. 178 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:25:22,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:22,459 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611406008] [2024-12-02 06:25:22,459 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [611406008] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:22,459 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:22,459 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:25:22,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232457635] [2024-12-02 06:25:22,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:22,460 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:25:22,460 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:22,460 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:25:22,460 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:25:22,460 INFO L87 Difference]: Start difference. First operand 6213 states and 8944 transitions. Second operand has 8 states, 8 states have (on average 74.5) internal successors, (596), 8 states have internal predecessors, (596), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:23,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:23,606 INFO L93 Difference]: Finished difference Result 10239 states and 14688 transitions. [2024-12-02 06:25:23,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:25:23,607 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 74.5) internal successors, (596), 8 states have internal predecessors, (596), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 755 [2024-12-02 06:25:23,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:23,614 INFO L225 Difference]: With dead ends: 10239 [2024-12-02 06:25:23,614 INFO L226 Difference]: Without dead ends: 7503 [2024-12-02 06:25:23,618 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:25:23,618 INFO L435 NwaCegarLoop]: 884 mSDtfsCounter, 3186 mSDsluCounter, 3763 mSDsCounter, 0 mSdLazyCounter, 1915 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3191 SdHoareTripleChecker+Valid, 4647 SdHoareTripleChecker+Invalid, 1916 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1915 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:23,618 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3191 Valid, 4647 Invalid, 1916 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1915 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-12-02 06:25:23,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7503 states. [2024-12-02 06:25:23,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7503 to 7103. [2024-12-02 06:25:23,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7103 states, 7026 states have (on average 1.43467122117848) internal successors, (10080), 7026 states have internal predecessors, (10080), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:25:23,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7103 states to 7103 states and 10230 transitions. [2024-12-02 06:25:23,723 INFO L78 Accepts]: Start accepts. Automaton has 7103 states and 10230 transitions. Word has length 755 [2024-12-02 06:25:23,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:23,724 INFO L471 AbstractCegarLoop]: Abstraction has 7103 states and 10230 transitions. [2024-12-02 06:25:23,724 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 74.5) internal successors, (596), 8 states have internal predecessors, (596), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:23,724 INFO L276 IsEmpty]: Start isEmpty. Operand 7103 states and 10230 transitions. [2024-12-02 06:25:23,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 756 [2024-12-02 06:25:23,730 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:23,730 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:23,730 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable55 [2024-12-02 06:25:23,730 INFO L396 AbstractCegarLoop]: === Iteration 57 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:23,730 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:23,730 INFO L85 PathProgramCache]: Analyzing trace with hash 1239201029, now seen corresponding path program 1 times [2024-12-02 06:25:23,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:23,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594326389] [2024-12-02 06:25:23,731 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:23,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:25,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:27,473 INFO L134 CoverageAnalysis]: Checked inductivity of 854 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 820 trivial. 0 not checked. [2024-12-02 06:25:27,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:27,473 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1594326389] [2024-12-02 06:25:27,473 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1594326389] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:27,473 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:27,473 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:25:27,473 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1154411929] [2024-12-02 06:25:27,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:27,473 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:25:27,473 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:27,474 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:25:27,474 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:25:27,474 INFO L87 Difference]: Start difference. First operand 7103 states and 10230 transitions. Second operand has 8 states, 8 states have (on average 57.5) internal successors, (460), 8 states have internal predecessors, (460), 2 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) [2024-12-02 06:25:27,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:27,661 INFO L93 Difference]: Finished difference Result 13275 states and 19099 transitions. [2024-12-02 06:25:27,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:25:27,661 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 57.5) internal successors, (460), 8 states have internal predecessors, (460), 2 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) Word has length 755 [2024-12-02 06:25:27,662 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:27,669 INFO L225 Difference]: With dead ends: 13275 [2024-12-02 06:25:27,669 INFO L226 Difference]: Without dead ends: 7223 [2024-12-02 06:25:27,674 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:25:27,675 INFO L435 NwaCegarLoop]: 1070 mSDtfsCounter, 1014 mSDsluCounter, 5318 mSDsCounter, 0 mSdLazyCounter, 157 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1017 SdHoareTripleChecker+Valid, 6388 SdHoareTripleChecker+Invalid, 158 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 157 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:27,675 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1017 Valid, 6388 Invalid, 158 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 157 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:25:27,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7223 states. [2024-12-02 06:25:27,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7223 to 7163. [2024-12-02 06:25:27,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7163 states, 7086 states have (on average 1.4331075359864522) internal successors, (10155), 7086 states have internal predecessors, (10155), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:25:27,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7163 states to 7163 states and 10305 transitions. [2024-12-02 06:25:27,801 INFO L78 Accepts]: Start accepts. Automaton has 7163 states and 10305 transitions. Word has length 755 [2024-12-02 06:25:27,801 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:27,801 INFO L471 AbstractCegarLoop]: Abstraction has 7163 states and 10305 transitions. [2024-12-02 06:25:27,801 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 57.5) internal successors, (460), 8 states have internal predecessors, (460), 2 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) [2024-12-02 06:25:27,801 INFO L276 IsEmpty]: Start isEmpty. Operand 7163 states and 10305 transitions. [2024-12-02 06:25:27,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 758 [2024-12-02 06:25:27,807 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:27,808 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:27,808 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable56 [2024-12-02 06:25:27,808 INFO L396 AbstractCegarLoop]: === Iteration 58 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:27,808 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:27,808 INFO L85 PathProgramCache]: Analyzing trace with hash -224738487, now seen corresponding path program 1 times [2024-12-02 06:25:27,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:27,808 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [18012802] [2024-12-02 06:25:27,808 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:27,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:29,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:30,238 INFO L134 CoverageAnalysis]: Checked inductivity of 855 backedges. 35 proven. 0 refuted. 0 times theorem prover too weak. 820 trivial. 0 not checked. [2024-12-02 06:25:30,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:30,238 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [18012802] [2024-12-02 06:25:30,239 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [18012802] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:30,239 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:30,239 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:25:30,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [148992899] [2024-12-02 06:25:30,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:30,240 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:25:30,240 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:30,240 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:25:30,240 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:25:30,241 INFO L87 Difference]: Start difference. First operand 7163 states and 10305 transitions. Second operand has 4 states, 4 states have (on average 115.5) internal successors, (462), 4 states have internal predecessors, (462), 2 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) [2024-12-02 06:25:30,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:30,357 INFO L93 Difference]: Finished difference Result 13257 states and 19066 transitions. [2024-12-02 06:25:30,357 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:25:30,358 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 115.5) internal successors, (462), 4 states have internal predecessors, (462), 2 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) Word has length 757 [2024-12-02 06:25:30,358 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:30,363 INFO L225 Difference]: With dead ends: 13257 [2024-12-02 06:25:30,363 INFO L226 Difference]: Without dead ends: 7163 [2024-12-02 06:25:30,367 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:25:30,367 INFO L435 NwaCegarLoop]: 1075 mSDtfsCounter, 992 mSDsluCounter, 1082 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 995 SdHoareTripleChecker+Valid, 2157 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:30,367 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [995 Valid, 2157 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:25:30,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7163 states. [2024-12-02 06:25:30,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7163 to 7148. [2024-12-02 06:25:30,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7148 states, 7071 states have (on average 1.429783623249894) internal successors, (10110), 7071 states have internal predecessors, (10110), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:25:30,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7148 states to 7148 states and 10260 transitions. [2024-12-02 06:25:30,466 INFO L78 Accepts]: Start accepts. Automaton has 7148 states and 10260 transitions. Word has length 757 [2024-12-02 06:25:30,466 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:30,466 INFO L471 AbstractCegarLoop]: Abstraction has 7148 states and 10260 transitions. [2024-12-02 06:25:30,467 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 115.5) internal successors, (462), 4 states have internal predecessors, (462), 2 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) [2024-12-02 06:25:30,467 INFO L276 IsEmpty]: Start isEmpty. Operand 7148 states and 10260 transitions. [2024-12-02 06:25:30,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 758 [2024-12-02 06:25:30,473 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:30,473 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:30,473 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable57 [2024-12-02 06:25:30,474 INFO L396 AbstractCegarLoop]: === Iteration 59 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:30,474 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:30,474 INFO L85 PathProgramCache]: Analyzing trace with hash 468222921, now seen corresponding path program 1 times [2024-12-02 06:25:30,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:30,474 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178122215] [2024-12-02 06:25:30,474 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:30,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:32,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:34,193 INFO L134 CoverageAnalysis]: Checked inductivity of 855 backedges. 54 proven. 0 refuted. 0 times theorem prover too weak. 801 trivial. 0 not checked. [2024-12-02 06:25:34,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:34,193 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [178122215] [2024-12-02 06:25:34,193 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [178122215] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:34,193 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:34,193 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2024-12-02 06:25:34,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2028240472] [2024-12-02 06:25:34,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:34,194 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 06:25:34,194 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:34,195 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 06:25:34,195 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:25:34,195 INFO L87 Difference]: Start difference. First operand 7148 states and 10260 transitions. Second operand has 10 states, 10 states have (on average 48.0) internal successors, (480), 10 states have internal predecessors, (480), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-12-02 06:25:35,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:35,305 INFO L93 Difference]: Finished difference Result 13152 states and 18886 transitions. [2024-12-02 06:25:35,306 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:25:35,306 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 48.0) internal successors, (480), 10 states have internal predecessors, (480), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 757 [2024-12-02 06:25:35,306 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:35,311 INFO L225 Difference]: With dead ends: 13152 [2024-12-02 06:25:35,311 INFO L226 Difference]: Without dead ends: 7388 [2024-12-02 06:25:35,315 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:25:35,315 INFO L435 NwaCegarLoop]: 797 mSDtfsCounter, 1004 mSDsluCounter, 5539 mSDsCounter, 0 mSdLazyCounter, 2392 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1006 SdHoareTripleChecker+Valid, 6336 SdHoareTripleChecker+Invalid, 2395 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 2392 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:35,315 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1006 Valid, 6336 Invalid, 2395 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 2392 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-12-02 06:25:35,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7388 states. [2024-12-02 06:25:35,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7388 to 7328. [2024-12-02 06:25:35,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7328 states, 7251 states have (on average 1.4315266859743483) internal successors, (10380), 7251 states have internal predecessors, (10380), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:25:35,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7328 states to 7328 states and 10530 transitions. [2024-12-02 06:25:35,418 INFO L78 Accepts]: Start accepts. Automaton has 7328 states and 10530 transitions. Word has length 757 [2024-12-02 06:25:35,418 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:35,418 INFO L471 AbstractCegarLoop]: Abstraction has 7328 states and 10530 transitions. [2024-12-02 06:25:35,418 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 48.0) internal successors, (480), 10 states have internal predecessors, (480), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-12-02 06:25:35,418 INFO L276 IsEmpty]: Start isEmpty. Operand 7328 states and 10530 transitions. [2024-12-02 06:25:35,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 760 [2024-12-02 06:25:35,424 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:35,425 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:35,425 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable58 [2024-12-02 06:25:35,425 INFO L396 AbstractCegarLoop]: === Iteration 60 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:35,425 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:35,425 INFO L85 PathProgramCache]: Analyzing trace with hash 1585303213, now seen corresponding path program 1 times [2024-12-02 06:25:35,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:35,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106759417] [2024-12-02 06:25:35,425 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:35,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:37,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:38,369 INFO L134 CoverageAnalysis]: Checked inductivity of 856 backedges. 180 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:25:38,369 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:38,370 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106759417] [2024-12-02 06:25:38,370 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2106759417] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:38,370 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:38,370 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:25:38,370 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1973866798] [2024-12-02 06:25:38,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:38,371 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:25:38,371 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:38,371 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:25:38,372 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:25:38,372 INFO L87 Difference]: Start difference. First operand 7328 states and 10530 transitions. Second operand has 6 states, 6 states have (on average 100.0) internal successors, (600), 6 states have internal predecessors, (600), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:39,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:39,164 INFO L93 Difference]: Finished difference Result 13868 states and 19941 transitions. [2024-12-02 06:25:39,165 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:25:39,165 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 100.0) internal successors, (600), 6 states have internal predecessors, (600), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 759 [2024-12-02 06:25:39,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:39,173 INFO L225 Difference]: With dead ends: 13868 [2024-12-02 06:25:39,173 INFO L226 Difference]: Without dead ends: 11042 [2024-12-02 06:25:39,176 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:25:39,177 INFO L435 NwaCegarLoop]: 801 mSDtfsCounter, 1399 mSDsluCounter, 2373 mSDsCounter, 0 mSdLazyCounter, 1182 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1399 SdHoareTripleChecker+Valid, 3174 SdHoareTripleChecker+Invalid, 1183 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1182 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:39,177 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1399 Valid, 3174 Invalid, 1183 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1182 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-12-02 06:25:39,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11042 states. [2024-12-02 06:25:39,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11042 to 8154. [2024-12-02 06:25:39,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8154 states, 8077 states have (on average 1.4366720316949362) internal successors, (11604), 8077 states have internal predecessors, (11604), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:25:39,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8154 states to 8154 states and 11754 transitions. [2024-12-02 06:25:39,294 INFO L78 Accepts]: Start accepts. Automaton has 8154 states and 11754 transitions. Word has length 759 [2024-12-02 06:25:39,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:39,294 INFO L471 AbstractCegarLoop]: Abstraction has 8154 states and 11754 transitions. [2024-12-02 06:25:39,294 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 100.0) internal successors, (600), 6 states have internal predecessors, (600), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:39,294 INFO L276 IsEmpty]: Start isEmpty. Operand 8154 states and 11754 transitions. [2024-12-02 06:25:39,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 760 [2024-12-02 06:25:39,301 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:39,301 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:39,302 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable59 [2024-12-02 06:25:39,302 INFO L396 AbstractCegarLoop]: === Iteration 61 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:39,302 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:39,302 INFO L85 PathProgramCache]: Analyzing trace with hash -1229758547, now seen corresponding path program 1 times [2024-12-02 06:25:39,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:39,302 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494536619] [2024-12-02 06:25:39,302 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:39,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:41,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:42,281 INFO L134 CoverageAnalysis]: Checked inductivity of 858 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 775 trivial. 0 not checked. [2024-12-02 06:25:42,281 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:42,281 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [494536619] [2024-12-02 06:25:42,281 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [494536619] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:42,281 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:42,281 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:25:42,281 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2045267095] [2024-12-02 06:25:42,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:42,282 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:25:42,282 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:42,282 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:25:42,282 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:25:42,282 INFO L87 Difference]: Start difference. First operand 8154 states and 11754 transitions. Second operand has 7 states, 7 states have (on average 72.14285714285714) internal successors, (505), 7 states have internal predecessors, (505), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:25:42,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:42,711 INFO L93 Difference]: Finished difference Result 16571 states and 23868 transitions. [2024-12-02 06:25:42,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:25:42,711 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 72.14285714285714) internal successors, (505), 7 states have internal predecessors, (505), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 759 [2024-12-02 06:25:42,711 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:42,718 INFO L225 Difference]: With dead ends: 16571 [2024-12-02 06:25:42,718 INFO L226 Difference]: Without dead ends: 8214 [2024-12-02 06:25:42,726 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:25:42,726 INFO L435 NwaCegarLoop]: 1386 mSDtfsCounter, 1375 mSDsluCounter, 4953 mSDsCounter, 0 mSdLazyCounter, 423 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1376 SdHoareTripleChecker+Valid, 6339 SdHoareTripleChecker+Invalid, 435 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 423 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:42,727 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1376 Valid, 6339 Invalid, 435 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 423 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-12-02 06:25:42,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8214 states. [2024-12-02 06:25:42,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8214 to 8184. [2024-12-02 06:25:42,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8184 states, 8107 states have (on average 1.4332058714691007) internal successors, (11619), 8107 states have internal predecessors, (11619), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:25:42,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8184 states to 8184 states and 11769 transitions. [2024-12-02 06:25:42,850 INFO L78 Accepts]: Start accepts. Automaton has 8184 states and 11769 transitions. Word has length 759 [2024-12-02 06:25:42,850 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:42,850 INFO L471 AbstractCegarLoop]: Abstraction has 8184 states and 11769 transitions. [2024-12-02 06:25:42,850 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 72.14285714285714) internal successors, (505), 7 states have internal predecessors, (505), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:25:42,850 INFO L276 IsEmpty]: Start isEmpty. Operand 8184 states and 11769 transitions. [2024-12-02 06:25:42,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 762 [2024-12-02 06:25:42,858 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:42,858 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:42,858 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable60 [2024-12-02 06:25:42,858 INFO L396 AbstractCegarLoop]: === Iteration 62 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:42,859 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:42,859 INFO L85 PathProgramCache]: Analyzing trace with hash -1990308317, now seen corresponding path program 1 times [2024-12-02 06:25:42,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:42,859 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563583210] [2024-12-02 06:25:42,859 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:42,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:45,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:46,439 INFO L134 CoverageAnalysis]: Checked inductivity of 859 backedges. 183 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:25:46,439 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:46,439 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1563583210] [2024-12-02 06:25:46,439 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1563583210] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:46,439 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:46,439 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:25:46,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1623539095] [2024-12-02 06:25:46,439 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:46,440 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:25:46,440 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:46,441 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:25:46,441 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:25:46,441 INFO L87 Difference]: Start difference. First operand 8184 states and 11769 transitions. Second operand has 8 states, 8 states have (on average 75.25) internal successors, (602), 8 states have internal predecessors, (602), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:25:47,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:47,108 INFO L93 Difference]: Finished difference Result 16894 states and 24308 transitions. [2024-12-02 06:25:47,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:25:47,108 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 75.25) internal successors, (602), 8 states have internal predecessors, (602), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 761 [2024-12-02 06:25:47,108 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:47,119 INFO L225 Difference]: With dead ends: 16894 [2024-12-02 06:25:47,119 INFO L226 Difference]: Without dead ends: 9988 [2024-12-02 06:25:47,126 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:25:47,127 INFO L435 NwaCegarLoop]: 1036 mSDtfsCounter, 1501 mSDsluCounter, 4649 mSDsCounter, 0 mSdLazyCounter, 933 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1502 SdHoareTripleChecker+Valid, 5685 SdHoareTripleChecker+Invalid, 933 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 933 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:47,127 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1502 Valid, 5685 Invalid, 933 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 933 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-12-02 06:25:47,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9988 states. [2024-12-02 06:25:47,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9988 to 8836. [2024-12-02 06:25:47,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8836 states, 8753 states have (on average 1.4327659088312579) internal successors, (12541), 8753 states have internal predecessors, (12541), 81 states have call successors, (81), 1 states have call predecessors, (81), 1 states have return successors, (81), 81 states have call predecessors, (81), 81 states have call successors, (81) [2024-12-02 06:25:47,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8836 states to 8836 states and 12703 transitions. [2024-12-02 06:25:47,269 INFO L78 Accepts]: Start accepts. Automaton has 8836 states and 12703 transitions. Word has length 761 [2024-12-02 06:25:47,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:47,269 INFO L471 AbstractCegarLoop]: Abstraction has 8836 states and 12703 transitions. [2024-12-02 06:25:47,269 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 75.25) internal successors, (602), 8 states have internal predecessors, (602), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:25:47,269 INFO L276 IsEmpty]: Start isEmpty. Operand 8836 states and 12703 transitions. [2024-12-02 06:25:47,277 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 763 [2024-12-02 06:25:47,278 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:47,278 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:47,278 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable61 [2024-12-02 06:25:47,278 INFO L396 AbstractCegarLoop]: === Iteration 63 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:47,279 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:47,279 INFO L85 PathProgramCache]: Analyzing trace with hash 608454249, now seen corresponding path program 1 times [2024-12-02 06:25:47,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:47,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236854405] [2024-12-02 06:25:47,279 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:47,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:49,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:50,723 INFO L134 CoverageAnalysis]: Checked inductivity of 859 backedges. 183 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:25:50,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:50,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236854405] [2024-12-02 06:25:50,723 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [236854405] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:50,723 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:50,723 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:25:50,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [215742014] [2024-12-02 06:25:50,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:50,724 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:25:50,724 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:50,725 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:25:50,725 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:25:50,725 INFO L87 Difference]: Start difference. First operand 8836 states and 12703 transitions. Second operand has 6 states, 6 states have (on average 100.5) internal successors, (603), 6 states have internal predecessors, (603), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:50,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:50,893 INFO L93 Difference]: Finished difference Result 16584 states and 23872 transitions. [2024-12-02 06:25:50,893 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:25:50,893 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 100.5) internal successors, (603), 6 states have internal predecessors, (603), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 762 [2024-12-02 06:25:50,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:50,901 INFO L225 Difference]: With dead ends: 16584 [2024-12-02 06:25:50,901 INFO L226 Difference]: Without dead ends: 12221 [2024-12-02 06:25:50,905 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:25:50,905 INFO L435 NwaCegarLoop]: 1081 mSDtfsCounter, 301 mSDsluCounter, 4312 mSDsCounter, 0 mSdLazyCounter, 55 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 301 SdHoareTripleChecker+Valid, 5393 SdHoareTripleChecker+Invalid, 55 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 55 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:50,905 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [301 Valid, 5393 Invalid, 55 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 55 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:25:50,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12221 states. [2024-12-02 06:25:51,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12221 to 11906. [2024-12-02 06:25:51,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11906 states, 11823 states have (on average 1.43914404127548) internal successors, (17015), 11823 states have internal predecessors, (17015), 81 states have call successors, (81), 1 states have call predecessors, (81), 1 states have return successors, (81), 81 states have call predecessors, (81), 81 states have call successors, (81) [2024-12-02 06:25:51,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11906 states to 11906 states and 17177 transitions. [2024-12-02 06:25:51,060 INFO L78 Accepts]: Start accepts. Automaton has 11906 states and 17177 transitions. Word has length 762 [2024-12-02 06:25:51,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:51,060 INFO L471 AbstractCegarLoop]: Abstraction has 11906 states and 17177 transitions. [2024-12-02 06:25:51,060 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 100.5) internal successors, (603), 6 states have internal predecessors, (603), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:51,060 INFO L276 IsEmpty]: Start isEmpty. Operand 11906 states and 17177 transitions. [2024-12-02 06:25:51,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 764 [2024-12-02 06:25:51,070 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:51,071 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:51,071 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable62 [2024-12-02 06:25:51,071 INFO L396 AbstractCegarLoop]: === Iteration 64 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:51,071 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:51,072 INFO L85 PathProgramCache]: Analyzing trace with hash 1582868379, now seen corresponding path program 1 times [2024-12-02 06:25:51,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:51,072 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [13213294] [2024-12-02 06:25:51,072 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:51,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:53,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:54,498 INFO L134 CoverageAnalysis]: Checked inductivity of 857 backedges. 181 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:25:54,499 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:54,499 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [13213294] [2024-12-02 06:25:54,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [13213294] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:54,499 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:25:54,499 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:25:54,499 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1437850337] [2024-12-02 06:25:54,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:54,500 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:25:54,500 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:54,500 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:25:54,501 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:25:54,501 INFO L87 Difference]: Start difference. First operand 11906 states and 17177 transitions. Second operand has 8 states, 8 states have (on average 75.5) internal successors, (604), 8 states have internal predecessors, (604), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:54,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:54,705 INFO L93 Difference]: Finished difference Result 20316 states and 29283 transitions. [2024-12-02 06:25:54,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:25:54,705 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 75.5) internal successors, (604), 8 states have internal predecessors, (604), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 763 [2024-12-02 06:25:54,706 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:54,715 INFO L225 Difference]: With dead ends: 20316 [2024-12-02 06:25:54,715 INFO L226 Difference]: Without dead ends: 14059 [2024-12-02 06:25:54,720 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:25:54,721 INFO L435 NwaCegarLoop]: 1481 mSDtfsCounter, 767 mSDsluCounter, 6279 mSDsCounter, 0 mSdLazyCounter, 95 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 767 SdHoareTripleChecker+Valid, 7760 SdHoareTripleChecker+Invalid, 96 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 95 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:54,721 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [767 Valid, 7760 Invalid, 96 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 95 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:25:54,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14059 states. [2024-12-02 06:25:54,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14059 to 13254. [2024-12-02 06:25:54,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13254 states, 13171 states have (on average 1.4418798876319185) internal successors, (18991), 13171 states have internal predecessors, (18991), 81 states have call successors, (81), 1 states have call predecessors, (81), 1 states have return successors, (81), 81 states have call predecessors, (81), 81 states have call successors, (81) [2024-12-02 06:25:54,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13254 states to 13254 states and 19153 transitions. [2024-12-02 06:25:54,881 INFO L78 Accepts]: Start accepts. Automaton has 13254 states and 19153 transitions. Word has length 763 [2024-12-02 06:25:54,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:54,882 INFO L471 AbstractCegarLoop]: Abstraction has 13254 states and 19153 transitions. [2024-12-02 06:25:54,882 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 75.5) internal successors, (604), 8 states have internal predecessors, (604), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:54,882 INFO L276 IsEmpty]: Start isEmpty. Operand 13254 states and 19153 transitions. [2024-12-02 06:25:54,891 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 764 [2024-12-02 06:25:54,891 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:54,892 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:54,892 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable63 [2024-12-02 06:25:54,892 INFO L396 AbstractCegarLoop]: === Iteration 65 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:54,892 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:54,892 INFO L85 PathProgramCache]: Analyzing trace with hash 884510119, now seen corresponding path program 1 times [2024-12-02 06:25:54,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:54,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020963481] [2024-12-02 06:25:54,892 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:54,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:57,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:58,421 INFO L134 CoverageAnalysis]: Checked inductivity of 859 backedges. 179 proven. 4 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:25:58,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:58,421 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1020963481] [2024-12-02 06:25:58,421 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1020963481] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:25:58,421 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [637953127] [2024-12-02 06:25:58,421 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:58,421 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:25:58,421 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:25:58,423 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:25:58,424 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2024-12-02 06:26:00,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:00,869 INFO L256 TraceCheckSpWp]: Trace formula consists of 3666 conjuncts, 47 conjuncts are in the unsatisfiable core [2024-12-02 06:26:00,877 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:26:02,104 INFO L134 CoverageAnalysis]: Checked inductivity of 859 backedges. 195 proven. 1 refuted. 0 times theorem prover too weak. 663 trivial. 0 not checked. [2024-12-02 06:26:02,104 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:26:04,040 INFO L134 CoverageAnalysis]: Checked inductivity of 859 backedges. 183 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:26:04,040 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [637953127] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:26:04,041 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:26:04,041 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [8, 7] total 21 [2024-12-02 06:26:04,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550322434] [2024-12-02 06:26:04,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:26:04,042 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 06:26:04,042 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:26:04,043 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 06:26:04,043 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=350, Unknown=0, NotChecked=0, Total=420 [2024-12-02 06:26:04,043 INFO L87 Difference]: Start difference. First operand 13254 states and 19153 transitions. Second operand has 10 states, 10 states have (on average 60.4) internal successors, (604), 10 states have internal predecessors, (604), 4 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) [2024-12-02 06:26:05,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:26:05,340 INFO L93 Difference]: Finished difference Result 25178 states and 36369 transitions. [2024-12-02 06:26:05,340 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:26:05,340 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 60.4) internal successors, (604), 10 states have internal predecessors, (604), 4 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) Word has length 763 [2024-12-02 06:26:05,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:26:05,349 INFO L225 Difference]: With dead ends: 25178 [2024-12-02 06:26:05,349 INFO L226 Difference]: Without dead ends: 13284 [2024-12-02 06:26:05,356 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1538 GetRequests, 1516 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 93 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=94, Invalid=458, Unknown=0, NotChecked=0, Total=552 [2024-12-02 06:26:05,357 INFO L435 NwaCegarLoop]: 798 mSDtfsCounter, 731 mSDsluCounter, 5492 mSDsCounter, 0 mSdLazyCounter, 2425 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 732 SdHoareTripleChecker+Valid, 6290 SdHoareTripleChecker+Invalid, 2429 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 2425 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:26:05,357 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [732 Valid, 6290 Invalid, 2429 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 2425 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-12-02 06:26:05,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13284 states. [2024-12-02 06:26:05,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13284 to 13104. [2024-12-02 06:26:05,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13104 states, 13021 states have (on average 1.4389063819983103) internal successors, (18736), 13021 states have internal predecessors, (18736), 81 states have call successors, (81), 1 states have call predecessors, (81), 1 states have return successors, (81), 81 states have call predecessors, (81), 81 states have call successors, (81) [2024-12-02 06:26:05,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13104 states to 13104 states and 18898 transitions. [2024-12-02 06:26:05,566 INFO L78 Accepts]: Start accepts. Automaton has 13104 states and 18898 transitions. Word has length 763 [2024-12-02 06:26:05,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:26:05,566 INFO L471 AbstractCegarLoop]: Abstraction has 13104 states and 18898 transitions. [2024-12-02 06:26:05,566 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 60.4) internal successors, (604), 10 states have internal predecessors, (604), 4 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) [2024-12-02 06:26:05,566 INFO L276 IsEmpty]: Start isEmpty. Operand 13104 states and 18898 transitions. [2024-12-02 06:26:05,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 764 [2024-12-02 06:26:05,575 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:26:05,576 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:26:05,595 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Forceful destruction successful, exit code 0 [2024-12-02 06:26:05,776 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable64,31 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:26:05,776 INFO L396 AbstractCegarLoop]: === Iteration 66 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:26:05,776 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:26:05,777 INFO L85 PathProgramCache]: Analyzing trace with hash 1446971431, now seen corresponding path program 1 times [2024-12-02 06:26:05,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:26:05,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1066165092] [2024-12-02 06:26:05,777 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:05,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:26:07,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:09,491 INFO L134 CoverageAnalysis]: Checked inductivity of 859 backedges. 52 proven. 0 refuted. 0 times theorem prover too weak. 807 trivial. 0 not checked. [2024-12-02 06:26:09,491 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:26:09,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1066165092] [2024-12-02 06:26:09,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1066165092] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:26:09,491 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:26:09,491 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:26:09,491 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1442881379] [2024-12-02 06:26:09,491 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:26:09,492 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:26:09,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:26:09,493 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:26:09,493 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:26:09,493 INFO L87 Difference]: Start difference. First operand 13104 states and 18898 transitions. Second operand has 8 states, 8 states have (on average 60.0) internal successors, (480), 8 states have internal predecessors, (480), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-12-02 06:26:09,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:26:09,781 INFO L93 Difference]: Finished difference Result 25022 states and 36093 transitions. [2024-12-02 06:26:09,781 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:26:09,781 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 60.0) internal successors, (480), 8 states have internal predecessors, (480), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 763 [2024-12-02 06:26:09,781 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:26:09,792 INFO L225 Difference]: With dead ends: 25022 [2024-12-02 06:26:09,792 INFO L226 Difference]: Without dead ends: 13284 [2024-12-02 06:26:09,797 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:26:09,798 INFO L435 NwaCegarLoop]: 1068 mSDtfsCounter, 998 mSDsluCounter, 5290 mSDsCounter, 0 mSdLazyCounter, 151 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1000 SdHoareTripleChecker+Valid, 6358 SdHoareTripleChecker+Invalid, 152 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 151 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:26:09,798 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1000 Valid, 6358 Invalid, 152 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 151 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:26:09,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13284 states. [2024-12-02 06:26:09,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13284 to 13239. [2024-12-02 06:26:09,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13239 states, 13156 states have (on average 1.4389632107023411) internal successors, (18931), 13156 states have internal predecessors, (18931), 81 states have call successors, (81), 1 states have call predecessors, (81), 1 states have return successors, (81), 81 states have call predecessors, (81), 81 states have call successors, (81) [2024-12-02 06:26:09,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13239 states to 13239 states and 19093 transitions. [2024-12-02 06:26:09,972 INFO L78 Accepts]: Start accepts. Automaton has 13239 states and 19093 transitions. Word has length 763 [2024-12-02 06:26:09,972 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:26:09,972 INFO L471 AbstractCegarLoop]: Abstraction has 13239 states and 19093 transitions. [2024-12-02 06:26:09,972 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 60.0) internal successors, (480), 8 states have internal predecessors, (480), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-12-02 06:26:09,972 INFO L276 IsEmpty]: Start isEmpty. Operand 13239 states and 19093 transitions. [2024-12-02 06:26:09,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 766 [2024-12-02 06:26:09,982 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:26:09,982 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:26:09,982 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable65 [2024-12-02 06:26:09,982 INFO L396 AbstractCegarLoop]: === Iteration 67 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:26:09,983 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:26:09,983 INFO L85 PathProgramCache]: Analyzing trace with hash -1533878163, now seen corresponding path program 1 times [2024-12-02 06:26:09,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:26:09,983 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412887232] [2024-12-02 06:26:09,983 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:09,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:26:12,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:13,998 INFO L134 CoverageAnalysis]: Checked inductivity of 860 backedges. 184 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:26:13,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:26:13,998 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412887232] [2024-12-02 06:26:13,998 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412887232] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:26:13,998 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:26:13,998 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:26:13,998 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1586358519] [2024-12-02 06:26:13,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:26:13,999 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:26:13,999 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:26:13,999 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:26:14,000 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:26:14,000 INFO L87 Difference]: Start difference. First operand 13239 states and 19093 transitions. Second operand has 7 states, 7 states have (on average 86.57142857142857) internal successors, (606), 7 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:26:15,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:26:15,131 INFO L93 Difference]: Finished difference Result 22965 states and 33040 transitions. [2024-12-02 06:26:15,131 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:26:15,131 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 86.57142857142857) internal successors, (606), 7 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 765 [2024-12-02 06:26:15,132 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:26:15,142 INFO L225 Difference]: With dead ends: 22965 [2024-12-02 06:26:15,142 INFO L226 Difference]: Without dead ends: 15954 [2024-12-02 06:26:15,148 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:26:15,148 INFO L435 NwaCegarLoop]: 1350 mSDtfsCounter, 1637 mSDsluCounter, 4100 mSDsCounter, 0 mSdLazyCounter, 1913 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1642 SdHoareTripleChecker+Valid, 5450 SdHoareTripleChecker+Invalid, 1914 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1913 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-12-02 06:26:15,149 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1642 Valid, 5450 Invalid, 1914 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1913 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-12-02 06:26:15,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15954 states. [2024-12-02 06:26:15,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15954 to 15424. [2024-12-02 06:26:15,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15424 states, 15341 states have (on average 1.4403885014014732) internal successors, (22097), 15341 states have internal predecessors, (22097), 81 states have call successors, (81), 1 states have call predecessors, (81), 1 states have return successors, (81), 81 states have call predecessors, (81), 81 states have call successors, (81) [2024-12-02 06:26:15,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15424 states to 15424 states and 22259 transitions. [2024-12-02 06:26:15,381 INFO L78 Accepts]: Start accepts. Automaton has 15424 states and 22259 transitions. Word has length 765 [2024-12-02 06:26:15,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:26:15,381 INFO L471 AbstractCegarLoop]: Abstraction has 15424 states and 22259 transitions. [2024-12-02 06:26:15,381 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 86.57142857142857) internal successors, (606), 7 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:26:15,381 INFO L276 IsEmpty]: Start isEmpty. Operand 15424 states and 22259 transitions. [2024-12-02 06:26:15,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 767 [2024-12-02 06:26:15,392 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:26:15,392 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:26:15,392 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable66 [2024-12-02 06:26:15,393 INFO L396 AbstractCegarLoop]: === Iteration 68 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:26:15,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:26:15,393 INFO L85 PathProgramCache]: Analyzing trace with hash -467547661, now seen corresponding path program 1 times [2024-12-02 06:26:15,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:26:15,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887680051] [2024-12-02 06:26:15,393 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:15,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:26:15,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:16,452 INFO L134 CoverageAnalysis]: Checked inductivity of 858 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:26:16,452 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:26:16,452 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1887680051] [2024-12-02 06:26:16,452 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1887680051] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:26:16,452 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:26:16,452 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:26:16,452 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467515887] [2024-12-02 06:26:16,452 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:26:16,453 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:26:16,453 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:26:16,454 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:26:16,454 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:26:16,454 INFO L87 Difference]: Start difference. First operand 15424 states and 22259 transitions. Second operand has 6 states, 6 states have (on average 101.16666666666667) internal successors, (607), 6 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:26:17,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:26:17,093 INFO L93 Difference]: Finished difference Result 22467 states and 32350 transitions. [2024-12-02 06:26:17,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:26:17,093 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 101.16666666666667) internal successors, (607), 6 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 766 [2024-12-02 06:26:17,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:26:17,104 INFO L225 Difference]: With dead ends: 22467 [2024-12-02 06:26:17,104 INFO L226 Difference]: Without dead ends: 15456 [2024-12-02 06:26:17,110 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:26:17,110 INFO L435 NwaCegarLoop]: 803 mSDtfsCounter, 789 mSDsluCounter, 2365 mSDsCounter, 0 mSdLazyCounter, 1163 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 789 SdHoareTripleChecker+Valid, 3168 SdHoareTripleChecker+Invalid, 1164 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1163 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:26:17,110 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [789 Valid, 3168 Invalid, 1164 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1163 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-12-02 06:26:17,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15456 states. [2024-12-02 06:26:17,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15456 to 15440. [2024-12-02 06:26:17,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15440 states, 15357 states have (on average 1.4399296737644072) internal successors, (22113), 15357 states have internal predecessors, (22113), 81 states have call successors, (81), 1 states have call predecessors, (81), 1 states have return successors, (81), 81 states have call predecessors, (81), 81 states have call successors, (81) [2024-12-02 06:26:17,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15440 states to 15440 states and 22275 transitions. [2024-12-02 06:26:17,345 INFO L78 Accepts]: Start accepts. Automaton has 15440 states and 22275 transitions. Word has length 766 [2024-12-02 06:26:17,345 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:26:17,345 INFO L471 AbstractCegarLoop]: Abstraction has 15440 states and 22275 transitions. [2024-12-02 06:26:17,345 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 101.16666666666667) internal successors, (607), 6 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:26:17,345 INFO L276 IsEmpty]: Start isEmpty. Operand 15440 states and 22275 transitions. [2024-12-02 06:26:17,356 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 767 [2024-12-02 06:26:17,356 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:26:17,356 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:26:17,356 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable67 [2024-12-02 06:26:17,356 INFO L396 AbstractCegarLoop]: === Iteration 69 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:26:17,357 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:26:17,357 INFO L85 PathProgramCache]: Analyzing trace with hash 1743827111, now seen corresponding path program 1 times [2024-12-02 06:26:17,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:26:17,357 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [802650030] [2024-12-02 06:26:17,357 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:17,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:26:20,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:21,240 INFO L134 CoverageAnalysis]: Checked inductivity of 858 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:26:21,241 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:26:21,241 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [802650030] [2024-12-02 06:26:21,241 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [802650030] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:26:21,241 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:26:21,241 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:26:21,241 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2123997341] [2024-12-02 06:26:21,241 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:26:21,242 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:26:21,242 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:26:21,243 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:26:21,243 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:26:21,243 INFO L87 Difference]: Start difference. First operand 15440 states and 22275 transitions. Second operand has 8 states, 8 states have (on average 75.875) internal successors, (607), 8 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:26:22,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:26:22,551 INFO L93 Difference]: Finished difference Result 24232 states and 34844 transitions. [2024-12-02 06:26:22,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:26:22,552 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 75.875) internal successors, (607), 8 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 766 [2024-12-02 06:26:22,552 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:26:22,563 INFO L225 Difference]: With dead ends: 24232 [2024-12-02 06:26:22,564 INFO L226 Difference]: Without dead ends: 17181 [2024-12-02 06:26:22,570 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:26:22,570 INFO L435 NwaCegarLoop]: 1012 mSDtfsCounter, 1970 mSDsluCounter, 4756 mSDsCounter, 0 mSdLazyCounter, 2337 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1975 SdHoareTripleChecker+Valid, 5768 SdHoareTripleChecker+Invalid, 2339 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 2337 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:26:22,570 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1975 Valid, 5768 Invalid, 2339 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 2337 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-12-02 06:26:22,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17181 states. [2024-12-02 06:26:22,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17181 to 16691. [2024-12-02 06:26:22,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16691 states, 16608 states have (on average 1.4398482658959537) internal successors, (23913), 16608 states have internal predecessors, (23913), 81 states have call successors, (81), 1 states have call predecessors, (81), 1 states have return successors, (81), 81 states have call predecessors, (81), 81 states have call successors, (81) [2024-12-02 06:26:22,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16691 states to 16691 states and 24075 transitions. [2024-12-02 06:26:22,790 INFO L78 Accepts]: Start accepts. Automaton has 16691 states and 24075 transitions. Word has length 766 [2024-12-02 06:26:22,790 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:26:22,790 INFO L471 AbstractCegarLoop]: Abstraction has 16691 states and 24075 transitions. [2024-12-02 06:26:22,790 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 75.875) internal successors, (607), 8 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:26:22,790 INFO L276 IsEmpty]: Start isEmpty. Operand 16691 states and 24075 transitions. [2024-12-02 06:26:22,801 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 767 [2024-12-02 06:26:22,802 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:26:22,802 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:26:22,802 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable68 [2024-12-02 06:26:22,802 INFO L396 AbstractCegarLoop]: === Iteration 70 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:26:22,802 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:26:22,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1071350101, now seen corresponding path program 1 times [2024-12-02 06:26:22,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:26:22,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1300881326] [2024-12-02 06:26:22,803 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:22,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:26:25,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:26,356 INFO L134 CoverageAnalysis]: Checked inductivity of 858 backedges. 56 proven. 0 refuted. 0 times theorem prover too weak. 802 trivial. 0 not checked. [2024-12-02 06:26:26,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:26:26,356 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1300881326] [2024-12-02 06:26:26,356 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1300881326] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:26:26,356 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:26:26,356 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:26:26,356 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [670463064] [2024-12-02 06:26:26,356 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:26:26,357 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:26:26,357 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:26:26,357 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:26:26,357 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:26:26,357 INFO L87 Difference]: Start difference. First operand 16691 states and 24075 transitions. Second operand has 6 states, 6 states have (on average 81.5) internal successors, (489), 6 states have internal predecessors, (489), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-12-02 06:26:27,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:26:27,159 INFO L93 Difference]: Finished difference Result 31929 states and 46075 transitions. [2024-12-02 06:26:27,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:26:27,160 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 81.5) internal successors, (489), 6 states have internal predecessors, (489), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 766 [2024-12-02 06:26:27,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:26:27,171 INFO L225 Difference]: With dead ends: 31929 [2024-12-02 06:26:27,171 INFO L226 Difference]: Without dead ends: 16721 [2024-12-02 06:26:27,180 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:26:27,180 INFO L435 NwaCegarLoop]: 791 mSDtfsCounter, 978 mSDsluCounter, 2362 mSDsCounter, 0 mSdLazyCounter, 1204 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 980 SdHoareTripleChecker+Valid, 3153 SdHoareTripleChecker+Invalid, 1204 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1204 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-12-02 06:26:27,181 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [980 Valid, 3153 Invalid, 1204 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1204 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-12-02 06:26:27,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16721 states. [2024-12-02 06:26:27,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16721 to 16706. [2024-12-02 06:26:27,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16706 states, 16623 states have (on average 1.4394513625699332) internal successors, (23928), 16623 states have internal predecessors, (23928), 81 states have call successors, (81), 1 states have call predecessors, (81), 1 states have return successors, (81), 81 states have call predecessors, (81), 81 states have call successors, (81) [2024-12-02 06:26:27,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16706 states to 16706 states and 24090 transitions. [2024-12-02 06:26:27,411 INFO L78 Accepts]: Start accepts. Automaton has 16706 states and 24090 transitions. Word has length 766 [2024-12-02 06:26:27,411 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:26:27,411 INFO L471 AbstractCegarLoop]: Abstraction has 16706 states and 24090 transitions. [2024-12-02 06:26:27,411 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 81.5) internal successors, (489), 6 states have internal predecessors, (489), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-12-02 06:26:27,411 INFO L276 IsEmpty]: Start isEmpty. Operand 16706 states and 24090 transitions. [2024-12-02 06:26:27,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 767 [2024-12-02 06:26:27,423 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:26:27,424 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:26:27,424 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable69 [2024-12-02 06:26:27,424 INFO L396 AbstractCegarLoop]: === Iteration 71 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:26:27,424 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:26:27,424 INFO L85 PathProgramCache]: Analyzing trace with hash 1017546741, now seen corresponding path program 1 times [2024-12-02 06:26:27,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:26:27,424 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982316941] [2024-12-02 06:26:27,424 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:27,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:26:30,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:31,323 INFO L134 CoverageAnalysis]: Checked inductivity of 858 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:26:31,323 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:26:31,323 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982316941] [2024-12-02 06:26:31,323 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [982316941] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:26:31,323 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:26:31,324 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:26:31,324 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100248432] [2024-12-02 06:26:31,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:26:31,324 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:26:31,324 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:26:31,325 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:26:31,325 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:26:31,325 INFO L87 Difference]: Start difference. First operand 16706 states and 24090 transitions. Second operand has 6 states, 6 states have (on average 101.16666666666667) internal successors, (607), 6 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:26:32,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:26:32,292 INFO L93 Difference]: Finished difference Result 27371 states and 39329 transitions. [2024-12-02 06:26:32,292 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:26:32,293 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 101.16666666666667) internal successors, (607), 6 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 766 [2024-12-02 06:26:32,293 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:26:32,305 INFO L225 Difference]: With dead ends: 27371 [2024-12-02 06:26:32,305 INFO L226 Difference]: Without dead ends: 20066 [2024-12-02 06:26:32,311 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:26:32,311 INFO L435 NwaCegarLoop]: 945 mSDtfsCounter, 1379 mSDsluCounter, 2651 mSDsCounter, 0 mSdLazyCounter, 1359 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1379 SdHoareTripleChecker+Valid, 3596 SdHoareTripleChecker+Invalid, 1359 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1359 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-12-02 06:26:32,311 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1379 Valid, 3596 Invalid, 1359 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1359 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-12-02 06:26:32,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20066 states. [2024-12-02 06:26:32,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20066 to 18675. [2024-12-02 06:26:32,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18675 states, 18592 states have (on average 1.4409423407917383) internal successors, (26790), 18592 states have internal predecessors, (26790), 81 states have call successors, (81), 1 states have call predecessors, (81), 1 states have return successors, (81), 81 states have call predecessors, (81), 81 states have call successors, (81) [2024-12-02 06:26:32,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18675 states to 18675 states and 26952 transitions. [2024-12-02 06:26:32,575 INFO L78 Accepts]: Start accepts. Automaton has 18675 states and 26952 transitions. Word has length 766 [2024-12-02 06:26:32,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:26:32,576 INFO L471 AbstractCegarLoop]: Abstraction has 18675 states and 26952 transitions. [2024-12-02 06:26:32,576 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 101.16666666666667) internal successors, (607), 6 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:26:32,576 INFO L276 IsEmpty]: Start isEmpty. Operand 18675 states and 26952 transitions. [2024-12-02 06:26:32,588 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 767 [2024-12-02 06:26:32,588 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:26:32,589 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:26:32,589 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable70 [2024-12-02 06:26:32,589 INFO L396 AbstractCegarLoop]: === Iteration 72 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:26:32,589 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:26:32,589 INFO L85 PathProgramCache]: Analyzing trace with hash -831172389, now seen corresponding path program 1 times [2024-12-02 06:26:32,590 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:26:32,590 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514562449] [2024-12-02 06:26:32,590 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:32,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:26:33,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:34,496 INFO L134 CoverageAnalysis]: Checked inductivity of 859 backedges. 183 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:26:34,496 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:26:34,496 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514562449] [2024-12-02 06:26:34,496 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514562449] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:26:34,496 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:26:34,496 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:26:34,496 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [43313554] [2024-12-02 06:26:34,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:26:34,497 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:26:34,497 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:26:34,497 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:26:34,497 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:26:34,498 INFO L87 Difference]: Start difference. First operand 18675 states and 26952 transitions. Second operand has 8 states, 8 states have (on average 75.875) internal successors, (607), 8 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:26:34,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:26:34,819 INFO L93 Difference]: Finished difference Result 32972 states and 47529 transitions. [2024-12-02 06:26:34,820 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:26:34,820 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 75.875) internal successors, (607), 8 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 766 [2024-12-02 06:26:34,820 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:26:34,837 INFO L225 Difference]: With dead ends: 32972 [2024-12-02 06:26:34,837 INFO L226 Difference]: Without dead ends: 25935 [2024-12-02 06:26:34,845 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:26:34,846 INFO L435 NwaCegarLoop]: 1724 mSDtfsCounter, 464 mSDsluCounter, 6863 mSDsCounter, 0 mSdLazyCounter, 94 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 464 SdHoareTripleChecker+Valid, 8587 SdHoareTripleChecker+Invalid, 94 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 94 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:26:34,846 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [464 Valid, 8587 Invalid, 94 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 94 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:26:34,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25935 states. [2024-12-02 06:26:35,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25935 to 25170. [2024-12-02 06:26:35,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25170 states, 25087 states have (on average 1.4432973253079284) internal successors, (36208), 25087 states have internal predecessors, (36208), 81 states have call successors, (81), 1 states have call predecessors, (81), 1 states have return successors, (81), 81 states have call predecessors, (81), 81 states have call successors, (81) [2024-12-02 06:26:35,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25170 states to 25170 states and 36370 transitions. [2024-12-02 06:26:35,184 INFO L78 Accepts]: Start accepts. Automaton has 25170 states and 36370 transitions. Word has length 766 [2024-12-02 06:26:35,185 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:26:35,185 INFO L471 AbstractCegarLoop]: Abstraction has 25170 states and 36370 transitions. [2024-12-02 06:26:35,185 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 75.875) internal successors, (607), 8 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:26:35,185 INFO L276 IsEmpty]: Start isEmpty. Operand 25170 states and 36370 transitions. [2024-12-02 06:26:35,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 767 [2024-12-02 06:26:35,256 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:26:35,256 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:26:35,256 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable71 [2024-12-02 06:26:35,256 INFO L396 AbstractCegarLoop]: === Iteration 73 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:26:35,257 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:26:35,257 INFO L85 PathProgramCache]: Analyzing trace with hash 233395120, now seen corresponding path program 1 times [2024-12-02 06:26:35,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:26:35,257 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925716462] [2024-12-02 06:26:35,257 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:35,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:26:38,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:39,471 INFO L134 CoverageAnalysis]: Checked inductivity of 860 backedges. 180 proven. 4 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:26:39,471 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:26:39,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [925716462] [2024-12-02 06:26:39,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [925716462] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:26:39,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [102155544] [2024-12-02 06:26:39,471 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:39,471 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:26:39,471 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:26:39,473 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:26:39,473 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2024-12-02 06:26:42,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:42,252 INFO L256 TraceCheckSpWp]: Trace formula consists of 3669 conjuncts, 40 conjuncts are in the unsatisfiable core [2024-12-02 06:26:42,259 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:26:42,549 INFO L134 CoverageAnalysis]: Checked inductivity of 860 backedges. 54 proven. 0 refuted. 0 times theorem prover too weak. 806 trivial. 0 not checked. [2024-12-02 06:26:42,550 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:26:42,550 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [102155544] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:26:42,550 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:26:42,550 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 12 [2024-12-02 06:26:42,550 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1475569046] [2024-12-02 06:26:42,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:26:42,550 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:26:42,551 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:26:42,551 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:26:42,551 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:26:42,551 INFO L87 Difference]: Start difference. First operand 25170 states and 36370 transitions. Second operand has 6 states, 6 states have (on average 75.5) internal successors, (453), 6 states have internal predecessors, (453), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:26:43,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:26:43,447 INFO L93 Difference]: Finished difference Result 49790 states and 71970 transitions. [2024-12-02 06:26:43,447 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:26:43,447 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 75.5) internal successors, (453), 6 states have internal predecessors, (453), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 766 [2024-12-02 06:26:43,447 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:26:43,464 INFO L225 Difference]: With dead ends: 49790 [2024-12-02 06:26:43,464 INFO L226 Difference]: Without dead ends: 25230 [2024-12-02 06:26:43,474 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 775 GetRequests, 765 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:26:43,474 INFO L435 NwaCegarLoop]: 790 mSDtfsCounter, 1012 mSDsluCounter, 2332 mSDsCounter, 0 mSdLazyCounter, 1204 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1016 SdHoareTripleChecker+Valid, 3122 SdHoareTripleChecker+Invalid, 1206 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 1204 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-12-02 06:26:43,474 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1016 Valid, 3122 Invalid, 1206 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 1204 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-12-02 06:26:43,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25230 states. [2024-12-02 06:26:43,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25230 to 25215. [2024-12-02 06:26:43,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25215 states, 25132 states have (on average 1.44190673245265) internal successors, (36238), 25132 states have internal predecessors, (36238), 81 states have call successors, (81), 1 states have call predecessors, (81), 1 states have return successors, (81), 81 states have call predecessors, (81), 81 states have call successors, (81) [2024-12-02 06:26:43,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25215 states to 25215 states and 36400 transitions. [2024-12-02 06:26:43,797 INFO L78 Accepts]: Start accepts. Automaton has 25215 states and 36400 transitions. Word has length 766 [2024-12-02 06:26:43,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:26:43,798 INFO L471 AbstractCegarLoop]: Abstraction has 25215 states and 36400 transitions. [2024-12-02 06:26:43,798 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 75.5) internal successors, (453), 6 states have internal predecessors, (453), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:26:43,798 INFO L276 IsEmpty]: Start isEmpty. Operand 25215 states and 36400 transitions. [2024-12-02 06:26:43,816 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 771 [2024-12-02 06:26:43,816 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:26:43,816 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:26:43,836 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Ended with exit code 0 [2024-12-02 06:26:44,016 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable72,32 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:26:44,017 INFO L396 AbstractCegarLoop]: === Iteration 74 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:26:44,017 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:26:44,017 INFO L85 PathProgramCache]: Analyzing trace with hash 477142032, now seen corresponding path program 1 times [2024-12-02 06:26:44,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:26:44,017 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177825216] [2024-12-02 06:26:44,017 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:44,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:26:46,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:47,892 INFO L134 CoverageAnalysis]: Checked inductivity of 862 backedges. 121 proven. 4 refuted. 0 times theorem prover too weak. 737 trivial. 0 not checked. [2024-12-02 06:26:47,892 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:26:47,892 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177825216] [2024-12-02 06:26:47,893 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [177825216] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:26:47,893 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [225963552] [2024-12-02 06:26:47,893 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:47,893 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:26:47,893 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:26:47,894 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:26:47,895 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2024-12-02 06:26:50,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:50,851 INFO L256 TraceCheckSpWp]: Trace formula consists of 3677 conjuncts, 37 conjuncts are in the unsatisfiable core [2024-12-02 06:26:50,858 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:26:52,322 INFO L134 CoverageAnalysis]: Checked inductivity of 862 backedges. 157 proven. 33 refuted. 0 times theorem prover too weak. 672 trivial. 0 not checked. [2024-12-02 06:26:52,322 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:26:53,429 INFO L134 CoverageAnalysis]: Checked inductivity of 862 backedges. 182 proven. 4 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:26:53,429 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [225963552] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:26:53,429 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:26:53,429 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 10, 9] total 20 [2024-12-02 06:26:53,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126947711] [2024-12-02 06:26:53,429 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:26:53,430 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 20 states [2024-12-02 06:26:53,430 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:26:53,430 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2024-12-02 06:26:53,430 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=298, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:26:53,431 INFO L87 Difference]: Start difference. First operand 25215 states and 36400 transitions. Second operand has 20 states, 20 states have (on average 52.75) internal successors, (1055), 20 states have internal predecessors, (1055), 4 states have call successors, (16), 2 states have call predecessors, (16), 2 states have return successors, (16), 4 states have call predecessors, (16), 4 states have call successors, (16) [2024-12-02 06:26:54,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:26:54,769 INFO L93 Difference]: Finished difference Result 25236 states and 36419 transitions. [2024-12-02 06:26:54,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:26:54,769 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 52.75) internal successors, (1055), 20 states have internal predecessors, (1055), 4 states have call successors, (16), 2 states have call predecessors, (16), 2 states have return successors, (16), 4 states have call predecessors, (16), 4 states have call successors, (16) Word has length 770 [2024-12-02 06:26:54,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:26:54,786 INFO L225 Difference]: With dead ends: 25236 [2024-12-02 06:26:54,787 INFO L226 Difference]: Without dead ends: 24593 [2024-12-02 06:26:54,792 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1546 GetRequests, 1527 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 119 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=91, Invalid=329, Unknown=0, NotChecked=0, Total=420 [2024-12-02 06:26:54,792 INFO L435 NwaCegarLoop]: 788 mSDtfsCounter, 1322 mSDsluCounter, 6268 mSDsCounter, 0 mSdLazyCounter, 2737 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1322 SdHoareTripleChecker+Valid, 7056 SdHoareTripleChecker+Invalid, 2739 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 2737 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:26:54,793 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1322 Valid, 7056 Invalid, 2739 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 2737 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-12-02 06:26:54,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24593 states. [2024-12-02 06:26:55,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24593 to 24578. [2024-12-02 06:26:55,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24578 states, 24501 states have (on average 1.4420227745806293) internal successors, (35331), 24501 states have internal predecessors, (35331), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:26:55,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24578 states to 24578 states and 35481 transitions. [2024-12-02 06:26:55,110 INFO L78 Accepts]: Start accepts. Automaton has 24578 states and 35481 transitions. Word has length 770 [2024-12-02 06:26:55,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:26:55,111 INFO L471 AbstractCegarLoop]: Abstraction has 24578 states and 35481 transitions. [2024-12-02 06:26:55,111 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 20 states, 20 states have (on average 52.75) internal successors, (1055), 20 states have internal predecessors, (1055), 4 states have call successors, (16), 2 states have call predecessors, (16), 2 states have return successors, (16), 4 states have call predecessors, (16), 4 states have call successors, (16) [2024-12-02 06:26:55,111 INFO L276 IsEmpty]: Start isEmpty. Operand 24578 states and 35481 transitions. [2024-12-02 06:26:55,126 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 772 [2024-12-02 06:26:55,127 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:26:55,127 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:26:55,147 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Ended with exit code 0 [2024-12-02 06:26:55,327 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable73,33 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:26:55,327 INFO L396 AbstractCegarLoop]: === Iteration 75 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:26:55,327 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:26:55,328 INFO L85 PathProgramCache]: Analyzing trace with hash -1232161812, now seen corresponding path program 1 times [2024-12-02 06:26:55,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:26:55,328 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1578968090] [2024-12-02 06:26:55,328 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:55,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:26:58,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:00,443 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 187 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:27:00,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:27:00,444 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1578968090] [2024-12-02 06:27:00,444 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1578968090] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:27:00,444 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:27:00,444 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:27:00,444 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [352040287] [2024-12-02 06:27:00,444 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:27:00,445 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:27:00,445 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:27:00,445 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:27:00,445 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:27:00,446 INFO L87 Difference]: Start difference. First operand 24578 states and 35481 transitions. Second operand has 7 states, 7 states have (on average 87.42857142857143) internal successors, (612), 7 states have internal predecessors, (612), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:27:00,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:27:00,830 INFO L93 Difference]: Finished difference Result 33916 states and 48815 transitions. [2024-12-02 06:27:00,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:27:00,831 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 87.42857142857143) internal successors, (612), 7 states have internal predecessors, (612), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 771 [2024-12-02 06:27:00,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:27:00,848 INFO L225 Difference]: With dead ends: 33916 [2024-12-02 06:27:00,848 INFO L226 Difference]: Without dead ends: 24638 [2024-12-02 06:27:00,856 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:27:00,856 INFO L435 NwaCegarLoop]: 1043 mSDtfsCounter, 813 mSDsluCounter, 4142 mSDsCounter, 0 mSdLazyCounter, 247 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 813 SdHoareTripleChecker+Valid, 5185 SdHoareTripleChecker+Invalid, 248 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 247 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:27:00,856 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [813 Valid, 5185 Invalid, 248 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 247 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:27:00,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24638 states. [2024-12-02 06:27:01,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24638 to 24638. [2024-12-02 06:27:01,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24638 states, 24561 states have (on average 1.4409429583486015) internal successors, (35391), 24561 states have internal predecessors, (35391), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:27:01,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24638 states to 24638 states and 35541 transitions. [2024-12-02 06:27:01,295 INFO L78 Accepts]: Start accepts. Automaton has 24638 states and 35541 transitions. Word has length 771 [2024-12-02 06:27:01,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:27:01,296 INFO L471 AbstractCegarLoop]: Abstraction has 24638 states and 35541 transitions. [2024-12-02 06:27:01,296 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 87.42857142857143) internal successors, (612), 7 states have internal predecessors, (612), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:27:01,296 INFO L276 IsEmpty]: Start isEmpty. Operand 24638 states and 35541 transitions. [2024-12-02 06:27:01,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 773 [2024-12-02 06:27:01,313 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:27:01,313 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:27:01,313 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable74 [2024-12-02 06:27:01,313 INFO L396 AbstractCegarLoop]: === Iteration 76 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:27:01,313 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:27:01,314 INFO L85 PathProgramCache]: Analyzing trace with hash -1278931718, now seen corresponding path program 1 times [2024-12-02 06:27:01,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:27:01,314 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989416515] [2024-12-02 06:27:01,314 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:27:01,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:27:04,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:05,157 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:27:05,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:27:05,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [989416515] [2024-12-02 06:27:05,157 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [989416515] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:27:05,157 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:27:05,157 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:27:05,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2064522267] [2024-12-02 06:27:05,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:27:05,158 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:27:05,158 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:27:05,158 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:27:05,158 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:27:05,159 INFO L87 Difference]: Start difference. First operand 24638 states and 35541 transitions. Second operand has 8 states, 8 states have (on average 76.625) internal successors, (613), 8 states have internal predecessors, (613), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:27:06,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:27:06,327 INFO L93 Difference]: Finished difference Result 34840 states and 50050 transitions. [2024-12-02 06:27:06,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:27:06,328 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 76.625) internal successors, (613), 8 states have internal predecessors, (613), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 772 [2024-12-02 06:27:06,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:27:06,346 INFO L225 Difference]: With dead ends: 34840 [2024-12-02 06:27:06,346 INFO L226 Difference]: Without dead ends: 25706 [2024-12-02 06:27:06,354 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:27:06,354 INFO L435 NwaCegarLoop]: 886 mSDtfsCounter, 1644 mSDsluCounter, 4255 mSDsCounter, 0 mSdLazyCounter, 1915 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1644 SdHoareTripleChecker+Valid, 5141 SdHoareTripleChecker+Invalid, 1917 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 1915 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-12-02 06:27:06,354 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1644 Valid, 5141 Invalid, 1917 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 1915 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-12-02 06:27:06,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25706 states. [2024-12-02 06:27:06,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25706 to 23643. [2024-12-02 06:27:06,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23643 states, 23566 states have (on average 1.4399134346091826) internal successors, (33933), 23566 states have internal predecessors, (33933), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:27:06,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23643 states to 23643 states and 34083 transitions. [2024-12-02 06:27:06,728 INFO L78 Accepts]: Start accepts. Automaton has 23643 states and 34083 transitions. Word has length 772 [2024-12-02 06:27:06,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:27:06,729 INFO L471 AbstractCegarLoop]: Abstraction has 23643 states and 34083 transitions. [2024-12-02 06:27:06,729 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 76.625) internal successors, (613), 8 states have internal predecessors, (613), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:27:06,729 INFO L276 IsEmpty]: Start isEmpty. Operand 23643 states and 34083 transitions. [2024-12-02 06:27:06,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 773 [2024-12-02 06:27:06,744 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:27:06,744 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:27:06,744 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable75 [2024-12-02 06:27:06,744 INFO L396 AbstractCegarLoop]: === Iteration 77 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:27:06,744 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:27:06,744 INFO L85 PathProgramCache]: Analyzing trace with hash 1280955822, now seen corresponding path program 1 times [2024-12-02 06:27:06,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:27:06,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390485186] [2024-12-02 06:27:06,745 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:27:06,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:27:10,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:12,020 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 187 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:27:12,021 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:27:12,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390485186] [2024-12-02 06:27:12,021 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390485186] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:27:12,021 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:27:12,021 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:27:12,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982255040] [2024-12-02 06:27:12,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:27:12,021 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:27:12,021 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:27:12,022 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:27:12,022 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:27:12,022 INFO L87 Difference]: Start difference. First operand 23643 states and 34083 transitions. Second operand has 7 states, 7 states have (on average 87.57142857142857) internal successors, (613), 7 states have internal predecessors, (613), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:27:12,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:27:12,374 INFO L93 Difference]: Finished difference Result 33233 states and 47757 transitions. [2024-12-02 06:27:12,375 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:27:12,375 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 87.57142857142857) internal successors, (613), 7 states have internal predecessors, (613), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 772 [2024-12-02 06:27:12,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:27:12,391 INFO L225 Difference]: With dead ends: 33233 [2024-12-02 06:27:12,391 INFO L226 Difference]: Without dead ends: 23667 [2024-12-02 06:27:12,399 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:27:12,399 INFO L435 NwaCegarLoop]: 1046 mSDtfsCounter, 807 mSDsluCounter, 4157 mSDsCounter, 0 mSdLazyCounter, 269 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 807 SdHoareTripleChecker+Valid, 5203 SdHoareTripleChecker+Invalid, 269 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 269 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:27:12,399 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [807 Valid, 5203 Invalid, 269 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 269 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:27:12,409 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23667 states. [2024-12-02 06:27:12,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23667 to 23655. [2024-12-02 06:27:12,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23655 states, 23578 states have (on average 1.4396895410976334) internal successors, (33945), 23578 states have internal predecessors, (33945), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:27:12,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23655 states to 23655 states and 34095 transitions. [2024-12-02 06:27:12,705 INFO L78 Accepts]: Start accepts. Automaton has 23655 states and 34095 transitions. Word has length 772 [2024-12-02 06:27:12,705 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:27:12,705 INFO L471 AbstractCegarLoop]: Abstraction has 23655 states and 34095 transitions. [2024-12-02 06:27:12,705 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 87.57142857142857) internal successors, (613), 7 states have internal predecessors, (613), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:27:12,705 INFO L276 IsEmpty]: Start isEmpty. Operand 23655 states and 34095 transitions. [2024-12-02 06:27:12,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 773 [2024-12-02 06:27:12,720 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:27:12,720 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:27:12,721 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable76 [2024-12-02 06:27:12,721 INFO L396 AbstractCegarLoop]: === Iteration 78 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:27:12,721 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:27:12,721 INFO L85 PathProgramCache]: Analyzing trace with hash -904018866, now seen corresponding path program 1 times [2024-12-02 06:27:12,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:27:12,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116406756] [2024-12-02 06:27:12,721 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:27:12,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:27:13,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:13,738 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 187 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:27:13,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:27:13,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116406756] [2024-12-02 06:27:13,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1116406756] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:27:13,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:27:13,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:27:13,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1645113337] [2024-12-02 06:27:13,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:27:13,739 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:27:13,739 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:27:13,739 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:27:13,739 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:27:13,739 INFO L87 Difference]: Start difference. First operand 23655 states and 34095 transitions. Second operand has 5 states, 5 states have (on average 122.6) internal successors, (613), 5 states have internal predecessors, (613), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:27:13,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:27:13,992 INFO L93 Difference]: Finished difference Result 33779 states and 48491 transitions. [2024-12-02 06:27:13,993 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:27:13,993 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 122.6) internal successors, (613), 5 states have internal predecessors, (613), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 772 [2024-12-02 06:27:13,993 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:27:14,008 INFO L225 Difference]: With dead ends: 33779 [2024-12-02 06:27:14,009 INFO L226 Difference]: Without dead ends: 24169 [2024-12-02 06:27:14,017 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:27:14,017 INFO L435 NwaCegarLoop]: 1651 mSDtfsCounter, 601 mSDsluCounter, 4367 mSDsCounter, 0 mSdLazyCounter, 55 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 601 SdHoareTripleChecker+Valid, 6018 SdHoareTripleChecker+Invalid, 55 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 55 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:27:14,017 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [601 Valid, 6018 Invalid, 55 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 55 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:27:14,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24169 states. [2024-12-02 06:27:14,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24169 to 23623. [2024-12-02 06:27:14,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23623 states, 23546 states have (on average 1.4396075766584557) internal successors, (33897), 23546 states have internal predecessors, (33897), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:27:14,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23623 states to 23623 states and 34047 transitions. [2024-12-02 06:27:14,312 INFO L78 Accepts]: Start accepts. Automaton has 23623 states and 34047 transitions. Word has length 772 [2024-12-02 06:27:14,312 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:27:14,312 INFO L471 AbstractCegarLoop]: Abstraction has 23623 states and 34047 transitions. [2024-12-02 06:27:14,312 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 122.6) internal successors, (613), 5 states have internal predecessors, (613), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:27:14,312 INFO L276 IsEmpty]: Start isEmpty. Operand 23623 states and 34047 transitions. [2024-12-02 06:27:14,327 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 774 [2024-12-02 06:27:14,327 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:27:14,327 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:27:14,327 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable77 [2024-12-02 06:27:14,327 INFO L396 AbstractCegarLoop]: === Iteration 79 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:27:14,327 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:27:14,328 INFO L85 PathProgramCache]: Analyzing trace with hash -1511374778, now seen corresponding path program 1 times [2024-12-02 06:27:14,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:27:14,328 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696997298] [2024-12-02 06:27:14,328 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:27:14,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:27:16,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:18,233 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 88 proven. 0 refuted. 0 times theorem prover too weak. 773 trivial. 0 not checked. [2024-12-02 06:27:18,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:27:18,234 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [696997298] [2024-12-02 06:27:18,234 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [696997298] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:27:18,234 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:27:18,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:27:18,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1563397075] [2024-12-02 06:27:18,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:27:18,234 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:27:18,234 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:27:18,235 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:27:18,235 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:27:18,235 INFO L87 Difference]: Start difference. First operand 23623 states and 34047 transitions. Second operand has 6 states, 6 states have (on average 87.0) internal successors, (522), 6 states have internal predecessors, (522), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:27:19,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:27:19,155 INFO L93 Difference]: Finished difference Result 34450 states and 49389 transitions. [2024-12-02 06:27:19,155 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:27:19,155 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 87.0) internal successors, (522), 6 states have internal predecessors, (522), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 773 [2024-12-02 06:27:19,156 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:27:19,168 INFO L225 Difference]: With dead ends: 34450 [2024-12-02 06:27:19,168 INFO L226 Difference]: Without dead ends: 18665 [2024-12-02 06:27:19,177 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:27:19,178 INFO L435 NwaCegarLoop]: 796 mSDtfsCounter, 1690 mSDsluCounter, 2313 mSDsCounter, 0 mSdLazyCounter, 1129 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1695 SdHoareTripleChecker+Valid, 3109 SdHoareTripleChecker+Invalid, 1132 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1129 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-12-02 06:27:19,178 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1695 Valid, 3109 Invalid, 1132 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1129 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-12-02 06:27:19,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18665 states. [2024-12-02 06:27:19,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18665 to 17380. [2024-12-02 06:27:19,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17380 states, 17303 states have (on average 1.4295208923308096) internal successors, (24735), 17303 states have internal predecessors, (24735), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:27:19,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17380 states to 17380 states and 24885 transitions. [2024-12-02 06:27:19,422 INFO L78 Accepts]: Start accepts. Automaton has 17380 states and 24885 transitions. Word has length 773 [2024-12-02 06:27:19,422 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:27:19,422 INFO L471 AbstractCegarLoop]: Abstraction has 17380 states and 24885 transitions. [2024-12-02 06:27:19,422 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 87.0) internal successors, (522), 6 states have internal predecessors, (522), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:27:19,422 INFO L276 IsEmpty]: Start isEmpty. Operand 17380 states and 24885 transitions. [2024-12-02 06:27:19,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 774 [2024-12-02 06:27:19,433 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:27:19,434 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:27:19,434 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable78 [2024-12-02 06:27:19,434 INFO L396 AbstractCegarLoop]: === Iteration 80 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:27:19,434 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:27:19,434 INFO L85 PathProgramCache]: Analyzing trace with hash -906523100, now seen corresponding path program 1 times [2024-12-02 06:27:19,434 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:27:19,434 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1833710907] [2024-12-02 06:27:19,434 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:27:19,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:27:22,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:23,985 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 187 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:27:23,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:27:23,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1833710907] [2024-12-02 06:27:23,986 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1833710907] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:27:23,986 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:27:23,986 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2024-12-02 06:27:23,986 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306536243] [2024-12-02 06:27:23,986 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:27:23,986 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 06:27:23,986 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:27:23,987 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 06:27:23,987 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:27:23,987 INFO L87 Difference]: Start difference. First operand 17380 states and 24885 transitions. Second operand has 10 states, 10 states have (on average 61.4) internal successors, (614), 10 states have internal predecessors, (614), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:27:25,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:27:25,687 INFO L93 Difference]: Finished difference Result 28193 states and 40221 transitions. [2024-12-02 06:27:25,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:27:25,688 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 61.4) internal successors, (614), 10 states have internal predecessors, (614), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 773 [2024-12-02 06:27:25,688 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:27:25,702 INFO L225 Difference]: With dead ends: 28193 [2024-12-02 06:27:25,702 INFO L226 Difference]: Without dead ends: 18803 [2024-12-02 06:27:25,710 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=42, Invalid=140, Unknown=0, NotChecked=0, Total=182 [2024-12-02 06:27:25,710 INFO L435 NwaCegarLoop]: 851 mSDtfsCounter, 1136 mSDsluCounter, 6191 mSDsCounter, 0 mSdLazyCounter, 2460 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1136 SdHoareTripleChecker+Valid, 7042 SdHoareTripleChecker+Invalid, 2463 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 2460 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:27:25,710 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1136 Valid, 7042 Invalid, 2463 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 2460 Invalid, 0 Unknown, 0 Unchecked, 1.4s Time] [2024-12-02 06:27:25,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18803 states. [2024-12-02 06:27:25,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18803 to 17654. [2024-12-02 06:27:25,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17654 states, 17577 states have (on average 1.4288558912214826) internal successors, (25115), 17577 states have internal predecessors, (25115), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:27:25,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17654 states to 17654 states and 25265 transitions. [2024-12-02 06:27:25,991 INFO L78 Accepts]: Start accepts. Automaton has 17654 states and 25265 transitions. Word has length 773 [2024-12-02 06:27:25,991 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:27:25,991 INFO L471 AbstractCegarLoop]: Abstraction has 17654 states and 25265 transitions. [2024-12-02 06:27:25,992 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 61.4) internal successors, (614), 10 states have internal predecessors, (614), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:27:25,992 INFO L276 IsEmpty]: Start isEmpty. Operand 17654 states and 25265 transitions. [2024-12-02 06:27:26,004 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 774 [2024-12-02 06:27:26,004 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:27:26,004 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:27:26,004 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable79 [2024-12-02 06:27:26,005 INFO L396 AbstractCegarLoop]: === Iteration 81 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:27:26,005 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:27:26,005 INFO L85 PathProgramCache]: Analyzing trace with hash -231997623, now seen corresponding path program 1 times [2024-12-02 06:27:26,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:27:26,005 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162343843] [2024-12-02 06:27:26,005 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:27:26,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:27:30,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:33,226 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 187 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:27:33,226 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:27:33,226 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162343843] [2024-12-02 06:27:33,226 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162343843] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:27:33,226 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:27:33,226 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2024-12-02 06:27:33,227 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1397726708] [2024-12-02 06:27:33,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:27:33,227 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2024-12-02 06:27:33,227 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:27:33,227 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2024-12-02 06:27:33,227 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:27:33,227 INFO L87 Difference]: Start difference. First operand 17654 states and 25265 transitions. Second operand has 12 states, 12 states have (on average 51.166666666666664) internal successors, (614), 12 states have internal predecessors, (614), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:27:34,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:27:34,648 INFO L93 Difference]: Finished difference Result 27496 states and 39271 transitions. [2024-12-02 06:27:34,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2024-12-02 06:27:34,649 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 51.166666666666664) internal successors, (614), 12 states have internal predecessors, (614), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 773 [2024-12-02 06:27:34,649 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:27:34,663 INFO L225 Difference]: With dead ends: 27496 [2024-12-02 06:27:34,663 INFO L226 Difference]: Without dead ends: 17742 [2024-12-02 06:27:34,671 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=163, Unknown=0, NotChecked=0, Total=210 [2024-12-02 06:27:34,671 INFO L435 NwaCegarLoop]: 790 mSDtfsCounter, 1734 mSDsluCounter, 6226 mSDsCounter, 0 mSdLazyCounter, 2727 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1738 SdHoareTripleChecker+Valid, 7016 SdHoareTripleChecker+Invalid, 2730 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 2727 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:27:34,671 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1738 Valid, 7016 Invalid, 2730 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 2727 Invalid, 0 Unknown, 0 Unchecked, 1.2s Time] [2024-12-02 06:27:34,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17742 states. [2024-12-02 06:27:34,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17742 to 17742. [2024-12-02 06:27:34,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17742 states, 17665 states have (on average 1.4264930653835268) internal successors, (25199), 17665 states have internal predecessors, (25199), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:27:34,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17742 states to 17742 states and 25349 transitions. [2024-12-02 06:27:35,001 INFO L78 Accepts]: Start accepts. Automaton has 17742 states and 25349 transitions. Word has length 773 [2024-12-02 06:27:35,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:27:35,001 INFO L471 AbstractCegarLoop]: Abstraction has 17742 states and 25349 transitions. [2024-12-02 06:27:35,001 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 51.166666666666664) internal successors, (614), 12 states have internal predecessors, (614), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:27:35,001 INFO L276 IsEmpty]: Start isEmpty. Operand 17742 states and 25349 transitions. [2024-12-02 06:27:35,013 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 775 [2024-12-02 06:27:35,013 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:27:35,013 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:27:35,014 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable80 [2024-12-02 06:27:35,014 INFO L396 AbstractCegarLoop]: === Iteration 82 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:27:35,014 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:27:35,014 INFO L85 PathProgramCache]: Analyzing trace with hash -730036079, now seen corresponding path program 1 times [2024-12-02 06:27:35,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:27:35,014 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [273925289] [2024-12-02 06:27:35,014 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:27:35,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:27:39,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:41,210 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 187 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:27:41,210 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:27:41,211 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [273925289] [2024-12-02 06:27:41,211 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [273925289] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:27:41,211 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:27:41,211 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:27:41,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1409512217] [2024-12-02 06:27:41,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:27:41,211 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:27:41,211 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:27:41,212 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:27:41,212 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:27:41,212 INFO L87 Difference]: Start difference. First operand 17742 states and 25349 transitions. Second operand has 8 states, 8 states have (on average 76.875) internal successors, (615), 8 states have internal predecessors, (615), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:27:42,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:27:42,087 INFO L93 Difference]: Finished difference Result 27520 states and 39239 transitions. [2024-12-02 06:27:42,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:27:42,088 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 76.875) internal successors, (615), 8 states have internal predecessors, (615), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 774 [2024-12-02 06:27:42,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:27:42,101 INFO L225 Difference]: With dead ends: 27520 [2024-12-02 06:27:42,101 INFO L226 Difference]: Without dead ends: 17842 [2024-12-02 06:27:42,108 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=79, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:27:42,108 INFO L435 NwaCegarLoop]: 794 mSDtfsCounter, 1697 mSDsluCounter, 3146 mSDsCounter, 0 mSdLazyCounter, 1492 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1701 SdHoareTripleChecker+Valid, 3940 SdHoareTripleChecker+Invalid, 1494 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 1492 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-12-02 06:27:42,108 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1701 Valid, 3940 Invalid, 1494 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 1492 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-12-02 06:27:42,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17842 states. [2024-12-02 06:27:42,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17842 to 17842. [2024-12-02 06:27:42,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17842 states, 17765 states have (on average 1.4240923163523782) internal successors, (25299), 17765 states have internal predecessors, (25299), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:27:42,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17842 states to 17842 states and 25449 transitions. [2024-12-02 06:27:42,420 INFO L78 Accepts]: Start accepts. Automaton has 17842 states and 25449 transitions. Word has length 774 [2024-12-02 06:27:42,421 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:27:42,421 INFO L471 AbstractCegarLoop]: Abstraction has 17842 states and 25449 transitions. [2024-12-02 06:27:42,421 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 76.875) internal successors, (615), 8 states have internal predecessors, (615), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:27:42,421 INFO L276 IsEmpty]: Start isEmpty. Operand 17842 states and 25449 transitions. [2024-12-02 06:27:42,432 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 776 [2024-12-02 06:27:42,432 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:27:42,432 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:27:42,432 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable81 [2024-12-02 06:27:42,432 INFO L396 AbstractCegarLoop]: === Iteration 83 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:27:42,433 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:27:42,433 INFO L85 PathProgramCache]: Analyzing trace with hash 1300973945, now seen corresponding path program 1 times [2024-12-02 06:27:42,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:27:42,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [777592609] [2024-12-02 06:27:42,433 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:27:42,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:27:46,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:47,589 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 187 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:27:47,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:27:47,589 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [777592609] [2024-12-02 06:27:47,589 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [777592609] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:27:47,589 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:27:47,590 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:27:47,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [830138917] [2024-12-02 06:27:47,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:27:47,590 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:27:47,590 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:27:47,591 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:27:47,591 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:27:47,591 INFO L87 Difference]: Start difference. First operand 17842 states and 25449 transitions. Second operand has 8 states, 8 states have (on average 77.0) internal successors, (616), 8 states have internal predecessors, (616), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:27:47,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:27:47,985 INFO L93 Difference]: Finished difference Result 28062 states and 39925 transitions. [2024-12-02 06:27:47,985 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:27:47,986 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 77.0) internal successors, (616), 8 states have internal predecessors, (616), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 775 [2024-12-02 06:27:47,986 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:27:47,999 INFO L225 Difference]: With dead ends: 28062 [2024-12-02 06:27:47,999 INFO L226 Difference]: Without dead ends: 18392 [2024-12-02 06:27:48,006 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:27:48,006 INFO L435 NwaCegarLoop]: 1558 mSDtfsCounter, 1644 mSDsluCounter, 7189 mSDsCounter, 0 mSdLazyCounter, 415 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1649 SdHoareTripleChecker+Valid, 8747 SdHoareTripleChecker+Invalid, 417 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 415 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:27:48,006 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1649 Valid, 8747 Invalid, 417 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 415 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:27:48,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18392 states. [2024-12-02 06:27:48,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18392 to 17846. [2024-12-02 06:27:48,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17846 states, 17769 states have (on average 1.4237717372952896) internal successors, (25299), 17769 states have internal predecessors, (25299), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:27:48,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17846 states to 17846 states and 25449 transitions. [2024-12-02 06:27:48,264 INFO L78 Accepts]: Start accepts. Automaton has 17846 states and 25449 transitions. Word has length 775 [2024-12-02 06:27:48,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:27:48,265 INFO L471 AbstractCegarLoop]: Abstraction has 17846 states and 25449 transitions. [2024-12-02 06:27:48,265 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 77.0) internal successors, (616), 8 states have internal predecessors, (616), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:27:48,265 INFO L276 IsEmpty]: Start isEmpty. Operand 17846 states and 25449 transitions. [2024-12-02 06:27:48,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 776 [2024-12-02 06:27:48,276 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:27:48,276 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:27:48,276 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable82 [2024-12-02 06:27:48,276 INFO L396 AbstractCegarLoop]: === Iteration 84 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:27:48,277 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:27:48,277 INFO L85 PathProgramCache]: Analyzing trace with hash -1244259623, now seen corresponding path program 1 times [2024-12-02 06:27:48,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:27:48,277 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119365859] [2024-12-02 06:27:48,277 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:27:48,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:27:52,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:53,179 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 12 proven. 27 refuted. 0 times theorem prover too weak. 824 trivial. 0 not checked. [2024-12-02 06:27:53,180 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:27:53,180 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [119365859] [2024-12-02 06:27:53,180 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [119365859] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:27:53,180 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1256253241] [2024-12-02 06:27:53,180 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:27:53,180 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:27:53,180 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:27:53,181 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:27:53,182 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2024-12-02 06:27:57,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:57,822 INFO L256 TraceCheckSpWp]: Trace formula consists of 3688 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 06:27:57,829 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:27:57,865 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 269 proven. 0 refuted. 0 times theorem prover too weak. 594 trivial. 0 not checked. [2024-12-02 06:27:57,865 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:27:57,865 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1256253241] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:27:57,865 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:27:57,865 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 9 [2024-12-02 06:27:57,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2099009783] [2024-12-02 06:27:57,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:27:57,866 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:27:57,866 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:27:57,866 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:27:57,866 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:27:57,866 INFO L87 Difference]: Start difference. First operand 17846 states and 25449 transitions. Second operand has 6 states, 5 states have (on average 120.8) internal successors, (604), 6 states have internal predecessors, (604), 3 states have call successors, (9), 2 states have call predecessors, (9), 3 states have return successors, (9), 2 states have call predecessors, (9), 3 states have call successors, (9) [2024-12-02 06:27:58,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:27:58,115 INFO L93 Difference]: Finished difference Result 35031 states and 49984 transitions. [2024-12-02 06:27:58,115 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:27:58,115 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 120.8) internal successors, (604), 6 states have internal predecessors, (604), 3 states have call successors, (9), 2 states have call predecessors, (9), 3 states have return successors, (9), 2 states have call predecessors, (9), 3 states have call successors, (9) Word has length 775 [2024-12-02 06:27:58,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:27:58,131 INFO L225 Difference]: With dead ends: 35031 [2024-12-02 06:27:58,131 INFO L226 Difference]: Without dead ends: 17846 [2024-12-02 06:27:58,142 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 780 GetRequests, 773 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:27:58,143 INFO L435 NwaCegarLoop]: 1080 mSDtfsCounter, 0 mSDsluCounter, 4301 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5381 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:27:58,143 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5381 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:27:58,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17846 states. [2024-12-02 06:27:58,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17846 to 17846. [2024-12-02 06:27:58,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17846 states, 17769 states have (on average 1.4229275704879285) internal successors, (25284), 17769 states have internal predecessors, (25284), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:27:58,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17846 states to 17846 states and 25434 transitions. [2024-12-02 06:27:58,433 INFO L78 Accepts]: Start accepts. Automaton has 17846 states and 25434 transitions. Word has length 775 [2024-12-02 06:27:58,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:27:58,433 INFO L471 AbstractCegarLoop]: Abstraction has 17846 states and 25434 transitions. [2024-12-02 06:27:58,433 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 120.8) internal successors, (604), 6 states have internal predecessors, (604), 3 states have call successors, (9), 2 states have call predecessors, (9), 3 states have return successors, (9), 2 states have call predecessors, (9), 3 states have call successors, (9) [2024-12-02 06:27:58,433 INFO L276 IsEmpty]: Start isEmpty. Operand 17846 states and 25434 transitions. [2024-12-02 06:27:58,446 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 776 [2024-12-02 06:27:58,446 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:27:58,447 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:27:58,474 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Forceful destruction successful, exit code 0 [2024-12-02 06:27:58,647 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 34 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable83 [2024-12-02 06:27:58,647 INFO L396 AbstractCegarLoop]: === Iteration 85 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:27:58,647 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:27:58,648 INFO L85 PathProgramCache]: Analyzing trace with hash 1894784729, now seen corresponding path program 1 times [2024-12-02 06:27:58,648 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:27:58,648 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1027259640] [2024-12-02 06:27:58,648 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:27:58,648 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:28:03,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:28:07,172 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 85 proven. 89 refuted. 0 times theorem prover too weak. 689 trivial. 0 not checked. [2024-12-02 06:28:07,172 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:28:07,172 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1027259640] [2024-12-02 06:28:07,172 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1027259640] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:28:07,172 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [129793700] [2024-12-02 06:28:07,172 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:28:07,172 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:28:07,172 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:28:07,174 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:28:07,174 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2024-12-02 06:28:11,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:28:11,570 INFO L256 TraceCheckSpWp]: Trace formula consists of 3688 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 06:28:11,575 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:28:11,616 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 232 proven. 0 refuted. 0 times theorem prover too weak. 631 trivial. 0 not checked. [2024-12-02 06:28:11,617 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:28:11,617 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [129793700] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:28:11,617 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:28:11,617 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 12 [2024-12-02 06:28:11,617 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987571975] [2024-12-02 06:28:11,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:28:11,617 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:28:11,617 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:28:11,618 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:28:11,618 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:28:11,618 INFO L87 Difference]: Start difference. First operand 17846 states and 25434 transitions. Second operand has 6 states, 5 states have (on average 117.0) internal successors, (585), 6 states have internal predecessors, (585), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) [2024-12-02 06:28:11,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:28:11,857 INFO L93 Difference]: Finished difference Result 34563 states and 49288 transitions. [2024-12-02 06:28:11,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:28:11,858 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 117.0) internal successors, (585), 6 states have internal predecessors, (585), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) Word has length 775 [2024-12-02 06:28:11,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:28:11,870 INFO L225 Difference]: With dead ends: 34563 [2024-12-02 06:28:11,870 INFO L226 Difference]: Without dead ends: 17846 [2024-12-02 06:28:11,880 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 782 GetRequests, 772 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:28:11,880 INFO L435 NwaCegarLoop]: 1079 mSDtfsCounter, 0 mSDsluCounter, 4297 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5376 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:28:11,880 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5376 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:28:11,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17846 states. [2024-12-02 06:28:12,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17846 to 17786. [2024-12-02 06:28:12,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17786 states, 17709 states have (on average 1.4226664407928171) internal successors, (25194), 17709 states have internal predecessors, (25194), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:28:12,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17786 states to 17786 states and 25344 transitions. [2024-12-02 06:28:12,150 INFO L78 Accepts]: Start accepts. Automaton has 17786 states and 25344 transitions. Word has length 775 [2024-12-02 06:28:12,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:28:12,150 INFO L471 AbstractCegarLoop]: Abstraction has 17786 states and 25344 transitions. [2024-12-02 06:28:12,151 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 117.0) internal successors, (585), 6 states have internal predecessors, (585), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) [2024-12-02 06:28:12,151 INFO L276 IsEmpty]: Start isEmpty. Operand 17786 states and 25344 transitions. [2024-12-02 06:28:12,163 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 776 [2024-12-02 06:28:12,163 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:28:12,163 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:28:12,190 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Ended with exit code 0 [2024-12-02 06:28:12,363 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable84,35 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:28:12,363 INFO L396 AbstractCegarLoop]: === Iteration 86 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:28:12,364 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:28:12,364 INFO L85 PathProgramCache]: Analyzing trace with hash 1890894457, now seen corresponding path program 1 times [2024-12-02 06:28:12,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:28:12,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112713810] [2024-12-02 06:28:12,364 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:28:12,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:28:12,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:28:13,545 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 31 proven. 0 refuted. 0 times theorem prover too weak. 832 trivial. 0 not checked. [2024-12-02 06:28:13,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:28:13,546 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112713810] [2024-12-02 06:28:13,546 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1112713810] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:28:13,546 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:28:13,546 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:28:13,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2013166580] [2024-12-02 06:28:13,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:28:13,547 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:28:13,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:28:13,547 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:28:13,547 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:28:13,547 INFO L87 Difference]: Start difference. First operand 17786 states and 25344 transitions. Second operand has 5 states, 5 states have (on average 93.4) internal successors, (467), 5 states have internal predecessors, (467), 3 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 3 states have call predecessors, (7), 3 states have call successors, (7) [2024-12-02 06:28:14,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:28:14,206 INFO L93 Difference]: Finished difference Result 34686 states and 49450 transitions. [2024-12-02 06:28:14,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:28:14,206 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 93.4) internal successors, (467), 5 states have internal predecessors, (467), 3 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 3 states have call predecessors, (7), 3 states have call successors, (7) Word has length 775 [2024-12-02 06:28:14,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:28:14,219 INFO L225 Difference]: With dead ends: 34686 [2024-12-02 06:28:14,219 INFO L226 Difference]: Without dead ends: 17816 [2024-12-02 06:28:14,228 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:28:14,229 INFO L435 NwaCegarLoop]: 805 mSDtfsCounter, 1061 mSDsluCounter, 1585 mSDsCounter, 0 mSdLazyCounter, 855 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1065 SdHoareTripleChecker+Valid, 2390 SdHoareTripleChecker+Invalid, 857 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 855 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:28:14,229 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1065 Valid, 2390 Invalid, 857 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 855 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 06:28:14,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17816 states. [2024-12-02 06:28:14,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17816 to 17816. [2024-12-02 06:28:14,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17816 states, 17739 states have (on average 1.421951631997294) internal successors, (25224), 17739 states have internal predecessors, (25224), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-12-02 06:28:14,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17816 states to 17816 states and 25374 transitions. [2024-12-02 06:28:14,481 INFO L78 Accepts]: Start accepts. Automaton has 17816 states and 25374 transitions. Word has length 775 [2024-12-02 06:28:14,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:28:14,481 INFO L471 AbstractCegarLoop]: Abstraction has 17816 states and 25374 transitions. [2024-12-02 06:28:14,481 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 93.4) internal successors, (467), 5 states have internal predecessors, (467), 3 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 3 states have call predecessors, (7), 3 states have call successors, (7) [2024-12-02 06:28:14,481 INFO L276 IsEmpty]: Start isEmpty. Operand 17816 states and 25374 transitions. [2024-12-02 06:28:14,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 778 [2024-12-02 06:28:14,493 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:28:14,493 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:28:14,493 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable85 [2024-12-02 06:28:14,493 INFO L396 AbstractCegarLoop]: === Iteration 87 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:28:14,493 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:28:14,494 INFO L85 PathProgramCache]: Analyzing trace with hash -1318854161, now seen corresponding path program 1 times [2024-12-02 06:28:14,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:28:14,494 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [723321190] [2024-12-02 06:28:14,494 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:28:14,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:28:18,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:28:22,138 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 83 proven. 92 refuted. 0 times theorem prover too weak. 689 trivial. 0 not checked. [2024-12-02 06:28:22,138 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:28:22,138 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [723321190] [2024-12-02 06:28:22,138 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [723321190] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:28:22,139 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [785462561] [2024-12-02 06:28:22,139 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:28:22,139 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:28:22,139 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:28:22,140 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:28:22,141 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2024-12-02 06:28:27,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:28:27,103 INFO L256 TraceCheckSpWp]: Trace formula consists of 3694 conjuncts, 199 conjuncts are in the unsatisfiable core [2024-12-02 06:28:27,118 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:28:30,193 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 115 proven. 73 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:28:30,193 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:28:32,217 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 679 trivial. 0 not checked. [2024-12-02 06:28:32,217 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [785462561] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:28:32,217 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:28:32,218 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [8, 34] total 55 [2024-12-02 06:28:32,218 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1981761018] [2024-12-02 06:28:32,218 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:28:32,218 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-12-02 06:28:32,218 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:28:32,219 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-12-02 06:28:32,219 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=425, Invalid=2545, Unknown=0, NotChecked=0, Total=2970 [2024-12-02 06:28:32,220 INFO L87 Difference]: Start difference. First operand 17816 states and 25374 transitions. Second operand has 18 states, 18 states have (on average 34.22222222222222) internal successors, (616), 18 states have internal predecessors, (616), 4 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) [2024-12-02 06:28:33,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:28:33,501 INFO L93 Difference]: Finished difference Result 30596 states and 43490 transitions. [2024-12-02 06:28:33,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2024-12-02 06:28:33,502 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 34.22222222222222) internal successors, (616), 18 states have internal predecessors, (616), 4 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) Word has length 777 [2024-12-02 06:28:33,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:28:33,516 INFO L225 Difference]: With dead ends: 30596 [2024-12-02 06:28:33,516 INFO L226 Difference]: Without dead ends: 19759 [2024-12-02 06:28:33,523 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1573 GetRequests, 1512 SyntacticMatches, 0 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1256 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=549, Invalid=3357, Unknown=0, NotChecked=0, Total=3906 [2024-12-02 06:28:33,524 INFO L435 NwaCegarLoop]: 1255 mSDtfsCounter, 603 mSDsluCounter, 15383 mSDsCounter, 0 mSdLazyCounter, 792 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 607 SdHoareTripleChecker+Valid, 16638 SdHoareTripleChecker+Invalid, 799 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 792 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-12-02 06:28:33,524 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [607 Valid, 16638 Invalid, 799 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 792 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-12-02 06:28:33,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19759 states. [2024-12-02 06:28:33,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19759 to 19019. [2024-12-02 06:28:33,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19019 states, 18917 states have (on average 1.419252524184596) internal successors, (26848), 18917 states have internal predecessors, (26848), 100 states have call successors, (100), 1 states have call predecessors, (100), 1 states have return successors, (100), 100 states have call predecessors, (100), 100 states have call successors, (100) [2024-12-02 06:28:33,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19019 states to 19019 states and 27048 transitions. [2024-12-02 06:28:33,822 INFO L78 Accepts]: Start accepts. Automaton has 19019 states and 27048 transitions. Word has length 777 [2024-12-02 06:28:33,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:28:33,822 INFO L471 AbstractCegarLoop]: Abstraction has 19019 states and 27048 transitions. [2024-12-02 06:28:33,823 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 34.22222222222222) internal successors, (616), 18 states have internal predecessors, (616), 4 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) [2024-12-02 06:28:33,823 INFO L276 IsEmpty]: Start isEmpty. Operand 19019 states and 27048 transitions. [2024-12-02 06:28:33,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 780 [2024-12-02 06:28:33,834 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:28:33,835 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:28:33,857 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Ended with exit code 0 [2024-12-02 06:28:34,035 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable86,36 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:28:34,035 INFO L396 AbstractCegarLoop]: === Iteration 88 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:28:34,036 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:28:34,036 INFO L85 PathProgramCache]: Analyzing trace with hash -1891131548, now seen corresponding path program 1 times [2024-12-02 06:28:34,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:28:34,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [303072339] [2024-12-02 06:28:34,036 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:28:34,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:28:36,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:28:37,928 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 187 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:28:37,928 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:28:37,928 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [303072339] [2024-12-02 06:28:37,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [303072339] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:28:37,928 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:28:37,928 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2024-12-02 06:28:37,928 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [514679676] [2024-12-02 06:28:37,928 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:28:37,929 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2024-12-02 06:28:37,929 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:28:37,929 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2024-12-02 06:28:37,930 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:28:37,930 INFO L87 Difference]: Start difference. First operand 19019 states and 27048 transitions. Second operand has 11 states, 11 states have (on average 56.36363636363637) internal successors, (620), 11 states have internal predecessors, (620), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:28:38,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:28:38,617 INFO L93 Difference]: Finished difference Result 43287 states and 61489 transitions. [2024-12-02 06:28:38,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2024-12-02 06:28:38,617 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 56.36363636363637) internal successors, (620), 11 states have internal predecessors, (620), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 779 [2024-12-02 06:28:38,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:28:38,640 INFO L225 Difference]: With dead ends: 43287 [2024-12-02 06:28:38,640 INFO L226 Difference]: Without dead ends: 33071 [2024-12-02 06:28:38,651 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=70, Invalid=350, Unknown=0, NotChecked=0, Total=420 [2024-12-02 06:28:38,651 INFO L435 NwaCegarLoop]: 2487 mSDtfsCounter, 1464 mSDsluCounter, 17764 mSDsCounter, 0 mSdLazyCounter, 429 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1465 SdHoareTripleChecker+Valid, 20251 SdHoareTripleChecker+Invalid, 440 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 429 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:28:38,651 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1465 Valid, 20251 Invalid, 440 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 429 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:28:38,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33071 states. [2024-12-02 06:28:39,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33071 to 31960. [2024-12-02 06:28:39,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31960 states, 31818 states have (on average 1.4194481111320636) internal successors, (45164), 31818 states have internal predecessors, (45164), 140 states have call successors, (140), 1 states have call predecessors, (140), 1 states have return successors, (140), 140 states have call predecessors, (140), 140 states have call successors, (140) [2024-12-02 06:28:39,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31960 states to 31960 states and 45444 transitions. [2024-12-02 06:28:39,139 INFO L78 Accepts]: Start accepts. Automaton has 31960 states and 45444 transitions. Word has length 779 [2024-12-02 06:28:39,139 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:28:39,140 INFO L471 AbstractCegarLoop]: Abstraction has 31960 states and 45444 transitions. [2024-12-02 06:28:39,140 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 56.36363636363637) internal successors, (620), 11 states have internal predecessors, (620), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:28:39,140 INFO L276 IsEmpty]: Start isEmpty. Operand 31960 states and 45444 transitions. [2024-12-02 06:28:39,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 780 [2024-12-02 06:28:39,159 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:28:39,159 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:28:39,159 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable87 [2024-12-02 06:28:39,159 INFO L396 AbstractCegarLoop]: === Iteration 89 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:28:39,159 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:28:39,160 INFO L85 PathProgramCache]: Analyzing trace with hash 811006468, now seen corresponding path program 1 times [2024-12-02 06:28:39,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:28:39,160 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929061378] [2024-12-02 06:28:39,160 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:28:39,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:28:42,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:28:43,354 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 187 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:28:43,354 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:28:43,354 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [929061378] [2024-12-02 06:28:43,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [929061378] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:28:43,354 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:28:43,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:28:43,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [521383018] [2024-12-02 06:28:43,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:28:43,355 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:28:43,355 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:28:43,356 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:28:43,356 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:28:43,356 INFO L87 Difference]: Start difference. First operand 31960 states and 45444 transitions. Second operand has 7 states, 7 states have (on average 88.57142857142857) internal successors, (620), 7 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:28:44,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:28:44,538 INFO L93 Difference]: Finished difference Result 55187 states and 78306 transitions. [2024-12-02 06:28:44,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:28:44,538 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 88.57142857142857) internal successors, (620), 7 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 779 [2024-12-02 06:28:44,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:28:44,567 INFO L225 Difference]: With dead ends: 55187 [2024-12-02 06:28:44,567 INFO L226 Difference]: Without dead ends: 33268 [2024-12-02 06:28:44,583 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:28:44,584 INFO L435 NwaCegarLoop]: 959 mSDtfsCounter, 889 mSDsluCounter, 3619 mSDsCounter, 0 mSdLazyCounter, 1666 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 889 SdHoareTripleChecker+Valid, 4578 SdHoareTripleChecker+Invalid, 1667 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1666 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2024-12-02 06:28:44,584 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [889 Valid, 4578 Invalid, 1667 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1666 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2024-12-02 06:28:44,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33268 states. [2024-12-02 06:28:45,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33268 to 31960. [2024-12-02 06:28:45,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31960 states, 31818 states have (on average 1.4194481111320636) internal successors, (45164), 31818 states have internal predecessors, (45164), 140 states have call successors, (140), 1 states have call predecessors, (140), 1 states have return successors, (140), 140 states have call predecessors, (140), 140 states have call successors, (140) [2024-12-02 06:28:45,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31960 states to 31960 states and 45444 transitions. [2024-12-02 06:28:45,139 INFO L78 Accepts]: Start accepts. Automaton has 31960 states and 45444 transitions. Word has length 779 [2024-12-02 06:28:45,139 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:28:45,139 INFO L471 AbstractCegarLoop]: Abstraction has 31960 states and 45444 transitions. [2024-12-02 06:28:45,139 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 88.57142857142857) internal successors, (620), 7 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:28:45,139 INFO L276 IsEmpty]: Start isEmpty. Operand 31960 states and 45444 transitions. [2024-12-02 06:28:45,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 780 [2024-12-02 06:28:45,162 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:28:45,162 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:28:45,163 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable88 [2024-12-02 06:28:45,163 INFO L396 AbstractCegarLoop]: === Iteration 90 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:28:45,163 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:28:45,163 INFO L85 PathProgramCache]: Analyzing trace with hash -137729383, now seen corresponding path program 1 times [2024-12-02 06:28:45,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:28:45,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1569957812] [2024-12-02 06:28:45,163 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:28:45,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:28:49,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:28:50,683 INFO L134 CoverageAnalysis]: Checked inductivity of 865 backedges. 12 proven. 27 refuted. 0 times theorem prover too weak. 826 trivial. 0 not checked. [2024-12-02 06:28:50,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:28:50,683 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1569957812] [2024-12-02 06:28:50,683 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1569957812] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:28:50,684 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [856640195] [2024-12-02 06:28:50,684 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:28:50,684 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:28:50,684 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:28:50,685 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:28:50,686 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2024-12-02 06:28:54,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:28:54,824 INFO L256 TraceCheckSpWp]: Trace formula consists of 3700 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 06:28:54,833 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:28:54,862 INFO L134 CoverageAnalysis]: Checked inductivity of 865 backedges. 167 proven. 0 refuted. 0 times theorem prover too weak. 698 trivial. 0 not checked. [2024-12-02 06:28:54,862 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:28:54,862 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [856640195] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:28:54,862 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:28:54,862 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 9 [2024-12-02 06:28:54,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [424454437] [2024-12-02 06:28:54,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:28:54,863 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:28:54,863 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:28:54,863 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:28:54,863 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:28:54,863 INFO L87 Difference]: Start difference. First operand 31960 states and 45444 transitions. Second operand has 6 states, 5 states have (on average 100.8) internal successors, (504), 6 states have internal predecessors, (504), 3 states have call successors, (9), 2 states have call predecessors, (9), 3 states have return successors, (9), 2 states have call predecessors, (9), 3 states have call successors, (9) [2024-12-02 06:28:55,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:28:55,293 INFO L93 Difference]: Finished difference Result 62127 states and 88378 transitions. [2024-12-02 06:28:55,293 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:28:55,293 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 100.8) internal successors, (504), 6 states have internal predecessors, (504), 3 states have call successors, (9), 2 states have call predecessors, (9), 3 states have return successors, (9), 2 states have call predecessors, (9), 3 states have call successors, (9) Word has length 779 [2024-12-02 06:28:55,294 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:28:55,320 INFO L225 Difference]: With dead ends: 62127 [2024-12-02 06:28:55,320 INFO L226 Difference]: Without dead ends: 31960 [2024-12-02 06:28:55,337 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 784 GetRequests, 777 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:28:55,337 INFO L435 NwaCegarLoop]: 1078 mSDtfsCounter, 0 mSDsluCounter, 4293 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5371 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:28:55,337 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5371 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:28:55,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31960 states. [2024-12-02 06:28:55,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31960 to 31960. [2024-12-02 06:28:55,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31960 states, 31818 states have (on average 1.4185681061034634) internal successors, (45136), 31818 states have internal predecessors, (45136), 140 states have call successors, (140), 1 states have call predecessors, (140), 1 states have return successors, (140), 140 states have call predecessors, (140), 140 states have call successors, (140) [2024-12-02 06:28:55,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31960 states to 31960 states and 45416 transitions. [2024-12-02 06:28:55,834 INFO L78 Accepts]: Start accepts. Automaton has 31960 states and 45416 transitions. Word has length 779 [2024-12-02 06:28:55,835 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:28:55,835 INFO L471 AbstractCegarLoop]: Abstraction has 31960 states and 45416 transitions. [2024-12-02 06:28:55,835 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 100.8) internal successors, (504), 6 states have internal predecessors, (504), 3 states have call successors, (9), 2 states have call predecessors, (9), 3 states have return successors, (9), 2 states have call predecessors, (9), 3 states have call successors, (9) [2024-12-02 06:28:55,835 INFO L276 IsEmpty]: Start isEmpty. Operand 31960 states and 45416 transitions. [2024-12-02 06:28:55,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 782 [2024-12-02 06:28:55,856 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:28:55,857 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:28:55,884 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Ended with exit code 0 [2024-12-02 06:28:56,057 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 37 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable89 [2024-12-02 06:28:56,057 INFO L396 AbstractCegarLoop]: === Iteration 91 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:28:56,057 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:28:56,058 INFO L85 PathProgramCache]: Analyzing trace with hash 1754648205, now seen corresponding path program 1 times [2024-12-02 06:28:56,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:28:56,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765190594] [2024-12-02 06:28:56,058 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:28:56,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:28:59,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:29:00,885 INFO L134 CoverageAnalysis]: Checked inductivity of 866 backedges. 57 proven. 0 refuted. 0 times theorem prover too weak. 809 trivial. 0 not checked. [2024-12-02 06:29:00,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:29:00,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765190594] [2024-12-02 06:29:00,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765190594] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:29:00,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:29:00,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:29:00,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164323992] [2024-12-02 06:29:00,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:29:00,886 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:29:00,886 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:29:00,886 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:29:00,886 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:29:00,887 INFO L87 Difference]: Start difference. First operand 31960 states and 45416 transitions. Second operand has 7 states, 7 states have (on average 70.71428571428571) internal successors, (495), 7 states have internal predecessors, (495), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-12-02 06:29:01,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:29:01,479 INFO L93 Difference]: Finished difference Result 62615 states and 88970 transitions. [2024-12-02 06:29:01,479 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:29:01,479 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 70.71428571428571) internal successors, (495), 7 states have internal predecessors, (495), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 781 [2024-12-02 06:29:01,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:29:01,505 INFO L225 Difference]: With dead ends: 62615 [2024-12-02 06:29:01,505 INFO L226 Difference]: Without dead ends: 32324 [2024-12-02 06:29:01,525 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:29:01,525 INFO L435 NwaCegarLoop]: 1065 mSDtfsCounter, 978 mSDsluCounter, 4187 mSDsCounter, 0 mSdLazyCounter, 149 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 980 SdHoareTripleChecker+Valid, 5252 SdHoareTripleChecker+Invalid, 150 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 149 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:29:01,525 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [980 Valid, 5252 Invalid, 150 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 149 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:29:01,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32324 states. [2024-12-02 06:29:02,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32324 to 32044. [2024-12-02 06:29:02,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32044 states, 31902 states have (on average 1.4183436775123817) internal successors, (45248), 31902 states have internal predecessors, (45248), 140 states have call successors, (140), 1 states have call predecessors, (140), 1 states have return successors, (140), 140 states have call predecessors, (140), 140 states have call successors, (140) [2024-12-02 06:29:02,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32044 states to 32044 states and 45528 transitions. [2024-12-02 06:29:02,093 INFO L78 Accepts]: Start accepts. Automaton has 32044 states and 45528 transitions. Word has length 781 [2024-12-02 06:29:02,093 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:29:02,093 INFO L471 AbstractCegarLoop]: Abstraction has 32044 states and 45528 transitions. [2024-12-02 06:29:02,093 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 70.71428571428571) internal successors, (495), 7 states have internal predecessors, (495), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-12-02 06:29:02,093 INFO L276 IsEmpty]: Start isEmpty. Operand 32044 states and 45528 transitions. [2024-12-02 06:29:02,112 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 782 [2024-12-02 06:29:02,112 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:29:02,113 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:29:02,113 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable90 [2024-12-02 06:29:02,113 INFO L396 AbstractCegarLoop]: === Iteration 92 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:29:02,113 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:29:02,113 INFO L85 PathProgramCache]: Analyzing trace with hash -107398727, now seen corresponding path program 1 times [2024-12-02 06:29:02,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:29:02,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1200448307] [2024-12-02 06:29:02,114 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:29:02,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:29:06,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:29:07,855 INFO L134 CoverageAnalysis]: Checked inductivity of 866 backedges. 12 proven. 27 refuted. 0 times theorem prover too weak. 827 trivial. 0 not checked. [2024-12-02 06:29:07,855 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:29:07,855 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1200448307] [2024-12-02 06:29:07,855 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1200448307] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:29:07,855 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1150666654] [2024-12-02 06:29:07,855 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:29:07,855 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:29:07,855 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:29:07,857 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:29:07,857 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2024-12-02 06:29:16,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:29:16,758 INFO L256 TraceCheckSpWp]: Trace formula consists of 3706 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 06:29:16,764 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:29:16,781 INFO L134 CoverageAnalysis]: Checked inductivity of 866 backedges. 48 proven. 0 refuted. 0 times theorem prover too weak. 818 trivial. 0 not checked. [2024-12-02 06:29:16,781 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:29:16,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1150666654] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:29:16,782 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:29:16,782 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 7 [2024-12-02 06:29:16,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858192980] [2024-12-02 06:29:16,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:29:16,782 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:29:16,782 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:29:16,782 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:29:16,782 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:29:16,783 INFO L87 Difference]: Start difference. First operand 32044 states and 45528 transitions. Second operand has 6 states, 5 states have (on average 91.0) internal successors, (455), 6 states have internal predecessors, (455), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 1 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:29:17,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:29:17,186 INFO L93 Difference]: Finished difference Result 63097 states and 89683 transitions. [2024-12-02 06:29:17,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:29:17,187 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 91.0) internal successors, (455), 6 states have internal predecessors, (455), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 1 states have call predecessors, (6), 2 states have call successors, (6) Word has length 781 [2024-12-02 06:29:17,187 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:29:17,209 INFO L225 Difference]: With dead ends: 63097 [2024-12-02 06:29:17,209 INFO L226 Difference]: Without dead ends: 32044 [2024-12-02 06:29:17,227 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 786 GetRequests, 781 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:29:17,228 INFO L435 NwaCegarLoop]: 1079 mSDtfsCounter, 0 mSDsluCounter, 4293 mSDsCounter, 0 mSdLazyCounter, 53 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5372 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 53 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:29:17,228 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5372 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 53 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:29:17,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32044 states. [2024-12-02 06:29:17,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32044 to 32044. [2024-12-02 06:29:17,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32044 states, 31902 states have (on average 1.417685411572942) internal successors, (45227), 31902 states have internal predecessors, (45227), 140 states have call successors, (140), 1 states have call predecessors, (140), 1 states have return successors, (140), 140 states have call predecessors, (140), 140 states have call successors, (140) [2024-12-02 06:29:17,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32044 states to 32044 states and 45507 transitions. [2024-12-02 06:29:17,800 INFO L78 Accepts]: Start accepts. Automaton has 32044 states and 45507 transitions. Word has length 781 [2024-12-02 06:29:17,800 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:29:17,800 INFO L471 AbstractCegarLoop]: Abstraction has 32044 states and 45507 transitions. [2024-12-02 06:29:17,800 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 91.0) internal successors, (455), 6 states have internal predecessors, (455), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 1 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:29:17,800 INFO L276 IsEmpty]: Start isEmpty. Operand 32044 states and 45507 transitions. [2024-12-02 06:29:17,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 784 [2024-12-02 06:29:17,820 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:29:17,821 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:29:17,847 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Ended with exit code 0 [2024-12-02 06:29:18,021 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable91,38 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:29:18,021 INFO L396 AbstractCegarLoop]: === Iteration 93 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:29:18,021 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:29:18,022 INFO L85 PathProgramCache]: Analyzing trace with hash -2084424423, now seen corresponding path program 1 times [2024-12-02 06:29:18,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:29:18,022 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575054235] [2024-12-02 06:29:18,022 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:29:18,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:29:22,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:29:25,270 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 85 proven. 93 refuted. 0 times theorem prover too weak. 689 trivial. 0 not checked. [2024-12-02 06:29:25,270 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:29:25,270 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [575054235] [2024-12-02 06:29:25,270 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [575054235] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:29:25,270 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1081271050] [2024-12-02 06:29:25,270 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:29:25,270 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:29:25,270 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:29:25,272 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:29:25,272 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2024-12-02 06:29:33,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:29:33,774 INFO L256 TraceCheckSpWp]: Trace formula consists of 3708 conjuncts, 127 conjuncts are in the unsatisfiable core [2024-12-02 06:29:33,791 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:29:35,550 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 208 proven. 36 refuted. 0 times theorem prover too weak. 623 trivial. 0 not checked. [2024-12-02 06:29:35,551 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:29:37,415 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 37 proven. 2 refuted. 0 times theorem prover too weak. 828 trivial. 0 not checked. [2024-12-02 06:29:37,415 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1081271050] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:29:37,415 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:29:37,416 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 18, 16] total 38 [2024-12-02 06:29:37,416 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [484257051] [2024-12-02 06:29:37,416 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:29:37,416 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 38 states [2024-12-02 06:29:37,416 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:29:37,417 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2024-12-02 06:29:37,417 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=1213, Unknown=0, NotChecked=0, Total=1406 [2024-12-02 06:29:37,417 INFO L87 Difference]: Start difference. First operand 32044 states and 45507 transitions. Second operand has 38 states, 38 states have (on average 33.13157894736842) internal successors, (1259), 38 states have internal predecessors, (1259), 9 states have call successors, (26), 2 states have call predecessors, (26), 2 states have return successors, (26), 9 states have call predecessors, (26), 9 states have call successors, (26) [2024-12-02 06:29:43,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:29:43,436 INFO L93 Difference]: Finished difference Result 89053 states and 126697 transitions. [2024-12-02 06:29:43,436 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-12-02 06:29:43,436 INFO L78 Accepts]: Start accepts. Automaton has has 38 states, 38 states have (on average 33.13157894736842) internal successors, (1259), 38 states have internal predecessors, (1259), 9 states have call successors, (26), 2 states have call predecessors, (26), 2 states have return successors, (26), 9 states have call predecessors, (26), 9 states have call successors, (26) Word has length 783 [2024-12-02 06:29:43,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:29:43,475 INFO L225 Difference]: With dead ends: 89053 [2024-12-02 06:29:43,476 INFO L226 Difference]: Without dead ends: 58285 [2024-12-02 06:29:43,495 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1599 GetRequests, 1536 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 887 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=588, Invalid=3572, Unknown=0, NotChecked=0, Total=4160 [2024-12-02 06:29:43,495 INFO L435 NwaCegarLoop]: 797 mSDtfsCounter, 6689 mSDsluCounter, 18018 mSDsCounter, 0 mSdLazyCounter, 8792 mSolverCounterSat, 46 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 6703 SdHoareTripleChecker+Valid, 18815 SdHoareTripleChecker+Invalid, 8838 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 46 IncrementalHoareTripleChecker+Valid, 8792 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 4.3s IncrementalHoareTripleChecker+Time [2024-12-02 06:29:43,495 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [6703 Valid, 18815 Invalid, 8838 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [46 Valid, 8792 Invalid, 0 Unknown, 0 Unchecked, 4.3s Time] [2024-12-02 06:29:43,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58285 states. [2024-12-02 06:29:44,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58285 to 37098. [2024-12-02 06:29:44,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37098 states, 36862 states have (on average 1.4113178883402961) internal successors, (52024), 36862 states have internal predecessors, (52024), 234 states have call successors, (234), 1 states have call predecessors, (234), 1 states have return successors, (234), 234 states have call predecessors, (234), 234 states have call successors, (234) [2024-12-02 06:29:44,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37098 states to 37098 states and 52492 transitions. [2024-12-02 06:29:44,164 INFO L78 Accepts]: Start accepts. Automaton has 37098 states and 52492 transitions. Word has length 783 [2024-12-02 06:29:44,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:29:44,164 INFO L471 AbstractCegarLoop]: Abstraction has 37098 states and 52492 transitions. [2024-12-02 06:29:44,164 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 38 states, 38 states have (on average 33.13157894736842) internal successors, (1259), 38 states have internal predecessors, (1259), 9 states have call successors, (26), 2 states have call predecessors, (26), 2 states have return successors, (26), 9 states have call predecessors, (26), 9 states have call successors, (26) [2024-12-02 06:29:44,164 INFO L276 IsEmpty]: Start isEmpty. Operand 37098 states and 52492 transitions. [2024-12-02 06:29:44,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 784 [2024-12-02 06:29:44,196 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:29:44,197 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:29:44,227 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Ended with exit code 0 [2024-12-02 06:29:44,397 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable92,39 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:29:44,397 INFO L396 AbstractCegarLoop]: === Iteration 94 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:29:44,397 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:29:44,398 INFO L85 PathProgramCache]: Analyzing trace with hash 330050740, now seen corresponding path program 1 times [2024-12-02 06:29:44,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:29:44,398 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976324992] [2024-12-02 06:29:44,398 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:29:44,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:29:48,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:29:50,811 INFO L134 CoverageAnalysis]: Checked inductivity of 865 backedges. 189 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:29:50,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:29:50,811 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [976324992] [2024-12-02 06:29:50,811 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [976324992] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:29:50,811 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:29:50,811 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2024-12-02 06:29:50,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160847600] [2024-12-02 06:29:50,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:29:50,811 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 06:29:50,811 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:29:50,812 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 06:29:50,812 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:29:50,812 INFO L87 Difference]: Start difference. First operand 37098 states and 52492 transitions. Second operand has 10 states, 10 states have (on average 62.4) internal successors, (624), 10 states have internal predecessors, (624), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:29:51,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:29:51,447 INFO L93 Difference]: Finished difference Result 62772 states and 88620 transitions. [2024-12-02 06:29:51,447 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:29:51,447 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 62.4) internal successors, (624), 10 states have internal predecessors, (624), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 783 [2024-12-02 06:29:51,448 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:29:51,471 INFO L225 Difference]: With dead ends: 62772 [2024-12-02 06:29:51,471 INFO L226 Difference]: Without dead ends: 39229 [2024-12-02 06:29:51,481 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=139, Unknown=0, NotChecked=0, Total=182 [2024-12-02 06:29:51,481 INFO L435 NwaCegarLoop]: 1090 mSDtfsCounter, 740 mSDsluCounter, 7702 mSDsCounter, 0 mSdLazyCounter, 180 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 740 SdHoareTripleChecker+Valid, 8792 SdHoareTripleChecker+Invalid, 181 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 180 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:29:51,481 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [740 Valid, 8792 Invalid, 181 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 180 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:29:51,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39229 states. [2024-12-02 06:29:52,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39229 to 37098. [2024-12-02 06:29:52,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37098 states, 36862 states have (on average 1.411399272964028) internal successors, (52027), 36862 states have internal predecessors, (52027), 234 states have call successors, (234), 1 states have call predecessors, (234), 1 states have return successors, (234), 234 states have call predecessors, (234), 234 states have call successors, (234) [2024-12-02 06:29:52,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37098 states to 37098 states and 52495 transitions. [2024-12-02 06:29:52,070 INFO L78 Accepts]: Start accepts. Automaton has 37098 states and 52495 transitions. Word has length 783 [2024-12-02 06:29:52,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:29:52,071 INFO L471 AbstractCegarLoop]: Abstraction has 37098 states and 52495 transitions. [2024-12-02 06:29:52,071 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 62.4) internal successors, (624), 10 states have internal predecessors, (624), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:29:52,071 INFO L276 IsEmpty]: Start isEmpty. Operand 37098 states and 52495 transitions. [2024-12-02 06:29:52,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 785 [2024-12-02 06:29:52,093 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:29:52,093 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:29:52,093 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable93 [2024-12-02 06:29:52,093 INFO L396 AbstractCegarLoop]: === Iteration 95 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:29:52,094 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:29:52,094 INFO L85 PathProgramCache]: Analyzing trace with hash 108849404, now seen corresponding path program 1 times [2024-12-02 06:29:52,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:29:52,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [824646725] [2024-12-02 06:29:52,094 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:29:52,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:29:55,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:29:58,065 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 104 proven. 0 refuted. 0 times theorem prover too weak. 759 trivial. 0 not checked. [2024-12-02 06:29:58,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:29:58,065 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [824646725] [2024-12-02 06:29:58,065 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [824646725] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:29:58,065 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:29:58,066 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:29:58,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [586183430] [2024-12-02 06:29:58,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:29:58,066 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:29:58,066 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:29:58,067 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:29:58,067 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:29:58,067 INFO L87 Difference]: Start difference. First operand 37098 states and 52495 transitions. Second operand has 6 states, 6 states have (on average 91.0) internal successors, (546), 6 states have internal predecessors, (546), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:29:58,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:29:58,561 INFO L93 Difference]: Finished difference Result 70819 states and 100229 transitions. [2024-12-02 06:29:58,561 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:29:58,562 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 91.0) internal successors, (546), 6 states have internal predecessors, (546), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 784 [2024-12-02 06:29:58,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:29:58,590 INFO L225 Difference]: With dead ends: 70819 [2024-12-02 06:29:58,590 INFO L226 Difference]: Without dead ends: 38142 [2024-12-02 06:29:58,608 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:29:58,609 INFO L435 NwaCegarLoop]: 1074 mSDtfsCounter, 119 mSDsluCounter, 4280 mSDsCounter, 0 mSdLazyCounter, 52 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 119 SdHoareTripleChecker+Valid, 5354 SdHoareTripleChecker+Invalid, 52 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 52 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:29:58,609 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [119 Valid, 5354 Invalid, 52 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 52 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:29:58,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38142 states. [2024-12-02 06:29:59,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38142 to 38142. [2024-12-02 06:29:59,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38142 states, 37908 states have (on average 1.410150891632373) internal successors, (53456), 37908 states have internal predecessors, (53456), 232 states have call successors, (232), 1 states have call predecessors, (232), 1 states have return successors, (232), 232 states have call predecessors, (232), 232 states have call successors, (232) [2024-12-02 06:29:59,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38142 states to 38142 states and 53920 transitions. [2024-12-02 06:29:59,255 INFO L78 Accepts]: Start accepts. Automaton has 38142 states and 53920 transitions. Word has length 784 [2024-12-02 06:29:59,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:29:59,255 INFO L471 AbstractCegarLoop]: Abstraction has 38142 states and 53920 transitions. [2024-12-02 06:29:59,255 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 91.0) internal successors, (546), 6 states have internal predecessors, (546), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:29:59,255 INFO L276 IsEmpty]: Start isEmpty. Operand 38142 states and 53920 transitions. [2024-12-02 06:29:59,281 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 785 [2024-12-02 06:29:59,281 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:29:59,281 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:29:59,281 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable94 [2024-12-02 06:29:59,281 INFO L396 AbstractCegarLoop]: === Iteration 96 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:29:59,282 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:29:59,282 INFO L85 PathProgramCache]: Analyzing trace with hash 622013756, now seen corresponding path program 1 times [2024-12-02 06:29:59,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:29:59,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556731748] [2024-12-02 06:29:59,282 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:29:59,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:30:04,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:30:07,999 INFO L134 CoverageAnalysis]: Checked inductivity of 865 backedges. 80 proven. 0 refuted. 0 times theorem prover too weak. 785 trivial. 0 not checked. [2024-12-02 06:30:07,999 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:30:07,999 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1556731748] [2024-12-02 06:30:07,999 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1556731748] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:30:07,999 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:30:07,999 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-12-02 06:30:07,999 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1603288445] [2024-12-02 06:30:07,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:30:08,000 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:30:08,000 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:30:08,001 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:30:08,001 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:30:08,001 INFO L87 Difference]: Start difference. First operand 38142 states and 53920 transitions. Second operand has 9 states, 9 states have (on average 57.77777777777778) internal successors, (520), 9 states have internal predecessors, (520), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:30:09,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:30:09,099 INFO L93 Difference]: Finished difference Result 94864 states and 133919 transitions. [2024-12-02 06:30:09,100 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:30:09,100 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 57.77777777777778) internal successors, (520), 9 states have internal predecessors, (520), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 784 [2024-12-02 06:30:09,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:30:09,157 INFO L225 Difference]: With dead ends: 94864 [2024-12-02 06:30:09,157 INFO L226 Difference]: Without dead ends: 68838 [2024-12-02 06:30:09,177 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:30:09,178 INFO L435 NwaCegarLoop]: 1065 mSDtfsCounter, 1963 mSDsluCounter, 7457 mSDsCounter, 0 mSdLazyCounter, 165 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1973 SdHoareTripleChecker+Valid, 8522 SdHoareTripleChecker+Invalid, 171 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 165 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:30:09,178 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1973 Valid, 8522 Invalid, 171 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 165 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:30:09,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68838 states. [2024-12-02 06:30:10,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68838 to 39069. [2024-12-02 06:30:10,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39069 states, 38817 states have (on average 1.4100522966741376) internal successors, (54734), 38817 states have internal predecessors, (54734), 250 states have call successors, (250), 1 states have call predecessors, (250), 1 states have return successors, (250), 250 states have call predecessors, (250), 250 states have call successors, (250) [2024-12-02 06:30:10,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39069 states to 39069 states and 55234 transitions. [2024-12-02 06:30:10,062 INFO L78 Accepts]: Start accepts. Automaton has 39069 states and 55234 transitions. Word has length 784 [2024-12-02 06:30:10,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:30:10,062 INFO L471 AbstractCegarLoop]: Abstraction has 39069 states and 55234 transitions. [2024-12-02 06:30:10,062 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 57.77777777777778) internal successors, (520), 9 states have internal predecessors, (520), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:30:10,062 INFO L276 IsEmpty]: Start isEmpty. Operand 39069 states and 55234 transitions. [2024-12-02 06:30:10,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 785 [2024-12-02 06:30:10,086 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:30:10,086 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:30:10,086 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable95 [2024-12-02 06:30:10,086 INFO L396 AbstractCegarLoop]: === Iteration 97 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:30:10,086 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:30:10,086 INFO L85 PathProgramCache]: Analyzing trace with hash 1441320570, now seen corresponding path program 1 times [2024-12-02 06:30:10,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:30:10,087 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413391035] [2024-12-02 06:30:10,087 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:30:10,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:30:13,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:30:16,220 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 78 proven. 0 refuted. 0 times theorem prover too weak. 785 trivial. 0 not checked. [2024-12-02 06:30:16,220 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:30:16,220 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [413391035] [2024-12-02 06:30:16,220 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [413391035] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:30:16,220 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:30:16,220 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:30:16,221 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [697850521] [2024-12-02 06:30:16,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:30:16,221 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:30:16,221 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:30:16,222 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:30:16,222 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:30:16,222 INFO L87 Difference]: Start difference. First operand 39069 states and 55234 transitions. Second operand has 8 states, 8 states have (on average 65.25) internal successors, (522), 8 states have internal predecessors, (522), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:30:16,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:30:16,938 INFO L93 Difference]: Finished difference Result 74560 states and 105508 transitions. [2024-12-02 06:30:16,938 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:30:16,938 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 65.25) internal successors, (522), 8 states have internal predecessors, (522), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 784 [2024-12-02 06:30:16,938 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:30:16,970 INFO L225 Difference]: With dead ends: 74560 [2024-12-02 06:30:16,970 INFO L226 Difference]: Without dead ends: 41733 [2024-12-02 06:30:16,991 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:30:16,991 INFO L435 NwaCegarLoop]: 1215 mSDtfsCounter, 1173 mSDsluCounter, 4544 mSDsCounter, 0 mSdLazyCounter, 174 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1178 SdHoareTripleChecker+Valid, 5759 SdHoareTripleChecker+Invalid, 174 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 174 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:30:16,992 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1178 Valid, 5759 Invalid, 174 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 174 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:30:17,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41733 states. [2024-12-02 06:30:17,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41733 to 41699. [2024-12-02 06:30:17,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41699 states, 41369 states have (on average 1.407019749087481) internal successors, (58207), 41369 states have internal predecessors, (58207), 328 states have call successors, (328), 1 states have call predecessors, (328), 1 states have return successors, (328), 328 states have call predecessors, (328), 328 states have call successors, (328) [2024-12-02 06:30:17,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41699 states to 41699 states and 58863 transitions. [2024-12-02 06:30:17,761 INFO L78 Accepts]: Start accepts. Automaton has 41699 states and 58863 transitions. Word has length 784 [2024-12-02 06:30:17,762 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:30:17,762 INFO L471 AbstractCegarLoop]: Abstraction has 41699 states and 58863 transitions. [2024-12-02 06:30:17,762 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 65.25) internal successors, (522), 8 states have internal predecessors, (522), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:30:17,762 INFO L276 IsEmpty]: Start isEmpty. Operand 41699 states and 58863 transitions. [2024-12-02 06:30:17,787 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 786 [2024-12-02 06:30:17,788 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:30:17,788 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:30:17,788 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable96 [2024-12-02 06:30:17,788 INFO L396 AbstractCegarLoop]: === Iteration 98 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:30:17,788 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:30:17,788 INFO L85 PathProgramCache]: Analyzing trace with hash -104932402, now seen corresponding path program 1 times [2024-12-02 06:30:17,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:30:17,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544496571] [2024-12-02 06:30:17,789 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:30:17,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:30:20,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:30:22,327 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 187 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:30:22,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:30:22,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [544496571] [2024-12-02 06:30:22,328 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [544496571] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:30:22,328 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:30:22,328 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:30:22,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [125539151] [2024-12-02 06:30:22,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:30:22,329 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:30:22,329 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:30:22,329 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:30:22,329 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:30:22,329 INFO L87 Difference]: Start difference. First operand 41699 states and 58863 transitions. Second operand has 8 states, 8 states have (on average 78.25) internal successors, (626), 8 states have internal predecessors, (626), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:30:23,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:30:23,795 INFO L93 Difference]: Finished difference Result 81399 states and 115128 transitions. [2024-12-02 06:30:23,796 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:30:23,796 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 78.25) internal successors, (626), 8 states have internal predecessors, (626), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 785 [2024-12-02 06:30:23,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:30:23,836 INFO L225 Difference]: With dead ends: 81399 [2024-12-02 06:30:23,836 INFO L226 Difference]: Without dead ends: 55706 [2024-12-02 06:30:23,856 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:30:23,857 INFO L435 NwaCegarLoop]: 1224 mSDtfsCounter, 1252 mSDsluCounter, 4433 mSDsCounter, 0 mSdLazyCounter, 1855 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1252 SdHoareTripleChecker+Valid, 5657 SdHoareTripleChecker+Invalid, 1855 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1855 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-12-02 06:30:23,857 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1252 Valid, 5657 Invalid, 1855 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1855 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-12-02 06:30:23,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55706 states. [2024-12-02 06:30:24,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55706 to 49756. [2024-12-02 06:30:24,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49756 states, 49426 states have (on average 1.412758467203496) internal successors, (69827), 49426 states have internal predecessors, (69827), 328 states have call successors, (328), 1 states have call predecessors, (328), 1 states have return successors, (328), 328 states have call predecessors, (328), 328 states have call successors, (328) [2024-12-02 06:30:24,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49756 states to 49756 states and 70483 transitions. [2024-12-02 06:30:24,757 INFO L78 Accepts]: Start accepts. Automaton has 49756 states and 70483 transitions. Word has length 785 [2024-12-02 06:30:24,758 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:30:24,758 INFO L471 AbstractCegarLoop]: Abstraction has 49756 states and 70483 transitions. [2024-12-02 06:30:24,758 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 78.25) internal successors, (626), 8 states have internal predecessors, (626), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:30:24,758 INFO L276 IsEmpty]: Start isEmpty. Operand 49756 states and 70483 transitions. [2024-12-02 06:30:24,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 786 [2024-12-02 06:30:24,786 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:30:24,787 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:30:24,787 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable97 [2024-12-02 06:30:24,787 INFO L396 AbstractCegarLoop]: === Iteration 99 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:30:24,787 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:30:24,787 INFO L85 PathProgramCache]: Analyzing trace with hash -368196338, now seen corresponding path program 1 times [2024-12-02 06:30:24,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:30:24,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209643435] [2024-12-02 06:30:24,787 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:30:24,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:30:29,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:30:31,637 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 181 proven. 0 refuted. 0 times theorem prover too weak. 682 trivial. 0 not checked. [2024-12-02 06:30:31,637 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:30:31,637 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209643435] [2024-12-02 06:30:31,637 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1209643435] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:30:31,637 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:30:31,637 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:30:31,637 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1446187668] [2024-12-02 06:30:31,637 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:30:31,637 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:30:31,637 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:30:31,638 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:30:31,638 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:30:31,638 INFO L87 Difference]: Start difference. First operand 49756 states and 70483 transitions. Second operand has 6 states, 6 states have (on average 103.83333333333333) internal successors, (623), 6 states have internal predecessors, (623), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:30:32,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:30:32,566 INFO L93 Difference]: Finished difference Result 103614 states and 146444 transitions. [2024-12-02 06:30:32,566 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:30:32,566 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 103.83333333333333) internal successors, (623), 6 states have internal predecessors, (623), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 785 [2024-12-02 06:30:32,566 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:30:32,615 INFO L225 Difference]: With dead ends: 103614 [2024-12-02 06:30:32,615 INFO L226 Difference]: Without dead ends: 70678 [2024-12-02 06:30:32,638 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:30:32,638 INFO L435 NwaCegarLoop]: 1083 mSDtfsCounter, 763 mSDsluCounter, 4182 mSDsCounter, 0 mSdLazyCounter, 45 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 763 SdHoareTripleChecker+Valid, 5265 SdHoareTripleChecker+Invalid, 45 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 45 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:30:32,638 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [763 Valid, 5265 Invalid, 45 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 45 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:30:32,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70678 states. [2024-12-02 06:30:33,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70678 to 65779. [2024-12-02 06:30:33,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65779 states, 65269 states have (on average 1.4135960409995556) internal successors, (92264), 65269 states have internal predecessors, (92264), 508 states have call successors, (508), 1 states have call predecessors, (508), 1 states have return successors, (508), 508 states have call predecessors, (508), 508 states have call successors, (508) [2024-12-02 06:30:33,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65779 states to 65779 states and 93280 transitions. [2024-12-02 06:30:33,676 INFO L78 Accepts]: Start accepts. Automaton has 65779 states and 93280 transitions. Word has length 785 [2024-12-02 06:30:33,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:30:33,677 INFO L471 AbstractCegarLoop]: Abstraction has 65779 states and 93280 transitions. [2024-12-02 06:30:33,677 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 103.83333333333333) internal successors, (623), 6 states have internal predecessors, (623), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:30:33,677 INFO L276 IsEmpty]: Start isEmpty. Operand 65779 states and 93280 transitions. [2024-12-02 06:30:33,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 787 [2024-12-02 06:30:33,720 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:30:33,720 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:30:33,720 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable98 [2024-12-02 06:30:33,720 INFO L396 AbstractCegarLoop]: === Iteration 100 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:30:33,720 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:30:33,721 INFO L85 PathProgramCache]: Analyzing trace with hash -17148143, now seen corresponding path program 1 times [2024-12-02 06:30:33,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:30:33,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1474730827] [2024-12-02 06:30:33,721 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:30:33,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:30:38,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:30:41,172 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 126 proven. 62 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:30:41,172 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:30:41,172 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1474730827] [2024-12-02 06:30:41,172 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1474730827] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:30:41,172 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [276970380] [2024-12-02 06:30:41,172 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:30:41,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:30:41,173 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:30:41,174 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:30:41,175 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2024-12-02 06:30:48,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:30:48,201 INFO L256 TraceCheckSpWp]: Trace formula consists of 3715 conjuncts, 192 conjuncts are in the unsatisfiable core [2024-12-02 06:30:48,214 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:30:50,902 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 269 proven. 44 refuted. 0 times theorem prover too weak. 551 trivial. 0 not checked. [2024-12-02 06:30:50,903 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:30:55,505 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 113 proven. 75 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:30:55,506 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [276970380] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:30:55,506 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:30:55,506 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 37, 30] total 71 [2024-12-02 06:30:55,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [209260424] [2024-12-02 06:30:55,506 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:30:55,507 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 71 states [2024-12-02 06:30:55,507 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:30:55,508 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2024-12-02 06:30:55,509 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=977, Invalid=3993, Unknown=0, NotChecked=0, Total=4970 [2024-12-02 06:30:55,509 INFO L87 Difference]: Start difference. First operand 65779 states and 93280 transitions. Second operand has 71 states, 71 states have (on average 23.056338028169016) internal successors, (1637), 71 states have internal predecessors, (1637), 11 states have call successors, (30), 2 states have call predecessors, (30), 2 states have return successors, (30), 11 states have call predecessors, (30), 11 states have call successors, (30) [2024-12-02 06:31:17,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:31:17,954 INFO L93 Difference]: Finished difference Result 230030 states and 326279 transitions. [2024-12-02 06:31:17,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 121 states. [2024-12-02 06:31:17,955 INFO L78 Accepts]: Start accepts. Automaton has has 71 states, 71 states have (on average 23.056338028169016) internal successors, (1637), 71 states have internal predecessors, (1637), 11 states have call successors, (30), 2 states have call predecessors, (30), 2 states have return successors, (30), 11 states have call predecessors, (30), 11 states have call successors, (30) Word has length 786 [2024-12-02 06:31:17,955 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:31:18,099 INFO L225 Difference]: With dead ends: 230030 [2024-12-02 06:31:18,099 INFO L226 Difference]: Without dead ends: 196469 [2024-12-02 06:31:18,148 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1704 GetRequests, 1516 SyntacticMatches, 0 SemanticMatches, 188 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10105 ImplicationChecksByTransitivity, 6.4s TimeCoverageRelationStatistics Valid=6135, Invalid=29775, Unknown=0, NotChecked=0, Total=35910 [2024-12-02 06:31:18,148 INFO L435 NwaCegarLoop]: 1203 mSDtfsCounter, 11468 mSDsluCounter, 40210 mSDsCounter, 0 mSdLazyCounter, 31539 mSolverCounterSat, 96 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 12.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 11468 SdHoareTripleChecker+Valid, 41413 SdHoareTripleChecker+Invalid, 31635 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 96 IncrementalHoareTripleChecker+Valid, 31539 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 14.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:31:18,148 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [11468 Valid, 41413 Invalid, 31635 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [96 Valid, 31539 Invalid, 0 Unknown, 0 Unchecked, 14.4s Time] [2024-12-02 06:31:18,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196469 states. [2024-12-02 06:31:20,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196469 to 77719. [2024-12-02 06:31:20,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77719 states, 77077 states have (on average 1.4012091804299596) internal successors, (108001), 77077 states have internal predecessors, (108001), 640 states have call successors, (640), 1 states have call predecessors, (640), 1 states have return successors, (640), 640 states have call predecessors, (640), 640 states have call successors, (640) [2024-12-02 06:31:20,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77719 states to 77719 states and 109281 transitions. [2024-12-02 06:31:20,359 INFO L78 Accepts]: Start accepts. Automaton has 77719 states and 109281 transitions. Word has length 786 [2024-12-02 06:31:20,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:31:20,360 INFO L471 AbstractCegarLoop]: Abstraction has 77719 states and 109281 transitions. [2024-12-02 06:31:20,360 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 71 states, 71 states have (on average 23.056338028169016) internal successors, (1637), 71 states have internal predecessors, (1637), 11 states have call successors, (30), 2 states have call predecessors, (30), 2 states have return successors, (30), 11 states have call predecessors, (30), 11 states have call successors, (30) [2024-12-02 06:31:20,360 INFO L276 IsEmpty]: Start isEmpty. Operand 77719 states and 109281 transitions. [2024-12-02 06:31:20,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 788 [2024-12-02 06:31:20,416 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:31:20,417 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:31:20,448 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Forceful destruction successful, exit code 0 [2024-12-02 06:31:20,617 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 40 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable99 [2024-12-02 06:31:20,617 INFO L396 AbstractCegarLoop]: === Iteration 101 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:31:20,617 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:31:20,618 INFO L85 PathProgramCache]: Analyzing trace with hash 183695983, now seen corresponding path program 1 times [2024-12-02 06:31:20,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:31:20,618 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1914574088] [2024-12-02 06:31:20,618 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:31:20,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:31:25,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:31:26,905 INFO L134 CoverageAnalysis]: Checked inductivity of 865 backedges. 132 proven. 3 refuted. 0 times theorem prover too weak. 730 trivial. 0 not checked. [2024-12-02 06:31:26,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:31:26,906 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1914574088] [2024-12-02 06:31:26,906 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1914574088] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:31:26,906 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1284542038] [2024-12-02 06:31:26,906 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:31:26,906 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:31:26,906 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:31:26,907 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:31:26,908 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2024-12-02 06:31:37,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:31:37,758 INFO L256 TraceCheckSpWp]: Trace formula consists of 3716 conjuncts, 224 conjuncts are in the unsatisfiable core [2024-12-02 06:31:37,771 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:31:42,371 INFO L134 CoverageAnalysis]: Checked inductivity of 865 backedges. 280 proven. 56 refuted. 0 times theorem prover too weak. 529 trivial. 0 not checked. [2024-12-02 06:31:42,371 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:31:51,259 INFO L134 CoverageAnalysis]: Checked inductivity of 865 backedges. 146 proven. 79 refuted. 0 times theorem prover too weak. 640 trivial. 0 not checked. [2024-12-02 06:31:51,259 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1284542038] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:31:51,259 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:31:51,259 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 37, 39] total 80 [2024-12-02 06:31:51,259 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2063828033] [2024-12-02 06:31:51,259 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:31:51,260 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 80 states [2024-12-02 06:31:51,260 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:31:51,261 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2024-12-02 06:31:51,261 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1102, Invalid=5218, Unknown=0, NotChecked=0, Total=6320 [2024-12-02 06:31:51,262 INFO L87 Difference]: Start difference. First operand 77719 states and 109281 transitions. Second operand has 80 states, 80 states have (on average 20.0375) internal successors, (1603), 80 states have internal predecessors, (1603), 10 states have call successors, (26), 2 states have call predecessors, (26), 2 states have return successors, (26), 10 states have call predecessors, (26), 10 states have call successors, (26) [2024-12-02 06:32:08,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:32:08,091 INFO L93 Difference]: Finished difference Result 191829 states and 269967 transitions. [2024-12-02 06:32:08,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2024-12-02 06:32:08,091 INFO L78 Accepts]: Start accepts. Automaton has has 80 states, 80 states have (on average 20.0375) internal successors, (1603), 80 states have internal predecessors, (1603), 10 states have call successors, (26), 2 states have call predecessors, (26), 2 states have return successors, (26), 10 states have call predecessors, (26), 10 states have call successors, (26) Word has length 787 [2024-12-02 06:32:08,092 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:32:08,187 INFO L225 Difference]: With dead ends: 191829 [2024-12-02 06:32:08,187 INFO L226 Difference]: Without dead ends: 125187 [2024-12-02 06:32:08,236 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1637 GetRequests, 1502 SyntacticMatches, 0 SemanticMatches, 135 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5108 ImplicationChecksByTransitivity, 5.6s TimeCoverageRelationStatistics Valid=3112, Invalid=15520, Unknown=0, NotChecked=0, Total=18632 [2024-12-02 06:32:08,237 INFO L435 NwaCegarLoop]: 1236 mSDtfsCounter, 13669 mSDsluCounter, 42394 mSDsCounter, 0 mSdLazyCounter, 22750 mSolverCounterSat, 61 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 10.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 13687 SdHoareTripleChecker+Valid, 43630 SdHoareTripleChecker+Invalid, 22811 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 61 IncrementalHoareTripleChecker+Valid, 22750 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 11.9s IncrementalHoareTripleChecker+Time [2024-12-02 06:32:08,237 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [13687 Valid, 43630 Invalid, 22811 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [61 Valid, 22750 Invalid, 0 Unknown, 0 Unchecked, 11.9s Time] [2024-12-02 06:32:08,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125187 states. [2024-12-02 06:32:09,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125187 to 78987. [2024-12-02 06:32:09,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78987 states, 78293 states have (on average 1.3987585097007396) internal successors, (109513), 78293 states have internal predecessors, (109513), 692 states have call successors, (692), 1 states have call predecessors, (692), 1 states have return successors, (692), 692 states have call predecessors, (692), 692 states have call successors, (692) [2024-12-02 06:32:10,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78987 states to 78987 states and 110897 transitions. [2024-12-02 06:32:10,049 INFO L78 Accepts]: Start accepts. Automaton has 78987 states and 110897 transitions. Word has length 787 [2024-12-02 06:32:10,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:32:10,050 INFO L471 AbstractCegarLoop]: Abstraction has 78987 states and 110897 transitions. [2024-12-02 06:32:10,050 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 80 states, 80 states have (on average 20.0375) internal successors, (1603), 80 states have internal predecessors, (1603), 10 states have call successors, (26), 2 states have call predecessors, (26), 2 states have return successors, (26), 10 states have call predecessors, (26), 10 states have call successors, (26) [2024-12-02 06:32:10,050 INFO L276 IsEmpty]: Start isEmpty. Operand 78987 states and 110897 transitions. [2024-12-02 06:32:10,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 789 [2024-12-02 06:32:10,098 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:32:10,099 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:32:10,128 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Forceful destruction successful, exit code 0 [2024-12-02 06:32:10,299 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 41 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable100 [2024-12-02 06:32:10,299 INFO L396 AbstractCegarLoop]: === Iteration 102 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:32:10,299 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:32:10,299 INFO L85 PathProgramCache]: Analyzing trace with hash -82452987, now seen corresponding path program 1 times [2024-12-02 06:32:10,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:32:10,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432119444] [2024-12-02 06:32:10,300 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:32:10,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:32:14,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:32:16,076 INFO L134 CoverageAnalysis]: Checked inductivity of 866 backedges. 122 proven. 4 refuted. 0 times theorem prover too weak. 740 trivial. 0 not checked. [2024-12-02 06:32:16,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:32:16,076 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432119444] [2024-12-02 06:32:16,076 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [432119444] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:32:16,076 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [486970241] [2024-12-02 06:32:16,076 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:32:16,076 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:32:16,076 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:32:16,078 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:32:16,078 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2024-12-02 06:32:25,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:32:25,450 INFO L256 TraceCheckSpWp]: Trace formula consists of 3719 conjuncts, 245 conjuncts are in the unsatisfiable core [2024-12-02 06:32:25,463 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:32:31,863 INFO L134 CoverageAnalysis]: Checked inductivity of 866 backedges. 164 proven. 137 refuted. 0 times theorem prover too weak. 565 trivial. 0 not checked. [2024-12-02 06:32:31,863 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:32:40,806 INFO L134 CoverageAnalysis]: Checked inductivity of 866 backedges. 154 proven. 99 refuted. 0 times theorem prover too weak. 613 trivial. 0 not checked. [2024-12-02 06:32:40,807 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [486970241] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:32:40,807 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:32:40,807 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 46, 42] total 88 [2024-12-02 06:32:40,807 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109286001] [2024-12-02 06:32:40,807 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:32:40,808 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 88 states [2024-12-02 06:32:40,808 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:32:40,809 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2024-12-02 06:32:40,809 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1803, Invalid=5853, Unknown=0, NotChecked=0, Total=7656 [2024-12-02 06:32:40,810 INFO L87 Difference]: Start difference. First operand 78987 states and 110897 transitions. Second operand has 88 states, 86 states have (on average 18.069767441860463) internal successors, (1554), 88 states have internal predecessors, (1554), 12 states have call successors, (26), 2 states have call predecessors, (26), 3 states have return successors, (26), 10 states have call predecessors, (26), 12 states have call successors, (26) [2024-12-02 06:32:52,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:32:52,228 INFO L93 Difference]: Finished difference Result 151081 states and 212265 transitions. [2024-12-02 06:32:52,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2024-12-02 06:32:52,228 INFO L78 Accepts]: Start accepts. Automaton has has 88 states, 86 states have (on average 18.069767441860463) internal successors, (1554), 88 states have internal predecessors, (1554), 12 states have call successors, (26), 2 states have call predecessors, (26), 3 states have return successors, (26), 10 states have call predecessors, (26), 12 states have call successors, (26) Word has length 788 [2024-12-02 06:32:52,229 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:32:52,297 INFO L225 Difference]: With dead ends: 151081 [2024-12-02 06:32:52,297 INFO L226 Difference]: Without dead ends: 83187 [2024-12-02 06:32:52,326 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1637 GetRequests, 1496 SyntacticMatches, 0 SemanticMatches, 141 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6599 ImplicationChecksByTransitivity, 6.0s TimeCoverageRelationStatistics Valid=4246, Invalid=16060, Unknown=0, NotChecked=0, Total=20306 [2024-12-02 06:32:52,327 INFO L435 NwaCegarLoop]: 822 mSDtfsCounter, 10482 mSDsluCounter, 23295 mSDsCounter, 0 mSdLazyCounter, 13767 mSolverCounterSat, 81 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 6.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 10500 SdHoareTripleChecker+Valid, 24117 SdHoareTripleChecker+Invalid, 13848 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 81 IncrementalHoareTripleChecker+Valid, 13767 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 7.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:32:52,327 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [10500 Valid, 24117 Invalid, 13848 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [81 Valid, 13767 Invalid, 0 Unknown, 0 Unchecked, 7.2s Time] [2024-12-02 06:32:52,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83187 states. [2024-12-02 06:32:53,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83187 to 78663. [2024-12-02 06:32:53,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78663 states, 77969 states have (on average 1.3990303838705127) internal successors, (109081), 77969 states have internal predecessors, (109081), 692 states have call successors, (692), 1 states have call predecessors, (692), 1 states have return successors, (692), 692 states have call predecessors, (692), 692 states have call successors, (692) [2024-12-02 06:32:54,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78663 states to 78663 states and 110465 transitions. [2024-12-02 06:32:54,201 INFO L78 Accepts]: Start accepts. Automaton has 78663 states and 110465 transitions. Word has length 788 [2024-12-02 06:32:54,201 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:32:54,202 INFO L471 AbstractCegarLoop]: Abstraction has 78663 states and 110465 transitions. [2024-12-02 06:32:54,202 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 88 states, 86 states have (on average 18.069767441860463) internal successors, (1554), 88 states have internal predecessors, (1554), 12 states have call successors, (26), 2 states have call predecessors, (26), 3 states have return successors, (26), 10 states have call predecessors, (26), 12 states have call successors, (26) [2024-12-02 06:32:54,202 INFO L276 IsEmpty]: Start isEmpty. Operand 78663 states and 110465 transitions. [2024-12-02 06:32:54,255 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 789 [2024-12-02 06:32:54,255 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:32:54,255 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:32:54,288 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Ended with exit code 0 [2024-12-02 06:32:54,455 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 42 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable101 [2024-12-02 06:32:54,455 INFO L396 AbstractCegarLoop]: === Iteration 103 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:32:54,456 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:32:54,456 INFO L85 PathProgramCache]: Analyzing trace with hash 1285803048, now seen corresponding path program 1 times [2024-12-02 06:32:54,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:32:54,456 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1629798800] [2024-12-02 06:32:54,456 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:32:54,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:32:59,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:33:03,079 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:33:03,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:33:03,079 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1629798800] [2024-12-02 06:33:03,079 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1629798800] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:33:03,079 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:33:03,080 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2024-12-02 06:33:03,080 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39269435] [2024-12-02 06:33:03,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:33:03,080 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 06:33:03,080 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:33:03,081 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 06:33:03,081 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:33:03,081 INFO L87 Difference]: Start difference. First operand 78663 states and 110465 transitions. Second operand has 10 states, 10 states have (on average 62.9) internal successors, (629), 10 states have internal predecessors, (629), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:33:05,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:05,353 INFO L93 Difference]: Finished difference Result 165431 states and 231606 transitions. [2024-12-02 06:33:05,353 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-12-02 06:33:05,353 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 62.9) internal successors, (629), 10 states have internal predecessors, (629), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 788 [2024-12-02 06:33:05,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:05,430 INFO L225 Difference]: With dead ends: 165431 [2024-12-02 06:33:05,430 INFO L226 Difference]: Without dead ends: 122701 [2024-12-02 06:33:05,454 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=39, Invalid=171, Unknown=0, NotChecked=0, Total=210 [2024-12-02 06:33:05,454 INFO L435 NwaCegarLoop]: 1958 mSDtfsCounter, 1132 mSDsluCounter, 14753 mSDsCounter, 0 mSdLazyCounter, 236 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1137 SdHoareTripleChecker+Valid, 16711 SdHoareTripleChecker+Invalid, 238 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 236 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:05,454 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1137 Valid, 16711 Invalid, 238 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 236 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:33:05,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122701 states. [2024-12-02 06:33:07,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122701 to 81391. [2024-12-02 06:33:07,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81391 states, 80653 states have (on average 1.3965134588917958) internal successors, (112633), 80653 states have internal predecessors, (112633), 736 states have call successors, (736), 1 states have call predecessors, (736), 1 states have return successors, (736), 736 states have call predecessors, (736), 736 states have call successors, (736) [2024-12-02 06:33:07,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81391 states to 81391 states and 114105 transitions. [2024-12-02 06:33:07,439 INFO L78 Accepts]: Start accepts. Automaton has 81391 states and 114105 transitions. Word has length 788 [2024-12-02 06:33:07,439 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:07,439 INFO L471 AbstractCegarLoop]: Abstraction has 81391 states and 114105 transitions. [2024-12-02 06:33:07,439 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 62.9) internal successors, (629), 10 states have internal predecessors, (629), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:33:07,439 INFO L276 IsEmpty]: Start isEmpty. Operand 81391 states and 114105 transitions. [2024-12-02 06:33:07,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 789 [2024-12-02 06:33:07,488 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:07,489 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:07,489 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable102 [2024-12-02 06:33:07,489 INFO L396 AbstractCegarLoop]: === Iteration 104 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:07,489 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:07,489 INFO L85 PathProgramCache]: Analyzing trace with hash -1448408228, now seen corresponding path program 1 times [2024-12-02 06:33:07,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:33:07,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143245306] [2024-12-02 06:33:07,489 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:33:07,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:33:10,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:33:13,351 INFO L134 CoverageAnalysis]: Checked inductivity of 866 backedges. 177 proven. 0 refuted. 0 times theorem prover too weak. 689 trivial. 0 not checked. [2024-12-02 06:33:13,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:33:13,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143245306] [2024-12-02 06:33:13,352 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2143245306] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:33:13,352 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:33:13,352 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:33:13,352 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [671849723] [2024-12-02 06:33:13,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:33:13,352 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:33:13,352 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:33:13,353 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:33:13,353 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:33:13,353 INFO L87 Difference]: Start difference. First operand 81391 states and 114105 transitions. Second operand has 5 states, 5 states have (on average 124.0) internal successors, (620), 5 states have internal predecessors, (620), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2024-12-02 06:33:14,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:14,221 INFO L93 Difference]: Finished difference Result 100954 states and 141226 transitions. [2024-12-02 06:33:14,221 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:33:14,221 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 124.0) internal successors, (620), 5 states have internal predecessors, (620), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) Word has length 788 [2024-12-02 06:33:14,222 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:14,268 INFO L225 Difference]: With dead ends: 100954 [2024-12-02 06:33:14,268 INFO L226 Difference]: Without dead ends: 49241 [2024-12-02 06:33:14,300 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:33:14,301 INFO L435 NwaCegarLoop]: 1069 mSDtfsCounter, 117 mSDsluCounter, 2995 mSDsCounter, 0 mSdLazyCounter, 40 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 117 SdHoareTripleChecker+Valid, 4064 SdHoareTripleChecker+Invalid, 41 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 40 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:14,301 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [117 Valid, 4064 Invalid, 41 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 40 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:33:14,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49241 states. [2024-12-02 06:33:15,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49241 to 45227. [2024-12-02 06:33:15,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45227 states, 44749 states have (on average 1.3919417193680306) internal successors, (62288), 44749 states have internal predecessors, (62288), 476 states have call successors, (476), 1 states have call predecessors, (476), 1 states have return successors, (476), 476 states have call predecessors, (476), 476 states have call successors, (476) [2024-12-02 06:33:15,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45227 states to 45227 states and 63240 transitions. [2024-12-02 06:33:15,376 INFO L78 Accepts]: Start accepts. Automaton has 45227 states and 63240 transitions. Word has length 788 [2024-12-02 06:33:15,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:15,376 INFO L471 AbstractCegarLoop]: Abstraction has 45227 states and 63240 transitions. [2024-12-02 06:33:15,376 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 124.0) internal successors, (620), 5 states have internal predecessors, (620), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2024-12-02 06:33:15,376 INFO L276 IsEmpty]: Start isEmpty. Operand 45227 states and 63240 transitions. [2024-12-02 06:33:15,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 790 [2024-12-02 06:33:15,406 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:15,406 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:15,406 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable103 [2024-12-02 06:33:15,406 INFO L396 AbstractCegarLoop]: === Iteration 105 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:15,406 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:15,406 INFO L85 PathProgramCache]: Analyzing trace with hash -1816274519, now seen corresponding path program 1 times [2024-12-02 06:33:15,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:33:15,406 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1617104467] [2024-12-02 06:33:15,407 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:33:15,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:33:17,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:33:20,299 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-12-02 06:33:20,299 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:33:20,299 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1617104467] [2024-12-02 06:33:20,299 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1617104467] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:33:20,299 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:33:20,299 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2024-12-02 06:33:20,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1450649594] [2024-12-02 06:33:20,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:33:20,300 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 06:33:20,300 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:33:20,300 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 06:33:20,300 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=61, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:33:20,301 INFO L87 Difference]: Start difference. First operand 45227 states and 63240 transitions. Second operand has 10 states, 10 states have (on average 63.0) internal successors, (630), 10 states have internal predecessors, (630), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:33:22,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:22,214 INFO L93 Difference]: Finished difference Result 118228 states and 165201 transitions. [2024-12-02 06:33:22,215 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:33:22,215 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 63.0) internal successors, (630), 10 states have internal predecessors, (630), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 789 [2024-12-02 06:33:22,215 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:22,297 INFO L225 Difference]: With dead ends: 118228 [2024-12-02 06:33:22,297 INFO L226 Difference]: Without dead ends: 98961 [2024-12-02 06:33:22,328 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=74, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:33:22,329 INFO L435 NwaCegarLoop]: 988 mSDtfsCounter, 2397 mSDsluCounter, 6414 mSDsCounter, 0 mSdLazyCounter, 808 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2407 SdHoareTripleChecker+Valid, 7402 SdHoareTripleChecker+Invalid, 809 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 808 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:22,329 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2407 Valid, 7402 Invalid, 809 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 808 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 06:33:22,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98961 states. [2024-12-02 06:33:23,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98961 to 72698. [2024-12-02 06:33:23,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72698 states, 71932 states have (on average 1.392467886337096) internal successors, (100163), 71932 states have internal predecessors, (100163), 764 states have call successors, (764), 1 states have call predecessors, (764), 1 states have return successors, (764), 764 states have call predecessors, (764), 764 states have call successors, (764) [2024-12-02 06:33:24,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72698 states to 72698 states and 101691 transitions. [2024-12-02 06:33:24,064 INFO L78 Accepts]: Start accepts. Automaton has 72698 states and 101691 transitions. Word has length 789 [2024-12-02 06:33:24,064 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:24,064 INFO L471 AbstractCegarLoop]: Abstraction has 72698 states and 101691 transitions. [2024-12-02 06:33:24,064 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 63.0) internal successors, (630), 10 states have internal predecessors, (630), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:33:24,064 INFO L276 IsEmpty]: Start isEmpty. Operand 72698 states and 101691 transitions. [2024-12-02 06:33:24,117 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 790 [2024-12-02 06:33:24,117 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:24,117 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:24,117 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable104 [2024-12-02 06:33:24,117 INFO L396 AbstractCegarLoop]: === Iteration 106 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:24,118 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:24,118 INFO L85 PathProgramCache]: Analyzing trace with hash 1143463848, now seen corresponding path program 1 times [2024-12-02 06:33:24,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:33:24,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694407705] [2024-12-02 06:33:24,118 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:33:24,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:33:31,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 06:33:31,839 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 06:33:38,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 06:33:39,370 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-12-02 06:33:39,371 INFO L340 BasicCegarLoop]: Counterexample is feasible [2024-12-02 06:33:39,372 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-12-02 06:33:39,373 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable105 [2024-12-02 06:33:39,377 INFO L422 BasicCegarLoop]: Path program histogram: [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:39,745 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-12-02 06:33:39,748 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.12 06:33:39 BoogieIcfgContainer [2024-12-02 06:33:39,748 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-12-02 06:33:39,749 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-12-02 06:33:39,749 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-12-02 06:33:39,749 INFO L274 PluginConnector]: Witness Printer initialized [2024-12-02 06:33:39,749 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:22:59" (3/4) ... [2024-12-02 06:33:39,751 INFO L149 WitnessPrinter]: No result that supports witness generation found [2024-12-02 06:33:39,752 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-12-02 06:33:39,753 INFO L158 Benchmark]: Toolchain (without parser) took 644043.61ms. Allocated memory was 142.6MB in the beginning and 5.2GB in the end (delta: 5.1GB). Free memory was 116.0MB in the beginning and 1.4GB in the end (delta: -1.3GB). Peak memory consumption was 3.8GB. Max. memory is 16.1GB. [2024-12-02 06:33:39,753 INFO L158 Benchmark]: CDTParser took 0.37ms. Allocated memory is still 142.6MB. Free memory is still 82.9MB. There was no memory consumed. Max. memory is 16.1GB. [2024-12-02 06:33:39,753 INFO L158 Benchmark]: CACSL2BoogieTranslator took 479.23ms. Allocated memory is still 142.6MB. Free memory was 115.8MB in the beginning and 75.3MB in the end (delta: 40.5MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2024-12-02 06:33:39,753 INFO L158 Benchmark]: Boogie Procedure Inliner took 241.06ms. Allocated memory is still 142.6MB. Free memory was 75.0MB in the beginning and 68.8MB in the end (delta: 6.2MB). Peak memory consumption was 42.4MB. Max. memory is 16.1GB. [2024-12-02 06:33:39,754 INFO L158 Benchmark]: Boogie Preprocessor took 304.11ms. Allocated memory is still 142.6MB. Free memory was 68.8MB in the beginning and 70.8MB in the end (delta: -2.0MB). Peak memory consumption was 44.2MB. Max. memory is 16.1GB. [2024-12-02 06:33:39,754 INFO L158 Benchmark]: RCFGBuilder took 2990.08ms. Allocated memory was 142.6MB in the beginning and 318.8MB in the end (delta: 176.2MB). Free memory was 70.8MB in the beginning and 208.1MB in the end (delta: -137.3MB). Peak memory consumption was 175.4MB. Max. memory is 16.1GB. [2024-12-02 06:33:39,754 INFO L158 Benchmark]: TraceAbstraction took 640019.76ms. Allocated memory was 318.8MB in the beginning and 5.2GB in the end (delta: 4.9GB). Free memory was 208.1MB in the beginning and 1.4GB in the end (delta: -1.2GB). Peak memory consumption was 3.7GB. Max. memory is 16.1GB. [2024-12-02 06:33:39,754 INFO L158 Benchmark]: Witness Printer took 3.88ms. Allocated memory is still 5.2GB. Free memory was 1.4GB in the beginning and 1.4GB in the end (delta: 4.5MB). There was no memory consumed. Max. memory is 16.1GB. [2024-12-02 06:33:39,754 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.37ms. Allocated memory is still 142.6MB. Free memory is still 82.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 479.23ms. Allocated memory is still 142.6MB. Free memory was 115.8MB in the beginning and 75.3MB in the end (delta: 40.5MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 241.06ms. Allocated memory is still 142.6MB. Free memory was 75.0MB in the beginning and 68.8MB in the end (delta: 6.2MB). Peak memory consumption was 42.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 304.11ms. Allocated memory is still 142.6MB. Free memory was 68.8MB in the beginning and 70.8MB in the end (delta: -2.0MB). Peak memory consumption was 44.2MB. Max. memory is 16.1GB. * RCFGBuilder took 2990.08ms. Allocated memory was 142.6MB in the beginning and 318.8MB in the end (delta: 176.2MB). Free memory was 70.8MB in the beginning and 208.1MB in the end (delta: -137.3MB). Peak memory consumption was 175.4MB. Max. memory is 16.1GB. * TraceAbstraction took 640019.76ms. Allocated memory was 318.8MB in the beginning and 5.2GB in the end (delta: 4.9GB). Free memory was 208.1MB in the beginning and 1.4GB in the end (delta: -1.2GB). Peak memory consumption was 3.7GB. Max. memory is 16.1GB. * Witness Printer took 3.88ms. Allocated memory is still 5.2GB. Free memory was 1.4GB in the beginning and 1.4GB in the end (delta: 4.5MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 21]: Unable to prove that a call to reach_error is unreachable Unable to prove that a call to reach_error is unreachable Reason: overapproximation of bitwiseOr at line 142, overapproximation of bitwiseOr at line 391, overapproximation of bitwiseOr at line 208, overapproximation of bitwiseOr at line 178, overapproximation of bitwiseAnd at line 303, overapproximation of bitwiseAnd at line 220, overapproximation of bitwiseAnd at line 253, overapproximation of bitwiseAnd at line 256, overapproximation of bitwiseAnd at line 648, overapproximation of bitwiseAnd at line 632, overapproximation of bitwiseAnd at line 613, overapproximation of bitwiseAnd at line 569, overapproximation of bitwiseAnd at line 128, overapproximation of bitwiseAnd at line 148, overapproximation of bitwiseAnd at line 759, overapproximation of bitwiseAnd at line 493, overapproximation of bitwiseAnd at line 396, overapproximation of bitwiseAnd at line 266. Possible FailurePath: [L26] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L27] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L29] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 16); [L30] const SORT_3 msb_SORT_3 = (SORT_3)1 << (16 - 1); [L32] const SORT_5 mask_SORT_5 = (SORT_5)-1 >> (sizeof(SORT_5) * 8 - 2); [L33] const SORT_5 msb_SORT_5 = (SORT_5)1 << (2 - 1); [L35] const SORT_11 mask_SORT_11 = (SORT_11)-1 >> (sizeof(SORT_11) * 8 - 8); [L36] const SORT_11 msb_SORT_11 = (SORT_11)1 << (8 - 1); [L38] const SORT_12 mask_SORT_12 = (SORT_12)-1 >> (sizeof(SORT_12) * 8 - 3); [L39] const SORT_12 msb_SORT_12 = (SORT_12)1 << (3 - 1); [L42] const SORT_15 mask_SORT_15 = (SORT_15)-1 >> (sizeof(SORT_15) * 8 - 4); [L43] const SORT_15 msb_SORT_15 = (SORT_15)1 << (4 - 1); [L45] const SORT_36 mask_SORT_36 = (SORT_36)-1 >> (sizeof(SORT_36) * 8 - 5); [L46] const SORT_36 msb_SORT_36 = (SORT_36)1 << (5 - 1); [L48] const SORT_38 mask_SORT_38 = (SORT_38)-1 >> (sizeof(SORT_38) * 8 - 6); [L49] const SORT_38 msb_SORT_38 = (SORT_38)1 << (6 - 1); [L51] const SORT_40 mask_SORT_40 = (SORT_40)-1 >> (sizeof(SORT_40) * 8 - 7); [L52] const SORT_40 msb_SORT_40 = (SORT_40)1 << (7 - 1); [L54] const SORT_227 mask_SORT_227 = (SORT_227)-1 >> (sizeof(SORT_227) * 8 - 32); [L55] const SORT_227 msb_SORT_227 = (SORT_227)1 << (32 - 1); [L57] const SORT_15 var_27 = 8; [L58] const SORT_15 var_97 = 0; [L59] const SORT_1 var_107 = 1; [L60] const SORT_1 var_108 = 0; [L61] const SORT_11 var_181 = 0; [L62] const SORT_227 var_228 = 2; [L63] const SORT_11 var_408 = 255; [L65] SORT_1 input_2; [L66] SORT_3 input_4; [L67] SORT_5 input_6; [L68] SORT_3 input_7; [L69] SORT_5 input_8; [L70] SORT_1 input_9; [L71] SORT_1 input_10; [L73] SORT_13 state_14; [L74] unsigned char i = 0; VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] COND TRUE i < (1 << 3) VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] COND TRUE i < (1 << 3) VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] COND TRUE i < (1 << 3) VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] COND TRUE i < (1 << 3) VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] COND TRUE i < (1 << 3) VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] COND TRUE i < (1 << 3) VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] COND TRUE i < (1 << 3) VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] COND TRUE i < (1 << 3) VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L74] COND FALSE !(i < (1 << 3)) VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L75] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L75] SORT_15 state_16 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L76] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L76] SORT_15 state_19 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L77] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L77] SORT_11 state_26 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L78] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L78] SORT_1 state_31 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L79] SORT_13 state_44; [L80] unsigned char i = 0; VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] COND TRUE i < (1 << 3) VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] COND TRUE i < (1 << 3) VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] COND TRUE i < (1 << 3) VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] COND TRUE i < (1 << 3) VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] COND TRUE i < (1 << 3) VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] COND TRUE i < (1 << 3) VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] COND TRUE i < (1 << 3) VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] COND TRUE i < (1 << 3) VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L80] COND FALSE !(i < (1 << 3)) VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L81] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L81] SORT_15 state_45 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L82] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L82] SORT_15 state_48 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L83] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L83] SORT_11 state_55 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L84] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L84] SORT_1 state_83 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L85] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L85] SORT_1 state_84 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L86] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L86] SORT_15 state_87 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L87] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L87] SORT_11 state_103 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L88] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L88] SORT_1 state_109 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L89] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L89] SORT_1 state_331 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L90] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L90] SORT_1 state_332 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L91] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L91] SORT_1 state_333 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L92] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L92] SORT_1 state_334 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L93] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L93] SORT_1 state_335 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L94] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L94] SORT_1 state_336 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L95] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L95] SORT_1 state_337 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L96] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L96] SORT_1 state_338 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L98] SORT_1 init_110_arg_1 = var_107; [L99] state_109 = init_110_arg_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L102] input_2 = __VERIFIER_nondet_uchar() [L103] input_4 = __VERIFIER_nondet_ushort() [L104] input_6 = __VERIFIER_nondet_uchar() [L105] input_7 = __VERIFIER_nondet_ushort() [L106] input_8 = __VERIFIER_nondet_uchar() [L107] input_9 = __VERIFIER_nondet_uchar() [L108] EXPR input_9 & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L108] input_9 = input_9 & mask_SORT_1 [L109] input_10 = __VERIFIER_nondet_uchar() [L111] SORT_15 var_52_arg_0 = state_48; [L112] SORT_15 var_52_arg_1 = state_45; [L113] SORT_1 var_52 = var_52_arg_0 == var_52_arg_1; [L114] SORT_1 var_115_arg_0 = var_52; [L115] SORT_1 var_115 = ~var_115_arg_0; [L116] SORT_5 var_51_arg_0 = input_8; [L117] SORT_1 var_51 = var_51_arg_0 >> 0; [L118] SORT_1 var_116_arg_0 = var_51; [L119] SORT_1 var_116 = ~var_116_arg_0; [L120] SORT_1 var_117_arg_0 = var_115; [L121] SORT_1 var_117_arg_1 = var_116; VAL [input_8=-255, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_117_arg_0=-2, var_117_arg_1=-2, var_181=0, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L122] EXPR var_117_arg_0 | var_117_arg_1 VAL [input_8=-255, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L122] SORT_1 var_117 = var_117_arg_0 | var_117_arg_1; [L123] SORT_1 var_118_arg_0 = var_107; [L124] SORT_1 var_118 = ~var_118_arg_0; [L125] SORT_1 var_119_arg_0 = var_117; [L126] SORT_1 var_119_arg_1 = var_118; VAL [input_8=-255, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_119_arg_0=254, var_119_arg_1=-2, var_181=0, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L127] EXPR var_119_arg_0 | var_119_arg_1 VAL [input_8=-255, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L127] SORT_1 var_119 = var_119_arg_0 | var_119_arg_1; [L128] EXPR var_119 & mask_SORT_1 VAL [input_8=-255, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L128] var_119 = var_119 & mask_SORT_1 [L129] SORT_1 constr_120_arg_0 = var_119; VAL [constr_120_arg_0=1, input_8=-255, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L130] CALL assume_abort_if_not(constr_120_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L130] RET assume_abort_if_not(constr_120_arg_0) VAL [constr_120_arg_0=1, input_8=-255, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L131] SORT_15 var_23_arg_0 = state_19; [L132] SORT_15 var_23_arg_1 = state_16; [L133] SORT_1 var_23 = var_23_arg_0 == var_23_arg_1; [L134] SORT_1 var_121_arg_0 = var_23; [L135] SORT_1 var_121 = ~var_121_arg_0; [L136] SORT_5 var_22_arg_0 = input_8; [L137] SORT_1 var_22 = var_22_arg_0 >> 1; [L138] SORT_1 var_122_arg_0 = var_22; [L139] SORT_1 var_122 = ~var_122_arg_0; [L140] SORT_1 var_123_arg_0 = var_121; [L141] SORT_1 var_123_arg_1 = var_122; VAL [constr_120_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_123_arg_0=-2, var_123_arg_1=-1, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L142] EXPR var_123_arg_0 | var_123_arg_1 VAL [constr_120_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L142] SORT_1 var_123 = var_123_arg_0 | var_123_arg_1; [L143] SORT_1 var_124_arg_0 = var_107; [L144] SORT_1 var_124 = ~var_124_arg_0; [L145] SORT_1 var_125_arg_0 = var_123; [L146] SORT_1 var_125_arg_1 = var_124; VAL [constr_120_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_125_arg_0=256, var_125_arg_1=-2, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L147] EXPR var_125_arg_0 | var_125_arg_1 VAL [constr_120_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L147] SORT_1 var_125 = var_125_arg_0 | var_125_arg_1; [L148] EXPR var_125 & mask_SORT_1 VAL [constr_120_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L148] var_125 = var_125 & mask_SORT_1 [L149] SORT_1 constr_126_arg_0 = var_125; VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L150] CALL assume_abort_if_not(constr_126_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L150] RET assume_abort_if_not(constr_126_arg_0) VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L151] SORT_15 var_73_arg_0 = state_48; [L152] SORT_1 var_73 = var_73_arg_0 >> 3; VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_73=0, var_97=0] [L153] EXPR var_73 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L153] var_73 = var_73 & mask_SORT_1 [L154] SORT_15 var_74_arg_0 = state_45; [L155] SORT_1 var_74 = var_74_arg_0 >> 3; VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_73=0, var_74=0, var_97=0] [L156] EXPR var_74 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_73=0, var_97=0] [L156] var_74 = var_74 & mask_SORT_1 [L157] SORT_1 var_75_arg_0 = var_73; [L158] SORT_1 var_75_arg_1 = var_74; [L159] SORT_1 var_75 = var_75_arg_0 != var_75_arg_1; [L160] SORT_1 var_76_arg_0 = var_52; [L161] SORT_1 var_76_arg_1 = var_75; VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_76_arg_0=1, var_76_arg_1=0, var_97=0] [L162] EXPR var_76_arg_0 & var_76_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L162] SORT_1 var_76 = var_76_arg_0 & var_76_arg_1; [L163] EXPR var_76 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L163] var_76 = var_76 & mask_SORT_1 [L164] SORT_1 var_127_arg_0 = var_76; [L165] SORT_1 var_127 = ~var_127_arg_0; [L166] SORT_5 var_90_arg_0 = input_6; [L167] SORT_1 var_90 = var_90_arg_0 >> 0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_127=-1, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L168] EXPR var_90 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_127=-1, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L168] var_90 = var_90 & mask_SORT_1 [L169] SORT_1 var_128_arg_0 = var_90; [L170] SORT_1 var_128 = ~var_128_arg_0; [L171] SORT_1 var_129_arg_0 = var_127; [L172] SORT_1 var_129_arg_1 = var_128; VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_129_arg_0=-1, var_129_arg_1=-1, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L173] EXPR var_129_arg_0 | var_129_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L173] SORT_1 var_129 = var_129_arg_0 | var_129_arg_1; [L174] SORT_1 var_130_arg_0 = var_107; [L175] SORT_1 var_130 = ~var_130_arg_0; [L176] SORT_1 var_131_arg_0 = var_129; [L177] SORT_1 var_131_arg_1 = var_130; VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_131_arg_0=255, var_131_arg_1=-2, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L178] EXPR var_131_arg_0 | var_131_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L178] SORT_1 var_131 = var_131_arg_0 | var_131_arg_1; [L179] EXPR var_131 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L179] var_131 = var_131 & mask_SORT_1 [L180] SORT_1 constr_132_arg_0 = var_131; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L181] CALL assume_abort_if_not(constr_132_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L181] RET assume_abort_if_not(constr_132_arg_0) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L182] SORT_15 var_77_arg_0 = state_19; [L183] SORT_1 var_77 = var_77_arg_0 >> 3; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_77=0, var_90=0, var_97=0] [L184] EXPR var_77 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L184] var_77 = var_77 & mask_SORT_1 [L185] SORT_15 var_78_arg_0 = state_16; [L186] SORT_1 var_78 = var_78_arg_0 >> 3; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_77=0, var_78=0, var_90=0, var_97=0] [L187] EXPR var_78 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_77=0, var_90=0, var_97=0] [L187] var_78 = var_78 & mask_SORT_1 [L188] SORT_1 var_79_arg_0 = var_77; [L189] SORT_1 var_79_arg_1 = var_78; [L190] SORT_1 var_79 = var_79_arg_0 != var_79_arg_1; [L191] SORT_1 var_80_arg_0 = var_23; [L192] SORT_1 var_80_arg_1 = var_79; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_80_arg_0=1, var_80_arg_1=0, var_90=0, var_97=0] [L193] EXPR var_80_arg_0 & var_80_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L193] SORT_1 var_80 = var_80_arg_0 & var_80_arg_1; [L194] SORT_1 var_133_arg_0 = var_80; [L195] SORT_1 var_133 = ~var_133_arg_0; [L196] SORT_5 var_134_arg_0 = input_6; [L197] SORT_1 var_134 = var_134_arg_0 >> 1; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_133=-1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L198] EXPR var_134 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_133=-1, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L198] var_134 = var_134 & mask_SORT_1 [L199] SORT_1 var_135_arg_0 = var_134; [L200] SORT_1 var_135 = ~var_135_arg_0; [L201] SORT_1 var_136_arg_0 = var_133; [L202] SORT_1 var_136_arg_1 = var_135; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_136_arg_0=-1, var_136_arg_1=-1, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L203] EXPR var_136_arg_0 | var_136_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L203] SORT_1 var_136 = var_136_arg_0 | var_136_arg_1; [L204] SORT_1 var_137_arg_0 = var_107; [L205] SORT_1 var_137 = ~var_137_arg_0; [L206] SORT_1 var_138_arg_0 = var_136; [L207] SORT_1 var_138_arg_1 = var_137; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_138_arg_0=255, var_138_arg_1=-2, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L208] EXPR var_138_arg_0 | var_138_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L208] SORT_1 var_138 = var_138_arg_0 | var_138_arg_1; [L209] EXPR var_138 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L209] var_138 = var_138 & mask_SORT_1 [L210] SORT_1 constr_139_arg_0 = var_138; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L211] CALL assume_abort_if_not(constr_139_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L211] RET assume_abort_if_not(constr_139_arg_0) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L212] SORT_1 var_140_arg_0 = state_109; [L213] SORT_1 var_140_arg_1 = input_9; [L214] SORT_1 var_140 = var_140_arg_0 == var_140_arg_1; [L215] SORT_1 var_141_arg_0 = var_107; [L216] SORT_1 var_141 = ~var_141_arg_0; [L217] SORT_1 var_142_arg_0 = var_140; [L218] SORT_1 var_142_arg_1 = var_141; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_142_arg_0=0, var_142_arg_1=-2, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L219] EXPR var_142_arg_0 | var_142_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L219] SORT_1 var_142 = var_142_arg_0 | var_142_arg_1; [L220] EXPR var_142 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L220] var_142 = var_142 & mask_SORT_1 [L221] SORT_1 constr_143_arg_0 = var_142; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L222] CALL assume_abort_if_not(constr_143_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L222] RET assume_abort_if_not(constr_143_arg_0) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L224] SORT_1 var_111_arg_0 = state_109; [L225] SORT_1 var_111_arg_1 = var_108; [L226] SORT_1 var_111_arg_2 = var_107; [L227] SORT_1 var_111 = var_111_arg_0 ? var_111_arg_1 : var_111_arg_2; [L228] SORT_1 var_85_arg_0 = state_84; [L229] SORT_1 var_85 = ~var_85_arg_0; [L230] SORT_1 var_86_arg_0 = state_83; [L231] SORT_1 var_86_arg_1 = var_85; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_86_arg_0=0, var_86_arg_1=-1, var_90=0, var_97=0] [L232] EXPR var_86_arg_0 & var_86_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L232] SORT_1 var_86 = var_86_arg_0 & var_86_arg_1; [L233] SORT_15 var_88_arg_0 = state_87; [L234] SORT_1 var_88 = var_88_arg_0 != 0; [L235] SORT_1 var_89_arg_0 = var_86; [L236] SORT_1 var_89_arg_1 = var_88; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_89_arg_0=0, var_89_arg_1=0, var_90=0, var_97=0] [L237] EXPR var_89_arg_0 & var_89_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L237] SORT_1 var_89 = var_89_arg_0 & var_89_arg_1; [L238] SORT_1 var_91_arg_0 = state_83; [L239] SORT_1 var_91 = ~var_91_arg_0; [L240] SORT_1 var_92_arg_0 = var_90; [L241] SORT_1 var_92_arg_1 = var_91; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_89=0, var_90=0, var_91=-1, var_92_arg_0=0, var_92_arg_1=-1, var_97=0] [L242] EXPR var_92_arg_0 & var_92_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_89=0, var_90=0, var_91=-1, var_97=0] [L242] SORT_1 var_92 = var_92_arg_0 & var_92_arg_1; [L243] SORT_1 var_93_arg_0 = var_92; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_89=0, var_90=0, var_91=-1, var_93_arg_0=0, var_97=0] [L244] EXPR var_93_arg_0 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_89=0, var_90=0, var_91=-1, var_97=0] [L244] var_93_arg_0 = var_93_arg_0 & mask_SORT_1 [L245] SORT_15 var_93 = var_93_arg_0; [L246] SORT_15 var_94_arg_0 = state_87; [L247] SORT_15 var_94_arg_1 = var_93; [L248] SORT_15 var_94 = var_94_arg_0 + var_94_arg_1; [L249] SORT_1 var_53_arg_0 = var_52; [L250] SORT_1 var_53 = ~var_53_arg_0; [L251] SORT_1 var_54_arg_0 = var_51; [L252] SORT_1 var_54_arg_1 = var_53; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54_arg_0=1, var_54_arg_1=-2, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L253] EXPR var_54_arg_0 & var_54_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L253] SORT_1 var_54 = var_54_arg_0 & var_54_arg_1; [L254] EXPR var_54 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L254] var_54 = var_54 & mask_SORT_1 [L255] SORT_15 var_56_arg_0 = var_27; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_56_arg_0=8, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L256] EXPR var_56_arg_0 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L256] var_56_arg_0 = var_56_arg_0 & mask_SORT_15 [L257] SORT_11 var_56 = var_56_arg_0; [L258] SORT_11 var_57_arg_0 = state_55; [L259] SORT_11 var_57_arg_1 = var_56; [L260] SORT_1 var_57 = var_57_arg_0 >= var_57_arg_1; [L261] SORT_1 var_58_arg_0 = var_54; [L262] SORT_1 var_58_arg_1 = var_57; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_58_arg_0=0, var_58_arg_1=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L263] EXPR var_58_arg_0 & var_58_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L263] SORT_1 var_58 = var_58_arg_0 & var_58_arg_1; [L264] SORT_1 var_59_arg_0 = state_31; [L265] SORT_1 var_59 = ~var_59_arg_0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_58=0, var_59=-1, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L266] EXPR var_59 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_58=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L266] var_59 = var_59 & mask_SORT_1 [L267] SORT_1 var_60_arg_0 = var_58; [L268] SORT_1 var_60_arg_1 = var_59; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60_arg_0=0, var_60_arg_1=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L269] EXPR var_60_arg_0 & var_60_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L269] SORT_1 var_60 = var_60_arg_0 & var_60_arg_1; [L270] EXPR var_60 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L270] var_60 = var_60 & mask_SORT_1 [L271] SORT_1 var_95_arg_0 = var_60; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_95_arg_0=0, var_97=0] [L272] EXPR var_95_arg_0 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L272] var_95_arg_0 = var_95_arg_0 & mask_SORT_1 [L273] SORT_15 var_95 = var_95_arg_0; [L274] SORT_15 var_96_arg_0 = var_94; [L275] SORT_15 var_96_arg_1 = var_95; [L276] SORT_15 var_96 = var_96_arg_0 - var_96_arg_1; [L277] SORT_1 var_98_arg_0 = input_9; [L278] SORT_15 var_98_arg_1 = var_97; [L279] SORT_15 var_98_arg_2 = var_96; [L280] SORT_15 var_98 = var_98_arg_0 ? var_98_arg_1 : var_98_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_89=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L281] EXPR var_98 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_89=0, var_90=0, var_91=-1, var_97=0] [L281] var_98 = var_98 & mask_SORT_15 [L282] SORT_15 var_99_arg_0 = var_98; [L283] SORT_1 var_99 = var_99_arg_0 != 0; [L284] SORT_1 var_100_arg_0 = var_99; [L285] SORT_1 var_100 = ~var_100_arg_0; [L286] SORT_1 var_101_arg_0 = var_89; [L287] SORT_1 var_101_arg_1 = var_100; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101_arg_0=0, var_101_arg_1=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L288] EXPR var_101_arg_0 & var_101_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L288] SORT_1 var_101 = var_101_arg_0 & var_101_arg_1; [L289] SORT_1 var_102_arg_0 = var_101; [L290] SORT_1 var_102 = ~var_102_arg_0; [L291] SORT_15 var_20_arg_0 = state_19; [L292] SORT_12 var_20 = var_20_arg_0 >> 0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_20=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L293] EXPR var_20 & mask_SORT_12 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L293] var_20 = var_20 & mask_SORT_12 [L294] SORT_11* var_21_arg_0 = state_14; [L295] SORT_12 var_21_arg_1 = var_20; [L296] EXPR var_21_arg_0[(unsigned char) var_21_arg_1] [L296] SORT_11 var_21 = var_21_arg_0[(unsigned char) var_21_arg_1]; [L297] SORT_1 var_24_arg_0 = var_23; [L298] SORT_1 var_24 = ~var_24_arg_0; [L299] SORT_1 var_25_arg_0 = var_22; [L300] SORT_1 var_25_arg_1 = var_24; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25_arg_0=0, var_25_arg_1=-2, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L301] EXPR var_25_arg_0 & var_25_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L301] SORT_1 var_25 = var_25_arg_0 & var_25_arg_1; [L302] SORT_15 var_28_arg_0 = var_27; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_28_arg_0=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L303] EXPR var_28_arg_0 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L303] var_28_arg_0 = var_28_arg_0 & mask_SORT_15 [L304] SORT_11 var_28 = var_28_arg_0; [L305] SORT_11 var_29_arg_0 = state_26; [L306] SORT_11 var_29_arg_1 = var_28; [L307] SORT_1 var_29 = var_29_arg_0 >= var_29_arg_1; [L308] SORT_1 var_30_arg_0 = var_25; [L309] SORT_1 var_30_arg_1 = var_29; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_30_arg_0=0, var_30_arg_1=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L310] EXPR var_30_arg_0 & var_30_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L310] SORT_1 var_30 = var_30_arg_0 & var_30_arg_1; [L311] SORT_1 var_32_arg_0 = var_30; [L312] SORT_1 var_32_arg_1 = state_31; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32_arg_0=0, var_32_arg_1=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L313] EXPR var_32_arg_0 & var_32_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L313] SORT_1 var_32 = var_32_arg_0 & var_32_arg_1; [L314] EXPR var_32 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L314] var_32 = var_32 & mask_SORT_1 [L315] SORT_1 var_33_arg_0 = var_32; [L316] SORT_1 var_33_arg_1 = var_32; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_33_arg_0=0, var_33_arg_1=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L317] EXPR ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L317] SORT_5 var_33 = ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1; [L318] EXPR var_33 & mask_SORT_5 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L318] var_33 = var_33 & mask_SORT_5 [L319] SORT_1 var_34_arg_0 = var_32; [L320] SORT_5 var_34_arg_1 = var_33; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_34_arg_0=0, var_34_arg_1=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L321] EXPR ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L321] SORT_12 var_34 = ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1; [L322] EXPR var_34 & mask_SORT_12 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L322] var_34 = var_34 & mask_SORT_12 [L323] SORT_1 var_35_arg_0 = var_32; [L324] SORT_12 var_35_arg_1 = var_34; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_35_arg_0=0, var_35_arg_1=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L325] EXPR ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L325] SORT_15 var_35 = ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1; [L326] EXPR var_35 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L326] var_35 = var_35 & mask_SORT_15 [L327] SORT_1 var_37_arg_0 = var_32; [L328] SORT_15 var_37_arg_1 = var_35; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_37_arg_0=0, var_37_arg_1=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L329] EXPR ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L329] SORT_36 var_37 = ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1; [L330] EXPR var_37 & mask_SORT_36 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L330] var_37 = var_37 & mask_SORT_36 [L331] SORT_1 var_39_arg_0 = var_32; [L332] SORT_36 var_39_arg_1 = var_37; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_39_arg_0=0, var_39_arg_1=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L333] EXPR ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L333] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1; [L334] EXPR var_39 & mask_SORT_38 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L334] var_39 = var_39 & mask_SORT_38 [L335] SORT_1 var_41_arg_0 = var_32; [L336] SORT_38 var_41_arg_1 = var_39; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_41_arg_0=0, var_41_arg_1=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L337] EXPR ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L337] SORT_40 var_41 = ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1; [L338] EXPR var_41 & mask_SORT_40 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L338] var_41 = var_41 & mask_SORT_40 [L339] SORT_1 var_42_arg_0 = var_32; [L340] SORT_40 var_42_arg_1 = var_41; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_42_arg_0=0, var_42_arg_1=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L341] EXPR ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L341] SORT_11 var_42 = ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1; [L342] SORT_11 var_43_arg_0 = var_21; [L343] SORT_11 var_43_arg_1 = var_42; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43_arg_0=0, var_43_arg_1=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L344] EXPR var_43_arg_0 & var_43_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L344] SORT_11 var_43 = var_43_arg_0 & var_43_arg_1; [L345] SORT_15 var_49_arg_0 = state_48; [L346] SORT_12 var_49 = var_49_arg_0 >> 0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_49=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L347] EXPR var_49 & mask_SORT_12 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L347] var_49 = var_49 & mask_SORT_12 [L348] SORT_11* var_50_arg_0 = state_44; [L349] SORT_12 var_50_arg_1 = var_49; [L350] EXPR var_50_arg_0[(unsigned char) var_50_arg_1] [L350] SORT_11 var_50 = var_50_arg_0[(unsigned char) var_50_arg_1]; [L351] EXPR var_50 & mask_SORT_11 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L351] var_50 = var_50 & mask_SORT_11 [L352] SORT_1 var_61_arg_0 = var_60; [L353] SORT_1 var_61_arg_1 = var_60; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_61_arg_0=0, var_61_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L354] EXPR ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L354] SORT_5 var_61 = ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1; [L355] EXPR var_61 & mask_SORT_5 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L355] var_61 = var_61 & mask_SORT_5 [L356] SORT_1 var_62_arg_0 = var_60; [L357] SORT_5 var_62_arg_1 = var_61; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_62_arg_0=0, var_62_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L358] EXPR ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L358] SORT_12 var_62 = ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1; [L359] EXPR var_62 & mask_SORT_12 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L359] var_62 = var_62 & mask_SORT_12 [L360] SORT_1 var_63_arg_0 = var_60; [L361] SORT_12 var_63_arg_1 = var_62; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_63_arg_0=0, var_63_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L362] EXPR ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L362] SORT_15 var_63 = ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1; [L363] EXPR var_63 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L363] var_63 = var_63 & mask_SORT_15 [L364] SORT_1 var_64_arg_0 = var_60; [L365] SORT_15 var_64_arg_1 = var_63; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_64_arg_0=0, var_64_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L366] EXPR ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L366] SORT_36 var_64 = ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1; [L367] EXPR var_64 & mask_SORT_36 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L367] var_64 = var_64 & mask_SORT_36 [L368] SORT_1 var_65_arg_0 = var_60; [L369] SORT_36 var_65_arg_1 = var_64; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_65_arg_0=0, var_65_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L370] EXPR ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L370] SORT_38 var_65 = ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1; [L371] EXPR var_65 & mask_SORT_38 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L371] var_65 = var_65 & mask_SORT_38 [L372] SORT_1 var_66_arg_0 = var_60; [L373] SORT_38 var_66_arg_1 = var_65; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_66_arg_0=0, var_66_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L374] EXPR ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L374] SORT_40 var_66 = ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1; [L375] EXPR var_66 & mask_SORT_40 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L375] var_66 = var_66 & mask_SORT_40 [L376] SORT_1 var_67_arg_0 = var_60; [L377] SORT_40 var_67_arg_1 = var_66; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_67_arg_0=0, var_67_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L378] EXPR ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L378] SORT_11 var_67 = ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1; [L379] SORT_11 var_68_arg_0 = var_50; [L380] SORT_11 var_68_arg_1 = var_67; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_54=0, var_59=0, var_60=0, var_68_arg_0=0, var_68_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L381] EXPR var_68_arg_0 & var_68_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L381] SORT_11 var_68 = var_68_arg_0 & var_68_arg_1; [L382] SORT_11 var_69_arg_0 = var_43; [L383] SORT_11 var_69_arg_1 = var_68; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_69_arg_0=0, var_69_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L384] EXPR var_69_arg_0 | var_69_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L384] SORT_11 var_69 = var_69_arg_0 | var_69_arg_1; [L385] EXPR var_69 & mask_SORT_11 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L385] var_69 = var_69 & mask_SORT_11 [L386] SORT_11 var_104_arg_0 = state_103; [L387] SORT_11 var_104_arg_1 = var_69; [L388] SORT_1 var_104 = var_104_arg_0 == var_104_arg_1; [L389] SORT_1 var_105_arg_0 = var_102; [L390] SORT_1 var_105_arg_1 = var_104; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_105_arg_0=-1, var_105_arg_1=1, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L391] EXPR var_105_arg_0 | var_105_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_111=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L391] SORT_1 var_105 = var_105_arg_0 | var_105_arg_1; [L392] SORT_1 var_112_arg_0 = var_105; [L393] SORT_1 var_112 = ~var_112_arg_0; [L394] SORT_1 var_113_arg_0 = var_111; [L395] SORT_1 var_113_arg_1 = var_112; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_113_arg_0=0, var_113_arg_1=-256, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L396] EXPR var_113_arg_0 & var_113_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L396] SORT_1 var_113 = var_113_arg_0 & var_113_arg_1; [L397] EXPR var_113 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L397] var_113 = var_113 & mask_SORT_1 [L398] SORT_1 bad_114_arg_0 = var_113; [L399] CALL __VERIFIER_assert(!(bad_114_arg_0)) [L21] COND FALSE !(!(cond)) [L399] RET __VERIFIER_assert(!(bad_114_arg_0)) [L401] SORT_1 var_296_arg_0 = var_134; [L402] SORT_1 var_296_arg_1 = var_32; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_296_arg_0=0, var_296_arg_1=0, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L403] EXPR var_296_arg_0 | var_296_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L403] SORT_1 var_296 = var_296_arg_0 | var_296_arg_1; [L404] SORT_1 var_297_arg_0 = var_296; [L405] SORT_1 var_297_arg_1 = input_9; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_297_arg_0=0, var_297_arg_1=0, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L406] EXPR var_297_arg_0 | var_297_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L406] SORT_1 var_297 = var_297_arg_0 | var_297_arg_1; [L407] EXPR var_297 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L407] var_297 = var_297 & mask_SORT_1 [L408] SORT_1 var_308_arg_0 = var_134; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_297=0, var_308_arg_0=0, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L409] EXPR var_308_arg_0 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_297=0, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L409] var_308_arg_0 = var_308_arg_0 & mask_SORT_1 [L410] SORT_15 var_308 = var_308_arg_0; [L411] SORT_15 var_309_arg_0 = state_16; [L412] SORT_15 var_309_arg_1 = var_308; [L413] SORT_15 var_309 = var_309_arg_0 + var_309_arg_1; [L414] SORT_1 var_402_arg_0 = var_297; [L415] SORT_15 var_402_arg_1 = var_309; [L416] SORT_15 var_402_arg_2 = state_16; [L417] SORT_15 var_402 = var_402_arg_0 ? var_402_arg_1 : var_402_arg_2; [L418] SORT_1 var_403_arg_0 = input_9; [L419] SORT_15 var_403_arg_1 = var_97; [L420] SORT_15 var_403_arg_2 = var_402; [L421] SORT_15 var_403 = var_403_arg_0 ? var_403_arg_1 : var_403_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_297=0, var_32=0, var_403=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L422] EXPR var_403 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_297=0, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L422] var_403 = var_403 & mask_SORT_15 [L423] SORT_15 next_404_arg_1 = var_403; [L424] SORT_1 var_302_arg_0 = var_32; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_297=0, var_302_arg_0=0, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L425] EXPR var_302_arg_0 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_297=0, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L425] var_302_arg_0 = var_302_arg_0 & mask_SORT_1 [L426] SORT_15 var_302 = var_302_arg_0; [L427] SORT_15 var_303_arg_0 = state_19; [L428] SORT_15 var_303_arg_1 = var_302; [L429] SORT_15 var_303 = var_303_arg_0 + var_303_arg_1; [L430] SORT_1 var_405_arg_0 = var_297; [L431] SORT_15 var_405_arg_1 = var_303; [L432] SORT_15 var_405_arg_2 = state_19; [L433] SORT_15 var_405 = var_405_arg_0 ? var_405_arg_1 : var_405_arg_2; [L434] SORT_1 var_406_arg_0 = input_9; [L435] SORT_15 var_406_arg_1 = var_97; [L436] SORT_15 var_406_arg_2 = var_405; [L437] SORT_15 var_406 = var_406_arg_0 ? var_406_arg_1 : var_406_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, state_103=0, state_14={10:0}, state_16=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_406=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L438] EXPR var_406 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, state_103=0, state_14={10:0}, state_16=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L438] var_406 = var_406 & mask_SORT_15 [L439] SORT_15 next_407_arg_1 = var_406; [L440] SORT_11 var_415_arg_0 = var_408; [L441] SORT_1 var_415 = var_415_arg_0 != 0; [L442] SORT_15 var_17_arg_0 = state_16; [L443] SORT_12 var_17 = var_17_arg_0 >> 0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_17=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L444] EXPR var_17 & mask_SORT_12 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L444] var_17 = var_17 & mask_SORT_12 [L445] SORT_3 var_256_arg_0 = input_4; [L446] SORT_11 var_256 = var_256_arg_0 >> 8; [L447] SORT_11* var_18_arg_0 = state_14; [L448] SORT_12 var_18_arg_1 = var_17; [L449] EXPR var_18_arg_0[(unsigned char) var_18_arg_1] [L449] SORT_11 var_18 = var_18_arg_0[(unsigned char) var_18_arg_1]; [L450] SORT_1 var_315_arg_0 = var_134; [L451] SORT_11 var_315_arg_1 = var_256; [L452] SORT_11 var_315_arg_2 = var_18; [L453] SORT_11 var_315 = var_315_arg_0 ? var_315_arg_1 : var_315_arg_2; [L454] SORT_11 var_412_arg_0 = var_315; [L455] SORT_11 var_412_arg_1 = var_408; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_17=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_412_arg_0=0, var_412_arg_1=255, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L456] EXPR var_412_arg_0 & var_412_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_17=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L456] SORT_11 var_412 = var_412_arg_0 & var_412_arg_1; [L457] SORT_11* var_409_arg_0 = state_14; [L458] SORT_12 var_409_arg_1 = var_17; [L459] EXPR var_409_arg_0[(unsigned char) var_409_arg_1] [L459] SORT_11 var_409 = var_409_arg_0[(unsigned char) var_409_arg_1]; [L460] SORT_11 var_410_arg_0 = var_408; [L461] SORT_11 var_410 = ~var_410_arg_0; [L462] SORT_11 var_411_arg_0 = var_409; [L463] SORT_11 var_411_arg_1 = var_410; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_17=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_411_arg_0=0, var_411_arg_1=-256, var_412=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L464] EXPR var_411_arg_0 & var_411_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_17=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_412=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L464] SORT_11 var_411 = var_411_arg_0 & var_411_arg_1; [L465] SORT_11 var_413_arg_0 = var_412; [L466] SORT_11 var_413_arg_1 = var_411; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_17=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_413_arg_0=0, var_413_arg_1=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L467] EXPR var_413_arg_0 | var_413_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_17=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L467] SORT_11 var_413 = var_413_arg_0 | var_413_arg_1; [L468] SORT_11* var_414_arg_0 = state_14; [L469] SORT_12 var_414_arg_1 = var_17; [L470] SORT_11 var_414_arg_2 = var_413; [L471] SORT_13 var_414; [L472] unsigned char i = 0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=0, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=0, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] EXPR var_414_arg_0[i] [L472] var_414[i] = var_414_arg_0[i] [L472] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] EXPR var_414_arg_0[i] [L472] var_414[i] = var_414_arg_0[i] [L472] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=2, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=2, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] EXPR var_414_arg_0[i] [L472] var_414[i] = var_414_arg_0[i] [L472] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=3, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=3, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] EXPR var_414_arg_0[i] [L472] var_414[i] = var_414_arg_0[i] [L472] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=4, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=4, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] EXPR var_414_arg_0[i] [L472] var_414[i] = var_414_arg_0[i] [L472] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=5, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=5, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] EXPR var_414_arg_0[i] [L472] var_414[i] = var_414_arg_0[i] [L472] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=6, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=6, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] EXPR var_414_arg_0[i] [L472] var_414[i] = var_414_arg_0[i] [L472] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=7, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=7, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] EXPR var_414_arg_0[i] [L472] var_414[i] = var_414_arg_0[i] [L472] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=8, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L472] COND FALSE !(i < (1 << 3)) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414={13:0}, var_414_arg_0={10:0}, var_414_arg_1=0, var_414_arg_2=0, var_415=1, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L473] var_414[(unsigned char) var_414_arg_1] = var_414_arg_2 [L474] SORT_1 var_416_arg_0 = var_415; [L475] SORT_11* var_416_arg_1 = var_414; [L476] SORT_11* var_416_arg_2 = state_14; [L477] SORT_11* var_416 = var_416_arg_0 ? var_416_arg_1 : var_416_arg_2; [L478] SORT_11* next_417_arg_1 = var_416; [L479] SORT_1 var_155_arg_0 = var_25; [L480] SORT_1 var_155_arg_1 = var_54; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155_arg_0=0, var_155_arg_1=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L481] EXPR ((SORT_5)var_155_arg_0 << 1) | var_155_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L481] SORT_5 var_155 = ((SORT_5)var_155_arg_0 << 1) | var_155_arg_1; [L482] EXPR var_155 & mask_SORT_5 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L482] var_155 = var_155 & mask_SORT_5 [L483] SORT_1 var_160_arg_0 = state_31; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155=0, var_160_arg_0=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L484] EXPR var_160_arg_0 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L484] var_160_arg_0 = var_160_arg_0 & mask_SORT_1 [L485] SORT_5 var_160 = var_160_arg_0; [L486] SORT_1 var_161_arg_0 = var_107; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155=0, var_160=0, var_161_arg_0=1, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L487] EXPR var_161_arg_0 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155=0, var_160=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L487] var_161_arg_0 = var_161_arg_0 & mask_SORT_1 [L488] SORT_5 var_161 = var_161_arg_0; [L489] SORT_5 var_162_arg_0 = var_160; [L490] SORT_5 var_162_arg_1 = var_161; [L491] SORT_5 var_162 = var_162_arg_0 + var_162_arg_1; [L492] SORT_5 var_163_arg_0 = var_162; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155=0, var_163_arg_0=1, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L493] EXPR var_163_arg_0 & mask_SORT_5 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L493] var_163_arg_0 = var_163_arg_0 & mask_SORT_5 [L494] SORT_12 var_163 = var_163_arg_0; [L495] SORT_1 var_164_arg_0 = var_107; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155=0, var_163=0, var_164_arg_0=1, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L496] EXPR var_164_arg_0 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155=0, var_163=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L496] var_164_arg_0 = var_164_arg_0 & mask_SORT_1 [L497] SORT_12 var_164 = var_164_arg_0; [L498] SORT_12 var_165_arg_0 = var_163; [L499] SORT_12 var_165_arg_1 = var_164; [L500] SORT_12 var_165 = var_165_arg_0 + var_165_arg_1; [L501] SORT_12 var_166_arg_0 = var_165; [L502] SORT_1 var_166 = var_166_arg_0 >> 0; [L503] SORT_1 var_167_arg_0 = var_166; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155=0, var_166=1, var_167_arg_0=1, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L504] EXPR var_167_arg_0 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155=0, var_166=1, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L504] var_167_arg_0 = var_167_arg_0 & mask_SORT_1 [L505] SORT_5 var_167 = var_167_arg_0; [L506] SORT_5 var_168_arg_0 = var_155; [L507] SORT_5 var_168_arg_1 = var_167; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155=0, var_166=1, var_168_arg_0=0, var_168_arg_1=1, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L508] EXPR var_168_arg_0 >> var_168_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155=0, var_166=1, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L508] SORT_5 var_168 = var_168_arg_0 >> var_168_arg_1; [L509] SORT_5 var_169_arg_0 = var_168; [L510] SORT_1 var_169 = var_169_arg_0 >> 0; [L511] SORT_1 var_150_arg_0 = var_108; [L512] SORT_1 var_150_arg_1 = state_31; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_150_arg_0=0, var_150_arg_1=0, var_155=0, var_166=1, var_169=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L513] EXPR ((SORT_5)var_150_arg_0 << 1) | var_150_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155=0, var_166=1, var_169=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L513] SORT_5 var_150 = ((SORT_5)var_150_arg_0 << 1) | var_150_arg_1; [L514] SORT_5 var_151_arg_0 = var_150; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_151_arg_0=0, var_155=0, var_166=1, var_169=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L515] EXPR var_151_arg_0 & mask_SORT_5 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_155=0, var_166=1, var_169=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L515] var_151_arg_0 = var_151_arg_0 & mask_SORT_5 [L516] SORT_12 var_151 = var_151_arg_0; [L517] SORT_1 var_152_arg_0 = var_107; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_151=0, var_152_arg_0=1, var_155=0, var_166=1, var_169=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L518] EXPR var_152_arg_0 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_151=0, var_155=0, var_166=1, var_169=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L518] var_152_arg_0 = var_152_arg_0 & mask_SORT_1 [L519] SORT_12 var_152 = var_152_arg_0; [L520] SORT_12 var_153_arg_0 = var_151; [L521] SORT_12 var_153_arg_1 = var_152; [L522] SORT_12 var_153 = var_153_arg_0 + var_153_arg_1; [L523] SORT_12 var_154_arg_0 = var_153; [L524] SORT_1 var_154 = var_154_arg_0 >> 0; [L525] SORT_1 var_156_arg_0 = var_154; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_154=1, var_155=0, var_156_arg_0=1, var_166=1, var_169=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L526] EXPR var_156_arg_0 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_154=1, var_155=0, var_166=1, var_169=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L526] var_156_arg_0 = var_156_arg_0 & mask_SORT_1 [L527] SORT_5 var_156 = var_156_arg_0; [L528] SORT_5 var_157_arg_0 = var_155; [L529] SORT_5 var_157_arg_1 = var_156; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_154=1, var_157_arg_0=0, var_157_arg_1=1, var_166=1, var_169=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L530] EXPR var_157_arg_0 >> var_157_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_154=1, var_166=1, var_169=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L530] SORT_5 var_157 = var_157_arg_0 >> var_157_arg_1; [L531] SORT_5 var_158_arg_0 = var_157; [L532] SORT_1 var_158 = var_158_arg_0 >> 0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_154=1, var_158=0, var_166=1, var_169=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L533] EXPR var_158 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_154=1, var_166=1, var_169=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L533] var_158 = var_158 & mask_SORT_1 [L534] SORT_1 var_170_arg_0 = var_158; [L535] SORT_1 var_170 = ~var_170_arg_0; [L536] SORT_1 var_171_arg_0 = var_169; [L537] SORT_1 var_171_arg_1 = var_170; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_154=1, var_158=0, var_166=1, var_171_arg_0=0, var_171_arg_1=-1, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L538] EXPR var_171_arg_0 & var_171_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_154=1, var_158=0, var_166=1, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L538] SORT_1 var_171 = var_171_arg_0 & var_171_arg_1; [L539] EXPR var_171 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_154=1, var_158=0, var_166=1, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L539] var_171 = var_171 & mask_SORT_1 [L540] SORT_1 var_159_arg_0 = var_158; [L541] SORT_1 var_159_arg_1 = var_154; [L542] SORT_1 var_159_arg_2 = state_31; [L543] SORT_1 var_159 = var_159_arg_0 ? var_159_arg_1 : var_159_arg_2; [L544] SORT_1 var_172_arg_0 = var_171; [L545] SORT_1 var_172_arg_1 = var_166; [L546] SORT_1 var_172_arg_2 = var_159; [L547] SORT_1 var_172 = var_172_arg_0 ? var_172_arg_1 : var_172_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L548] EXPR var_172 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L548] var_172 = var_172 & mask_SORT_1 [L549] SORT_1 var_202_arg_0 = var_172; [L550] SORT_1 var_202_arg_1 = state_31; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_202_arg_0=0, var_202_arg_1=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L551] EXPR var_202_arg_0 | var_202_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L551] SORT_1 var_202 = var_202_arg_0 | var_202_arg_1; [L552] EXPR var_202 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L552] var_202 = var_202 & mask_SORT_1 [L553] SORT_1 var_196_arg_0 = var_25; [L554] SORT_1 var_196 = ~var_196_arg_0; [L555] SORT_1 var_197_arg_0 = state_31; [L556] SORT_1 var_197_arg_1 = var_196; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_196=-1, var_197_arg_0=0, var_197_arg_1=-1, var_202=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L557] EXPR var_197_arg_0 & var_197_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_196=-1, var_202=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L557] SORT_1 var_197 = var_197_arg_0 & var_197_arg_1; [L558] EXPR var_197 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_196=-1, var_202=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L558] var_197 = var_197 & mask_SORT_1 [L559] SORT_3 var_189_arg_0 = input_7; [L560] SORT_11 var_189 = var_189_arg_0 >> 8; [L561] SORT_11 var_190_arg_0 = state_26; [L562] SORT_11 var_190_arg_1 = var_189; [L563] SORT_11 var_190 = var_190_arg_0 + var_190_arg_1; [L564] SORT_1 var_191_arg_0 = var_172; [L565] SORT_11 var_191_arg_1 = var_190; [L566] SORT_11 var_191_arg_2 = state_26; [L567] SORT_11 var_191 = var_191_arg_0 ? var_191_arg_1 : var_191_arg_2; [L568] SORT_15 var_193_arg_0 = var_27; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_191=0, var_193_arg_0=8, var_196=-1, var_197=0, var_202=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L569] EXPR var_193_arg_0 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_191=0, var_196=-1, var_197=0, var_202=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L569] var_193_arg_0 = var_193_arg_0 & mask_SORT_15 [L570] SORT_11 var_193 = var_193_arg_0; [L571] SORT_11 var_194_arg_0 = var_191; [L572] SORT_11 var_194_arg_1 = var_193; [L573] SORT_11 var_194 = var_194_arg_0 - var_194_arg_1; [L574] SORT_1 var_195_arg_0 = var_32; [L575] SORT_11 var_195_arg_1 = var_194; [L576] SORT_11 var_195_arg_2 = var_191; [L577] SORT_11 var_195 = var_195_arg_0 ? var_195_arg_1 : var_195_arg_2; [L578] SORT_1 var_198_arg_0 = var_197; [L579] SORT_11 var_198_arg_1 = state_26; [L580] SORT_11 var_198_arg_2 = var_195; [L581] SORT_11 var_198 = var_198_arg_0 ? var_198_arg_1 : var_198_arg_2; [L582] SORT_1 var_199_arg_0 = input_9; [L583] SORT_11 var_199_arg_1 = var_181; [L584] SORT_11 var_199_arg_2 = var_198; [L585] SORT_11 var_199 = var_199_arg_0 ? var_199_arg_1 : var_199_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_196=-1, var_199=0, var_202=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L586] EXPR var_199 & mask_SORT_11 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_196=-1, var_202=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L586] var_199 = var_199 & mask_SORT_11 [L587] SORT_1 var_418_arg_0 = var_202; [L588] SORT_11 var_418_arg_1 = var_199; [L589] SORT_11 var_418_arg_2 = state_26; [L590] SORT_11 var_418 = var_418_arg_0 ? var_418_arg_1 : var_418_arg_2; [L591] SORT_1 var_419_arg_0 = input_9; [L592] SORT_11 var_419_arg_1 = var_181; [L593] SORT_11 var_419_arg_2 = var_418; [L594] SORT_11 var_419 = var_419_arg_0 ? var_419_arg_1 : var_419_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_196=-1, var_199=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_419=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L595] EXPR var_419 & mask_SORT_11 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_196=-1, var_199=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L595] var_419 = var_419 & mask_SORT_11 [L596] SORT_11 next_420_arg_1 = var_419; [L597] SORT_1 var_178_arg_0 = var_54; [L598] SORT_1 var_178 = ~var_178_arg_0; [L599] SORT_1 var_179_arg_0 = var_59; [L600] SORT_1 var_179_arg_1 = var_178; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_178=-1, var_179_arg_0=0, var_179_arg_1=-1, var_181=0, var_196=-1, var_199=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L601] EXPR var_179_arg_0 & var_179_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_178=-1, var_181=0, var_196=-1, var_199=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L601] SORT_1 var_179 = var_179_arg_0 & var_179_arg_1; [L602] EXPR var_179 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_178=-1, var_181=0, var_196=-1, var_199=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L602] var_179 = var_179 & mask_SORT_1 [L603] SORT_3 var_148_arg_0 = input_7; [L604] SORT_11 var_148 = var_148_arg_0 >> 0; [L605] SORT_11 var_149_arg_0 = state_55; [L606] SORT_11 var_149_arg_1 = var_148; [L607] SORT_11 var_149 = var_149_arg_0 + var_149_arg_1; [L608] SORT_1 var_173_arg_0 = var_172; [L609] SORT_11 var_173_arg_1 = state_55; [L610] SORT_11 var_173_arg_2 = var_149; [L611] SORT_11 var_173 = var_173_arg_0 ? var_173_arg_1 : var_173_arg_2; [L612] SORT_15 var_175_arg_0 = var_27; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_173=0, var_175_arg_0=8, var_178=-1, var_179=0, var_181=0, var_196=-1, var_199=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L613] EXPR var_175_arg_0 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_173=0, var_178=-1, var_179=0, var_181=0, var_196=-1, var_199=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L613] var_175_arg_0 = var_175_arg_0 & mask_SORT_15 [L614] SORT_11 var_175 = var_175_arg_0; [L615] SORT_11 var_176_arg_0 = var_173; [L616] SORT_11 var_176_arg_1 = var_175; [L617] SORT_11 var_176 = var_176_arg_0 - var_176_arg_1; [L618] SORT_1 var_177_arg_0 = var_60; [L619] SORT_11 var_177_arg_1 = var_176; [L620] SORT_11 var_177_arg_2 = var_173; [L621] SORT_11 var_177 = var_177_arg_0 ? var_177_arg_1 : var_177_arg_2; [L622] SORT_1 var_180_arg_0 = var_179; [L623] SORT_11 var_180_arg_1 = state_55; [L624] SORT_11 var_180_arg_2 = var_177; [L625] SORT_11 var_180 = var_180_arg_0 ? var_180_arg_1 : var_180_arg_2; [L626] SORT_1 var_182_arg_0 = input_9; [L627] SORT_11 var_182_arg_1 = var_181; [L628] SORT_11 var_182_arg_2 = var_180; [L629] SORT_11 var_182 = var_182_arg_0 ? var_182_arg_1 : var_182_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_178=-1, var_181=0, var_182=0, var_196=-1, var_199=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L630] EXPR var_182 & mask_SORT_11 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_178=-1, var_181=0, var_196=-1, var_199=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L630] var_182 = var_182 & mask_SORT_11 [L631] SORT_15 var_210_arg_0 = var_27; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_178=-1, var_181=0, var_182=0, var_196=-1, var_199=0, var_210_arg_0=8, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L632] EXPR var_210_arg_0 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_178=-1, var_181=0, var_182=0, var_196=-1, var_199=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L632] var_210_arg_0 = var_210_arg_0 & mask_SORT_15 [L633] SORT_11 var_210 = var_210_arg_0; [L634] SORT_11 var_211_arg_0 = var_182; [L635] SORT_11 var_211_arg_1 = var_210; [L636] SORT_1 var_211 = var_211_arg_0 < var_211_arg_1; [L637] SORT_1 var_212_arg_0 = var_178; [L638] SORT_1 var_212_arg_1 = var_211; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_196=-1, var_199=0, var_212_arg_0=-1, var_212_arg_1=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L639] EXPR var_212_arg_0 | var_212_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_196=-1, var_199=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L639] SORT_1 var_212 = var_212_arg_0 | var_212_arg_1; [L640] SORT_1 var_213_arg_0 = var_59; [L641] SORT_1 var_213_arg_1 = var_212; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_196=-1, var_199=0, var_213_arg_0=0, var_213_arg_1=255, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L642] EXPR var_213_arg_0 & var_213_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_196=-1, var_199=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L642] SORT_1 var_213 = var_213_arg_0 & var_213_arg_1; [L643] SORT_1 var_214_arg_0 = var_60; [L644] SORT_1 var_214_arg_1 = var_213; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_196=-1, var_199=0, var_214_arg_0=0, var_214_arg_1=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L645] EXPR var_214_arg_0 & var_214_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_196=-1, var_199=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L645] SORT_1 var_214 = var_214_arg_0 & var_214_arg_1; [L646] EXPR var_214 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_196=-1, var_199=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L646] var_214 = var_214 & mask_SORT_1 [L647] SORT_15 var_205_arg_0 = var_27; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_196=-1, var_199=0, var_205_arg_0=8, var_214=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L648] EXPR var_205_arg_0 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_196=-1, var_199=0, var_214=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L648] var_205_arg_0 = var_205_arg_0 & mask_SORT_15 [L649] SORT_11 var_205 = var_205_arg_0; [L650] SORT_11 var_206_arg_0 = var_199; [L651] SORT_11 var_206_arg_1 = var_205; [L652] SORT_1 var_206 = var_206_arg_0 < var_206_arg_1; [L653] SORT_1 var_207_arg_0 = var_196; [L654] SORT_1 var_207_arg_1 = var_206; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_207_arg_0=-1, var_207_arg_1=0, var_214=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L655] EXPR var_207_arg_0 | var_207_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_214=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L655] SORT_1 var_207 = var_207_arg_0 | var_207_arg_1; [L656] SORT_1 var_208_arg_0 = state_31; [L657] SORT_1 var_208_arg_1 = var_207; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_208_arg_0=0, var_208_arg_1=255, var_214=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L658] EXPR var_208_arg_0 & var_208_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_214=0, var_27=8, var_32=0, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L658] SORT_1 var_208 = var_208_arg_0 & var_208_arg_1; [L659] SORT_1 var_209_arg_0 = var_32; [L660] SORT_1 var_209_arg_1 = var_208; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_209_arg_0=0, var_209_arg_1=0, var_214=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L661] EXPR var_209_arg_0 & var_209_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_214=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L661] SORT_1 var_209 = var_209_arg_0 & var_209_arg_1; [L662] EXPR var_209 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_214=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L662] var_209 = var_209 & mask_SORT_1 [L663] SORT_1 var_215_arg_0 = var_214; [L664] SORT_1 var_215_arg_1 = var_209; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_215_arg_0=0, var_215_arg_1=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L665] EXPR ((SORT_5)var_215_arg_0 << 1) | var_215_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L665] SORT_5 var_215 = ((SORT_5)var_215_arg_0 << 1) | var_215_arg_1; [L666] EXPR var_215 & mask_SORT_5 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L666] var_215 = var_215 & mask_SORT_5 [L667] SORT_5 var_216_arg_0 = var_215; [L668] SORT_1 var_216 = var_216_arg_0 != 0; [L669] SORT_1 var_421_arg_0 = var_216; [L670] SORT_1 var_421_arg_1 = var_172; [L671] SORT_1 var_421_arg_2 = state_31; [L672] SORT_1 var_421 = var_421_arg_0 ? var_421_arg_1 : var_421_arg_2; [L673] SORT_1 var_422_arg_0 = input_9; [L674] SORT_1 var_422_arg_1 = var_108; [L675] SORT_1 var_422_arg_2 = var_421; [L676] SORT_1 var_422 = var_422_arg_0 ? var_422_arg_1 : var_422_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_422=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L677] EXPR var_422 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L677] var_422 = var_422 & mask_SORT_1 [L678] SORT_1 next_423_arg_1 = var_422; [L679] SORT_1 var_267_arg_0 = var_90; [L680] SORT_1 var_267_arg_1 = var_60; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_267_arg_0=0, var_267_arg_1=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L681] EXPR var_267_arg_0 | var_267_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L681] SORT_1 var_267 = var_267_arg_0 | var_267_arg_1; [L682] SORT_1 var_268_arg_0 = var_267; [L683] SORT_1 var_268_arg_1 = input_9; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_268_arg_0=0, var_268_arg_1=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L684] EXPR var_268_arg_0 | var_268_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L684] SORT_1 var_268 = var_268_arg_0 | var_268_arg_1; [L685] EXPR var_268 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L685] var_268 = var_268 & mask_SORT_1 [L686] SORT_1 var_279_arg_0 = var_90; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_268=0, var_279_arg_0=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L687] EXPR var_279_arg_0 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L687] var_279_arg_0 = var_279_arg_0 & mask_SORT_1 [L688] SORT_15 var_279 = var_279_arg_0; [L689] SORT_15 var_280_arg_0 = state_45; [L690] SORT_15 var_280_arg_1 = var_279; [L691] SORT_15 var_280 = var_280_arg_0 + var_280_arg_1; [L692] SORT_1 var_424_arg_0 = var_268; [L693] SORT_15 var_424_arg_1 = var_280; [L694] SORT_15 var_424_arg_2 = state_45; [L695] SORT_15 var_424 = var_424_arg_0 ? var_424_arg_1 : var_424_arg_2; [L696] SORT_1 var_425_arg_0 = input_9; [L697] SORT_15 var_425_arg_1 = var_97; [L698] SORT_15 var_425_arg_2 = var_424; [L699] SORT_15 var_425 = var_425_arg_0 ? var_425_arg_1 : var_425_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_425=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L700] EXPR var_425 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L700] var_425 = var_425 & mask_SORT_15 [L701] SORT_15 next_426_arg_1 = var_425; [L702] SORT_1 var_273_arg_0 = var_60; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_268=0, var_273_arg_0=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L703] EXPR var_273_arg_0 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L703] var_273_arg_0 = var_273_arg_0 & mask_SORT_1 [L704] SORT_15 var_273 = var_273_arg_0; [L705] SORT_15 var_274_arg_0 = state_48; [L706] SORT_15 var_274_arg_1 = var_273; [L707] SORT_15 var_274 = var_274_arg_0 + var_274_arg_1; [L708] SORT_1 var_427_arg_0 = var_268; [L709] SORT_15 var_427_arg_1 = var_274; [L710] SORT_15 var_427_arg_2 = state_48; [L711] SORT_15 var_427 = var_427_arg_0 ? var_427_arg_1 : var_427_arg_2; [L712] SORT_1 var_428_arg_0 = input_9; [L713] SORT_15 var_428_arg_1 = var_97; [L714] SORT_15 var_428_arg_2 = var_427; [L715] SORT_15 var_428 = var_428_arg_0 ? var_428_arg_1 : var_428_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_428=0, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L716] EXPR var_428 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_45=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L716] var_428 = var_428 & mask_SORT_15 [L717] SORT_15 next_429_arg_1 = var_428; [L718] SORT_11 var_436_arg_0 = var_408; [L719] SORT_1 var_436 = var_436_arg_0 != 0; [L720] SORT_15 var_46_arg_0 = state_45; [L721] SORT_12 var_46 = var_46_arg_0 >> 0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_436=1, var_46=0, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L722] EXPR var_46 & mask_SORT_12 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L722] var_46 = var_46 & mask_SORT_12 [L723] SORT_3 var_254_arg_0 = input_4; [L724] SORT_11 var_254 = var_254_arg_0 >> 0; [L725] SORT_11* var_47_arg_0 = state_44; [L726] SORT_12 var_47_arg_1 = var_46; [L727] EXPR var_47_arg_0[(unsigned char) var_47_arg_1] [L727] SORT_11 var_47 = var_47_arg_0[(unsigned char) var_47_arg_1]; [L728] SORT_1 var_286_arg_0 = var_90; [L729] SORT_11 var_286_arg_1 = var_254; [L730] SORT_11 var_286_arg_2 = var_47; [L731] SORT_11 var_286 = var_286_arg_0 ? var_286_arg_1 : var_286_arg_2; [L732] SORT_11 var_433_arg_0 = var_286; [L733] SORT_11 var_433_arg_1 = var_408; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_433_arg_0=0, var_433_arg_1=255, var_436=1, var_46=0, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L734] EXPR var_433_arg_0 & var_433_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_436=1, var_46=0, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L734] SORT_11 var_433 = var_433_arg_0 & var_433_arg_1; [L735] SORT_11* var_430_arg_0 = state_44; [L736] SORT_12 var_430_arg_1 = var_46; [L737] EXPR var_430_arg_0[(unsigned char) var_430_arg_1] [L737] SORT_11 var_430 = var_430_arg_0[(unsigned char) var_430_arg_1]; [L738] SORT_11 var_431_arg_0 = var_408; [L739] SORT_11 var_431 = ~var_431_arg_0; [L740] SORT_11 var_432_arg_0 = var_430; [L741] SORT_11 var_432_arg_1 = var_431; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_432_arg_0=0, var_432_arg_1=-256, var_433=0, var_436=1, var_46=0, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L742] EXPR var_432_arg_0 & var_432_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_433=0, var_436=1, var_46=0, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L742] SORT_11 var_432 = var_432_arg_0 & var_432_arg_1; [L743] SORT_11 var_434_arg_0 = var_433; [L744] SORT_11 var_434_arg_1 = var_432; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_434_arg_0=0, var_434_arg_1=0, var_436=1, var_46=0, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L745] EXPR var_434_arg_0 | var_434_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_436=1, var_46=0, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L745] SORT_11 var_434 = var_434_arg_0 | var_434_arg_1; [L746] SORT_11* var_435_arg_0 = state_44; [L747] SORT_12 var_435_arg_1 = var_46; [L748] SORT_11 var_435_arg_2 = var_434; [L749] SORT_13 var_435; [L750] unsigned char i = 0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] EXPR var_435_arg_0[i] [L750] var_435[i] = var_435_arg_0[i] [L750] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] EXPR var_435_arg_0[i] [L750] var_435[i] = var_435_arg_0[i] [L750] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=2, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=2, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] EXPR var_435_arg_0[i] [L750] var_435[i] = var_435_arg_0[i] [L750] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=3, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=3, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] EXPR var_435_arg_0[i] [L750] var_435[i] = var_435_arg_0[i] [L750] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=4, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=4, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] EXPR var_435_arg_0[i] [L750] var_435[i] = var_435_arg_0[i] [L750] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=5, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=5, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] EXPR var_435_arg_0[i] [L750] var_435[i] = var_435_arg_0[i] [L750] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=6, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=6, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] EXPR var_435_arg_0[i] [L750] var_435[i] = var_435_arg_0[i] [L750] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=7, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=7, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] EXPR var_435_arg_0[i] [L750] var_435[i] = var_435_arg_0[i] [L750] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=8, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L750] COND FALSE !(i < (1 << 3)) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_172=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435={9:0}, var_435_arg_0={11:0}, var_435_arg_1=0, var_435_arg_2=0, var_436=1, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L751] var_435[(unsigned char) var_435_arg_1] = var_435_arg_2 [L752] SORT_1 var_437_arg_0 = var_436; [L753] SORT_11* var_437_arg_1 = var_435; [L754] SORT_11* var_437_arg_2 = state_44; [L755] SORT_11* var_437 = var_437_arg_0 ? var_437_arg_1 : var_437_arg_2; [L756] SORT_11* next_438_arg_1 = var_437; [L757] SORT_1 var_185_arg_0 = var_172; [L758] SORT_1 var_185 = ~var_185_arg_0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_182=0, var_185=-1, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L759] EXPR var_185 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_59=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L759] var_185 = var_185 & mask_SORT_1 [L760] SORT_1 var_186_arg_0 = var_185; [L761] SORT_1 var_186_arg_1 = var_59; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_182=0, var_186_arg_0=0, var_186_arg_1=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_90=0, var_91=-1, var_97=0, var_98=0] [L762] EXPR var_186_arg_0 | var_186_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_90=0, var_91=-1, var_97=0, var_98=0] [L762] SORT_1 var_186 = var_186_arg_0 | var_186_arg_1; [L763] EXPR var_186 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, state_103=0, state_14={10:0}, state_44={11:0}, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_182=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_90=0, var_91=-1, var_97=0, var_98=0] [L763] var_186 = var_186 & mask_SORT_1 [L764] SORT_1 var_439_arg_0 = var_186; [L765] SORT_11 var_439_arg_1 = var_182; [L766] SORT_11 var_439_arg_2 = state_55; [L767] SORT_11 var_439 = var_439_arg_0 ? var_439_arg_1 : var_439_arg_2; [L768] SORT_1 var_440_arg_0 = input_9; [L769] SORT_11 var_440_arg_1 = var_181; [L770] SORT_11 var_440_arg_2 = var_439; [L771] SORT_11 var_440 = var_440_arg_0 ? var_440_arg_1 : var_440_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, state_103=0, state_14={10:0}, state_44={11:0}, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_440=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L772] EXPR var_440 & mask_SORT_11 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, state_103=0, state_14={10:0}, state_44={11:0}, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_90=0, var_91=-1, var_97=0, var_98=0] [L772] var_440 = var_440 & mask_SORT_11 [L773] SORT_11 next_441_arg_1 = var_440; [L774] SORT_1 var_363_arg_0 = input_10; [L775] SORT_1 var_363_arg_1 = var_90; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_254=0, var_268=0, var_27=8, var_363_arg_0=0, var_363_arg_1=0, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_91=-1, var_97=0, var_98=0] [L776] EXPR var_363_arg_0 & var_363_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_254=0, var_268=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_91=-1, var_97=0, var_98=0] [L776] SORT_1 var_363 = var_363_arg_0 & var_363_arg_1; [L777] SORT_1 var_364_arg_0 = state_83; [L778] SORT_1 var_364_arg_1 = var_363; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_254=0, var_268=0, var_27=8, var_363=0, var_364_arg_0=0, var_364_arg_1=0, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_91=-1, var_97=0, var_98=0] [L779] EXPR var_364_arg_0 | var_364_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_254=0, var_268=0, var_27=8, var_363=0, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_91=-1, var_97=0, var_98=0] [L779] SORT_1 var_364 = var_364_arg_0 | var_364_arg_1; [L780] SORT_1 var_442_arg_0 = state_83; [L781] SORT_1 var_442_arg_1 = var_107; [L782] SORT_1 var_442_arg_2 = var_364; [L783] SORT_1 var_442 = var_442_arg_0 ? var_442_arg_1 : var_442_arg_2; [L784] SORT_1 var_443_arg_0 = input_9; [L785] SORT_1 var_443_arg_1 = var_108; [L786] SORT_1 var_443_arg_2 = var_442; [L787] SORT_1 var_443 = var_443_arg_0 ? var_443_arg_1 : var_443_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_254=0, var_268=0, var_27=8, var_363=0, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_443=0, var_91=-1, var_97=0, var_98=0] [L788] EXPR var_443 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_181=0, var_254=0, var_268=0, var_27=8, var_363=0, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_91=-1, var_97=0, var_98=0] [L788] var_443 = var_443 & mask_SORT_1 [L789] SORT_1 next_444_arg_1 = var_443; [L790] SORT_1 var_374_arg_0 = var_101; [L791] SORT_1 var_374_arg_1 = state_84; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_83=0, state_87=0, var_107=1, var_108=0, var_181=0, var_254=0, var_268=0, var_27=8, var_363=0, var_374_arg_0=0, var_374_arg_1=0, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_91=-1, var_97=0, var_98=0] [L792] EXPR var_374_arg_0 | var_374_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_83=0, state_87=0, var_107=1, var_108=0, var_181=0, var_254=0, var_268=0, var_27=8, var_363=0, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_91=-1, var_97=0, var_98=0] [L792] SORT_1 var_374 = var_374_arg_0 | var_374_arg_1; [L793] SORT_1 var_445_arg_0 = input_9; [L794] SORT_1 var_445_arg_1 = var_108; [L795] SORT_1 var_445_arg_2 = var_374; [L796] SORT_1 var_445 = var_445_arg_0 ? var_445_arg_1 : var_445_arg_2; [L797] SORT_1 next_446_arg_1 = var_445; [L798] SORT_1 var_386_arg_0 = var_268; [L799] SORT_1 var_386_arg_1 = state_83; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_87=0, var_107=1, var_108=0, var_181=0, var_254=0, var_27=8, var_363=0, var_386_arg_0=0, var_386_arg_1=0, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_91=-1, var_97=0, var_98=0] [L800] EXPR var_386_arg_0 | var_386_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_87=0, var_107=1, var_108=0, var_181=0, var_254=0, var_27=8, var_363=0, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_91=-1, var_97=0, var_98=0] [L800] SORT_1 var_386 = var_386_arg_0 | var_386_arg_1; [L801] EXPR var_386 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, state_87=0, var_107=1, var_108=0, var_181=0, var_254=0, var_27=8, var_363=0, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_91=-1, var_97=0, var_98=0] [L801] var_386 = var_386 & mask_SORT_1 [L802] SORT_1 var_447_arg_0 = var_386; [L803] SORT_15 var_447_arg_1 = var_98; [L804] SORT_15 var_447_arg_2 = state_87; [L805] SORT_15 var_447 = var_447_arg_0 ? var_447_arg_1 : var_447_arg_2; [L806] SORT_1 var_448_arg_0 = input_9; [L807] SORT_15 var_448_arg_1 = var_97; [L808] SORT_15 var_448_arg_2 = var_447; [L809] SORT_15 var_448 = var_448_arg_0 ? var_448_arg_1 : var_448_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_254=0, var_27=8, var_363=0, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_448=0, var_91=-1, var_97=0] [L810] EXPR var_448 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_254=0, var_27=8, var_363=0, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_91=-1, var_97=0] [L810] var_448 = var_448 & mask_SORT_15 [L811] SORT_15 next_449_arg_1 = var_448; [L812] SORT_1 var_371_arg_0 = var_363; [L813] SORT_1 var_371_arg_1 = var_91; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_254=0, var_27=8, var_371_arg_0=0, var_371_arg_1=-1, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L814] EXPR var_371_arg_0 & var_371_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_254=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L814] SORT_1 var_371 = var_371_arg_0 & var_371_arg_1; [L815] EXPR var_371 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, state_103=0, state_14={10:0}, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_254=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L815] var_371 = var_371 & mask_SORT_1 [L816] SORT_1 var_450_arg_0 = var_371; [L817] SORT_11 var_450_arg_1 = var_254; [L818] SORT_11 var_450_arg_2 = state_103; [L819] SORT_11 var_450 = var_450_arg_0 ? var_450_arg_1 : var_450_arg_2; [L820] SORT_1 var_451_arg_0 = input_9; [L821] SORT_11 var_451_arg_1 = var_181; [L822] SORT_11 var_451_arg_2 = var_450; [L823] SORT_11 var_451 = var_451_arg_0 ? var_451_arg_1 : var_451_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, state_14={10:0}, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_451=0, var_97=0] [L824] EXPR var_451 & mask_SORT_11 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_404_arg_1=0, next_407_arg_1=0, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, state_14={10:0}, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L824] var_451 = var_451 & mask_SORT_11 [L825] SORT_11 next_452_arg_1 = var_451; [L826] SORT_1 next_453_arg_1 = var_108; [L828] state_16 = next_404_arg_1 [L829] state_19 = next_407_arg_1 [L830] unsigned char i = 0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] EXPR next_417_arg_1[i] [L830] state_14[i] = next_417_arg_1[i] [L830] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] EXPR next_417_arg_1[i] [L830] state_14[i] = next_417_arg_1[i] [L830] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] EXPR next_417_arg_1[i] [L830] state_14[i] = next_417_arg_1[i] [L830] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] EXPR next_417_arg_1[i] [L830] state_14[i] = next_417_arg_1[i] [L830] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] EXPR next_417_arg_1[i] [L830] state_14[i] = next_417_arg_1[i] [L830] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] EXPR next_417_arg_1[i] [L830] state_14[i] = next_417_arg_1[i] [L830] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] EXPR next_417_arg_1[i] [L830] state_14[i] = next_417_arg_1[i] [L830] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] EXPR next_417_arg_1[i] [L830] state_14[i] = next_417_arg_1[i] [L830] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L830] COND FALSE !(i < (1 << 3)) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_429_arg_1=0, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L831] state_26 = next_420_arg_1 [L832] state_31 = next_423_arg_1 [L833] state_45 = next_426_arg_1 [L834] state_48 = next_429_arg_1 [L835] unsigned char i = 0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] EXPR next_438_arg_1[i] [L835] state_44[i] = next_438_arg_1[i] [L835] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] EXPR next_438_arg_1[i] [L835] state_44[i] = next_438_arg_1[i] [L835] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] EXPR next_438_arg_1[i] [L835] state_44[i] = next_438_arg_1[i] [L835] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] EXPR next_438_arg_1[i] [L835] state_44[i] = next_438_arg_1[i] [L835] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] EXPR next_438_arg_1[i] [L835] state_44[i] = next_438_arg_1[i] [L835] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] EXPR next_438_arg_1[i] [L835] state_44[i] = next_438_arg_1[i] [L835] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] EXPR next_438_arg_1[i] [L835] state_44[i] = next_438_arg_1[i] [L835] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] COND TRUE i < (1 << 3) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] EXPR next_438_arg_1[i] [L835] state_44[i] = next_438_arg_1[i] [L835] ++i VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L835] COND FALSE !(i < (1 << 3)) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_417_arg_1={13:0}, next_438_arg_1={9:0}, next_441_arg_1=0, next_444_arg_1=0, next_446_arg_1=0, next_449_arg_1=0, next_452_arg_1=0, next_453_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_414_arg_0={10:0}, var_435_arg_0={11:0}, var_97=0] [L836] state_55 = next_441_arg_1 [L837] state_83 = next_444_arg_1 [L838] state_84 = next_446_arg_1 [L839] state_87 = next_449_arg_1 [L840] state_103 = next_452_arg_1 [L841] state_109 = next_453_arg_1 [L102] input_2 = __VERIFIER_nondet_uchar() [L103] input_4 = __VERIFIER_nondet_ushort() [L104] input_6 = __VERIFIER_nondet_uchar() [L105] input_7 = __VERIFIER_nondet_ushort() [L106] input_8 = __VERIFIER_nondet_uchar() [L107] input_9 = __VERIFIER_nondet_uchar() [L108] EXPR input_9 & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_97=0] [L108] input_9 = input_9 & mask_SORT_1 [L109] input_10 = __VERIFIER_nondet_uchar() [L111] SORT_15 var_52_arg_0 = state_48; [L112] SORT_15 var_52_arg_1 = state_45; [L113] SORT_1 var_52 = var_52_arg_0 == var_52_arg_1; [L114] SORT_1 var_115_arg_0 = var_52; [L115] SORT_1 var_115 = ~var_115_arg_0; [L116] SORT_5 var_51_arg_0 = input_8; [L117] SORT_1 var_51 = var_51_arg_0 >> 0; [L118] SORT_1 var_116_arg_0 = var_51; [L119] SORT_1 var_116 = ~var_116_arg_0; [L120] SORT_1 var_117_arg_0 = var_115; [L121] SORT_1 var_117_arg_1 = var_116; VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_117_arg_0=-2, var_117_arg_1=-2, var_181=0, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L122] EXPR var_117_arg_0 | var_117_arg_1 VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L122] SORT_1 var_117 = var_117_arg_0 | var_117_arg_1; [L123] SORT_1 var_118_arg_0 = var_107; [L124] SORT_1 var_118 = ~var_118_arg_0; [L125] SORT_1 var_119_arg_0 = var_117; [L126] SORT_1 var_119_arg_1 = var_118; VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_119_arg_0=254, var_119_arg_1=-2, var_181=0, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L127] EXPR var_119_arg_0 | var_119_arg_1 VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L127] SORT_1 var_119 = var_119_arg_0 | var_119_arg_1; [L128] EXPR var_119 & mask_SORT_1 VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L128] var_119 = var_119 & mask_SORT_1 [L129] SORT_1 constr_120_arg_0 = var_119; VAL [constr_120_arg_0=1, input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L130] CALL assume_abort_if_not(constr_120_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L130] RET assume_abort_if_not(constr_120_arg_0) VAL [constr_120_arg_0=1, input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L131] SORT_15 var_23_arg_0 = state_19; [L132] SORT_15 var_23_arg_1 = state_16; [L133] SORT_1 var_23 = var_23_arg_0 == var_23_arg_1; [L134] SORT_1 var_121_arg_0 = var_23; [L135] SORT_1 var_121 = ~var_121_arg_0; [L136] SORT_5 var_22_arg_0 = input_8; [L137] SORT_1 var_22 = var_22_arg_0 >> 1; [L138] SORT_1 var_122_arg_0 = var_22; [L139] SORT_1 var_122 = ~var_122_arg_0; [L140] SORT_1 var_123_arg_0 = var_121; [L141] SORT_1 var_123_arg_1 = var_122; VAL [constr_120_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_123_arg_0=-2, var_123_arg_1=-1, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L142] EXPR var_123_arg_0 | var_123_arg_1 VAL [constr_120_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L142] SORT_1 var_123 = var_123_arg_0 | var_123_arg_1; [L143] SORT_1 var_124_arg_0 = var_107; [L144] SORT_1 var_124 = ~var_124_arg_0; [L145] SORT_1 var_125_arg_0 = var_123; [L146] SORT_1 var_125_arg_1 = var_124; VAL [constr_120_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_125_arg_0=256, var_125_arg_1=-2, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L147] EXPR var_125_arg_0 | var_125_arg_1 VAL [constr_120_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L147] SORT_1 var_125 = var_125_arg_0 | var_125_arg_1; [L148] EXPR var_125 & mask_SORT_1 VAL [constr_120_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L148] var_125 = var_125 & mask_SORT_1 [L149] SORT_1 constr_126_arg_0 = var_125; VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L150] CALL assume_abort_if_not(constr_126_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L150] RET assume_abort_if_not(constr_126_arg_0) VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L151] SORT_15 var_73_arg_0 = state_48; [L152] SORT_1 var_73 = var_73_arg_0 >> 3; VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_73=0, var_97=0] [L153] EXPR var_73 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L153] var_73 = var_73 & mask_SORT_1 [L154] SORT_15 var_74_arg_0 = state_45; [L155] SORT_1 var_74 = var_74_arg_0 >> 3; VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_73=0, var_74=0, var_97=0] [L156] EXPR var_74 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_73=0, var_97=0] [L156] var_74 = var_74 & mask_SORT_1 [L157] SORT_1 var_75_arg_0 = var_73; [L158] SORT_1 var_75_arg_1 = var_74; [L159] SORT_1 var_75 = var_75_arg_0 != var_75_arg_1; [L160] SORT_1 var_76_arg_0 = var_52; [L161] SORT_1 var_76_arg_1 = var_75; VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_76_arg_0=1, var_76_arg_1=0, var_97=0] [L162] EXPR var_76_arg_0 & var_76_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L162] SORT_1 var_76 = var_76_arg_0 & var_76_arg_1; [L163] EXPR var_76 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L163] var_76 = var_76 & mask_SORT_1 [L164] SORT_1 var_127_arg_0 = var_76; [L165] SORT_1 var_127 = ~var_127_arg_0; [L166] SORT_5 var_90_arg_0 = input_6; [L167] SORT_1 var_90 = var_90_arg_0 >> 0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_127=-1, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L168] EXPR var_90 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_127=-1, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_97=0] [L168] var_90 = var_90 & mask_SORT_1 [L169] SORT_1 var_128_arg_0 = var_90; [L170] SORT_1 var_128 = ~var_128_arg_0; [L171] SORT_1 var_129_arg_0 = var_127; [L172] SORT_1 var_129_arg_1 = var_128; VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_129_arg_0=-1, var_129_arg_1=-1, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L173] EXPR var_129_arg_0 | var_129_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L173] SORT_1 var_129 = var_129_arg_0 | var_129_arg_1; [L174] SORT_1 var_130_arg_0 = var_107; [L175] SORT_1 var_130 = ~var_130_arg_0; [L176] SORT_1 var_131_arg_0 = var_129; [L177] SORT_1 var_131_arg_1 = var_130; VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_131_arg_0=255, var_131_arg_1=-2, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L178] EXPR var_131_arg_0 | var_131_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L178] SORT_1 var_131 = var_131_arg_0 | var_131_arg_1; [L179] EXPR var_131 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L179] var_131 = var_131 & mask_SORT_1 [L180] SORT_1 constr_132_arg_0 = var_131; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L181] CALL assume_abort_if_not(constr_132_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L181] RET assume_abort_if_not(constr_132_arg_0) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L182] SORT_15 var_77_arg_0 = state_19; [L183] SORT_1 var_77 = var_77_arg_0 >> 3; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_77=0, var_90=0, var_97=0] [L184] EXPR var_77 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L184] var_77 = var_77 & mask_SORT_1 [L185] SORT_15 var_78_arg_0 = state_16; [L186] SORT_1 var_78 = var_78_arg_0 >> 3; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_77=0, var_78=0, var_90=0, var_97=0] [L187] EXPR var_78 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_77=0, var_90=0, var_97=0] [L187] var_78 = var_78 & mask_SORT_1 [L188] SORT_1 var_79_arg_0 = var_77; [L189] SORT_1 var_79_arg_1 = var_78; [L190] SORT_1 var_79 = var_79_arg_0 != var_79_arg_1; [L191] SORT_1 var_80_arg_0 = var_23; [L192] SORT_1 var_80_arg_1 = var_79; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_80_arg_0=1, var_80_arg_1=0, var_90=0, var_97=0] [L193] EXPR var_80_arg_0 & var_80_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L193] SORT_1 var_80 = var_80_arg_0 & var_80_arg_1; [L194] SORT_1 var_133_arg_0 = var_80; [L195] SORT_1 var_133 = ~var_133_arg_0; [L196] SORT_5 var_134_arg_0 = input_6; [L197] SORT_1 var_134 = var_134_arg_0 >> 1; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_133=-1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L198] EXPR var_134 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_133=-1, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L198] var_134 = var_134 & mask_SORT_1 [L199] SORT_1 var_135_arg_0 = var_134; [L200] SORT_1 var_135 = ~var_135_arg_0; [L201] SORT_1 var_136_arg_0 = var_133; [L202] SORT_1 var_136_arg_1 = var_135; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_136_arg_0=-1, var_136_arg_1=-1, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L203] EXPR var_136_arg_0 | var_136_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L203] SORT_1 var_136 = var_136_arg_0 | var_136_arg_1; [L204] SORT_1 var_137_arg_0 = var_107; [L205] SORT_1 var_137 = ~var_137_arg_0; [L206] SORT_1 var_138_arg_0 = var_136; [L207] SORT_1 var_138_arg_1 = var_137; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_138_arg_0=255, var_138_arg_1=-2, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L208] EXPR var_138_arg_0 | var_138_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L208] SORT_1 var_138 = var_138_arg_0 | var_138_arg_1; [L209] EXPR var_138 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L209] var_138 = var_138 & mask_SORT_1 [L210] SORT_1 constr_139_arg_0 = var_138; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L211] CALL assume_abort_if_not(constr_139_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L211] RET assume_abort_if_not(constr_139_arg_0) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L212] SORT_1 var_140_arg_0 = state_109; [L213] SORT_1 var_140_arg_1 = input_9; [L214] SORT_1 var_140 = var_140_arg_0 == var_140_arg_1; [L215] SORT_1 var_141_arg_0 = var_107; [L216] SORT_1 var_141 = ~var_141_arg_0; [L217] SORT_1 var_142_arg_0 = var_140; [L218] SORT_1 var_142_arg_1 = var_141; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_142_arg_0=0, var_142_arg_1=-2, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L219] EXPR var_142_arg_0 | var_142_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L219] SORT_1 var_142 = var_142_arg_0 | var_142_arg_1; [L220] EXPR var_142 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L220] var_142 = var_142 & mask_SORT_1 [L221] SORT_1 constr_143_arg_0 = var_142; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L222] CALL assume_abort_if_not(constr_143_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L222] RET assume_abort_if_not(constr_143_arg_0) VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_109=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L224] SORT_1 var_111_arg_0 = state_109; [L225] SORT_1 var_111_arg_1 = var_108; [L226] SORT_1 var_111_arg_2 = var_107; [L227] SORT_1 var_111 = var_111_arg_0 ? var_111_arg_1 : var_111_arg_2; [L228] SORT_1 var_85_arg_0 = state_84; [L229] SORT_1 var_85 = ~var_85_arg_0; [L230] SORT_1 var_86_arg_0 = state_83; [L231] SORT_1 var_86_arg_1 = var_85; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_86_arg_0=0, var_86_arg_1=-1, var_90=0, var_97=0] [L232] EXPR var_86_arg_0 & var_86_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L232] SORT_1 var_86 = var_86_arg_0 & var_86_arg_1; [L233] SORT_15 var_88_arg_0 = state_87; [L234] SORT_1 var_88 = var_88_arg_0 != 0; [L235] SORT_1 var_89_arg_0 = var_86; [L236] SORT_1 var_89_arg_1 = var_88; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_89_arg_0=0, var_89_arg_1=0, var_90=0, var_97=0] [L237] EXPR var_89_arg_0 & var_89_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_90=0, var_97=0] [L237] SORT_1 var_89 = var_89_arg_0 & var_89_arg_1; [L238] SORT_1 var_91_arg_0 = state_83; [L239] SORT_1 var_91 = ~var_91_arg_0; [L240] SORT_1 var_92_arg_0 = var_90; [L241] SORT_1 var_92_arg_1 = var_91; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_89=0, var_90=0, var_91=-1, var_92_arg_0=0, var_92_arg_1=-1, var_97=0] [L242] EXPR var_92_arg_0 & var_92_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_89=0, var_90=0, var_91=-1, var_97=0] [L242] SORT_1 var_92 = var_92_arg_0 & var_92_arg_1; [L243] SORT_1 var_93_arg_0 = var_92; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_89=0, var_90=0, var_91=-1, var_93_arg_0=0, var_97=0] [L244] EXPR var_93_arg_0 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_51=1, var_52=1, var_89=0, var_90=0, var_91=-1, var_97=0] [L244] var_93_arg_0 = var_93_arg_0 & mask_SORT_1 [L245] SORT_15 var_93 = var_93_arg_0; [L246] SORT_15 var_94_arg_0 = state_87; [L247] SORT_15 var_94_arg_1 = var_93; [L248] SORT_15 var_94 = var_94_arg_0 + var_94_arg_1; [L249] SORT_1 var_53_arg_0 = var_52; [L250] SORT_1 var_53 = ~var_53_arg_0; [L251] SORT_1 var_54_arg_0 = var_51; [L252] SORT_1 var_54_arg_1 = var_53; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54_arg_0=1, var_54_arg_1=-2, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L253] EXPR var_54_arg_0 & var_54_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L253] SORT_1 var_54 = var_54_arg_0 & var_54_arg_1; [L254] EXPR var_54 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L254] var_54 = var_54 & mask_SORT_1 [L255] SORT_15 var_56_arg_0 = var_27; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_56_arg_0=8, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L256] EXPR var_56_arg_0 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L256] var_56_arg_0 = var_56_arg_0 & mask_SORT_15 [L257] SORT_11 var_56 = var_56_arg_0; [L258] SORT_11 var_57_arg_0 = state_55; [L259] SORT_11 var_57_arg_1 = var_56; [L260] SORT_1 var_57 = var_57_arg_0 >= var_57_arg_1; [L261] SORT_1 var_58_arg_0 = var_54; [L262] SORT_1 var_58_arg_1 = var_57; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_58_arg_0=0, var_58_arg_1=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L263] EXPR var_58_arg_0 & var_58_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L263] SORT_1 var_58 = var_58_arg_0 & var_58_arg_1; [L264] SORT_1 var_59_arg_0 = state_31; [L265] SORT_1 var_59 = ~var_59_arg_0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_58=0, var_59=-1, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L266] EXPR var_59 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_58=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L266] var_59 = var_59 & mask_SORT_1 [L267] SORT_1 var_60_arg_0 = var_58; [L268] SORT_1 var_60_arg_1 = var_59; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60_arg_0=0, var_60_arg_1=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L269] EXPR var_60_arg_0 & var_60_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L269] SORT_1 var_60 = var_60_arg_0 & var_60_arg_1; [L270] EXPR var_60 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L270] var_60 = var_60 & mask_SORT_1 [L271] SORT_1 var_95_arg_0 = var_60; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_95_arg_0=0, var_97=0] [L272] EXPR var_95_arg_0 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_89=0, var_90=0, var_91=-1, var_94=0, var_97=0] [L272] var_95_arg_0 = var_95_arg_0 & mask_SORT_1 [L273] SORT_15 var_95 = var_95_arg_0; [L274] SORT_15 var_96_arg_0 = var_94; [L275] SORT_15 var_96_arg_1 = var_95; [L276] SORT_15 var_96 = var_96_arg_0 - var_96_arg_1; [L277] SORT_1 var_98_arg_0 = input_9; [L278] SORT_15 var_98_arg_1 = var_97; [L279] SORT_15 var_98_arg_2 = var_96; [L280] SORT_15 var_98 = var_98_arg_0 ? var_98_arg_1 : var_98_arg_2; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_89=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L281] EXPR var_98 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_89=0, var_90=0, var_91=-1, var_97=0] [L281] var_98 = var_98 & mask_SORT_15 [L282] SORT_15 var_99_arg_0 = var_98; [L283] SORT_1 var_99 = var_99_arg_0 != 0; [L284] SORT_1 var_100_arg_0 = var_99; [L285] SORT_1 var_100 = ~var_100_arg_0; [L286] SORT_1 var_101_arg_0 = var_89; [L287] SORT_1 var_101_arg_1 = var_100; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101_arg_0=0, var_101_arg_1=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L288] EXPR var_101_arg_0 & var_101_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L288] SORT_1 var_101 = var_101_arg_0 & var_101_arg_1; [L289] SORT_1 var_102_arg_0 = var_101; [L290] SORT_1 var_102 = ~var_102_arg_0; [L291] SORT_15 var_20_arg_0 = state_19; [L292] SORT_12 var_20 = var_20_arg_0 >> 0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_20=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L293] EXPR var_20 & mask_SORT_12 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_22=0, var_23=1, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L293] var_20 = var_20 & mask_SORT_12 [L294] SORT_11* var_21_arg_0 = state_14; [L295] SORT_12 var_21_arg_1 = var_20; [L296] EXPR var_21_arg_0[(unsigned char) var_21_arg_1] [L296] SORT_11 var_21 = var_21_arg_0[(unsigned char) var_21_arg_1]; [L297] SORT_1 var_24_arg_0 = var_23; [L298] SORT_1 var_24 = ~var_24_arg_0; [L299] SORT_1 var_25_arg_0 = var_22; [L300] SORT_1 var_25_arg_1 = var_24; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25_arg_0=0, var_25_arg_1=-2, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L301] EXPR var_25_arg_0 & var_25_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L301] SORT_1 var_25 = var_25_arg_0 & var_25_arg_1; [L302] SORT_15 var_28_arg_0 = var_27; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_28_arg_0=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L303] EXPR var_28_arg_0 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L303] var_28_arg_0 = var_28_arg_0 & mask_SORT_15 [L304] SORT_11 var_28 = var_28_arg_0; [L305] SORT_11 var_29_arg_0 = state_26; [L306] SORT_11 var_29_arg_1 = var_28; [L307] SORT_1 var_29 = var_29_arg_0 >= var_29_arg_1; [L308] SORT_1 var_30_arg_0 = var_25; [L309] SORT_1 var_30_arg_1 = var_29; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_30_arg_0=0, var_30_arg_1=1, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L310] EXPR var_30_arg_0 & var_30_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L310] SORT_1 var_30 = var_30_arg_0 & var_30_arg_1; [L311] SORT_1 var_32_arg_0 = var_30; [L312] SORT_1 var_32_arg_1 = state_31; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32_arg_0=0, var_32_arg_1=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L313] EXPR var_32_arg_0 & var_32_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L313] SORT_1 var_32 = var_32_arg_0 & var_32_arg_1; [L314] EXPR var_32 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L314] var_32 = var_32 & mask_SORT_1 [L315] SORT_1 var_33_arg_0 = var_32; [L316] SORT_1 var_33_arg_1 = var_32; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_33_arg_0=0, var_33_arg_1=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L317] EXPR ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L317] SORT_5 var_33 = ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1; [L318] EXPR var_33 & mask_SORT_5 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L318] var_33 = var_33 & mask_SORT_5 [L319] SORT_1 var_34_arg_0 = var_32; [L320] SORT_5 var_34_arg_1 = var_33; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_34_arg_0=0, var_34_arg_1=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L321] EXPR ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L321] SORT_12 var_34 = ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1; [L322] EXPR var_34 & mask_SORT_12 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L322] var_34 = var_34 & mask_SORT_12 [L323] SORT_1 var_35_arg_0 = var_32; [L324] SORT_12 var_35_arg_1 = var_34; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_35_arg_0=0, var_35_arg_1=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L325] EXPR ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L325] SORT_15 var_35 = ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1; [L326] EXPR var_35 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L326] var_35 = var_35 & mask_SORT_15 [L327] SORT_1 var_37_arg_0 = var_32; [L328] SORT_15 var_37_arg_1 = var_35; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_37_arg_0=0, var_37_arg_1=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L329] EXPR ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L329] SORT_36 var_37 = ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1; [L330] EXPR var_37 & mask_SORT_36 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L330] var_37 = var_37 & mask_SORT_36 [L331] SORT_1 var_39_arg_0 = var_32; [L332] SORT_36 var_39_arg_1 = var_37; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_39_arg_0=0, var_39_arg_1=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L333] EXPR ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L333] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1; [L334] EXPR var_39 & mask_SORT_38 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L334] var_39 = var_39 & mask_SORT_38 [L335] SORT_1 var_41_arg_0 = var_32; [L336] SORT_38 var_41_arg_1 = var_39; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_41_arg_0=0, var_41_arg_1=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L337] EXPR ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L337] SORT_40 var_41 = ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1; [L338] EXPR var_41 & mask_SORT_40 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L338] var_41 = var_41 & mask_SORT_40 [L339] SORT_1 var_42_arg_0 = var_32; [L340] SORT_40 var_42_arg_1 = var_41; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_42_arg_0=0, var_42_arg_1=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L341] EXPR ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_21=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L341] SORT_11 var_42 = ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1; [L342] SORT_11 var_43_arg_0 = var_21; [L343] SORT_11 var_43_arg_1 = var_42; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43_arg_0=0, var_43_arg_1=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L344] EXPR var_43_arg_0 & var_43_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L344] SORT_11 var_43 = var_43_arg_0 & var_43_arg_1; [L345] SORT_15 var_49_arg_0 = state_48; [L346] SORT_12 var_49 = var_49_arg_0 >> 0; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_49=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L347] EXPR var_49 & mask_SORT_12 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L347] var_49 = var_49 & mask_SORT_12 [L348] SORT_11* var_50_arg_0 = state_44; [L349] SORT_12 var_50_arg_1 = var_49; [L350] EXPR var_50_arg_0[(unsigned char) var_50_arg_1] [L350] SORT_11 var_50 = var_50_arg_0[(unsigned char) var_50_arg_1]; [L351] EXPR var_50 & mask_SORT_11 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L351] var_50 = var_50 & mask_SORT_11 [L352] SORT_1 var_61_arg_0 = var_60; [L353] SORT_1 var_61_arg_1 = var_60; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_61_arg_0=0, var_61_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L354] EXPR ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L354] SORT_5 var_61 = ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1; [L355] EXPR var_61 & mask_SORT_5 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L355] var_61 = var_61 & mask_SORT_5 [L356] SORT_1 var_62_arg_0 = var_60; [L357] SORT_5 var_62_arg_1 = var_61; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_62_arg_0=0, var_62_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L358] EXPR ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L358] SORT_12 var_62 = ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1; [L359] EXPR var_62 & mask_SORT_12 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L359] var_62 = var_62 & mask_SORT_12 [L360] SORT_1 var_63_arg_0 = var_60; [L361] SORT_12 var_63_arg_1 = var_62; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_63_arg_0=0, var_63_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L362] EXPR ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L362] SORT_15 var_63 = ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1; [L363] EXPR var_63 & mask_SORT_15 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L363] var_63 = var_63 & mask_SORT_15 [L364] SORT_1 var_64_arg_0 = var_60; [L365] SORT_15 var_64_arg_1 = var_63; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_64_arg_0=0, var_64_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L366] EXPR ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L366] SORT_36 var_64 = ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1; [L367] EXPR var_64 & mask_SORT_36 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L367] var_64 = var_64 & mask_SORT_36 [L368] SORT_1 var_65_arg_0 = var_60; [L369] SORT_36 var_65_arg_1 = var_64; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_65_arg_0=0, var_65_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L370] EXPR ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L370] SORT_38 var_65 = ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1; [L371] EXPR var_65 & mask_SORT_38 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L371] var_65 = var_65 & mask_SORT_38 [L372] SORT_1 var_66_arg_0 = var_60; [L373] SORT_38 var_66_arg_1 = var_65; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_66_arg_0=0, var_66_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L374] EXPR ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L374] SORT_40 var_66 = ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1; [L375] EXPR var_66 & mask_SORT_40 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L375] var_66 = var_66 & mask_SORT_40 [L376] SORT_1 var_67_arg_0 = var_60; [L377] SORT_40 var_67_arg_1 = var_66; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_67_arg_0=0, var_67_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L378] EXPR ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_50=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L378] SORT_11 var_67 = ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1; [L379] SORT_11 var_68_arg_0 = var_50; [L380] SORT_11 var_68_arg_1 = var_67; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_54=0, var_59=0, var_60=0, var_68_arg_0=0, var_68_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L381] EXPR var_68_arg_0 & var_68_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_43=0, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L381] SORT_11 var_68 = var_68_arg_0 & var_68_arg_1; [L382] SORT_11 var_69_arg_0 = var_43; [L383] SORT_11 var_69_arg_1 = var_68; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_69_arg_0=0, var_69_arg_1=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L384] EXPR var_69_arg_0 | var_69_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L384] SORT_11 var_69 = var_69_arg_0 | var_69_arg_1; [L385] EXPR var_69 & mask_SORT_11 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_102=-1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L385] var_69 = var_69 & mask_SORT_11 [L386] SORT_11 var_104_arg_0 = state_103; [L387] SORT_11 var_104_arg_1 = var_69; [L388] SORT_1 var_104 = var_104_arg_0 == var_104_arg_1; [L389] SORT_1 var_105_arg_0 = var_102; [L390] SORT_1 var_105_arg_1 = var_104; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_105_arg_0=-1, var_105_arg_1=1, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L391] EXPR var_105_arg_0 | var_105_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_111=1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L391] SORT_1 var_105 = var_105_arg_0 | var_105_arg_1; [L392] SORT_1 var_112_arg_0 = var_105; [L393] SORT_1 var_112 = ~var_112_arg_0; [L394] SORT_1 var_113_arg_0 = var_111; [L395] SORT_1 var_113_arg_1 = var_112; VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_113_arg_0=1, var_113_arg_1=-1, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L396] EXPR var_113_arg_0 & var_113_arg_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L396] SORT_1 var_113 = var_113_arg_0 & var_113_arg_1; [L397] EXPR var_113 & mask_SORT_1 VAL [constr_120_arg_0=1, constr_126_arg_0=1, constr_132_arg_0=1, constr_139_arg_0=1, constr_143_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_103=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_83=0, state_84=0, state_87=0, var_101=0, var_107=1, var_108=0, var_134=0, var_181=0, var_25=0, var_27=8, var_32=0, var_408=255, var_54=0, var_59=0, var_60=0, var_90=0, var_91=-1, var_97=0, var_98=0] [L397] var_113 = var_113 & mask_SORT_1 [L398] SORT_1 bad_114_arg_0 = var_113; [L399] CALL __VERIFIER_assert(!(bad_114_arg_0)) [L21] COND TRUE !(cond) [L21] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 752 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 639.6s, OverallIterations: 106, TraceHistogramMax: 10, PathProgramHistogramMax: 3, EmptinessCheckTime: 1.3s, AutomataDifference: 119.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 131361 SdHoareTripleChecker+Valid, 76.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 131157 mSDsluCounter, 699909 SdHoareTripleChecker+Invalid, 66.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 586663 mSDsCounter, 458 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 154033 IncrementalHoareTripleChecker+Invalid, 154491 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 458 mSolverCounterUnsat, 113246 mSDtfsCounter, 154033 mSolverCounterSat, 1.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 47746 GetRequests, 46325 SyntacticMatches, 0 SemanticMatches, 1421 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25191 ImplicationChecksByTransitivity, 28.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=81391occurred in iteration=103, InterpolantAutomatonStates: 1057, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 28.7s AutomataMinimizationTime, 105 MinimizatonAttempts, 327130 StatesRemovedByMinimization, 60 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 8.5s SsaConstructionTime, 214.6s SatisfiabilityAnalysisTime, 188.7s InterpolantComputationTime, 97582 NumberOfCodeBlocks, 93866 NumberOfCodeBlocksAsserted, 152 NumberOfCheckSat, 116882 ConstructedInterpolants, 0 QuantifiedInterpolants, 427219 SizeOfPredicates, 142 NumberOfNonLiveVariables, 121998 ConjunctsInSsa, 1671 ConjunctsInUnsatCore, 178 InterpolantComputations, 86 PerfectInterpolantSequences, 114152/117046 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2024-12-02 06:33:39,815 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1 --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 77ae88daffb8285870a38f38e30db5571fe2930110ef63da660dc306a4cb95e3 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-12-02 06:33:42,141 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-12-02 06:33:42,233 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Bitvector.epf [2024-12-02 06:33:42,239 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-12-02 06:33:42,240 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-12-02 06:33:42,263 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-12-02 06:33:42,264 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-12-02 06:33:42,264 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-12-02 06:33:42,264 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-12-02 06:33:42,264 INFO L153 SettingsManager]: * Use memory slicer=true [2024-12-02 06:33:42,265 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-12-02 06:33:42,265 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-12-02 06:33:42,265 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-12-02 06:33:42,265 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-12-02 06:33:42,265 INFO L153 SettingsManager]: * Use SBE=true [2024-12-02 06:33:42,266 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-12-02 06:33:42,266 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-12-02 06:33:42,266 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-12-02 06:33:42,266 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-12-02 06:33:42,266 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-12-02 06:33:42,266 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-12-02 06:33:42,266 INFO L153 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2024-12-02 06:33:42,266 INFO L153 SettingsManager]: * Use bitvectors instead of ints=true [2024-12-02 06:33:42,267 INFO L153 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2024-12-02 06:33:42,267 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-12-02 06:33:42,267 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-12-02 06:33:42,267 INFO L153 SettingsManager]: * Use constant arrays=true [2024-12-02 06:33:42,267 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-12-02 06:33:42,267 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 06:33:42,267 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 06:33:42,267 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 06:33:42,267 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:33:42,267 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-12-02 06:33:42,268 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 06:33:42,268 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 06:33:42,268 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 06:33:42,268 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:33:42,268 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-12-02 06:33:42,268 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-12-02 06:33:42,268 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-12-02 06:33:42,268 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-12-02 06:33:42,268 INFO L153 SettingsManager]: * Trace refinement strategy=FOX [2024-12-02 06:33:42,268 INFO L153 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2024-12-02 06:33:42,268 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-12-02 06:33:42,268 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-12-02 06:33:42,268 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-12-02 06:33:42,268 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-12-02 06:33:42,269 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 77ae88daffb8285870a38f38e30db5571fe2930110ef63da660dc306a4cb95e3 [2024-12-02 06:33:42,528 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-12-02 06:33:42,537 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-12-02 06:33:42,539 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-12-02 06:33:42,541 INFO L270 PluginConnector]: Initializing CDTParser... [2024-12-02 06:33:42,542 INFO L274 PluginConnector]: CDTParser initialized [2024-12-02 06:33:42,543 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c [2024-12-02 06:33:45,285 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/data/ed895183d/926a5cd474ec4deaadab213115733aeb/FLAGd4dc3c6ef [2024-12-02 06:33:45,517 INFO L384 CDTParser]: Found 1 translation units. [2024-12-02 06:33:45,518 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c [2024-12-02 06:33:45,529 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/data/ed895183d/926a5cd474ec4deaadab213115733aeb/FLAGd4dc3c6ef [2024-12-02 06:33:45,543 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/data/ed895183d/926a5cd474ec4deaadab213115733aeb [2024-12-02 06:33:45,545 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-12-02 06:33:45,546 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-12-02 06:33:45,548 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-12-02 06:33:45,548 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-12-02 06:33:45,552 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-12-02 06:33:45,553 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:33:45" (1/1) ... [2024-12-02 06:33:45,553 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1d70b5e7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:45, skipping insertion in model container [2024-12-02 06:33:45,554 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:33:45" (1/1) ... [2024-12-02 06:33:45,586 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-12-02 06:33:45,734 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c[1270,1283] [2024-12-02 06:33:45,908 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 06:33:45,919 INFO L200 MainTranslator]: Completed pre-run [2024-12-02 06:33:45,928 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c[1270,1283] [2024-12-02 06:33:46,019 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 06:33:46,034 INFO L204 MainTranslator]: Completed translation [2024-12-02 06:33:46,034 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46 WrapperNode [2024-12-02 06:33:46,034 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-12-02 06:33:46,036 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-12-02 06:33:46,036 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-12-02 06:33:46,036 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-12-02 06:33:46,042 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46" (1/1) ... [2024-12-02 06:33:46,062 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46" (1/1) ... [2024-12-02 06:33:46,107 INFO L138 Inliner]: procedures = 18, calls = 41, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 946 [2024-12-02 06:33:46,108 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-12-02 06:33:46,109 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-12-02 06:33:46,109 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-12-02 06:33:46,109 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-12-02 06:33:46,118 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46" (1/1) ... [2024-12-02 06:33:46,119 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46" (1/1) ... [2024-12-02 06:33:46,127 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46" (1/1) ... [2024-12-02 06:33:46,154 INFO L175 MemorySlicer]: Split 20 memory accesses to 3 slices as follows [2, 9, 9]. 45 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0, 0]. The 8 writes are split as follows [0, 4, 4]. [2024-12-02 06:33:46,154 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46" (1/1) ... [2024-12-02 06:33:46,154 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46" (1/1) ... [2024-12-02 06:33:46,178 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46" (1/1) ... [2024-12-02 06:33:46,179 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46" (1/1) ... [2024-12-02 06:33:46,184 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46" (1/1) ... [2024-12-02 06:33:46,188 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46" (1/1) ... [2024-12-02 06:33:46,191 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46" (1/1) ... [2024-12-02 06:33:46,198 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-12-02 06:33:46,199 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-12-02 06:33:46,200 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-12-02 06:33:46,200 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-12-02 06:33:46,201 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46" (1/1) ... [2024-12-02 06:33:46,207 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:33:46,220 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:46,233 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-12-02 06:33:46,237 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-12-02 06:33:46,263 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-12-02 06:33:46,263 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1#0 [2024-12-02 06:33:46,263 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1#1 [2024-12-02 06:33:46,263 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1#2 [2024-12-02 06:33:46,263 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#0 [2024-12-02 06:33:46,263 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#1 [2024-12-02 06:33:46,264 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#2 [2024-12-02 06:33:46,264 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-12-02 06:33:46,264 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-12-02 06:33:46,264 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-12-02 06:33:46,264 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-12-02 06:33:46,264 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-12-02 06:33:46,264 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1#0 [2024-12-02 06:33:46,264 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1#1 [2024-12-02 06:33:46,264 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1#2 [2024-12-02 06:33:46,264 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-12-02 06:33:46,462 INFO L234 CfgBuilder]: Building ICFG [2024-12-02 06:33:46,463 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-12-02 06:33:47,207 INFO L? ?]: Removed 675 outVars from TransFormulas that were not future-live. [2024-12-02 06:33:47,208 INFO L283 CfgBuilder]: Performing block encoding [2024-12-02 06:33:47,217 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-12-02 06:33:47,218 INFO L312 CfgBuilder]: Removed 7 assume(true) statements. [2024-12-02 06:33:47,218 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:33:47 BoogieIcfgContainer [2024-12-02 06:33:47,218 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-12-02 06:33:47,221 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-12-02 06:33:47,221 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-12-02 06:33:47,226 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-12-02 06:33:47,226 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 06:33:45" (1/3) ... [2024-12-02 06:33:47,227 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@575507fa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 06:33:47, skipping insertion in model container [2024-12-02 06:33:47,227 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:33:46" (2/3) ... [2024-12-02 06:33:47,227 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@575507fa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 06:33:47, skipping insertion in model container [2024-12-02 06:33:47,227 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:33:47" (3/3) ... [2024-12-02 06:33:47,228 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c [2024-12-02 06:33:47,244 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-12-02 06:33:47,246 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.unsafe_arbitrated_fifos_n2d8w8.c that has 2 procedures, 42 locations, 1 initial locations, 7 loop locations, and 1 error locations. [2024-12-02 06:33:47,294 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-12-02 06:33:47,304 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@3b5caad, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-12-02 06:33:47,304 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-12-02 06:33:47,307 INFO L276 IsEmpty]: Start isEmpty. Operand has 42 states, 34 states have (on average 1.4705882352941178) internal successors, (50), 35 states have internal predecessors, (50), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:33:47,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2024-12-02 06:33:47,314 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:47,315 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:47,315 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:47,319 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:47,320 INFO L85 PathProgramCache]: Analyzing trace with hash -172425956, now seen corresponding path program 1 times [2024-12-02 06:33:47,330 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:33:47,330 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1286977108] [2024-12-02 06:33:47,330 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:33:47,331 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:47,331 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:47,332 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:33:47,333 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-12-02 06:33:47,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:33:47,764 INFO L256 TraceCheckSpWp]: Trace formula consists of 366 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-12-02 06:33:47,770 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:33:47,795 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-12-02 06:33:47,795 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:33:47,796 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:33:47,796 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1286977108] [2024-12-02 06:33:47,796 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1286977108] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:33:47,797 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:33:47,797 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-12-02 06:33:47,799 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1593167599] [2024-12-02 06:33:47,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:33:47,803 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-12-02 06:33:47,803 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:33:47,822 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-12-02 06:33:47,822 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 06:33:47,825 INFO L87 Difference]: Start difference. First operand has 42 states, 34 states have (on average 1.4705882352941178) internal successors, (50), 35 states have internal predecessors, (50), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) Second operand has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:33:47,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:47,844 INFO L93 Difference]: Finished difference Result 77 states and 117 transitions. [2024-12-02 06:33:47,845 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-12-02 06:33:47,847 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) Word has length 39 [2024-12-02 06:33:47,847 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:47,853 INFO L225 Difference]: With dead ends: 77 [2024-12-02 06:33:47,853 INFO L226 Difference]: Without dead ends: 39 [2024-12-02 06:33:47,856 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 38 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 06:33:47,859 INFO L435 NwaCegarLoop]: 49 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 49 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:47,860 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:33:47,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2024-12-02 06:33:47,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2024-12-02 06:33:47,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 32 states have (on average 1.21875) internal successors, (39), 32 states have internal predecessors, (39), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:33:47,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 49 transitions. [2024-12-02 06:33:47,900 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 49 transitions. Word has length 39 [2024-12-02 06:33:47,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:47,901 INFO L471 AbstractCegarLoop]: Abstraction has 39 states and 49 transitions. [2024-12-02 06:33:47,901 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:33:47,901 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 49 transitions. [2024-12-02 06:33:47,903 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2024-12-02 06:33:47,903 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:47,903 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:47,915 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-12-02 06:33:48,104 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:48,104 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:48,105 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:48,105 INFO L85 PathProgramCache]: Analyzing trace with hash -1962528174, now seen corresponding path program 1 times [2024-12-02 06:33:48,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:33:48,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1313272487] [2024-12-02 06:33:48,106 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:33:48,106 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:48,106 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:48,108 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:33:48,109 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-12-02 06:33:48,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:33:48,456 INFO L256 TraceCheckSpWp]: Trace formula consists of 366 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-12-02 06:33:48,460 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:33:48,488 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:33:48,488 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:33:48,488 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:33:48,488 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1313272487] [2024-12-02 06:33:48,489 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1313272487] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:33:48,489 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:33:48,489 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:33:48,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1926500333] [2024-12-02 06:33:48,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:33:48,490 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:33:48,490 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:33:48,490 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:33:48,491 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:33:48,491 INFO L87 Difference]: Start difference. First operand 39 states and 49 transitions. Second operand has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 3 states have internal predecessors, (17), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:33:48,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:48,512 INFO L93 Difference]: Finished difference Result 76 states and 96 transitions. [2024-12-02 06:33:48,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:33:48,513 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 3 states have internal predecessors, (17), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 39 [2024-12-02 06:33:48,513 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:48,514 INFO L225 Difference]: With dead ends: 76 [2024-12-02 06:33:48,514 INFO L226 Difference]: Without dead ends: 41 [2024-12-02 06:33:48,514 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:33:48,515 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 44 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 91 SdHoareTripleChecker+Invalid, 6 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:48,515 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 91 Invalid, 6 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:33:48,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2024-12-02 06:33:48,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 40. [2024-12-02 06:33:48,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 33 states have (on average 1.2121212121212122) internal successors, (40), 33 states have internal predecessors, (40), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:33:48,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 50 transitions. [2024-12-02 06:33:48,521 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 50 transitions. Word has length 39 [2024-12-02 06:33:48,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:48,522 INFO L471 AbstractCegarLoop]: Abstraction has 40 states and 50 transitions. [2024-12-02 06:33:48,522 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 3 states have internal predecessors, (17), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:33:48,522 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 50 transitions. [2024-12-02 06:33:48,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2024-12-02 06:33:48,523 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:48,523 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:48,533 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-12-02 06:33:48,723 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:48,724 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:48,724 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:48,725 INFO L85 PathProgramCache]: Analyzing trace with hash 482086798, now seen corresponding path program 1 times [2024-12-02 06:33:48,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:33:48,726 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [536037494] [2024-12-02 06:33:48,726 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:33:48,726 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:48,726 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:48,728 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:33:48,730 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-12-02 06:33:49,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:33:49,078 INFO L256 TraceCheckSpWp]: Trace formula consists of 371 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-12-02 06:33:49,082 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:33:49,093 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:33:49,094 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:33:49,094 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:33:49,094 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [536037494] [2024-12-02 06:33:49,094 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [536037494] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:33:49,094 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:33:49,094 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:33:49,094 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1949684871] [2024-12-02 06:33:49,094 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:33:49,094 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:33:49,095 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:33:49,095 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:33:49,095 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:33:49,095 INFO L87 Difference]: Start difference. First operand 40 states and 50 transitions. Second operand has 3 states, 3 states have (on average 6.333333333333333) internal successors, (19), 3 states have internal predecessors, (19), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:33:49,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:49,122 INFO L93 Difference]: Finished difference Result 74 states and 93 transitions. [2024-12-02 06:33:49,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:33:49,123 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 6.333333333333333) internal successors, (19), 3 states have internal predecessors, (19), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 41 [2024-12-02 06:33:49,124 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:49,124 INFO L225 Difference]: With dead ends: 74 [2024-12-02 06:33:49,124 INFO L226 Difference]: Without dead ends: 42 [2024-12-02 06:33:49,125 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:33:49,125 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:49,126 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:33:49,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2024-12-02 06:33:49,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 41. [2024-12-02 06:33:49,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 34 states have (on average 1.2058823529411764) internal successors, (41), 34 states have internal predecessors, (41), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:33:49,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 51 transitions. [2024-12-02 06:33:49,132 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 51 transitions. Word has length 41 [2024-12-02 06:33:49,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:49,132 INFO L471 AbstractCegarLoop]: Abstraction has 41 states and 51 transitions. [2024-12-02 06:33:49,132 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 6.333333333333333) internal successors, (19), 3 states have internal predecessors, (19), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:33:49,132 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 51 transitions. [2024-12-02 06:33:49,133 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2024-12-02 06:33:49,133 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:49,133 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:49,144 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2024-12-02 06:33:49,333 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:49,334 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:49,334 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:49,334 INFO L85 PathProgramCache]: Analyzing trace with hash -1508766582, now seen corresponding path program 1 times [2024-12-02 06:33:49,335 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:33:49,335 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [373347957] [2024-12-02 06:33:49,335 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:33:49,335 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:49,335 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:49,337 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:33:49,338 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-12-02 06:33:49,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:33:49,683 INFO L256 TraceCheckSpWp]: Trace formula consists of 376 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-12-02 06:33:49,687 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:33:49,715 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:33:49,715 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:33:49,802 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:33:49,802 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:33:49,802 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [373347957] [2024-12-02 06:33:49,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [373347957] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:33:49,803 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:33:49,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-12-02 06:33:49,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [864388637] [2024-12-02 06:33:49,803 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:33:49,803 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:33:49,803 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:33:49,804 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:33:49,804 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:33:49,804 INFO L87 Difference]: Start difference. First operand 41 states and 51 transitions. Second operand has 7 states, 7 states have (on average 4.0) internal successors, (28), 7 states have internal predecessors, (28), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:33:49,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:49,877 INFO L93 Difference]: Finished difference Result 83 states and 105 transitions. [2024-12-02 06:33:49,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:33:49,879 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 4.0) internal successors, (28), 7 states have internal predecessors, (28), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 43 [2024-12-02 06:33:49,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:49,879 INFO L225 Difference]: With dead ends: 83 [2024-12-02 06:33:49,879 INFO L226 Difference]: Without dead ends: 47 [2024-12-02 06:33:49,880 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:33:49,881 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 132 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 179 SdHoareTripleChecker+Invalid, 23 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:49,881 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 179 Invalid, 23 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:33:49,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2024-12-02 06:33:49,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2024-12-02 06:33:49,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 40 states have (on average 1.175) internal successors, (47), 40 states have internal predecessors, (47), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:33:49,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 57 transitions. [2024-12-02 06:33:49,887 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 57 transitions. Word has length 43 [2024-12-02 06:33:49,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:49,887 INFO L471 AbstractCegarLoop]: Abstraction has 47 states and 57 transitions. [2024-12-02 06:33:49,888 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 4.0) internal successors, (28), 7 states have internal predecessors, (28), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:33:49,888 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 57 transitions. [2024-12-02 06:33:49,888 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2024-12-02 06:33:49,888 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:49,889 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:49,899 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-12-02 06:33:50,089 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:50,089 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:50,090 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:50,090 INFO L85 PathProgramCache]: Analyzing trace with hash 1082379582, now seen corresponding path program 2 times [2024-12-02 06:33:50,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:33:50,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1761029711] [2024-12-02 06:33:50,090 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:33:50,091 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:50,091 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:50,092 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:33:50,093 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-12-02 06:33:50,393 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:33:50,393 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:33:50,398 INFO L256 TraceCheckSpWp]: Trace formula consists of 261 conjuncts, 14 conjuncts are in the unsatisfiable core [2024-12-02 06:33:50,402 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:33:50,688 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 57 trivial. 0 not checked. [2024-12-02 06:33:50,689 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:33:50,689 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:33:50,689 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1761029711] [2024-12-02 06:33:50,689 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1761029711] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:33:50,689 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:33:50,689 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:33:50,689 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503791023] [2024-12-02 06:33:50,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:33:50,689 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:33:50,689 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:33:50,690 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:33:50,690 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:33:50,690 INFO L87 Difference]: Start difference. First operand 47 states and 57 transitions. Second operand has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:33:50,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:50,897 INFO L93 Difference]: Finished difference Result 61 states and 76 transitions. [2024-12-02 06:33:50,897 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:33:50,898 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 49 [2024-12-02 06:33:50,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:50,898 INFO L225 Difference]: With dead ends: 61 [2024-12-02 06:33:50,899 INFO L226 Difference]: Without dead ends: 59 [2024-12-02 06:33:50,899 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:33:50,900 INFO L435 NwaCegarLoop]: 37 mSDtfsCounter, 34 mSDsluCounter, 75 mSDsCounter, 0 mSdLazyCounter, 43 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 39 SdHoareTripleChecker+Valid, 112 SdHoareTripleChecker+Invalid, 48 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 43 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:50,900 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [39 Valid, 112 Invalid, 48 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 43 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:33:50,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2024-12-02 06:33:50,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2024-12-02 06:33:50,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 47 states have (on average 1.148936170212766) internal successors, (54), 47 states have internal predecessors, (54), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:33:50,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 74 transitions. [2024-12-02 06:33:50,911 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 74 transitions. Word has length 49 [2024-12-02 06:33:50,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:50,913 INFO L471 AbstractCegarLoop]: Abstraction has 59 states and 74 transitions. [2024-12-02 06:33:50,913 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:33:50,913 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 74 transitions. [2024-12-02 06:33:50,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2024-12-02 06:33:50,914 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:50,914 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:50,924 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2024-12-02 06:33:51,115 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:51,115 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:51,115 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:51,116 INFO L85 PathProgramCache]: Analyzing trace with hash -1262899509, now seen corresponding path program 1 times [2024-12-02 06:33:51,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:33:51,116 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [69448823] [2024-12-02 06:33:51,116 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:33:51,116 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:51,117 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:51,118 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:33:51,119 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-12-02 06:33:51,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:33:51,643 INFO L256 TraceCheckSpWp]: Trace formula consists of 1109 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-12-02 06:33:51,648 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:33:51,659 INFO L134 CoverageAnalysis]: Checked inductivity of 209 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:33:51,660 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:33:51,660 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:33:51,660 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [69448823] [2024-12-02 06:33:51,660 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [69448823] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:33:51,660 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:33:51,660 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:33:51,660 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [800241269] [2024-12-02 06:33:51,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:33:51,660 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:33:51,661 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:33:51,661 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:33:51,661 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:33:51,661 INFO L87 Difference]: Start difference. First operand 59 states and 74 transitions. Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:33:51,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:51,701 INFO L93 Difference]: Finished difference Result 92 states and 116 transitions. [2024-12-02 06:33:51,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:33:51,704 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 90 [2024-12-02 06:33:51,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:51,705 INFO L225 Difference]: With dead ends: 92 [2024-12-02 06:33:51,705 INFO L226 Difference]: Without dead ends: 61 [2024-12-02 06:33:51,705 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 89 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:33:51,706 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:51,706 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:33:51,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2024-12-02 06:33:51,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 60. [2024-12-02 06:33:51,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 48 states have (on average 1.1458333333333333) internal successors, (55), 48 states have internal predecessors, (55), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:33:51,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 75 transitions. [2024-12-02 06:33:51,716 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 75 transitions. Word has length 90 [2024-12-02 06:33:51,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:51,717 INFO L471 AbstractCegarLoop]: Abstraction has 60 states and 75 transitions. [2024-12-02 06:33:51,717 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:33:51,717 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 75 transitions. [2024-12-02 06:33:51,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2024-12-02 06:33:51,718 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:51,718 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:51,730 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-12-02 06:33:51,919 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:51,919 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:51,919 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:51,920 INFO L85 PathProgramCache]: Analyzing trace with hash 1332255303, now seen corresponding path program 1 times [2024-12-02 06:33:51,920 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:33:51,920 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1214173875] [2024-12-02 06:33:51,920 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:33:51,920 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:51,921 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:51,922 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:33:51,923 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-12-02 06:33:52,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:33:52,500 INFO L256 TraceCheckSpWp]: Trace formula consists of 1115 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-12-02 06:33:52,504 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:33:52,519 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2024-12-02 06:33:52,520 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:33:52,520 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:33:52,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1214173875] [2024-12-02 06:33:52,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1214173875] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:33:52,520 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:33:52,520 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:33:52,520 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [756182862] [2024-12-02 06:33:52,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:33:52,521 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:33:52,521 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:33:52,522 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:33:52,522 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:33:52,522 INFO L87 Difference]: Start difference. First operand 60 states and 75 transitions. Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:33:52,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:52,557 INFO L93 Difference]: Finished difference Result 94 states and 118 transitions. [2024-12-02 06:33:52,558 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:33:52,558 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 92 [2024-12-02 06:33:52,559 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:52,559 INFO L225 Difference]: With dead ends: 94 [2024-12-02 06:33:52,559 INFO L226 Difference]: Without dead ends: 62 [2024-12-02 06:33:52,560 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:33:52,560 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:52,560 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:33:52,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2024-12-02 06:33:52,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 61. [2024-12-02 06:33:52,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 49 states have (on average 1.1428571428571428) internal successors, (56), 49 states have internal predecessors, (56), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:33:52,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 76 transitions. [2024-12-02 06:33:52,569 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 76 transitions. Word has length 92 [2024-12-02 06:33:52,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:52,569 INFO L471 AbstractCegarLoop]: Abstraction has 61 states and 76 transitions. [2024-12-02 06:33:52,569 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:33:52,569 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 76 transitions. [2024-12-02 06:33:52,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2024-12-02 06:33:52,571 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:52,571 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:52,580 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-12-02 06:33:52,771 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:52,771 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:52,771 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:52,772 INFO L85 PathProgramCache]: Analyzing trace with hash -523258493, now seen corresponding path program 1 times [2024-12-02 06:33:52,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:33:52,773 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [950653188] [2024-12-02 06:33:52,773 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:33:52,773 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:52,773 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:52,774 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:33:52,775 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-12-02 06:33:53,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:33:53,340 INFO L256 TraceCheckSpWp]: Trace formula consists of 1121 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-12-02 06:33:53,343 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:33:53,353 INFO L134 CoverageAnalysis]: Checked inductivity of 211 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 99 trivial. 0 not checked. [2024-12-02 06:33:53,353 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:33:53,353 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:33:53,354 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [950653188] [2024-12-02 06:33:53,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [950653188] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:33:53,354 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:33:53,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:33:53,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [61058857] [2024-12-02 06:33:53,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:33:53,354 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:33:53,354 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:33:53,355 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:33:53,355 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:33:53,355 INFO L87 Difference]: Start difference. First operand 61 states and 76 transitions. Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:33:53,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:53,380 INFO L93 Difference]: Finished difference Result 96 states and 120 transitions. [2024-12-02 06:33:53,380 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:33:53,380 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 94 [2024-12-02 06:33:53,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:53,381 INFO L225 Difference]: With dead ends: 96 [2024-12-02 06:33:53,381 INFO L226 Difference]: Without dead ends: 63 [2024-12-02 06:33:53,382 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 92 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:33:53,382 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:53,383 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:33:53,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2024-12-02 06:33:53,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 62. [2024-12-02 06:33:53,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 50 states have (on average 1.14) internal successors, (57), 50 states have internal predecessors, (57), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:33:53,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 77 transitions. [2024-12-02 06:33:53,395 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 77 transitions. Word has length 94 [2024-12-02 06:33:53,396 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:53,396 INFO L471 AbstractCegarLoop]: Abstraction has 62 states and 77 transitions. [2024-12-02 06:33:53,396 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:33:53,396 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 77 transitions. [2024-12-02 06:33:53,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2024-12-02 06:33:53,397 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:53,397 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:53,409 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2024-12-02 06:33:53,598 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:53,598 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:53,599 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:53,599 INFO L85 PathProgramCache]: Analyzing trace with hash 1675280511, now seen corresponding path program 1 times [2024-12-02 06:33:53,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:33:53,600 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1138710617] [2024-12-02 06:33:53,600 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:33:53,600 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:53,600 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:53,602 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:33:53,603 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-12-02 06:33:54,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:33:54,241 INFO L256 TraceCheckSpWp]: Trace formula consists of 1127 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-12-02 06:33:54,244 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:33:54,252 INFO L134 CoverageAnalysis]: Checked inductivity of 212 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2024-12-02 06:33:54,252 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:33:54,252 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:33:54,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1138710617] [2024-12-02 06:33:54,252 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1138710617] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:33:54,252 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:33:54,252 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:33:54,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1292051042] [2024-12-02 06:33:54,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:33:54,253 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:33:54,253 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:33:54,254 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:33:54,254 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:33:54,254 INFO L87 Difference]: Start difference. First operand 62 states and 77 transitions. Second operand has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:33:54,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:54,276 INFO L93 Difference]: Finished difference Result 98 states and 122 transitions. [2024-12-02 06:33:54,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:33:54,277 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 96 [2024-12-02 06:33:54,277 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:54,278 INFO L225 Difference]: With dead ends: 98 [2024-12-02 06:33:54,278 INFO L226 Difference]: Without dead ends: 64 [2024-12-02 06:33:54,278 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:33:54,278 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:54,279 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:33:54,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2024-12-02 06:33:54,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 63. [2024-12-02 06:33:54,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 51 states have (on average 1.1372549019607843) internal successors, (58), 51 states have internal predecessors, (58), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:33:54,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 78 transitions. [2024-12-02 06:33:54,286 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 78 transitions. Word has length 96 [2024-12-02 06:33:54,287 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:54,287 INFO L471 AbstractCegarLoop]: Abstraction has 63 states and 78 transitions. [2024-12-02 06:33:54,287 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:33:54,287 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 78 transitions. [2024-12-02 06:33:54,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2024-12-02 06:33:54,288 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:54,288 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:54,298 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-12-02 06:33:54,488 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:54,489 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:54,489 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:54,489 INFO L85 PathProgramCache]: Analyzing trace with hash -571376837, now seen corresponding path program 1 times [2024-12-02 06:33:54,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:33:54,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [473299663] [2024-12-02 06:33:54,490 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:33:54,490 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:54,490 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:54,491 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:33:54,492 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-12-02 06:33:55,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:33:55,107 INFO L256 TraceCheckSpWp]: Trace formula consists of 1133 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-12-02 06:33:55,111 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:33:55,127 INFO L134 CoverageAnalysis]: Checked inductivity of 213 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 212 trivial. 0 not checked. [2024-12-02 06:33:55,128 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:33:55,189 INFO L134 CoverageAnalysis]: Checked inductivity of 213 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 212 trivial. 0 not checked. [2024-12-02 06:33:55,189 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:33:55,189 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [473299663] [2024-12-02 06:33:55,189 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [473299663] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:33:55,189 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:33:55,189 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-12-02 06:33:55,189 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [757139039] [2024-12-02 06:33:55,189 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:33:55,190 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:33:55,190 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:33:55,190 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:33:55,190 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:33:55,191 INFO L87 Difference]: Start difference. First operand 63 states and 78 transitions. Second operand has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 7 states have internal predecessors, (46), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:33:55,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:55,241 INFO L93 Difference]: Finished difference Result 117 states and 148 transitions. [2024-12-02 06:33:55,241 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:33:55,242 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 7 states have internal predecessors, (46), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 98 [2024-12-02 06:33:55,242 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:55,242 INFO L225 Difference]: With dead ends: 117 [2024-12-02 06:33:55,242 INFO L226 Difference]: Without dead ends: 69 [2024-12-02 06:33:55,242 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 195 GetRequests, 189 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:33:55,243 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 3 mSDsluCounter, 215 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 262 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:55,243 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 262 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:33:55,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2024-12-02 06:33:55,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2024-12-02 06:33:55,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 57 states have (on average 1.1228070175438596) internal successors, (64), 57 states have internal predecessors, (64), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:33:55,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 84 transitions. [2024-12-02 06:33:55,258 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 84 transitions. Word has length 98 [2024-12-02 06:33:55,258 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:55,258 INFO L471 AbstractCegarLoop]: Abstraction has 69 states and 84 transitions. [2024-12-02 06:33:55,258 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 7 states have internal predecessors, (46), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:33:55,258 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 84 transitions. [2024-12-02 06:33:55,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2024-12-02 06:33:55,259 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:55,259 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:55,269 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-12-02 06:33:55,459 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:55,460 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:55,460 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:55,460 INFO L85 PathProgramCache]: Analyzing trace with hash -327439417, now seen corresponding path program 2 times [2024-12-02 06:33:55,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:33:55,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1966737130] [2024-12-02 06:33:55,461 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:33:55,461 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:55,461 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:55,462 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:33:55,463 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-12-02 06:33:56,249 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:33:56,249 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:33:56,258 INFO L256 TraceCheckSpWp]: Trace formula consists of 1148 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-12-02 06:33:56,261 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:33:56,276 INFO L134 CoverageAnalysis]: Checked inductivity of 228 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 115 trivial. 0 not checked. [2024-12-02 06:33:56,276 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:33:56,333 INFO L134 CoverageAnalysis]: Checked inductivity of 228 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 215 trivial. 0 not checked. [2024-12-02 06:33:56,333 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:33:56,333 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1966737130] [2024-12-02 06:33:56,333 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1966737130] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:33:56,333 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:33:56,333 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-12-02 06:33:56,334 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1986233632] [2024-12-02 06:33:56,334 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:33:56,334 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:33:56,334 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:33:56,335 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:33:56,335 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:33:56,335 INFO L87 Difference]: Start difference. First operand 69 states and 84 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:33:56,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:56,404 INFO L93 Difference]: Finished difference Result 110 states and 136 transitions. [2024-12-02 06:33:56,406 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:33:56,407 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 104 [2024-12-02 06:33:56,407 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:56,407 INFO L225 Difference]: With dead ends: 110 [2024-12-02 06:33:56,407 INFO L226 Difference]: Without dead ends: 75 [2024-12-02 06:33:56,408 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 207 GetRequests, 201 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:33:56,408 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 86 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 133 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:56,408 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 133 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:33:56,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2024-12-02 06:33:56,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2024-12-02 06:33:56,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 63 states have (on average 1.1111111111111112) internal successors, (70), 63 states have internal predecessors, (70), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:33:56,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 90 transitions. [2024-12-02 06:33:56,415 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 90 transitions. Word has length 104 [2024-12-02 06:33:56,416 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:56,416 INFO L471 AbstractCegarLoop]: Abstraction has 75 states and 90 transitions. [2024-12-02 06:33:56,416 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:33:56,416 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 90 transitions. [2024-12-02 06:33:56,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2024-12-02 06:33:56,417 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:56,417 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:56,427 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-12-02 06:33:56,617 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:56,617 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:56,618 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:56,618 INFO L85 PathProgramCache]: Analyzing trace with hash -1578953669, now seen corresponding path program 3 times [2024-12-02 06:33:56,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:33:56,618 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [947325195] [2024-12-02 06:33:56,619 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-12-02 06:33:56,619 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:56,619 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:56,620 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:33:56,621 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-12-02 06:33:57,497 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2024-12-02 06:33:57,497 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:33:57,506 INFO L256 TraceCheckSpWp]: Trace formula consists of 982 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-12-02 06:33:57,509 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:33:57,524 INFO L134 CoverageAnalysis]: Checked inductivity of 243 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 130 trivial. 0 not checked. [2024-12-02 06:33:57,524 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:33:57,589 INFO L134 CoverageAnalysis]: Checked inductivity of 243 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 230 trivial. 0 not checked. [2024-12-02 06:33:57,589 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:33:57,589 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [947325195] [2024-12-02 06:33:57,589 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [947325195] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:33:57,590 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:33:57,590 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-12-02 06:33:57,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [948432959] [2024-12-02 06:33:57,590 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:33:57,590 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:33:57,590 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:33:57,591 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:33:57,591 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:33:57,591 INFO L87 Difference]: Start difference. First operand 75 states and 90 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:33:57,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:57,652 INFO L93 Difference]: Finished difference Result 122 states and 148 transitions. [2024-12-02 06:33:57,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:33:57,652 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 110 [2024-12-02 06:33:57,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:57,654 INFO L225 Difference]: With dead ends: 122 [2024-12-02 06:33:57,654 INFO L226 Difference]: Without dead ends: 81 [2024-12-02 06:33:57,654 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 219 GetRequests, 213 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:33:57,654 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 86 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 133 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:57,655 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 133 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:33:57,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2024-12-02 06:33:57,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2024-12-02 06:33:57,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81 states, 69 states have (on average 1.1014492753623188) internal successors, (76), 69 states have internal predecessors, (76), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:33:57,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 96 transitions. [2024-12-02 06:33:57,664 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 96 transitions. Word has length 110 [2024-12-02 06:33:57,664 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:57,664 INFO L471 AbstractCegarLoop]: Abstraction has 81 states and 96 transitions. [2024-12-02 06:33:57,665 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:33:57,665 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 96 transitions. [2024-12-02 06:33:57,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2024-12-02 06:33:57,666 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:57,666 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:57,678 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-12-02 06:33:57,866 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:57,867 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:57,867 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:57,867 INFO L85 PathProgramCache]: Analyzing trace with hash 710782511, now seen corresponding path program 4 times [2024-12-02 06:33:57,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:33:57,868 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [196249047] [2024-12-02 06:33:57,868 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-12-02 06:33:57,868 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:57,868 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:57,869 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:33:57,870 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-12-02 06:33:58,636 INFO L229 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-12-02 06:33:58,636 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:33:58,646 INFO L256 TraceCheckSpWp]: Trace formula consists of 1138 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-12-02 06:33:58,649 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:33:58,661 INFO L134 CoverageAnalysis]: Checked inductivity of 258 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2024-12-02 06:33:58,661 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:33:58,722 INFO L134 CoverageAnalysis]: Checked inductivity of 258 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2024-12-02 06:33:58,723 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:33:58,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [196249047] [2024-12-02 06:33:58,723 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [196249047] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:33:58,723 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:33:58,723 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-12-02 06:33:58,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1420315893] [2024-12-02 06:33:58,723 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:33:58,724 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:33:58,724 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:33:58,724 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:33:58,724 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:33:58,725 INFO L87 Difference]: Start difference. First operand 81 states and 96 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:33:58,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:33:58,798 INFO L93 Difference]: Finished difference Result 134 states and 160 transitions. [2024-12-02 06:33:58,799 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:33:58,799 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 116 [2024-12-02 06:33:58,799 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:33:58,800 INFO L225 Difference]: With dead ends: 134 [2024-12-02 06:33:58,800 INFO L226 Difference]: Without dead ends: 87 [2024-12-02 06:33:58,801 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 231 GetRequests, 225 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:33:58,801 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 129 mSDsCounter, 0 mSdLazyCounter, 24 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 176 SdHoareTripleChecker+Invalid, 26 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 24 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:33:58,801 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 176 Invalid, 26 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 24 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:33:58,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2024-12-02 06:33:58,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2024-12-02 06:33:58,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 75 states have (on average 1.0933333333333333) internal successors, (82), 75 states have internal predecessors, (82), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:33:58,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 102 transitions. [2024-12-02 06:33:58,812 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 102 transitions. Word has length 116 [2024-12-02 06:33:58,813 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:33:58,813 INFO L471 AbstractCegarLoop]: Abstraction has 87 states and 102 transitions. [2024-12-02 06:33:58,813 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:33:58,813 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 102 transitions. [2024-12-02 06:33:58,815 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2024-12-02 06:33:58,815 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:33:58,815 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:33:58,828 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2024-12-02 06:33:59,015 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:59,016 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:33:59,016 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:33:59,016 INFO L85 PathProgramCache]: Analyzing trace with hash -739418781, now seen corresponding path program 5 times [2024-12-02 06:33:59,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:33:59,017 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1302997647] [2024-12-02 06:33:59,018 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-12-02 06:33:59,018 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:33:59,018 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:33:59,020 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:33:59,020 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-12-02 06:34:05,543 INFO L229 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2024-12-02 06:34:05,543 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:34:05,556 INFO L256 TraceCheckSpWp]: Trace formula consists of 943 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-12-02 06:34:05,560 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:34:05,575 INFO L134 CoverageAnalysis]: Checked inductivity of 273 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2024-12-02 06:34:05,576 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:34:05,639 INFO L134 CoverageAnalysis]: Checked inductivity of 273 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2024-12-02 06:34:05,640 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:34:05,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1302997647] [2024-12-02 06:34:05,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1302997647] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:34:05,640 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:34:05,640 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-12-02 06:34:05,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000582454] [2024-12-02 06:34:05,640 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:34:05,640 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:34:05,641 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:34:05,641 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:34:05,641 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:34:05,641 INFO L87 Difference]: Start difference. First operand 87 states and 102 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:34:05,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:34:05,740 INFO L93 Difference]: Finished difference Result 146 states and 172 transitions. [2024-12-02 06:34:05,741 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:34:05,741 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 122 [2024-12-02 06:34:05,742 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:34:05,742 INFO L225 Difference]: With dead ends: 146 [2024-12-02 06:34:05,742 INFO L226 Difference]: Without dead ends: 93 [2024-12-02 06:34:05,742 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 243 GetRequests, 237 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:34:05,743 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 3 mSDsluCounter, 215 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 262 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:34:05,743 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 262 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:34:05,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2024-12-02 06:34:05,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2024-12-02 06:34:05,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93 states, 81 states have (on average 1.0864197530864197) internal successors, (88), 81 states have internal predecessors, (88), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-12-02 06:34:05,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 108 transitions. [2024-12-02 06:34:05,749 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 108 transitions. Word has length 122 [2024-12-02 06:34:05,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:34:05,749 INFO L471 AbstractCegarLoop]: Abstraction has 93 states and 108 transitions. [2024-12-02 06:34:05,749 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:34:05,749 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 108 transitions. [2024-12-02 06:34:05,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2024-12-02 06:34:05,750 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:34:05,750 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:34:05,763 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2024-12-02 06:34:05,950 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:34:05,950 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:34:05,951 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:34:05,951 INFO L85 PathProgramCache]: Analyzing trace with hash -651047657, now seen corresponding path program 6 times [2024-12-02 06:34:05,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:34:05,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1938122444] [2024-12-02 06:34:05,952 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-12-02 06:34:05,952 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:34:05,952 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:34:05,953 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:34:05,954 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-12-02 06:34:07,889 INFO L229 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2024-12-02 06:34:07,890 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:34:07,904 INFO L256 TraceCheckSpWp]: Trace formula consists of 1122 conjuncts, 45 conjuncts are in the unsatisfiable core [2024-12-02 06:34:07,914 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:34:08,926 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 12 proven. 34 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2024-12-02 06:34:08,926 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:34:09,044 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:34:09,044 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1938122444] [2024-12-02 06:34:09,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1938122444] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:34:09,044 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1753400570] [2024-12-02 06:34:09,044 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-12-02 06:34:09,044 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-12-02 06:34:09,044 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/cvc4 [2024-12-02 06:34:09,047 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-12-02 06:34:09,048 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (17)] Waiting until timeout for monitored process [2024-12-02 06:34:11,493 INFO L229 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2024-12-02 06:34:11,493 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:34:11,522 INFO L256 TraceCheckSpWp]: Trace formula consists of 1122 conjuncts, 42 conjuncts are in the unsatisfiable core [2024-12-02 06:34:11,529 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:34:12,415 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 12 proven. 27 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2024-12-02 06:34:12,415 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:34:12,478 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1753400570] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:34:12,478 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:34:12,478 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 11] total 17 [2024-12-02 06:34:12,478 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201452494] [2024-12-02 06:34:12,478 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:34:12,478 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2024-12-02 06:34:12,478 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:34:12,479 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2024-12-02 06:34:12,479 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=294, Unknown=0, NotChecked=0, Total=342 [2024-12-02 06:34:12,479 INFO L87 Difference]: Start difference. First operand 93 states and 108 transitions. Second operand has 17 states, 15 states have (on average 5.133333333333334) internal successors, (77), 16 states have internal predecessors, (77), 5 states have call successors, (16), 1 states have call predecessors, (16), 2 states have return successors, (16), 5 states have call predecessors, (16), 5 states have call successors, (16) [2024-12-02 06:34:13,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:34:13,431 INFO L93 Difference]: Finished difference Result 169 states and 195 transitions. [2024-12-02 06:34:13,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2024-12-02 06:34:13,432 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 15 states have (on average 5.133333333333334) internal successors, (77), 16 states have internal predecessors, (77), 5 states have call successors, (16), 1 states have call predecessors, (16), 2 states have return successors, (16), 5 states have call predecessors, (16), 5 states have call successors, (16) Word has length 128 [2024-12-02 06:34:13,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:34:13,434 INFO L225 Difference]: With dead ends: 169 [2024-12-02 06:34:13,434 INFO L226 Difference]: Without dead ends: 167 [2024-12-02 06:34:13,435 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 244 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 76 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=88, Invalid=464, Unknown=0, NotChecked=0, Total=552 [2024-12-02 06:34:13,435 INFO L435 NwaCegarLoop]: 39 mSDtfsCounter, 68 mSDsluCounter, 397 mSDsCounter, 0 mSdLazyCounter, 451 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 73 SdHoareTripleChecker+Valid, 436 SdHoareTripleChecker+Invalid, 455 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 451 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2024-12-02 06:34:13,435 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [73 Valid, 436 Invalid, 455 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 451 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2024-12-02 06:34:13,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2024-12-02 06:34:13,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 146. [2024-12-02 06:34:13,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146 states, 129 states have (on average 1.0852713178294573) internal successors, (140), 129 states have internal predecessors, (140), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:34:13,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 170 transitions. [2024-12-02 06:34:13,454 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 170 transitions. Word has length 128 [2024-12-02 06:34:13,454 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:34:13,454 INFO L471 AbstractCegarLoop]: Abstraction has 146 states and 170 transitions. [2024-12-02 06:34:13,454 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 15 states have (on average 5.133333333333334) internal successors, (77), 16 states have internal predecessors, (77), 5 states have call successors, (16), 1 states have call predecessors, (16), 2 states have return successors, (16), 5 states have call predecessors, (16), 5 states have call successors, (16) [2024-12-02 06:34:13,454 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 170 transitions. [2024-12-02 06:34:13,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 202 [2024-12-02 06:34:13,456 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:34:13,456 INFO L218 NwaCegarLoop]: trace histogram [15, 15, 15, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:34:13,483 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0 [2024-12-02 06:34:13,680 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (17)] Ended with exit code 0 [2024-12-02 06:34:13,857 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt [2024-12-02 06:34:13,857 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:34:13,858 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:34:13,858 INFO L85 PathProgramCache]: Analyzing trace with hash -1549169454, now seen corresponding path program 7 times [2024-12-02 06:34:13,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:34:13,859 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1717962967] [2024-12-02 06:34:13,859 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-12-02 06:34:13,859 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:34:13,859 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:34:13,860 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:34:13,861 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-12-02 06:34:15,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:34:15,065 INFO L256 TraceCheckSpWp]: Trace formula consists of 2034 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-12-02 06:34:15,070 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:34:15,106 INFO L134 CoverageAnalysis]: Checked inductivity of 785 backedges. 308 proven. 16 refuted. 0 times theorem prover too weak. 461 trivial. 0 not checked. [2024-12-02 06:34:15,107 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:34:15,261 INFO L134 CoverageAnalysis]: Checked inductivity of 785 backedges. 108 proven. 16 refuted. 0 times theorem prover too weak. 661 trivial. 0 not checked. [2024-12-02 06:34:15,261 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:34:15,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1717962967] [2024-12-02 06:34:15,261 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1717962967] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:34:15,261 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:34:15,261 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 13 [2024-12-02 06:34:15,261 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2046362722] [2024-12-02 06:34:15,261 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:34:15,261 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2024-12-02 06:34:15,261 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:34:15,262 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-12-02 06:34:15,262 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=103, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:34:15,262 INFO L87 Difference]: Start difference. First operand 146 states and 170 transitions. Second operand has 13 states, 13 states have (on average 5.615384615384615) internal successors, (73), 13 states have internal predecessors, (73), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:34:15,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:34:15,498 INFO L93 Difference]: Finished difference Result 262 states and 313 transitions. [2024-12-02 06:34:15,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-12-02 06:34:15,499 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 5.615384615384615) internal successors, (73), 13 states have internal predecessors, (73), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 201 [2024-12-02 06:34:15,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:34:15,500 INFO L225 Difference]: With dead ends: 262 [2024-12-02 06:34:15,500 INFO L226 Difference]: Without dead ends: 170 [2024-12-02 06:34:15,501 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 404 GetRequests, 389 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=97, Invalid=175, Unknown=0, NotChecked=0, Total=272 [2024-12-02 06:34:15,501 INFO L435 NwaCegarLoop]: 46 mSDtfsCounter, 5 mSDsluCounter, 258 mSDsCounter, 0 mSdLazyCounter, 76 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5 SdHoareTripleChecker+Valid, 304 SdHoareTripleChecker+Invalid, 81 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 76 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:34:15,502 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [5 Valid, 304 Invalid, 81 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 76 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:34:15,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2024-12-02 06:34:15,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 170. [2024-12-02 06:34:15,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 170 states, 153 states have (on average 1.0849673202614378) internal successors, (166), 153 states have internal predecessors, (166), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:34:15,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 196 transitions. [2024-12-02 06:34:15,521 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 196 transitions. Word has length 201 [2024-12-02 06:34:15,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:34:15,522 INFO L471 AbstractCegarLoop]: Abstraction has 170 states and 196 transitions. [2024-12-02 06:34:15,522 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 5.615384615384615) internal successors, (73), 13 states have internal predecessors, (73), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:34:15,522 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 196 transitions. [2024-12-02 06:34:15,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 218 [2024-12-02 06:34:15,524 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:34:15,525 INFO L218 NwaCegarLoop]: trace histogram [16, 16, 15, 15, 15, 8, 8, 8, 8, 8, 8, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:34:15,541 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Ended with exit code 0 [2024-12-02 06:34:15,725 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:34:15,725 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:34:15,726 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:34:15,726 INFO L85 PathProgramCache]: Analyzing trace with hash 831217618, now seen corresponding path program 8 times [2024-12-02 06:34:15,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:34:15,727 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1283265624] [2024-12-02 06:34:15,727 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:34:15,727 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:34:15,727 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:34:15,729 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:34:15,729 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-12-02 06:34:16,968 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:34:16,969 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:34:16,990 INFO L256 TraceCheckSpWp]: Trace formula consists of 2082 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-12-02 06:34:16,995 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:34:17,034 INFO L134 CoverageAnalysis]: Checked inductivity of 985 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 969 trivial. 0 not checked. [2024-12-02 06:34:17,034 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:34:17,179 INFO L134 CoverageAnalysis]: Checked inductivity of 985 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 969 trivial. 0 not checked. [2024-12-02 06:34:17,179 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:34:17,179 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1283265624] [2024-12-02 06:34:17,179 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1283265624] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:34:17,179 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:34:17,179 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 13 [2024-12-02 06:34:17,179 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1426928296] [2024-12-02 06:34:17,179 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 06:34:17,180 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2024-12-02 06:34:17,180 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 06:34:17,180 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-12-02 06:34:17,181 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=103, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:34:17,181 INFO L87 Difference]: Start difference. First operand 170 states and 196 transitions. Second operand has 13 states, 13 states have (on average 4.461538461538462) internal successors, (58), 13 states have internal predecessors, (58), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:34:17,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:34:17,335 INFO L93 Difference]: Finished difference Result 341 states and 398 transitions. [2024-12-02 06:34:17,336 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-12-02 06:34:17,336 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 4.461538461538462) internal successors, (58), 13 states have internal predecessors, (58), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 217 [2024-12-02 06:34:17,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:34:17,337 INFO L225 Difference]: With dead ends: 341 [2024-12-02 06:34:17,337 INFO L226 Difference]: Without dead ends: 182 [2024-12-02 06:34:17,338 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 436 GetRequests, 421 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=97, Invalid=175, Unknown=0, NotChecked=0, Total=272 [2024-12-02 06:34:17,338 INFO L435 NwaCegarLoop]: 46 mSDtfsCounter, 6 mSDsluCounter, 220 mSDsCounter, 0 mSdLazyCounter, 65 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 6 SdHoareTripleChecker+Valid, 266 SdHoareTripleChecker+Invalid, 70 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 65 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:34:17,338 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [6 Valid, 266 Invalid, 70 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 65 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:34:17,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2024-12-02 06:34:17,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 182. [2024-12-02 06:34:17,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 182 states, 165 states have (on average 1.084848484848485) internal successors, (179), 165 states have internal predecessors, (179), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:34:17,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 209 transitions. [2024-12-02 06:34:17,355 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 209 transitions. Word has length 217 [2024-12-02 06:34:17,355 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:34:17,356 INFO L471 AbstractCegarLoop]: Abstraction has 182 states and 209 transitions. [2024-12-02 06:34:17,356 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 4.461538461538462) internal successors, (58), 13 states have internal predecessors, (58), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:34:17,356 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 209 transitions. [2024-12-02 06:34:17,358 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 226 [2024-12-02 06:34:17,358 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:34:17,359 INFO L218 NwaCegarLoop]: trace histogram [16, 16, 15, 15, 15, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:34:17,381 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Ended with exit code 0 [2024-12-02 06:34:17,559 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:34:17,559 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:34:17,559 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:34:17,559 INFO L85 PathProgramCache]: Analyzing trace with hash 958267074, now seen corresponding path program 9 times [2024-12-02 06:34:17,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 06:34:17,561 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [703938135] [2024-12-02 06:34:17,561 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-12-02 06:34:17,561 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:34:17,561 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:34:17,562 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:34:17,563 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-12-02 06:34:20,573 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2024-12-02 06:34:20,573 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:34:20,598 INFO L256 TraceCheckSpWp]: Trace formula consists of 1733 conjuncts, 203 conjuncts are in the unsatisfiable core [2024-12-02 06:34:20,625 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:34:29,846 INFO L134 CoverageAnalysis]: Checked inductivity of 1033 backedges. 51 proven. 344 refuted. 0 times theorem prover too weak. 638 trivial. 0 not checked. [2024-12-02 06:34:29,846 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:34:34,778 WARN L851 $PredicateComparison]: unable to prove that (let ((.cse8 (= (_ bv0 8) |c_ULTIMATE.start_main_~input_9~0#1|)) (.cse3 ((_ zero_extend 24) |c_ULTIMATE.start_main_~mask_SORT_1~0#1|)) (.cse11 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_83~0#1|)) (.cse5 ((_ zero_extend 24) |c_ULTIMATE.start_main_~mask_SORT_15~0#1|))) (let ((.cse9 (forall ((|v_ULTIMATE.start_main_~var_98_arg_1~0#1_54| (_ BitVec 8))) (= (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_98_arg_1~0#1_54|))) .cse5)))))) (.cse6 (forall ((|v_ULTIMATE.start_main_~var_89_arg_1~0#1_55| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_113_arg_0~0#1_56| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_86_arg_1~0#1_55| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_105_arg_1~0#1_55| (_ BitVec 8))) (= (_ bv0 8) ((_ extract 7 0) (bvand .cse3 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_105_arg_1~0#1_55|) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand (_ bv254 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_86_arg_1~0#1_55|) .cse11))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_89_arg_1~0#1_55|)))))))))))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_113_arg_0~0#1_56|))))))))) (.cse2 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_87~0#1|)) (.cse4 ((_ zero_extend 24) ((_ extract 7 0) (bvnot .cse11)))) (.cse7 (not .cse8)) (.cse10 (forall ((|v_ULTIMATE.start_main_~var_98_arg_1~0#1_54| (_ BitVec 8))) (not (= (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_98_arg_1~0#1_54|))) .cse5))))))) (.cse1 (forall ((|v_ULTIMATE.start_main_~var_89_arg_1~0#1_55| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_113_arg_0~0#1_56| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_86_arg_1~0#1_55| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_105_arg_1~0#1_55| (_ BitVec 8))) (= (_ bv0 8) ((_ extract 7 0) (bvand .cse3 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_113_arg_0~0#1_56|) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvor ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_105_arg_1~0#1_55|) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand (_ bv255 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_86_arg_1~0#1_55|) .cse11))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_89_arg_1~0#1_55|)))))))))))))))))))))))) (.cse0 (bvsge ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_55~0#1|) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse5 ((_ zero_extend 24) |c_ULTIMATE.start_main_~var_27~0#1|))))))) (and (or .cse0 (and (or (and (or .cse1 (forall ((|v_ULTIMATE.start_main_~var_92_arg_0~0#1_54| (_ BitVec 8))) (not (= (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvadd .cse2 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse3 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_92_arg_0~0#1_54|) .cse4))))))))))))) .cse5))))))) (or .cse6 (forall ((|v_ULTIMATE.start_main_~var_92_arg_0~0#1_54| (_ BitVec 8))) (= (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvadd .cse2 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse3 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_92_arg_0~0#1_54|) .cse4))))))))))))) .cse5))))))) .cse7) (or .cse8 (and (or .cse9 .cse6) (or .cse10 .cse1))))) (or (and (or (and (or .cse8 .cse9) (or .cse7 (forall ((|v_ULTIMATE.start_main_~var_92_arg_0~0#1_54| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_58_arg_0~0#1_54| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_60_arg_1~0#1_54| (_ BitVec 8))) (= (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse5 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvadd ((_ zero_extend 24) ((_ extract 7 0) (bvadd .cse2 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse3 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_92_arg_0~0#1_54|) .cse4))))))))) (bvneg ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse3 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_60_arg_1~0#1_54|) ((_ zero_extend 24) ((_ extract 7 0) (bvand (_ bv1 32) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_58_arg_0~0#1_54|))))))) .cse3))))))))))))))))))) .cse6) (or (and (or (forall ((|v_ULTIMATE.start_main_~var_92_arg_0~0#1_54| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_58_arg_0~0#1_54| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_60_arg_1~0#1_54| (_ BitVec 8))) (not (= (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse5 ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvadd ((_ zero_extend 24) ((_ extract 7 0) (bvadd .cse2 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse3 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_92_arg_0~0#1_54|) .cse4))))))))) (bvneg ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse3 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_60_arg_1~0#1_54|) ((_ zero_extend 24) ((_ extract 7 0) (bvand (_ bv1 32) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_58_arg_0~0#1_54|))))))) .cse3)))))))))))))))))) .cse7) (or .cse8 .cse10)) .cse1)) (not .cse0))))) is different from false [2024-12-02 06:34:37,550 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 06:34:37,550 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [703938135] [2024-12-02 06:34:37,550 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [703938135] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:34:37,550 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1577309782] [2024-12-02 06:34:37,550 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-12-02 06:34:37,551 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-12-02 06:34:37,551 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/cvc4 [2024-12-02 06:34:37,552 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-12-02 06:34:37,553 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8de37ab-e947-4b1c-a961-d5564dbf72f6/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (21)] Waiting until timeout for monitored process [2024-12-02 06:34:41,105 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2024-12-02 06:34:41,105 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:34:41,196 INFO L256 TraceCheckSpWp]: Trace formula consists of 1733 conjuncts, 247 conjuncts are in the unsatisfiable core [2024-12-02 06:34:41,223 INFO L279 TraceCheckSpWp]: Computing forward predicates...