./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_linked_list_fifo_n2d4.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_linked_list_fifo_n2d4.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1 --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash eb904c0981d69b458d5d2831cb1cef4022d2f4fca573c75928a054243d001b7a --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-12-02 06:16:55,205 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-12-02 06:16:55,262 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Default.epf [2024-12-02 06:16:55,267 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-12-02 06:16:55,267 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-12-02 06:16:55,289 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-12-02 06:16:55,290 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-12-02 06:16:55,290 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-12-02 06:16:55,290 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-12-02 06:16:55,290 INFO L153 SettingsManager]: * Use memory slicer=true [2024-12-02 06:16:55,291 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-12-02 06:16:55,291 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-12-02 06:16:55,291 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-12-02 06:16:55,291 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-12-02 06:16:55,291 INFO L153 SettingsManager]: * Use SBE=true [2024-12-02 06:16:55,291 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-12-02 06:16:55,292 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-12-02 06:16:55,292 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-12-02 06:16:55,292 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-12-02 06:16:55,292 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-12-02 06:16:55,292 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-12-02 06:16:55,292 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-12-02 06:16:55,292 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-12-02 06:16:55,292 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-12-02 06:16:55,292 INFO L153 SettingsManager]: * Use constant arrays=true [2024-12-02 06:16:55,292 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-12-02 06:16:55,293 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 06:16:55,293 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 06:16:55,293 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 06:16:55,293 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:16:55,293 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-12-02 06:16:55,293 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 06:16:55,293 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 06:16:55,293 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 06:16:55,293 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:16:55,294 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-12-02 06:16:55,294 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-12-02 06:16:55,294 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-12-02 06:16:55,294 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-12-02 06:16:55,294 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-12-02 06:16:55,294 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-12-02 06:16:55,294 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-12-02 06:16:55,294 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-12-02 06:16:55,294 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-12-02 06:16:55,294 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-12-02 06:16:55,295 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> eb904c0981d69b458d5d2831cb1cef4022d2f4fca573c75928a054243d001b7a [2024-12-02 06:16:55,508 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-12-02 06:16:55,516 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-12-02 06:16:55,518 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-12-02 06:16:55,519 INFO L270 PluginConnector]: Initializing CDTParser... [2024-12-02 06:16:55,519 INFO L274 PluginConnector]: CDTParser initialized [2024-12-02 06:16:55,521 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_linked_list_fifo_n2d4.c [2024-12-02 06:16:58,191 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/data/b1486b90b/a63c6453cedf4b52bf5931d66d908520/FLAG2c4109da4 [2024-12-02 06:16:58,438 INFO L384 CDTParser]: Found 1 translation units. [2024-12-02 06:16:58,439 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_linked_list_fifo_n2d4.c [2024-12-02 06:16:58,451 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/data/b1486b90b/a63c6453cedf4b52bf5931d66d908520/FLAG2c4109da4 [2024-12-02 06:16:58,738 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/data/b1486b90b/a63c6453cedf4b52bf5931d66d908520 [2024-12-02 06:16:58,741 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-12-02 06:16:58,742 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-12-02 06:16:58,743 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-12-02 06:16:58,743 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-12-02 06:16:58,747 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-12-02 06:16:58,748 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:16:58" (1/1) ... [2024-12-02 06:16:58,748 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@72ee980b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:58, skipping insertion in model container [2024-12-02 06:16:58,748 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:16:58" (1/1) ... [2024-12-02 06:16:58,783 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-12-02 06:16:58,908 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_linked_list_fifo_n2d4.c[1268,1281] [2024-12-02 06:16:59,165 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 06:16:59,171 INFO L200 MainTranslator]: Completed pre-run [2024-12-02 06:16:59,179 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.unsafe_linked_list_fifo_n2d4.c[1268,1281] [2024-12-02 06:16:59,283 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 06:16:59,293 INFO L204 MainTranslator]: Completed translation [2024-12-02 06:16:59,294 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59 WrapperNode [2024-12-02 06:16:59,294 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-12-02 06:16:59,295 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-12-02 06:16:59,295 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-12-02 06:16:59,295 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-12-02 06:16:59,300 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59" (1/1) ... [2024-12-02 06:16:59,336 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59" (1/1) ... [2024-12-02 06:16:59,629 INFO L138 Inliner]: procedures = 18, calls = 107, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 3714 [2024-12-02 06:16:59,630 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-12-02 06:16:59,630 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-12-02 06:16:59,630 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-12-02 06:16:59,630 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-12-02 06:16:59,640 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59" (1/1) ... [2024-12-02 06:16:59,640 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59" (1/1) ... [2024-12-02 06:16:59,695 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59" (1/1) ... [2024-12-02 06:16:59,798 INFO L175 MemorySlicer]: Split 63 memory accesses to 4 slices as follows [2, 8, 29, 24]. 46 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0, 0, 0]. The 30 writes are split as follows [0, 4, 14, 12]. [2024-12-02 06:16:59,798 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59" (1/1) ... [2024-12-02 06:16:59,798 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59" (1/1) ... [2024-12-02 06:16:59,885 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59" (1/1) ... [2024-12-02 06:16:59,897 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59" (1/1) ... [2024-12-02 06:16:59,920 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59" (1/1) ... [2024-12-02 06:16:59,964 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59" (1/1) ... [2024-12-02 06:16:59,978 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59" (1/1) ... [2024-12-02 06:17:00,053 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-12-02 06:17:00,054 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-12-02 06:17:00,054 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-12-02 06:17:00,055 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-12-02 06:17:00,055 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59" (1/1) ... [2024-12-02 06:17:00,061 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 06:17:00,073 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:00,085 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-12-02 06:17:00,088 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-12-02 06:17:00,115 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-12-02 06:17:00,115 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-12-02 06:17:00,115 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-12-02 06:17:00,115 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-12-02 06:17:00,115 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2024-12-02 06:17:00,115 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#2 [2024-12-02 06:17:00,115 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#3 [2024-12-02 06:17:00,115 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-12-02 06:17:00,116 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2024-12-02 06:17:00,116 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2024-12-02 06:17:00,116 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#2 [2024-12-02 06:17:00,116 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#3 [2024-12-02 06:17:00,116 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-12-02 06:17:00,116 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-12-02 06:17:00,116 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2024-12-02 06:17:00,116 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2024-12-02 06:17:00,116 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#2 [2024-12-02 06:17:00,116 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#3 [2024-12-02 06:17:00,116 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-12-02 06:17:00,431 INFO L234 CfgBuilder]: Building ICFG [2024-12-02 06:17:00,432 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-12-02 06:17:04,180 INFO L? ?]: Removed 1909 outVars from TransFormulas that were not future-live. [2024-12-02 06:17:04,180 INFO L283 CfgBuilder]: Performing block encoding [2024-12-02 06:17:04,209 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-12-02 06:17:04,209 INFO L312 CfgBuilder]: Removed 19 assume(true) statements. [2024-12-02 06:17:04,209 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:17:04 BoogieIcfgContainer [2024-12-02 06:17:04,209 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-12-02 06:17:04,212 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-12-02 06:17:04,212 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-12-02 06:17:04,216 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-12-02 06:17:04,216 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 06:16:58" (1/3) ... [2024-12-02 06:17:04,217 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@32be16d9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 06:17:04, skipping insertion in model container [2024-12-02 06:17:04,217 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:16:59" (2/3) ... [2024-12-02 06:17:04,217 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@32be16d9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 06:17:04, skipping insertion in model container [2024-12-02 06:17:04,217 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:17:04" (3/3) ... [2024-12-02 06:17:04,218 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.unsafe_linked_list_fifo_n2d4.c [2024-12-02 06:17:04,234 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-12-02 06:17:04,235 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.unsafe_linked_list_fifo_n2d4.c that has 2 procedures, 1149 locations, 1 initial locations, 19 loop locations, and 1 error locations. [2024-12-02 06:17:04,315 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-12-02 06:17:04,325 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@38e0e9f5, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-12-02 06:17:04,325 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-12-02 06:17:04,331 INFO L276 IsEmpty]: Start isEmpty. Operand has 1149 states, 1141 states have (on average 1.5039439088518842) internal successors, (1716), 1142 states have internal predecessors, (1716), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:17:04,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 336 [2024-12-02 06:17:04,351 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:04,352 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:04,352 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:04,356 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:04,356 INFO L85 PathProgramCache]: Analyzing trace with hash -327356434, now seen corresponding path program 1 times [2024-12-02 06:17:04,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:04,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333019771] [2024-12-02 06:17:04,363 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:04,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:04,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:04,979 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-12-02 06:17:04,979 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:04,979 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333019771] [2024-12-02 06:17:04,980 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333019771] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:04,980 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2146168590] [2024-12-02 06:17:04,980 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:04,980 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:04,981 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:04,984 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:04,985 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-12-02 06:17:05,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:05,640 INFO L256 TraceCheckSpWp]: Trace formula consists of 1264 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-12-02 06:17:05,655 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:05,697 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-12-02 06:17:05,697 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:17:05,697 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2146168590] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:17:05,697 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:17:05,698 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 2 [2024-12-02 06:17:05,700 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [380142100] [2024-12-02 06:17:05,700 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:05,705 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-12-02 06:17:05,705 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:05,727 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-12-02 06:17:05,728 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 06:17:05,732 INFO L87 Difference]: Start difference. First operand has 1149 states, 1141 states have (on average 1.5039439088518842) internal successors, (1716), 1142 states have internal predecessors, (1716), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) Second operand has 2 states, 2 states have (on average 157.5) internal successors, (315), 2 states have internal predecessors, (315), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:17:05,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:05,816 INFO L93 Difference]: Finished difference Result 2287 states and 3443 transitions. [2024-12-02 06:17:05,817 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-12-02 06:17:05,818 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 157.5) internal successors, (315), 2 states have internal predecessors, (315), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) Word has length 335 [2024-12-02 06:17:05,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:05,832 INFO L225 Difference]: With dead ends: 2287 [2024-12-02 06:17:05,832 INFO L226 Difference]: Without dead ends: 1146 [2024-12-02 06:17:05,838 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 336 GetRequests, 336 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 06:17:05,841 INFO L435 NwaCegarLoop]: 1703 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1703 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:05,842 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1703 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:17:05,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1146 states. [2024-12-02 06:17:05,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1146 to 1146. [2024-12-02 06:17:05,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1146 states, 1139 states have (on average 1.4863915715539948) internal successors, (1693), 1139 states have internal predecessors, (1693), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:17:05,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1146 states to 1146 states and 1703 transitions. [2024-12-02 06:17:05,929 INFO L78 Accepts]: Start accepts. Automaton has 1146 states and 1703 transitions. Word has length 335 [2024-12-02 06:17:05,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:05,930 INFO L471 AbstractCegarLoop]: Abstraction has 1146 states and 1703 transitions. [2024-12-02 06:17:05,931 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 157.5) internal successors, (315), 2 states have internal predecessors, (315), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:17:05,931 INFO L276 IsEmpty]: Start isEmpty. Operand 1146 states and 1703 transitions. [2024-12-02 06:17:05,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 336 [2024-12-02 06:17:05,939 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:05,939 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:05,952 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-12-02 06:17:06,140 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0,2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:06,140 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:06,140 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:06,141 INFO L85 PathProgramCache]: Analyzing trace with hash -771185628, now seen corresponding path program 1 times [2024-12-02 06:17:06,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:06,141 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1367604834] [2024-12-02 06:17:06,141 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:06,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:06,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:07,004 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:17:07,004 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:07,005 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1367604834] [2024-12-02 06:17:07,005 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1367604834] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:17:07,005 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:17:07,005 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:17:07,005 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [316873432] [2024-12-02 06:17:07,005 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:07,006 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:17:07,007 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:07,008 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:17:07,008 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:17:07,008 INFO L87 Difference]: Start difference. First operand 1146 states and 1703 transitions. Second operand has 3 states, 3 states have (on average 104.33333333333333) internal successors, (313), 3 states have internal predecessors, (313), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:17:07,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:07,074 INFO L93 Difference]: Finished difference Result 2290 states and 3404 transitions. [2024-12-02 06:17:07,074 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:17:07,075 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 104.33333333333333) internal successors, (313), 3 states have internal predecessors, (313), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 335 [2024-12-02 06:17:07,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:07,080 INFO L225 Difference]: With dead ends: 2290 [2024-12-02 06:17:07,080 INFO L226 Difference]: Without dead ends: 1152 [2024-12-02 06:17:07,082 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:17:07,083 INFO L435 NwaCegarLoop]: 1701 mSDtfsCounter, 7 mSDsluCounter, 1698 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 3399 SdHoareTripleChecker+Invalid, 6 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:07,084 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 3399 Invalid, 6 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:17:07,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1152 states. [2024-12-02 06:17:07,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1152 to 1147. [2024-12-02 06:17:07,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1147 states, 1140 states have (on average 1.4859649122807017) internal successors, (1694), 1140 states have internal predecessors, (1694), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:17:07,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1147 states to 1147 states and 1704 transitions. [2024-12-02 06:17:07,127 INFO L78 Accepts]: Start accepts. Automaton has 1147 states and 1704 transitions. Word has length 335 [2024-12-02 06:17:07,128 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:07,128 INFO L471 AbstractCegarLoop]: Abstraction has 1147 states and 1704 transitions. [2024-12-02 06:17:07,128 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 104.33333333333333) internal successors, (313), 3 states have internal predecessors, (313), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:17:07,128 INFO L276 IsEmpty]: Start isEmpty. Operand 1147 states and 1704 transitions. [2024-12-02 06:17:07,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 340 [2024-12-02 06:17:07,136 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:07,136 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:07,136 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-12-02 06:17:07,136 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:07,137 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:07,137 INFO L85 PathProgramCache]: Analyzing trace with hash 1632648310, now seen corresponding path program 1 times [2024-12-02 06:17:07,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:07,137 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2060559737] [2024-12-02 06:17:07,138 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:07,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:07,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:07,848 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:17:07,848 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:07,849 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2060559737] [2024-12-02 06:17:07,849 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2060559737] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:07,849 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [497549354] [2024-12-02 06:17:07,849 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:07,849 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:07,849 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:07,851 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:07,852 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-12-02 06:17:08,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:08,444 INFO L256 TraceCheckSpWp]: Trace formula consists of 1275 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:17:08,455 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:08,485 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-12-02 06:17:08,486 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:17:08,536 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:17:08,537 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [497549354] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:08,537 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:17:08,537 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 6 [2024-12-02 06:17:08,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1281107737] [2024-12-02 06:17:08,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:08,538 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:17:08,538 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:08,539 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:17:08,539 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:17:08,539 INFO L87 Difference]: Start difference. First operand 1147 states and 1704 transitions. Second operand has 3 states, 3 states have (on average 105.66666666666667) internal successors, (317), 3 states have internal predecessors, (317), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:17:08,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:08,594 INFO L93 Difference]: Finished difference Result 2104 states and 3126 transitions. [2024-12-02 06:17:08,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:17:08,595 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 105.66666666666667) internal successors, (317), 3 states have internal predecessors, (317), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 339 [2024-12-02 06:17:08,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:08,600 INFO L225 Difference]: With dead ends: 2104 [2024-12-02 06:17:08,600 INFO L226 Difference]: Without dead ends: 1148 [2024-12-02 06:17:08,601 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 680 GetRequests, 676 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:17:08,602 INFO L435 NwaCegarLoop]: 1701 mSDtfsCounter, 7 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 3392 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:08,602 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 3392 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:17:08,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1148 states. [2024-12-02 06:17:08,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1148 to 1148. [2024-12-02 06:17:08,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1148 states, 1141 states have (on average 1.4855390008764242) internal successors, (1695), 1141 states have internal predecessors, (1695), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:17:08,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1148 states to 1148 states and 1705 transitions. [2024-12-02 06:17:08,632 INFO L78 Accepts]: Start accepts. Automaton has 1148 states and 1705 transitions. Word has length 339 [2024-12-02 06:17:08,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:08,633 INFO L471 AbstractCegarLoop]: Abstraction has 1148 states and 1705 transitions. [2024-12-02 06:17:08,633 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 105.66666666666667) internal successors, (317), 3 states have internal predecessors, (317), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:17:08,633 INFO L276 IsEmpty]: Start isEmpty. Operand 1148 states and 1705 transitions. [2024-12-02 06:17:08,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 344 [2024-12-02 06:17:08,639 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:08,639 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:08,650 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-12-02 06:17:08,839 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:08,840 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:08,840 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:08,840 INFO L85 PathProgramCache]: Analyzing trace with hash -1716404024, now seen corresponding path program 1 times [2024-12-02 06:17:08,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:08,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454263447] [2024-12-02 06:17:08,841 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:08,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:08,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:09,312 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:17:09,312 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:09,312 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1454263447] [2024-12-02 06:17:09,312 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1454263447] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:09,312 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1900332770] [2024-12-02 06:17:09,312 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:09,312 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:09,313 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:09,315 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:09,317 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-12-02 06:17:09,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:09,856 INFO L256 TraceCheckSpWp]: Trace formula consists of 1286 conjuncts, 18 conjuncts are in the unsatisfiable core [2024-12-02 06:17:09,863 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:09,881 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2024-12-02 06:17:09,882 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:17:09,882 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1900332770] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:17:09,882 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:17:09,882 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 5 [2024-12-02 06:17:09,882 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015733258] [2024-12-02 06:17:09,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:09,883 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:17:09,883 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:09,884 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:17:09,884 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:17:09,884 INFO L87 Difference]: Start difference. First operand 1148 states and 1705 transitions. Second operand has 3 states, 3 states have (on average 107.0) internal successors, (321), 3 states have internal predecessors, (321), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:17:09,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:09,933 INFO L93 Difference]: Finished difference Result 2286 states and 3397 transitions. [2024-12-02 06:17:09,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:17:09,934 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 107.0) internal successors, (321), 3 states have internal predecessors, (321), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 343 [2024-12-02 06:17:09,934 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:09,938 INFO L225 Difference]: With dead ends: 2286 [2024-12-02 06:17:09,938 INFO L226 Difference]: Without dead ends: 1154 [2024-12-02 06:17:09,940 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 346 GetRequests, 343 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:17:09,941 INFO L435 NwaCegarLoop]: 1701 mSDtfsCounter, 7 mSDsluCounter, 1697 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 3398 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:09,941 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 3398 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:17:09,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1154 states. [2024-12-02 06:17:09,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1154 to 1149. [2024-12-02 06:17:09,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1149 states, 1142 states have (on average 1.4851138353765323) internal successors, (1696), 1142 states have internal predecessors, (1696), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-12-02 06:17:09,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1149 states to 1149 states and 1706 transitions. [2024-12-02 06:17:09,970 INFO L78 Accepts]: Start accepts. Automaton has 1149 states and 1706 transitions. Word has length 343 [2024-12-02 06:17:09,971 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:09,971 INFO L471 AbstractCegarLoop]: Abstraction has 1149 states and 1706 transitions. [2024-12-02 06:17:09,971 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 107.0) internal successors, (321), 3 states have internal predecessors, (321), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:17:09,971 INFO L276 IsEmpty]: Start isEmpty. Operand 1149 states and 1706 transitions. [2024-12-02 06:17:09,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 348 [2024-12-02 06:17:09,977 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:09,977 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:09,989 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2024-12-02 06:17:10,177 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:10,178 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:10,178 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:10,178 INFO L85 PathProgramCache]: Analyzing trace with hash -476266918, now seen corresponding path program 1 times [2024-12-02 06:17:10,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:10,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [711450592] [2024-12-02 06:17:10,179 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:10,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:10,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:10,614 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2024-12-02 06:17:10,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:10,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [711450592] [2024-12-02 06:17:10,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [711450592] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:10,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1074761904] [2024-12-02 06:17:10,615 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:10,615 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:10,615 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:10,619 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:10,621 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-12-02 06:17:11,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:11,183 INFO L256 TraceCheckSpWp]: Trace formula consists of 1297 conjuncts, 72 conjuncts are in the unsatisfiable core [2024-12-02 06:17:11,194 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:11,251 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2024-12-02 06:17:11,251 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:17:13,497 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2024-12-02 06:17:13,497 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1074761904] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:17:13,497 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:17:13,497 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 14] total 18 [2024-12-02 06:17:13,497 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [251957729] [2024-12-02 06:17:13,497 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:17:13,499 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-12-02 06:17:13,499 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:13,500 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-12-02 06:17:13,501 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=243, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:17:13,501 INFO L87 Difference]: Start difference. First operand 1149 states and 1706 transitions. Second operand has 18 states, 18 states have (on average 34.72222222222222) internal successors, (625), 18 states have internal predecessors, (625), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (14), 3 states have call predecessors, (14), 3 states have call successors, (14) [2024-12-02 06:17:19,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:19,561 INFO L93 Difference]: Finished difference Result 3129 states and 4647 transitions. [2024-12-02 06:17:19,561 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2024-12-02 06:17:19,561 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 34.72222222222222) internal successors, (625), 18 states have internal predecessors, (625), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (14), 3 states have call predecessors, (14), 3 states have call successors, (14) Word has length 347 [2024-12-02 06:17:19,561 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:19,569 INFO L225 Difference]: With dead ends: 3129 [2024-12-02 06:17:19,569 INFO L226 Difference]: Without dead ends: 1989 [2024-12-02 06:17:19,571 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 716 GetRequests, 680 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 250 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=353, Invalid=1053, Unknown=0, NotChecked=0, Total=1406 [2024-12-02 06:17:19,571 INFO L435 NwaCegarLoop]: 1808 mSDtfsCounter, 9920 mSDsluCounter, 13764 mSDsCounter, 0 mSdLazyCounter, 6382 mSolverCounterSat, 197 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 4.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 9925 SdHoareTripleChecker+Valid, 15572 SdHoareTripleChecker+Invalid, 6579 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 197 IncrementalHoareTripleChecker+Valid, 6382 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 4.9s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:19,572 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [9925 Valid, 15572 Invalid, 6579 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [197 Valid, 6382 Invalid, 0 Unknown, 0 Unchecked, 4.9s Time] [2024-12-02 06:17:19,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1989 states. [2024-12-02 06:17:19,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1989 to 1254. [2024-12-02 06:17:19,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1254 states, 1243 states have (on average 1.4835076427996783) internal successors, (1844), 1243 states have internal predecessors, (1844), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-12-02 06:17:19,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1254 states to 1254 states and 1862 transitions. [2024-12-02 06:17:19,620 INFO L78 Accepts]: Start accepts. Automaton has 1254 states and 1862 transitions. Word has length 347 [2024-12-02 06:17:19,620 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:19,620 INFO L471 AbstractCegarLoop]: Abstraction has 1254 states and 1862 transitions. [2024-12-02 06:17:19,620 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 34.72222222222222) internal successors, (625), 18 states have internal predecessors, (625), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (14), 3 states have call predecessors, (14), 3 states have call successors, (14) [2024-12-02 06:17:19,620 INFO L276 IsEmpty]: Start isEmpty. Operand 1254 states and 1862 transitions. [2024-12-02 06:17:19,626 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 353 [2024-12-02 06:17:19,626 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:19,626 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:19,638 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2024-12-02 06:17:19,827 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:19,827 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:19,827 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:19,827 INFO L85 PathProgramCache]: Analyzing trace with hash 1700717894, now seen corresponding path program 1 times [2024-12-02 06:17:19,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:19,827 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109129174] [2024-12-02 06:17:19,827 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:19,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:19,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:20,111 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2024-12-02 06:17:20,112 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:20,112 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109129174] [2024-12-02 06:17:20,112 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109129174] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:20,112 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [519169766] [2024-12-02 06:17:20,112 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:20,112 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:20,112 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:20,114 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:20,115 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-12-02 06:17:20,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:20,653 INFO L256 TraceCheckSpWp]: Trace formula consists of 1311 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:17:20,658 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:20,692 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:17:20,692 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:17:20,741 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 47 trivial. 0 not checked. [2024-12-02 06:17:20,741 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [519169766] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:17:20,741 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:17:20,741 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 6, 4] total 9 [2024-12-02 06:17:20,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [741279027] [2024-12-02 06:17:20,742 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:17:20,743 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:17:20,743 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:20,743 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:17:20,744 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:17:20,744 INFO L87 Difference]: Start difference. First operand 1254 states and 1862 transitions. Second operand has 9 states, 9 states have (on average 49.111111111111114) internal successors, (442), 9 states have internal predecessors, (442), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:17:20,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:20,828 INFO L93 Difference]: Finished difference Result 2522 states and 3747 transitions. [2024-12-02 06:17:20,828 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:17:20,829 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 49.111111111111114) internal successors, (442), 9 states have internal predecessors, (442), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 352 [2024-12-02 06:17:20,829 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:20,833 INFO L225 Difference]: With dead ends: 2522 [2024-12-02 06:17:20,833 INFO L226 Difference]: Without dead ends: 1283 [2024-12-02 06:17:20,835 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 708 GetRequests, 700 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:17:20,835 INFO L435 NwaCegarLoop]: 1711 mSDtfsCounter, 56 mSDsluCounter, 6818 mSDsCounter, 0 mSdLazyCounter, 51 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 56 SdHoareTripleChecker+Valid, 8529 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 51 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:20,836 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [56 Valid, 8529 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 51 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:17:20,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1283 states. [2024-12-02 06:17:20,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1283 to 1278. [2024-12-02 06:17:20,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1267 states have (on average 1.4806629834254144) internal successors, (1876), 1267 states have internal predecessors, (1876), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-12-02 06:17:20,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1894 transitions. [2024-12-02 06:17:20,889 INFO L78 Accepts]: Start accepts. Automaton has 1278 states and 1894 transitions. Word has length 352 [2024-12-02 06:17:20,890 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:20,890 INFO L471 AbstractCegarLoop]: Abstraction has 1278 states and 1894 transitions. [2024-12-02 06:17:20,890 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 49.111111111111114) internal successors, (442), 9 states have internal predecessors, (442), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:17:20,890 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1894 transitions. [2024-12-02 06:17:20,891 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 369 [2024-12-02 06:17:20,891 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:20,892 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:20,902 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-12-02 06:17:21,092 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:21,092 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:21,093 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:21,093 INFO L85 PathProgramCache]: Analyzing trace with hash -1011162114, now seen corresponding path program 2 times [2024-12-02 06:17:21,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:21,093 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313142811] [2024-12-02 06:17:21,093 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:17:21,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:21,168 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:17:21,168 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:17:21,468 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2024-12-02 06:17:21,469 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:21,469 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1313142811] [2024-12-02 06:17:21,469 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1313142811] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:17:21,469 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:17:21,469 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:17:21,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1303422833] [2024-12-02 06:17:21,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:21,469 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:17:21,470 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:21,470 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:17:21,470 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:17:21,470 INFO L87 Difference]: Start difference. First operand 1278 states and 1894 transitions. Second operand has 4 states, 4 states have (on average 81.5) internal successors, (326), 4 states have internal predecessors, (326), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:17:21,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:21,502 INFO L93 Difference]: Finished difference Result 1282 states and 1898 transitions. [2024-12-02 06:17:21,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:17:21,503 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 81.5) internal successors, (326), 4 states have internal predecessors, (326), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 368 [2024-12-02 06:17:21,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:21,506 INFO L225 Difference]: With dead ends: 1282 [2024-12-02 06:17:21,506 INFO L226 Difference]: Without dead ends: 1280 [2024-12-02 06:17:21,507 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:17:21,508 INFO L435 NwaCegarLoop]: 1701 mSDtfsCounter, 0 mSDsluCounter, 3396 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5097 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:21,508 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5097 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:17:21,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1280 states. [2024-12-02 06:17:21,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1280 to 1280. [2024-12-02 06:17:21,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1280 states, 1269 states have (on average 1.4799054373522458) internal successors, (1878), 1269 states have internal predecessors, (1878), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-12-02 06:17:21,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1280 states to 1280 states and 1896 transitions. [2024-12-02 06:17:21,531 INFO L78 Accepts]: Start accepts. Automaton has 1280 states and 1896 transitions. Word has length 368 [2024-12-02 06:17:21,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:21,532 INFO L471 AbstractCegarLoop]: Abstraction has 1280 states and 1896 transitions. [2024-12-02 06:17:21,532 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 81.5) internal successors, (326), 4 states have internal predecessors, (326), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:17:21,532 INFO L276 IsEmpty]: Start isEmpty. Operand 1280 states and 1896 transitions. [2024-12-02 06:17:21,534 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 370 [2024-12-02 06:17:21,534 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:21,534 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:21,534 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2024-12-02 06:17:21,534 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:21,535 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:21,535 INFO L85 PathProgramCache]: Analyzing trace with hash -1279557299, now seen corresponding path program 1 times [2024-12-02 06:17:21,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:21,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [293506306] [2024-12-02 06:17:21,535 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:21,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:21,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:21,949 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 69 trivial. 0 not checked. [2024-12-02 06:17:21,949 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:21,949 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [293506306] [2024-12-02 06:17:21,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [293506306] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:21,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [535914971] [2024-12-02 06:17:21,950 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:21,950 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:21,950 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:21,952 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:21,953 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-12-02 06:17:22,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:22,472 INFO L256 TraceCheckSpWp]: Trace formula consists of 1358 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-12-02 06:17:22,478 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:22,504 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 69 trivial. 0 not checked. [2024-12-02 06:17:22,504 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:17:22,649 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 13 proven. 30 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-12-02 06:17:22,649 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [535914971] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:17:22,649 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:17:22,650 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 10] total 15 [2024-12-02 06:17:22,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [63554603] [2024-12-02 06:17:22,650 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:17:22,651 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2024-12-02 06:17:22,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:22,651 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2024-12-02 06:17:22,651 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=168, Unknown=0, NotChecked=0, Total=210 [2024-12-02 06:17:22,652 INFO L87 Difference]: Start difference. First operand 1280 states and 1896 transitions. Second operand has 15 states, 15 states have (on average 24.533333333333335) internal successors, (368), 15 states have internal predecessors, (368), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:17:22,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:22,762 INFO L93 Difference]: Finished difference Result 2550 states and 3780 transitions. [2024-12-02 06:17:22,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:17:22,763 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 24.533333333333335) internal successors, (368), 15 states have internal predecessors, (368), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 369 [2024-12-02 06:17:22,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:22,766 INFO L225 Difference]: With dead ends: 2550 [2024-12-02 06:17:22,766 INFO L226 Difference]: Without dead ends: 1291 [2024-12-02 06:17:22,767 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 742 GetRequests, 729 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=42, Invalid=168, Unknown=0, NotChecked=0, Total=210 [2024-12-02 06:17:22,768 INFO L435 NwaCegarLoop]: 1719 mSDtfsCounter, 37 mSDsluCounter, 17100 mSDsCounter, 0 mSdLazyCounter, 113 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 37 SdHoareTripleChecker+Valid, 18819 SdHoareTripleChecker+Invalid, 114 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 113 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:22,768 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [37 Valid, 18819 Invalid, 114 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 113 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:17:22,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1291 states. [2024-12-02 06:17:22,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1291 to 1286. [2024-12-02 06:17:22,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1286 states, 1275 states have (on average 1.4792156862745098) internal successors, (1886), 1275 states have internal predecessors, (1886), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-12-02 06:17:22,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1286 states to 1286 states and 1904 transitions. [2024-12-02 06:17:22,788 INFO L78 Accepts]: Start accepts. Automaton has 1286 states and 1904 transitions. Word has length 369 [2024-12-02 06:17:22,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:22,789 INFO L471 AbstractCegarLoop]: Abstraction has 1286 states and 1904 transitions. [2024-12-02 06:17:22,789 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 24.533333333333335) internal successors, (368), 15 states have internal predecessors, (368), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:17:22,789 INFO L276 IsEmpty]: Start isEmpty. Operand 1286 states and 1904 transitions. [2024-12-02 06:17:22,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 374 [2024-12-02 06:17:22,791 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:22,791 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:22,799 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2024-12-02 06:17:22,991 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:22,991 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:22,991 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:22,992 INFO L85 PathProgramCache]: Analyzing trace with hash 1418364191, now seen corresponding path program 2 times [2024-12-02 06:17:22,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:22,992 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2010292740] [2024-12-02 06:17:22,992 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:17:22,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:23,071 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:17:23,071 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:17:23,567 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:17:23,567 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:23,568 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2010292740] [2024-12-02 06:17:23,568 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2010292740] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:17:23,568 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:17:23,568 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:17:23,568 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [363823444] [2024-12-02 06:17:23,568 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:23,568 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:17:23,568 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:23,569 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:17:23,569 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:17:23,569 INFO L87 Difference]: Start difference. First operand 1286 states and 1904 transitions. Second operand has 5 states, 5 states have (on average 65.4) internal successors, (327), 5 states have internal predecessors, (327), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:17:24,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:24,603 INFO L93 Difference]: Finished difference Result 2078 states and 3077 transitions. [2024-12-02 06:17:24,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:17:24,604 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 65.4) internal successors, (327), 5 states have internal predecessors, (327), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 373 [2024-12-02 06:17:24,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:24,606 INFO L225 Difference]: With dead ends: 2078 [2024-12-02 06:17:24,607 INFO L226 Difference]: Without dead ends: 1288 [2024-12-02 06:17:24,607 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:17:24,608 INFO L435 NwaCegarLoop]: 1027 mSDtfsCounter, 1618 mSDsluCounter, 2029 mSDsCounter, 0 mSdLazyCounter, 2043 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1618 SdHoareTripleChecker+Valid, 3056 SdHoareTripleChecker+Invalid, 2045 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 2043 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:24,608 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1618 Valid, 3056 Invalid, 2045 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 2043 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-12-02 06:17:24,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1288 states. [2024-12-02 06:17:24,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1288 to 1288. [2024-12-02 06:17:24,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1288 states, 1277 states have (on average 1.4784651527016446) internal successors, (1888), 1277 states have internal predecessors, (1888), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-12-02 06:17:24,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1288 states to 1288 states and 1906 transitions. [2024-12-02 06:17:24,641 INFO L78 Accepts]: Start accepts. Automaton has 1288 states and 1906 transitions. Word has length 373 [2024-12-02 06:17:24,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:24,642 INFO L471 AbstractCegarLoop]: Abstraction has 1288 states and 1906 transitions. [2024-12-02 06:17:24,642 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 65.4) internal successors, (327), 5 states have internal predecessors, (327), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:17:24,642 INFO L276 IsEmpty]: Start isEmpty. Operand 1288 states and 1906 transitions. [2024-12-02 06:17:24,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 375 [2024-12-02 06:17:24,645 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:24,645 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:24,645 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2024-12-02 06:17:24,645 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:24,645 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:24,646 INFO L85 PathProgramCache]: Analyzing trace with hash -78346971, now seen corresponding path program 1 times [2024-12-02 06:17:24,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:24,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915207758] [2024-12-02 06:17:24,646 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:24,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:24,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:25,098 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:17:25,098 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:25,098 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1915207758] [2024-12-02 06:17:25,098 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1915207758] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:25,098 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1298897130] [2024-12-02 06:17:25,099 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:25,099 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:25,099 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:25,103 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:25,106 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-12-02 06:17:25,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:25,747 INFO L256 TraceCheckSpWp]: Trace formula consists of 1372 conjuncts, 10 conjuncts are in the unsatisfiable core [2024-12-02 06:17:25,752 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:25,800 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:17:25,801 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:17:25,801 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1298897130] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:17:25,801 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:17:25,801 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [4] total 8 [2024-12-02 06:17:25,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496038634] [2024-12-02 06:17:25,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:25,802 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:17:25,802 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:25,802 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:17:25,802 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:17:25,803 INFO L87 Difference]: Start difference. First operand 1288 states and 1906 transitions. Second operand has 6 states, 6 states have (on average 54.666666666666664) internal successors, (328), 6 states have internal predecessors, (328), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:17:26,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:26,913 INFO L93 Difference]: Finished difference Result 3020 states and 4473 transitions. [2024-12-02 06:17:26,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:17:26,914 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 54.666666666666664) internal successors, (328), 6 states have internal predecessors, (328), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 374 [2024-12-02 06:17:26,914 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:26,918 INFO L225 Difference]: With dead ends: 3020 [2024-12-02 06:17:26,918 INFO L226 Difference]: Without dead ends: 2228 [2024-12-02 06:17:26,919 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 378 GetRequests, 371 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:17:26,920 INFO L435 NwaCegarLoop]: 2067 mSDtfsCounter, 1067 mSDsluCounter, 6226 mSDsCounter, 0 mSdLazyCounter, 1758 mSolverCounterSat, 24 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1077 SdHoareTripleChecker+Valid, 8293 SdHoareTripleChecker+Invalid, 1782 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 24 IncrementalHoareTripleChecker+Valid, 1758 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:26,920 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1077 Valid, 8293 Invalid, 1782 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [24 Valid, 1758 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-12-02 06:17:26,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2228 states. [2024-12-02 06:17:26,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2228 to 1314. [2024-12-02 06:17:26,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1314 states, 1303 states have (on average 1.4773599386032232) internal successors, (1925), 1303 states have internal predecessors, (1925), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-12-02 06:17:26,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1314 states to 1314 states and 1943 transitions. [2024-12-02 06:17:26,947 INFO L78 Accepts]: Start accepts. Automaton has 1314 states and 1943 transitions. Word has length 374 [2024-12-02 06:17:26,948 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:26,948 INFO L471 AbstractCegarLoop]: Abstraction has 1314 states and 1943 transitions. [2024-12-02 06:17:26,948 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 54.666666666666664) internal successors, (328), 6 states have internal predecessors, (328), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:17:26,948 INFO L276 IsEmpty]: Start isEmpty. Operand 1314 states and 1943 transitions. [2024-12-02 06:17:26,950 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 375 [2024-12-02 06:17:26,950 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:26,950 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:26,960 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-12-02 06:17:27,151 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2024-12-02 06:17:27,151 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:27,151 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:27,151 INFO L85 PathProgramCache]: Analyzing trace with hash -960869195, now seen corresponding path program 1 times [2024-12-02 06:17:27,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:27,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704081192] [2024-12-02 06:17:27,152 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:27,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:27,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:27,508 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:17:27,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:27,509 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [704081192] [2024-12-02 06:17:27,509 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [704081192] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:27,509 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [999614699] [2024-12-02 06:17:27,509 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:27,509 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:27,509 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:27,511 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:27,512 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-12-02 06:17:28,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:28,081 INFO L256 TraceCheckSpWp]: Trace formula consists of 1372 conjuncts, 57 conjuncts are in the unsatisfiable core [2024-12-02 06:17:28,088 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:28,906 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 24 proven. 14 refuted. 0 times theorem prover too weak. 59 trivial. 0 not checked. [2024-12-02 06:17:28,906 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:17:29,074 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:17:29,074 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [999614699] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:29,074 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:17:29,075 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [4, 8] total 16 [2024-12-02 06:17:29,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1050540210] [2024-12-02 06:17:29,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:29,075 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:17:29,075 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:29,076 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:17:29,076 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=200, Unknown=0, NotChecked=0, Total=240 [2024-12-02 06:17:29,077 INFO L87 Difference]: Start difference. First operand 1314 states and 1943 transitions. Second operand has 8 states, 8 states have (on average 41.0) internal successors, (328), 8 states have internal predecessors, (328), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:17:30,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:30,649 INFO L93 Difference]: Finished difference Result 2739 states and 4052 transitions. [2024-12-02 06:17:30,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:17:30,649 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 41.0) internal successors, (328), 8 states have internal predecessors, (328), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 374 [2024-12-02 06:17:30,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:30,654 INFO L225 Difference]: With dead ends: 2739 [2024-12-02 06:17:30,654 INFO L226 Difference]: Without dead ends: 1316 [2024-12-02 06:17:30,656 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 752 GetRequests, 736 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 59 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=252, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:17:30,656 INFO L435 NwaCegarLoop]: 1774 mSDtfsCounter, 820 mSDsluCounter, 7643 mSDsCounter, 0 mSdLazyCounter, 2893 mSolverCounterSat, 44 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 824 SdHoareTripleChecker+Valid, 9417 SdHoareTripleChecker+Invalid, 2937 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 44 IncrementalHoareTripleChecker+Valid, 2893 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:30,656 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [824 Valid, 9417 Invalid, 2937 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [44 Valid, 2893 Invalid, 0 Unknown, 0 Unchecked, 1.5s Time] [2024-12-02 06:17:30,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1316 states. [2024-12-02 06:17:30,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1316 to 1316. [2024-12-02 06:17:30,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1316 states, 1305 states have (on average 1.4766283524904213) internal successors, (1927), 1305 states have internal predecessors, (1927), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-12-02 06:17:30,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1316 states to 1316 states and 1945 transitions. [2024-12-02 06:17:30,678 INFO L78 Accepts]: Start accepts. Automaton has 1316 states and 1945 transitions. Word has length 374 [2024-12-02 06:17:30,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:30,679 INFO L471 AbstractCegarLoop]: Abstraction has 1316 states and 1945 transitions. [2024-12-02 06:17:30,679 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 41.0) internal successors, (328), 8 states have internal predecessors, (328), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:17:30,679 INFO L276 IsEmpty]: Start isEmpty. Operand 1316 states and 1945 transitions. [2024-12-02 06:17:30,681 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 375 [2024-12-02 06:17:30,681 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:30,681 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:30,694 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2024-12-02 06:17:30,882 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:30,882 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:30,882 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:30,882 INFO L85 PathProgramCache]: Analyzing trace with hash -106608308, now seen corresponding path program 1 times [2024-12-02 06:17:30,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:30,883 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958948856] [2024-12-02 06:17:30,883 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:30,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:30,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:31,124 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:17:31,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:31,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [958948856] [2024-12-02 06:17:31,124 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [958948856] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:31,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [619783072] [2024-12-02 06:17:31,124 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:31,125 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:31,125 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:31,126 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:31,127 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-12-02 06:17:31,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:31,796 INFO L256 TraceCheckSpWp]: Trace formula consists of 1372 conjuncts, 56 conjuncts are in the unsatisfiable core [2024-12-02 06:17:31,802 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:32,495 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2024-12-02 06:17:32,495 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:17:32,748 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:17:32,748 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [619783072] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:32,748 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:17:32,748 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [4, 8] total 18 [2024-12-02 06:17:32,748 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1864139610] [2024-12-02 06:17:32,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:32,749 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 06:17:32,749 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:32,749 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 06:17:32,749 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=237, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:17:32,749 INFO L87 Difference]: Start difference. First operand 1316 states and 1945 transitions. Second operand has 10 states, 10 states have (on average 32.8) internal successors, (328), 10 states have internal predecessors, (328), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:17:34,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:34,532 INFO L93 Difference]: Finished difference Result 2139 states and 3161 transitions. [2024-12-02 06:17:34,533 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:17:34,533 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 32.8) internal successors, (328), 10 states have internal predecessors, (328), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 374 [2024-12-02 06:17:34,534 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:34,536 INFO L225 Difference]: With dead ends: 2139 [2024-12-02 06:17:34,536 INFO L226 Difference]: Without dead ends: 1319 [2024-12-02 06:17:34,537 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 754 GetRequests, 734 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=99, Invalid=363, Unknown=0, NotChecked=0, Total=462 [2024-12-02 06:17:34,537 INFO L435 NwaCegarLoop]: 1004 mSDtfsCounter, 3371 mSDsluCounter, 3019 mSDsCounter, 0 mSdLazyCounter, 2812 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3375 SdHoareTripleChecker+Valid, 4023 SdHoareTripleChecker+Invalid, 2820 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 2812 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.7s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:34,538 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3375 Valid, 4023 Invalid, 2820 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 2812 Invalid, 0 Unknown, 0 Unchecked, 1.7s Time] [2024-12-02 06:17:34,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1319 states. [2024-12-02 06:17:34,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1319 to 1319. [2024-12-02 06:17:34,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1319 states, 1308 states have (on average 1.4762996941896025) internal successors, (1931), 1308 states have internal predecessors, (1931), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-12-02 06:17:34,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1319 states to 1319 states and 1949 transitions. [2024-12-02 06:17:34,557 INFO L78 Accepts]: Start accepts. Automaton has 1319 states and 1949 transitions. Word has length 374 [2024-12-02 06:17:34,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:34,557 INFO L471 AbstractCegarLoop]: Abstraction has 1319 states and 1949 transitions. [2024-12-02 06:17:34,558 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 32.8) internal successors, (328), 10 states have internal predecessors, (328), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:17:34,558 INFO L276 IsEmpty]: Start isEmpty. Operand 1319 states and 1949 transitions. [2024-12-02 06:17:34,560 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 376 [2024-12-02 06:17:34,561 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:34,561 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:34,569 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-12-02 06:17:34,761 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable11 [2024-12-02 06:17:34,761 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:34,762 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:34,762 INFO L85 PathProgramCache]: Analyzing trace with hash -1929701448, now seen corresponding path program 1 times [2024-12-02 06:17:34,762 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:34,762 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115593924] [2024-12-02 06:17:34,762 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:34,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:34,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:35,124 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:17:35,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:35,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2115593924] [2024-12-02 06:17:35,124 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2115593924] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:35,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1786174877] [2024-12-02 06:17:35,125 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:35,125 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:35,125 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:35,126 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:35,127 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-12-02 06:17:35,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:35,786 INFO L256 TraceCheckSpWp]: Trace formula consists of 1375 conjuncts, 174 conjuncts are in the unsatisfiable core [2024-12-02 06:17:35,814 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:38,281 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 24 proven. 57 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-12-02 06:17:38,281 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:17:39,395 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:17:39,395 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1786174877] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:39,395 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:17:39,395 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [4, 30] total 49 [2024-12-02 06:17:39,396 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [955146525] [2024-12-02 06:17:39,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:39,396 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2024-12-02 06:17:39,396 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:39,396 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2024-12-02 06:17:39,397 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=440, Invalid=1912, Unknown=0, NotChecked=0, Total=2352 [2024-12-02 06:17:39,397 INFO L87 Difference]: Start difference. First operand 1319 states and 1949 transitions. Second operand has 19 states, 19 states have (on average 17.31578947368421) internal successors, (329), 19 states have internal predecessors, (329), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:17:43,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:43,566 INFO L93 Difference]: Finished difference Result 2141 states and 3168 transitions. [2024-12-02 06:17:43,566 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2024-12-02 06:17:43,566 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 17.31578947368421) internal successors, (329), 19 states have internal predecessors, (329), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 375 [2024-12-02 06:17:43,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:43,571 INFO L225 Difference]: With dead ends: 2141 [2024-12-02 06:17:43,571 INFO L226 Difference]: Without dead ends: 2139 [2024-12-02 06:17:43,572 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 766 GetRequests, 706 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 952 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=663, Invalid=3119, Unknown=0, NotChecked=0, Total=3782 [2024-12-02 06:17:43,572 INFO L435 NwaCegarLoop]: 1813 mSDtfsCounter, 11008 mSDsluCounter, 9220 mSDsCounter, 0 mSdLazyCounter, 6480 mSolverCounterSat, 33 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 11011 SdHoareTripleChecker+Valid, 11033 SdHoareTripleChecker+Invalid, 6513 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 33 IncrementalHoareTripleChecker+Valid, 6480 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 3.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:43,573 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [11011 Valid, 11033 Invalid, 6513 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [33 Valid, 6480 Invalid, 0 Unknown, 0 Unchecked, 3.5s Time] [2024-12-02 06:17:43,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2139 states. [2024-12-02 06:17:43,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2139 to 1325. [2024-12-02 06:17:43,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1325 states, 1314 states have (on average 1.4771689497716896) internal successors, (1941), 1314 states have internal predecessors, (1941), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-12-02 06:17:43,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1325 states to 1325 states and 1959 transitions. [2024-12-02 06:17:43,602 INFO L78 Accepts]: Start accepts. Automaton has 1325 states and 1959 transitions. Word has length 375 [2024-12-02 06:17:43,603 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:43,603 INFO L471 AbstractCegarLoop]: Abstraction has 1325 states and 1959 transitions. [2024-12-02 06:17:43,603 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 19 states have (on average 17.31578947368421) internal successors, (329), 19 states have internal predecessors, (329), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:17:43,603 INFO L276 IsEmpty]: Start isEmpty. Operand 1325 states and 1959 transitions. [2024-12-02 06:17:43,605 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 377 [2024-12-02 06:17:43,605 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:43,605 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:43,615 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-12-02 06:17:43,806 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable12 [2024-12-02 06:17:43,806 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:43,806 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:43,806 INFO L85 PathProgramCache]: Analyzing trace with hash 1873344367, now seen corresponding path program 1 times [2024-12-02 06:17:43,806 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:43,806 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763883295] [2024-12-02 06:17:43,807 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:43,807 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:43,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:44,178 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:17:44,178 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:44,178 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763883295] [2024-12-02 06:17:44,178 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763883295] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:44,178 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [598588019] [2024-12-02 06:17:44,179 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:44,179 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:44,179 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:44,181 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:44,182 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-12-02 06:17:44,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:44,837 INFO L256 TraceCheckSpWp]: Trace formula consists of 1376 conjuncts, 10 conjuncts are in the unsatisfiable core [2024-12-02 06:17:44,842 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:44,977 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 24 proven. 0 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-12-02 06:17:44,977 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:17:44,977 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [598588019] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:17:44,977 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:17:44,977 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [4] total 8 [2024-12-02 06:17:44,977 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1173711789] [2024-12-02 06:17:44,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:44,978 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:17:44,978 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:44,978 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:17:44,978 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:17:44,979 INFO L87 Difference]: Start difference. First operand 1325 states and 1959 transitions. Second operand has 6 states, 6 states have (on average 55.5) internal successors, (333), 6 states have internal predecessors, (333), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:17:46,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:46,172 INFO L93 Difference]: Finished difference Result 3606 states and 5337 transitions. [2024-12-02 06:17:46,173 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:17:46,173 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 55.5) internal successors, (333), 6 states have internal predecessors, (333), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 376 [2024-12-02 06:17:46,173 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:46,178 INFO L225 Difference]: With dead ends: 3606 [2024-12-02 06:17:46,178 INFO L226 Difference]: Without dead ends: 2777 [2024-12-02 06:17:46,180 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 380 GetRequests, 373 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:17:46,180 INFO L435 NwaCegarLoop]: 2355 mSDtfsCounter, 1737 mSDsluCounter, 6841 mSDsCounter, 0 mSdLazyCounter, 1884 mSolverCounterSat, 36 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1745 SdHoareTripleChecker+Valid, 9196 SdHoareTripleChecker+Invalid, 1920 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 36 IncrementalHoareTripleChecker+Valid, 1884 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:46,180 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1745 Valid, 9196 Invalid, 1920 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [36 Valid, 1884 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-12-02 06:17:46,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2777 states. [2024-12-02 06:17:46,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2777 to 1507. [2024-12-02 06:17:46,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1507 states, 1490 states have (on average 1.4751677852348992) internal successors, (2198), 1490 states have internal predecessors, (2198), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 06:17:46,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1507 states to 1507 states and 2228 transitions. [2024-12-02 06:17:46,217 INFO L78 Accepts]: Start accepts. Automaton has 1507 states and 2228 transitions. Word has length 376 [2024-12-02 06:17:46,217 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:46,217 INFO L471 AbstractCegarLoop]: Abstraction has 1507 states and 2228 transitions. [2024-12-02 06:17:46,218 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 55.5) internal successors, (333), 6 states have internal predecessors, (333), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:17:46,218 INFO L276 IsEmpty]: Start isEmpty. Operand 1507 states and 2228 transitions. [2024-12-02 06:17:46,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 377 [2024-12-02 06:17:46,220 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:46,220 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:46,234 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-12-02 06:17:46,421 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable13 [2024-12-02 06:17:46,421 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:46,421 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:46,421 INFO L85 PathProgramCache]: Analyzing trace with hash 2088435055, now seen corresponding path program 1 times [2024-12-02 06:17:46,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:46,421 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2041424278] [2024-12-02 06:17:46,422 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:46,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:46,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:46,836 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:17:46,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:46,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2041424278] [2024-12-02 06:17:46,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2041424278] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:46,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [361705637] [2024-12-02 06:17:46,837 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:46,837 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:46,837 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:46,839 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:46,841 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-12-02 06:17:47,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:47,516 INFO L256 TraceCheckSpWp]: Trace formula consists of 1376 conjuncts, 10 conjuncts are in the unsatisfiable core [2024-12-02 06:17:47,520 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:47,646 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 81 trivial. 0 not checked. [2024-12-02 06:17:47,646 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:17:47,646 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [361705637] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:17:47,646 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:17:47,647 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [4] total 8 [2024-12-02 06:17:47,647 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [521794616] [2024-12-02 06:17:47,647 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:47,647 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:17:47,647 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:47,648 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:17:47,648 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:17:47,649 INFO L87 Difference]: Start difference. First operand 1507 states and 2228 transitions. Second operand has 6 states, 6 states have (on average 55.5) internal successors, (333), 6 states have internal predecessors, (333), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:17:48,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:48,535 INFO L93 Difference]: Finished difference Result 3755 states and 5555 transitions. [2024-12-02 06:17:48,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:17:48,536 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 55.5) internal successors, (333), 6 states have internal predecessors, (333), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 376 [2024-12-02 06:17:48,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:48,540 INFO L225 Difference]: With dead ends: 3755 [2024-12-02 06:17:48,540 INFO L226 Difference]: Without dead ends: 2059 [2024-12-02 06:17:48,542 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 383 GetRequests, 373 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:17:48,542 INFO L435 NwaCegarLoop]: 1724 mSDtfsCounter, 1883 mSDsluCounter, 6555 mSDsCounter, 0 mSdLazyCounter, 983 mSolverCounterSat, 46 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1888 SdHoareTripleChecker+Valid, 8279 SdHoareTripleChecker+Invalid, 1029 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 46 IncrementalHoareTripleChecker+Valid, 983 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:48,542 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1888 Valid, 8279 Invalid, 1029 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [46 Valid, 983 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2024-12-02 06:17:48,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2059 states. [2024-12-02 06:17:48,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2059 to 1467. [2024-12-02 06:17:48,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1467 states, 1451 states have (on average 1.4748449345279118) internal successors, (2140), 1451 states have internal predecessors, (2140), 14 states have call successors, (14), 1 states have call predecessors, (14), 1 states have return successors, (14), 14 states have call predecessors, (14), 14 states have call successors, (14) [2024-12-02 06:17:48,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1467 states to 1467 states and 2168 transitions. [2024-12-02 06:17:48,574 INFO L78 Accepts]: Start accepts. Automaton has 1467 states and 2168 transitions. Word has length 376 [2024-12-02 06:17:48,575 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:48,575 INFO L471 AbstractCegarLoop]: Abstraction has 1467 states and 2168 transitions. [2024-12-02 06:17:48,575 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 55.5) internal successors, (333), 6 states have internal predecessors, (333), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:17:48,575 INFO L276 IsEmpty]: Start isEmpty. Operand 1467 states and 2168 transitions. [2024-12-02 06:17:48,576 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 378 [2024-12-02 06:17:48,577 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:48,577 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:48,589 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-12-02 06:17:48,777 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable14 [2024-12-02 06:17:48,777 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:48,778 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:48,778 INFO L85 PathProgramCache]: Analyzing trace with hash -662642504, now seen corresponding path program 1 times [2024-12-02 06:17:48,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:48,778 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347753528] [2024-12-02 06:17:48,778 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:48,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:48,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:49,190 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:17:49,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:49,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347753528] [2024-12-02 06:17:49,190 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347753528] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:49,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [626851659] [2024-12-02 06:17:49,190 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:49,190 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:49,190 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:49,192 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:49,194 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-12-02 06:17:49,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:49,949 INFO L256 TraceCheckSpWp]: Trace formula consists of 1379 conjuncts, 36 conjuncts are in the unsatisfiable core [2024-12-02 06:17:49,954 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:50,611 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2024-12-02 06:17:50,611 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:17:51,958 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:17:51,959 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [626851659] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:51,959 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:17:51,959 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [4, 8] total 15 [2024-12-02 06:17:51,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1712493630] [2024-12-02 06:17:51,959 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:51,959 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:17:51,959 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:51,960 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:17:51,960 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2024-12-02 06:17:51,960 INFO L87 Difference]: Start difference. First operand 1467 states and 2168 transitions. Second operand has 7 states, 7 states have (on average 47.285714285714285) internal successors, (331), 7 states have internal predecessors, (331), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:17:53,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:53,532 INFO L93 Difference]: Finished difference Result 2448 states and 3617 transitions. [2024-12-02 06:17:53,533 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:17:53,533 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 47.285714285714285) internal successors, (331), 7 states have internal predecessors, (331), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 377 [2024-12-02 06:17:53,533 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:53,536 INFO L225 Difference]: With dead ends: 2448 [2024-12-02 06:17:53,536 INFO L226 Difference]: Without dead ends: 1477 [2024-12-02 06:17:53,537 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 759 GetRequests, 743 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 68 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=69, Invalid=237, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:17:53,537 INFO L435 NwaCegarLoop]: 1004 mSDtfsCounter, 3115 mSDsluCounter, 3001 mSDsCounter, 0 mSdLazyCounter, 2806 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3120 SdHoareTripleChecker+Valid, 4005 SdHoareTripleChecker+Invalid, 2814 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 2806 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:53,538 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3120 Valid, 4005 Invalid, 2814 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 2806 Invalid, 0 Unknown, 0 Unchecked, 1.5s Time] [2024-12-02 06:17:53,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1477 states. [2024-12-02 06:17:53,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1477 to 1475. [2024-12-02 06:17:53,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1475 states, 1459 states have (on average 1.4688142563399589) internal successors, (2143), 1459 states have internal predecessors, (2143), 14 states have call successors, (14), 1 states have call predecessors, (14), 1 states have return successors, (14), 14 states have call predecessors, (14), 14 states have call successors, (14) [2024-12-02 06:17:53,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1475 states to 1475 states and 2171 transitions. [2024-12-02 06:17:53,583 INFO L78 Accepts]: Start accepts. Automaton has 1475 states and 2171 transitions. Word has length 377 [2024-12-02 06:17:53,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:53,583 INFO L471 AbstractCegarLoop]: Abstraction has 1475 states and 2171 transitions. [2024-12-02 06:17:53,583 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 47.285714285714285) internal successors, (331), 7 states have internal predecessors, (331), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:17:53,583 INFO L276 IsEmpty]: Start isEmpty. Operand 1475 states and 2171 transitions. [2024-12-02 06:17:53,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 379 [2024-12-02 06:17:53,585 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:53,585 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:53,594 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2024-12-02 06:17:53,785 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable15 [2024-12-02 06:17:53,786 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:53,786 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:53,786 INFO L85 PathProgramCache]: Analyzing trace with hash -1978365022, now seen corresponding path program 1 times [2024-12-02 06:17:53,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:53,786 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305867570] [2024-12-02 06:17:53,786 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:53,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:53,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:54,054 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:17:54,054 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:54,054 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [305867570] [2024-12-02 06:17:54,054 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [305867570] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:54,054 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1864698552] [2024-12-02 06:17:54,055 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:54,055 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:54,055 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:54,056 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:54,057 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-12-02 06:17:54,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:54,762 INFO L256 TraceCheckSpWp]: Trace formula consists of 1382 conjuncts, 45 conjuncts are in the unsatisfiable core [2024-12-02 06:17:54,767 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:55,379 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2024-12-02 06:17:55,379 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:17:55,708 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:17:55,709 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1864698552] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:55,709 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:17:55,709 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [4, 8] total 18 [2024-12-02 06:17:55,709 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205869346] [2024-12-02 06:17:55,709 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:55,709 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 06:17:55,709 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:55,710 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 06:17:55,710 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=228, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:17:55,710 INFO L87 Difference]: Start difference. First operand 1475 states and 2171 transitions. Second operand has 10 states, 10 states have (on average 33.2) internal successors, (332), 10 states have internal predecessors, (332), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:17:57,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:17:57,186 INFO L93 Difference]: Finished difference Result 2458 states and 3614 transitions. [2024-12-02 06:17:57,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:17:57,187 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 33.2) internal successors, (332), 10 states have internal predecessors, (332), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 378 [2024-12-02 06:17:57,187 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:17:57,190 INFO L225 Difference]: With dead ends: 2458 [2024-12-02 06:17:57,190 INFO L226 Difference]: Without dead ends: 1479 [2024-12-02 06:17:57,191 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 761 GetRequests, 742 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=102, Invalid=318, Unknown=0, NotChecked=0, Total=420 [2024-12-02 06:17:57,191 INFO L435 NwaCegarLoop]: 1003 mSDtfsCounter, 3312 mSDsluCounter, 2998 mSDsCounter, 0 mSdLazyCounter, 2806 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3314 SdHoareTripleChecker+Valid, 4001 SdHoareTripleChecker+Invalid, 2812 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 2806 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:17:57,191 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3314 Valid, 4001 Invalid, 2812 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 2806 Invalid, 0 Unknown, 0 Unchecked, 1.4s Time] [2024-12-02 06:17:57,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1479 states. [2024-12-02 06:17:57,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1479 to 1479. [2024-12-02 06:17:57,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1479 states, 1463 states have (on average 1.4661654135338347) internal successors, (2145), 1463 states have internal predecessors, (2145), 14 states have call successors, (14), 1 states have call predecessors, (14), 1 states have return successors, (14), 14 states have call predecessors, (14), 14 states have call successors, (14) [2024-12-02 06:17:57,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1479 states to 1479 states and 2173 transitions. [2024-12-02 06:17:57,221 INFO L78 Accepts]: Start accepts. Automaton has 1479 states and 2173 transitions. Word has length 378 [2024-12-02 06:17:57,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:17:57,221 INFO L471 AbstractCegarLoop]: Abstraction has 1479 states and 2173 transitions. [2024-12-02 06:17:57,221 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 33.2) internal successors, (332), 10 states have internal predecessors, (332), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:17:57,221 INFO L276 IsEmpty]: Start isEmpty. Operand 1479 states and 2173 transitions. [2024-12-02 06:17:57,223 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 380 [2024-12-02 06:17:57,223 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:17:57,223 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:17:57,237 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2024-12-02 06:17:57,423 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable16 [2024-12-02 06:17:57,424 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:17:57,424 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:17:57,424 INFO L85 PathProgramCache]: Analyzing trace with hash 650834213, now seen corresponding path program 1 times [2024-12-02 06:17:57,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:17:57,424 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596494556] [2024-12-02 06:17:57,424 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:57,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:17:57,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:57,675 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:17:57,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:17:57,675 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1596494556] [2024-12-02 06:17:57,675 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1596494556] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:57,675 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [849783017] [2024-12-02 06:17:57,676 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:17:57,676 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:17:57,676 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:17:57,677 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:17:57,678 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-12-02 06:17:58,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:17:58,404 INFO L256 TraceCheckSpWp]: Trace formula consists of 1385 conjuncts, 68 conjuncts are in the unsatisfiable core [2024-12-02 06:17:58,409 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:17:59,056 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2024-12-02 06:17:59,056 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:17:59,430 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:17:59,430 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [849783017] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:17:59,430 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:17:59,430 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [4, 8] total 21 [2024-12-02 06:17:59,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1156498128] [2024-12-02 06:17:59,431 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:17:59,431 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2024-12-02 06:17:59,431 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:17:59,431 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-12-02 06:17:59,432 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=117, Invalid=303, Unknown=0, NotChecked=0, Total=420 [2024-12-02 06:17:59,432 INFO L87 Difference]: Start difference. First operand 1479 states and 2173 transitions. Second operand has 13 states, 13 states have (on average 25.615384615384617) internal successors, (333), 13 states have internal predecessors, (333), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:18:01,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:01,096 INFO L93 Difference]: Finished difference Result 2464 states and 3616 transitions. [2024-12-02 06:18:01,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:18:01,097 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 25.615384615384617) internal successors, (333), 13 states have internal predecessors, (333), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 379 [2024-12-02 06:18:01,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:01,100 INFO L225 Difference]: With dead ends: 2464 [2024-12-02 06:18:01,100 INFO L226 Difference]: Without dead ends: 1481 [2024-12-02 06:18:01,101 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 763 GetRequests, 741 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 119 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=150, Invalid=402, Unknown=0, NotChecked=0, Total=552 [2024-12-02 06:18:01,101 INFO L435 NwaCegarLoop]: 1003 mSDtfsCounter, 10032 mSDsluCounter, 3016 mSDsCounter, 0 mSdLazyCounter, 2807 mSolverCounterSat, 23 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 10036 SdHoareTripleChecker+Valid, 4019 SdHoareTripleChecker+Invalid, 2830 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 23 IncrementalHoareTripleChecker+Valid, 2807 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:01,102 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [10036 Valid, 4019 Invalid, 2830 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [23 Valid, 2807 Invalid, 0 Unknown, 0 Unchecked, 1.5s Time] [2024-12-02 06:18:01,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1481 states. [2024-12-02 06:18:01,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1481 to 1481. [2024-12-02 06:18:01,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1481 states, 1465 states have (on average 1.4655290102389078) internal successors, (2147), 1465 states have internal predecessors, (2147), 14 states have call successors, (14), 1 states have call predecessors, (14), 1 states have return successors, (14), 14 states have call predecessors, (14), 14 states have call successors, (14) [2024-12-02 06:18:01,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1481 states to 1481 states and 2175 transitions. [2024-12-02 06:18:01,145 INFO L78 Accepts]: Start accepts. Automaton has 1481 states and 2175 transitions. Word has length 379 [2024-12-02 06:18:01,145 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:01,145 INFO L471 AbstractCegarLoop]: Abstraction has 1481 states and 2175 transitions. [2024-12-02 06:18:01,146 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 25.615384615384617) internal successors, (333), 13 states have internal predecessors, (333), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:18:01,146 INFO L276 IsEmpty]: Start isEmpty. Operand 1481 states and 2175 transitions. [2024-12-02 06:18:01,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 381 [2024-12-02 06:18:01,147 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:01,147 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:01,161 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0 [2024-12-02 06:18:01,348 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable17 [2024-12-02 06:18:01,348 INFO L396 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:01,348 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:01,349 INFO L85 PathProgramCache]: Analyzing trace with hash 1223310629, now seen corresponding path program 1 times [2024-12-02 06:18:01,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:01,349 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803530306] [2024-12-02 06:18:01,349 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:01,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:01,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:01,588 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:18:01,588 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:01,588 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803530306] [2024-12-02 06:18:01,588 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [803530306] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:01,588 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1379178361] [2024-12-02 06:18:01,588 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:01,588 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:01,589 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:01,590 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:01,591 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-12-02 06:18:02,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:02,293 INFO L256 TraceCheckSpWp]: Trace formula consists of 1386 conjuncts, 50 conjuncts are in the unsatisfiable core [2024-12-02 06:18:02,298 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:03,035 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2024-12-02 06:18:03,035 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:03,316 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:18:03,316 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1379178361] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:03,316 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:18:03,316 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [4, 8] total 18 [2024-12-02 06:18:03,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [197661681] [2024-12-02 06:18:03,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:03,317 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 06:18:03,317 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:03,318 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 06:18:03,318 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=228, Unknown=0, NotChecked=0, Total=306 [2024-12-02 06:18:03,318 INFO L87 Difference]: Start difference. First operand 1481 states and 2175 transitions. Second operand has 10 states, 10 states have (on average 33.4) internal successors, (334), 10 states have internal predecessors, (334), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:18:04,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:04,778 INFO L93 Difference]: Finished difference Result 2437 states and 3576 transitions. [2024-12-02 06:18:04,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:18:04,779 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 33.4) internal successors, (334), 10 states have internal predecessors, (334), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 380 [2024-12-02 06:18:04,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:04,781 INFO L225 Difference]: With dead ends: 2437 [2024-12-02 06:18:04,781 INFO L226 Difference]: Without dead ends: 1452 [2024-12-02 06:18:04,782 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 765 GetRequests, 746 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=102, Invalid=318, Unknown=0, NotChecked=0, Total=420 [2024-12-02 06:18:04,783 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 8326 mSDsluCounter, 3013 mSDsCounter, 0 mSdLazyCounter, 2806 mSolverCounterSat, 19 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 8329 SdHoareTripleChecker+Valid, 4015 SdHoareTripleChecker+Invalid, 2825 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 19 IncrementalHoareTripleChecker+Valid, 2806 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:04,783 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [8329 Valid, 4015 Invalid, 2825 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [19 Valid, 2806 Invalid, 0 Unknown, 0 Unchecked, 1.4s Time] [2024-12-02 06:18:04,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1452 states. [2024-12-02 06:18:04,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1452 to 1325. [2024-12-02 06:18:04,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1325 states, 1315 states have (on average 1.4699619771863117) internal successors, (1933), 1315 states have internal predecessors, (1933), 8 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 8 states have call predecessors, (8), 8 states have call successors, (8) [2024-12-02 06:18:04,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1325 states to 1325 states and 1949 transitions. [2024-12-02 06:18:04,809 INFO L78 Accepts]: Start accepts. Automaton has 1325 states and 1949 transitions. Word has length 380 [2024-12-02 06:18:04,810 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:04,810 INFO L471 AbstractCegarLoop]: Abstraction has 1325 states and 1949 transitions. [2024-12-02 06:18:04,810 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 33.4) internal successors, (334), 10 states have internal predecessors, (334), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:18:04,810 INFO L276 IsEmpty]: Start isEmpty. Operand 1325 states and 1949 transitions. [2024-12-02 06:18:04,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 382 [2024-12-02 06:18:04,811 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:04,811 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:04,820 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Ended with exit code 0 [2024-12-02 06:18:05,012 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18,17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:05,012 INFO L396 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:05,012 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:05,013 INFO L85 PathProgramCache]: Analyzing trace with hash -699122270, now seen corresponding path program 1 times [2024-12-02 06:18:05,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:05,013 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [201826006] [2024-12-02 06:18:05,013 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:05,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:05,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:05,252 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:18:05,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:05,253 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [201826006] [2024-12-02 06:18:05,253 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [201826006] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:05,253 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1602319717] [2024-12-02 06:18:05,253 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:05,253 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:05,253 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:05,255 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:05,255 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-12-02 06:18:06,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:06,013 INFO L256 TraceCheckSpWp]: Trace formula consists of 1387 conjuncts, 49 conjuncts are in the unsatisfiable core [2024-12-02 06:18:06,019 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:06,716 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 16 proven. 1 refuted. 0 times theorem prover too weak. 80 trivial. 0 not checked. [2024-12-02 06:18:06,716 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:06,943 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:18:06,943 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1602319717] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:06,943 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:18:06,943 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [4, 7] total 17 [2024-12-02 06:18:06,943 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695874598] [2024-12-02 06:18:06,943 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:06,943 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 06:18:06,944 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:06,944 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 06:18:06,944 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=219, Unknown=0, NotChecked=0, Total=272 [2024-12-02 06:18:06,944 INFO L87 Difference]: Start difference. First operand 1325 states and 1949 transitions. Second operand has 10 states, 10 states have (on average 33.5) internal successors, (335), 10 states have internal predecessors, (335), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:18:09,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:09,495 INFO L93 Difference]: Finished difference Result 2195 states and 3223 transitions. [2024-12-02 06:18:09,495 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:18:09,495 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 33.5) internal successors, (335), 10 states have internal predecessors, (335), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 381 [2024-12-02 06:18:09,496 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:09,498 INFO L225 Difference]: With dead ends: 2195 [2024-12-02 06:18:09,498 INFO L226 Difference]: Without dead ends: 1331 [2024-12-02 06:18:09,499 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 767 GetRequests, 749 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=77, Invalid=303, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:18:09,499 INFO L435 NwaCegarLoop]: 1009 mSDtfsCounter, 1763 mSDsluCounter, 5984 mSDsCounter, 0 mSdLazyCounter, 4904 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1767 SdHoareTripleChecker+Valid, 6993 SdHoareTripleChecker+Invalid, 4911 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 4904 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:09,499 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1767 Valid, 6993 Invalid, 4911 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 4904 Invalid, 0 Unknown, 0 Unchecked, 2.4s Time] [2024-12-02 06:18:09,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1331 states. [2024-12-02 06:18:09,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1331 to 1329. [2024-12-02 06:18:09,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1329 states, 1319 states have (on average 1.466262319939348) internal successors, (1934), 1319 states have internal predecessors, (1934), 8 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 8 states have call predecessors, (8), 8 states have call successors, (8) [2024-12-02 06:18:09,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1329 states to 1329 states and 1950 transitions. [2024-12-02 06:18:09,529 INFO L78 Accepts]: Start accepts. Automaton has 1329 states and 1950 transitions. Word has length 381 [2024-12-02 06:18:09,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:09,529 INFO L471 AbstractCegarLoop]: Abstraction has 1329 states and 1950 transitions. [2024-12-02 06:18:09,529 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 33.5) internal successors, (335), 10 states have internal predecessors, (335), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:18:09,529 INFO L276 IsEmpty]: Start isEmpty. Operand 1329 states and 1950 transitions. [2024-12-02 06:18:09,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 383 [2024-12-02 06:18:09,531 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:09,531 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:09,540 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Ended with exit code 0 [2024-12-02 06:18:09,731 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19,18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:09,732 INFO L396 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:09,732 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:09,732 INFO L85 PathProgramCache]: Analyzing trace with hash -1748653598, now seen corresponding path program 1 times [2024-12-02 06:18:09,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:09,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [383554722] [2024-12-02 06:18:09,732 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:09,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:09,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:09,988 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:18:09,988 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:09,989 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [383554722] [2024-12-02 06:18:09,989 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [383554722] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:09,989 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1104673339] [2024-12-02 06:18:09,989 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:09,989 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:09,989 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:09,990 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:09,991 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-12-02 06:18:10,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:10,734 INFO L256 TraceCheckSpWp]: Trace formula consists of 1390 conjuncts, 66 conjuncts are in the unsatisfiable core [2024-12-02 06:18:10,740 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:11,429 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 16 proven. 14 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2024-12-02 06:18:11,429 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:11,803 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:18:11,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1104673339] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:11,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:18:11,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [4, 9] total 19 [2024-12-02 06:18:11,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379512828] [2024-12-02 06:18:11,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:11,804 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 06:18:11,804 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:11,804 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 06:18:11,804 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=253, Unknown=0, NotChecked=0, Total=342 [2024-12-02 06:18:11,804 INFO L87 Difference]: Start difference. First operand 1329 states and 1950 transitions. Second operand has 10 states, 10 states have (on average 33.6) internal successors, (336), 10 states have internal predecessors, (336), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:18:13,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:13,344 INFO L93 Difference]: Finished difference Result 2164 states and 3170 transitions. [2024-12-02 06:18:13,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:18:13,345 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 33.6) internal successors, (336), 10 states have internal predecessors, (336), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 382 [2024-12-02 06:18:13,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:13,347 INFO L225 Difference]: With dead ends: 2164 [2024-12-02 06:18:13,347 INFO L226 Difference]: Without dead ends: 1329 [2024-12-02 06:18:13,348 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 769 GetRequests, 749 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 111 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=113, Invalid=349, Unknown=0, NotChecked=0, Total=462 [2024-12-02 06:18:13,348 INFO L435 NwaCegarLoop]: 1000 mSDtfsCounter, 4975 mSDsluCounter, 3007 mSDsCounter, 0 mSdLazyCounter, 2806 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4977 SdHoareTripleChecker+Valid, 4007 SdHoareTripleChecker+Invalid, 2815 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 2806 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:13,349 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4977 Valid, 4007 Invalid, 2815 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 2806 Invalid, 0 Unknown, 0 Unchecked, 1.4s Time] [2024-12-02 06:18:13,350 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1329 states. [2024-12-02 06:18:13,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1329 to 1329. [2024-12-02 06:18:13,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1329 states, 1319 states have (on average 1.4655041698256255) internal successors, (1933), 1319 states have internal predecessors, (1933), 8 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 8 states have call predecessors, (8), 8 states have call successors, (8) [2024-12-02 06:18:13,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1329 states to 1329 states and 1949 transitions. [2024-12-02 06:18:13,374 INFO L78 Accepts]: Start accepts. Automaton has 1329 states and 1949 transitions. Word has length 382 [2024-12-02 06:18:13,375 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:13,375 INFO L471 AbstractCegarLoop]: Abstraction has 1329 states and 1949 transitions. [2024-12-02 06:18:13,375 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 33.6) internal successors, (336), 10 states have internal predecessors, (336), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:18:13,375 INFO L276 IsEmpty]: Start isEmpty. Operand 1329 states and 1949 transitions. [2024-12-02 06:18:13,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 384 [2024-12-02 06:18:13,376 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:13,376 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:13,385 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Ended with exit code 0 [2024-12-02 06:18:13,577 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20,19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:13,577 INFO L396 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:13,577 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:13,577 INFO L85 PathProgramCache]: Analyzing trace with hash -1859211361, now seen corresponding path program 1 times [2024-12-02 06:18:13,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:13,577 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793759694] [2024-12-02 06:18:13,577 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:13,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:13,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:13,853 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:18:13,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:13,853 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1793759694] [2024-12-02 06:18:13,853 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1793759694] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:13,853 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1552312011] [2024-12-02 06:18:13,853 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:13,853 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:13,854 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:13,855 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:13,856 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-12-02 06:18:14,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:14,626 INFO L256 TraceCheckSpWp]: Trace formula consists of 1393 conjuncts, 49 conjuncts are in the unsatisfiable core [2024-12-02 06:18:14,631 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:15,294 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 16 proven. 1 refuted. 0 times theorem prover too weak. 80 trivial. 0 not checked. [2024-12-02 06:18:15,294 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:15,447 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:18:15,447 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1552312011] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:15,447 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:18:15,447 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [4, 7] total 16 [2024-12-02 06:18:15,447 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1332869826] [2024-12-02 06:18:15,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:15,448 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:18:15,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:15,448 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:18:15,448 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=198, Unknown=0, NotChecked=0, Total=240 [2024-12-02 06:18:15,449 INFO L87 Difference]: Start difference. First operand 1329 states and 1949 transitions. Second operand has 9 states, 9 states have (on average 37.44444444444444) internal successors, (337), 9 states have internal predecessors, (337), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:18:18,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:18,227 INFO L93 Difference]: Finished difference Result 2997 states and 4386 transitions. [2024-12-02 06:18:18,227 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:18:18,227 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 37.44444444444444) internal successors, (337), 9 states have internal predecessors, (337), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 383 [2024-12-02 06:18:18,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:18,232 INFO L225 Difference]: With dead ends: 2997 [2024-12-02 06:18:18,232 INFO L226 Difference]: Without dead ends: 2159 [2024-12-02 06:18:18,234 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 771 GetRequests, 754 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=63, Invalid=279, Unknown=0, NotChecked=0, Total=342 [2024-12-02 06:18:18,235 INFO L435 NwaCegarLoop]: 2448 mSDtfsCounter, 1998 mSDsluCounter, 8322 mSDsCounter, 0 mSdLazyCounter, 5063 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2002 SdHoareTripleChecker+Valid, 10770 SdHoareTripleChecker+Invalid, 5068 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 5063 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.7s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:18,235 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2002 Valid, 10770 Invalid, 5068 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 5063 Invalid, 0 Unknown, 0 Unchecked, 2.7s Time] [2024-12-02 06:18:18,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2159 states. [2024-12-02 06:18:18,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2159 to 2157. [2024-12-02 06:18:18,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2157 states, 2139 states have (on average 1.463768115942029) internal successors, (3131), 2139 states have internal predecessors, (3131), 16 states have call successors, (16), 1 states have call predecessors, (16), 1 states have return successors, (16), 16 states have call predecessors, (16), 16 states have call successors, (16) [2024-12-02 06:18:18,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2157 states to 2157 states and 3163 transitions. [2024-12-02 06:18:18,274 INFO L78 Accepts]: Start accepts. Automaton has 2157 states and 3163 transitions. Word has length 383 [2024-12-02 06:18:18,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:18,275 INFO L471 AbstractCegarLoop]: Abstraction has 2157 states and 3163 transitions. [2024-12-02 06:18:18,275 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 37.44444444444444) internal successors, (337), 9 states have internal predecessors, (337), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:18:18,275 INFO L276 IsEmpty]: Start isEmpty. Operand 2157 states and 3163 transitions. [2024-12-02 06:18:18,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 384 [2024-12-02 06:18:18,276 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:18,277 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:18,290 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Ended with exit code 0 [2024-12-02 06:18:18,477 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21,20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:18,477 INFO L396 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:18,477 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:18,478 INFO L85 PathProgramCache]: Analyzing trace with hash 1391897919, now seen corresponding path program 1 times [2024-12-02 06:18:18,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:18,478 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079171992] [2024-12-02 06:18:18,478 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:18,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:18,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:18,734 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:18:18,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:18,735 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079171992] [2024-12-02 06:18:18,735 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079171992] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:18,735 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [431576199] [2024-12-02 06:18:18,735 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:18,735 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:18,735 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:18,736 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:18,737 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2024-12-02 06:18:19,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:19,603 INFO L256 TraceCheckSpWp]: Trace formula consists of 1393 conjuncts, 37 conjuncts are in the unsatisfiable core [2024-12-02 06:18:19,609 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:20,146 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:18:20,146 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:20,296 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:18:20,296 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [431576199] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:20,296 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:18:20,296 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [4, 5] total 11 [2024-12-02 06:18:20,296 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1031617585] [2024-12-02 06:18:20,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:20,297 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:18:20,297 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:20,297 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:18:20,297 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=82, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:18:20,297 INFO L87 Difference]: Start difference. First operand 2157 states and 3163 transitions. Second operand has 6 states, 6 states have (on average 56.166666666666664) internal successors, (337), 6 states have internal predecessors, (337), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:18:21,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:21,263 INFO L93 Difference]: Finished difference Result 6803 states and 9957 transitions. [2024-12-02 06:18:21,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:18:21,263 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 56.166666666666664) internal successors, (337), 6 states have internal predecessors, (337), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 383 [2024-12-02 06:18:21,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:21,271 INFO L225 Difference]: With dead ends: 6803 [2024-12-02 06:18:21,271 INFO L226 Difference]: Without dead ends: 5138 [2024-12-02 06:18:21,273 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 769 GetRequests, 759 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:18:21,273 INFO L435 NwaCegarLoop]: 2589 mSDtfsCounter, 2635 mSDsluCounter, 6017 mSDsCounter, 0 mSdLazyCounter, 847 mSolverCounterSat, 45 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2642 SdHoareTripleChecker+Valid, 8606 SdHoareTripleChecker+Invalid, 892 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 45 IncrementalHoareTripleChecker+Valid, 847 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:21,273 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2642 Valid, 8606 Invalid, 892 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [45 Valid, 847 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-12-02 06:18:21,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5138 states. [2024-12-02 06:18:21,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5138 to 3942. [2024-12-02 06:18:21,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3942 states, 3902 states have (on average 1.460276781137878) internal successors, (5698), 3902 states have internal predecessors, (5698), 38 states have call successors, (38), 1 states have call predecessors, (38), 1 states have return successors, (38), 38 states have call predecessors, (38), 38 states have call successors, (38) [2024-12-02 06:18:21,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3942 states to 3942 states and 5774 transitions. [2024-12-02 06:18:21,345 INFO L78 Accepts]: Start accepts. Automaton has 3942 states and 5774 transitions. Word has length 383 [2024-12-02 06:18:21,346 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:21,346 INFO L471 AbstractCegarLoop]: Abstraction has 3942 states and 5774 transitions. [2024-12-02 06:18:21,346 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 56.166666666666664) internal successors, (337), 6 states have internal predecessors, (337), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 06:18:21,346 INFO L276 IsEmpty]: Start isEmpty. Operand 3942 states and 5774 transitions. [2024-12-02 06:18:21,348 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 384 [2024-12-02 06:18:21,348 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:21,348 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:21,358 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Ended with exit code 0 [2024-12-02 06:18:21,548 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22,21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:21,549 INFO L396 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:21,549 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:21,549 INFO L85 PathProgramCache]: Analyzing trace with hash 658468767, now seen corresponding path program 1 times [2024-12-02 06:18:21,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:21,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425532055] [2024-12-02 06:18:21,549 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:21,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:21,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:21,812 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:18:21,813 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:21,813 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1425532055] [2024-12-02 06:18:21,813 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1425532055] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:21,813 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [905705589] [2024-12-02 06:18:21,813 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:21,813 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:21,813 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:21,815 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:21,817 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2024-12-02 06:18:22,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:22,639 INFO L256 TraceCheckSpWp]: Trace formula consists of 1393 conjuncts, 49 conjuncts are in the unsatisfiable core [2024-12-02 06:18:22,644 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:23,380 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 16 proven. 1 refuted. 0 times theorem prover too weak. 80 trivial. 0 not checked. [2024-12-02 06:18:23,380 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:23,564 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-12-02 06:18:23,564 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [905705589] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:23,564 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:18:23,564 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [4, 7] total 16 [2024-12-02 06:18:23,564 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1179299997] [2024-12-02 06:18:23,564 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:23,565 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:18:23,565 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:23,565 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:18:23,565 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=198, Unknown=0, NotChecked=0, Total=240 [2024-12-02 06:18:23,565 INFO L87 Difference]: Start difference. First operand 3942 states and 5774 transitions. Second operand has 9 states, 9 states have (on average 37.44444444444444) internal successors, (337), 9 states have internal predecessors, (337), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:18:26,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:26,141 INFO L93 Difference]: Finished difference Result 5666 states and 8290 transitions. [2024-12-02 06:18:26,141 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 06:18:26,141 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 37.44444444444444) internal successors, (337), 9 states have internal predecessors, (337), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 383 [2024-12-02 06:18:26,141 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:26,146 INFO L225 Difference]: With dead ends: 5666 [2024-12-02 06:18:26,146 INFO L226 Difference]: Without dead ends: 3191 [2024-12-02 06:18:26,149 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 771 GetRequests, 754 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=63, Invalid=279, Unknown=0, NotChecked=0, Total=342 [2024-12-02 06:18:26,150 INFO L435 NwaCegarLoop]: 1594 mSDtfsCounter, 3942 mSDsluCounter, 6182 mSDsCounter, 0 mSdLazyCounter, 4644 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3945 SdHoareTripleChecker+Valid, 7776 SdHoareTripleChecker+Invalid, 4654 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 4644 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:26,150 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3945 Valid, 7776 Invalid, 4654 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 4644 Invalid, 0 Unknown, 0 Unchecked, 2.4s Time] [2024-12-02 06:18:26,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3191 states. [2024-12-02 06:18:26,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3191 to 3155. [2024-12-02 06:18:26,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3155 states, 3122 states have (on average 1.4548366431774504) internal successors, (4542), 3122 states have internal predecessors, (4542), 31 states have call successors, (31), 1 states have call predecessors, (31), 1 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2024-12-02 06:18:26,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3155 states to 3155 states and 4604 transitions. [2024-12-02 06:18:26,209 INFO L78 Accepts]: Start accepts. Automaton has 3155 states and 4604 transitions. Word has length 383 [2024-12-02 06:18:26,209 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:26,209 INFO L471 AbstractCegarLoop]: Abstraction has 3155 states and 4604 transitions. [2024-12-02 06:18:26,209 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 37.44444444444444) internal successors, (337), 9 states have internal predecessors, (337), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 06:18:26,209 INFO L276 IsEmpty]: Start isEmpty. Operand 3155 states and 4604 transitions. [2024-12-02 06:18:26,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 385 [2024-12-02 06:18:26,211 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:26,212 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:26,222 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Ended with exit code 0 [2024-12-02 06:18:26,412 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23,22 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:26,412 INFO L396 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:26,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:26,413 INFO L85 PathProgramCache]: Analyzing trace with hash -827458587, now seen corresponding path program 1 times [2024-12-02 06:18:26,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:26,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099561788] [2024-12-02 06:18:26,413 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:26,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:26,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:26,680 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:18:26,681 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:26,681 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1099561788] [2024-12-02 06:18:26,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1099561788] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:26,681 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [807127071] [2024-12-02 06:18:26,681 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:26,681 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:26,681 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:26,683 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:26,683 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2024-12-02 06:18:27,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:27,543 INFO L256 TraceCheckSpWp]: Trace formula consists of 1396 conjuncts, 16 conjuncts are in the unsatisfiable core [2024-12-02 06:18:27,546 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:27,608 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 17 refuted. 0 times theorem prover too weak. 80 trivial. 0 not checked. [2024-12-02 06:18:27,608 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:27,647 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 06:18:27,647 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [807127071] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:18:27,647 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:18:27,647 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 7, 4] total 11 [2024-12-02 06:18:27,647 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [700614178] [2024-12-02 06:18:27,647 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:18:27,648 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2024-12-02 06:18:27,648 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:27,648 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2024-12-02 06:18:27,648 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:18:27,648 INFO L87 Difference]: Start difference. First operand 3155 states and 4604 transitions. Second operand has 11 states, 11 states have (on average 33.09090909090909) internal successors, (364), 11 states have internal predecessors, (364), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:18:27,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:27,825 INFO L93 Difference]: Finished difference Result 6286 states and 9177 transitions. [2024-12-02 06:18:27,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:18:27,826 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 33.09090909090909) internal successors, (364), 11 states have internal predecessors, (364), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 384 [2024-12-02 06:18:27,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:27,830 INFO L225 Difference]: With dead ends: 6286 [2024-12-02 06:18:27,830 INFO L226 Difference]: Without dead ends: 3166 [2024-12-02 06:18:27,832 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 771 GetRequests, 761 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=93, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:18:27,832 INFO L435 NwaCegarLoop]: 1688 mSDtfsCounter, 1751 mSDsluCounter, 6701 mSDsCounter, 0 mSdLazyCounter, 147 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1756 SdHoareTripleChecker+Valid, 8389 SdHoareTripleChecker+Invalid, 148 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 147 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:27,832 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1756 Valid, 8389 Invalid, 148 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 147 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:18:27,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3166 states. [2024-12-02 06:18:27,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3166 to 3161. [2024-12-02 06:18:27,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3161 states, 3128 states have (on average 1.4546035805626598) internal successors, (4550), 3128 states have internal predecessors, (4550), 31 states have call successors, (31), 1 states have call predecessors, (31), 1 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2024-12-02 06:18:27,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3161 states to 3161 states and 4612 transitions. [2024-12-02 06:18:27,907 INFO L78 Accepts]: Start accepts. Automaton has 3161 states and 4612 transitions. Word has length 384 [2024-12-02 06:18:27,907 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:27,907 INFO L471 AbstractCegarLoop]: Abstraction has 3161 states and 4612 transitions. [2024-12-02 06:18:27,907 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 33.09090909090909) internal successors, (364), 11 states have internal predecessors, (364), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-12-02 06:18:27,907 INFO L276 IsEmpty]: Start isEmpty. Operand 3161 states and 4612 transitions. [2024-12-02 06:18:27,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 389 [2024-12-02 06:18:27,911 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:27,911 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:27,926 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Ended with exit code 0 [2024-12-02 06:18:28,111 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable24 [2024-12-02 06:18:28,111 INFO L396 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:28,112 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:28,112 INFO L85 PathProgramCache]: Analyzing trace with hash 421464723, now seen corresponding path program 2 times [2024-12-02 06:18:28,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:28,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485790344] [2024-12-02 06:18:28,112 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:18:28,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:28,301 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:18:28,301 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:18:29,202 INFO L134 CoverageAnalysis]: Checked inductivity of 102 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 102 trivial. 0 not checked. [2024-12-02 06:18:29,203 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:29,203 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [485790344] [2024-12-02 06:18:29,203 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [485790344] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:18:29,203 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:18:29,203 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:18:29,203 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [989044714] [2024-12-02 06:18:29,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:29,204 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:18:29,204 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:29,205 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:18:29,205 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:18:29,205 INFO L87 Difference]: Start difference. First operand 3161 states and 4612 transitions. Second operand has 6 states, 6 states have (on average 56.333333333333336) internal successors, (338), 6 states have internal predecessors, (338), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:18:29,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:29,475 INFO L93 Difference]: Finished difference Result 6490 states and 9438 transitions. [2024-12-02 06:18:29,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:18:29,476 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 56.333333333333336) internal successors, (338), 6 states have internal predecessors, (338), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 388 [2024-12-02 06:18:29,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:29,482 INFO L225 Difference]: With dead ends: 6490 [2024-12-02 06:18:29,482 INFO L226 Difference]: Without dead ends: 3829 [2024-12-02 06:18:29,485 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:18:29,486 INFO L435 NwaCegarLoop]: 1674 mSDtfsCounter, 1807 mSDsluCounter, 5016 mSDsCounter, 0 mSdLazyCounter, 110 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1812 SdHoareTripleChecker+Valid, 6690 SdHoareTripleChecker+Invalid, 115 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 110 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:29,486 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1812 Valid, 6690 Invalid, 115 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 110 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:18:29,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3829 states. [2024-12-02 06:18:29,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3829 to 3823. [2024-12-02 06:18:29,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3823 states, 3767 states have (on average 1.4454473055481816) internal successors, (5445), 3767 states have internal predecessors, (5445), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:18:29,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3823 states to 3823 states and 5553 transitions. [2024-12-02 06:18:29,630 INFO L78 Accepts]: Start accepts. Automaton has 3823 states and 5553 transitions. Word has length 388 [2024-12-02 06:18:29,630 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:29,631 INFO L471 AbstractCegarLoop]: Abstraction has 3823 states and 5553 transitions. [2024-12-02 06:18:29,631 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 56.333333333333336) internal successors, (338), 6 states have internal predecessors, (338), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:18:29,631 INFO L276 IsEmpty]: Start isEmpty. Operand 3823 states and 5553 transitions. [2024-12-02 06:18:29,641 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 776 [2024-12-02 06:18:29,641 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:29,641 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:29,642 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable25 [2024-12-02 06:18:29,642 INFO L396 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:29,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:29,643 INFO L85 PathProgramCache]: Analyzing trace with hash 693928831, now seen corresponding path program 1 times [2024-12-02 06:18:29,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:29,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [758968368] [2024-12-02 06:18:29,643 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:29,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:30,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:31,333 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2024-12-02 06:18:31,333 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:31,334 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [758968368] [2024-12-02 06:18:31,334 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [758968368] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:18:31,334 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:18:31,334 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:18:31,334 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1480266818] [2024-12-02 06:18:31,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:31,334 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:18:31,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:31,335 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:18:31,335 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:18:31,335 INFO L87 Difference]: Start difference. First operand 3823 states and 5553 transitions. Second operand has 5 states, 5 states have (on average 140.0) internal successors, (700), 5 states have internal predecessors, (700), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:32,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:32,259 INFO L93 Difference]: Finished difference Result 6484 states and 9426 transitions. [2024-12-02 06:18:32,260 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:18:32,260 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 140.0) internal successors, (700), 5 states have internal predecessors, (700), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 775 [2024-12-02 06:18:32,260 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:32,264 INFO L225 Difference]: With dead ends: 6484 [2024-12-02 06:18:32,264 INFO L226 Difference]: Without dead ends: 3823 [2024-12-02 06:18:32,267 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:18:32,267 INFO L435 NwaCegarLoop]: 1005 mSDtfsCounter, 2909 mSDsluCounter, 1007 mSDsCounter, 0 mSdLazyCounter, 1388 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2909 SdHoareTripleChecker+Valid, 2012 SdHoareTripleChecker+Invalid, 1389 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1388 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:32,267 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2909 Valid, 2012 Invalid, 1389 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1388 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2024-12-02 06:18:32,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3823 states. [2024-12-02 06:18:32,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3823 to 3823. [2024-12-02 06:18:32,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3823 states, 3767 states have (on average 1.444650915848155) internal successors, (5442), 3767 states have internal predecessors, (5442), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:18:32,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3823 states to 3823 states and 5550 transitions. [2024-12-02 06:18:32,357 INFO L78 Accepts]: Start accepts. Automaton has 3823 states and 5550 transitions. Word has length 775 [2024-12-02 06:18:32,357 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:32,357 INFO L471 AbstractCegarLoop]: Abstraction has 3823 states and 5550 transitions. [2024-12-02 06:18:32,357 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 140.0) internal successors, (700), 5 states have internal predecessors, (700), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:32,357 INFO L276 IsEmpty]: Start isEmpty. Operand 3823 states and 5550 transitions. [2024-12-02 06:18:32,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 777 [2024-12-02 06:18:32,363 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:32,363 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:32,363 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable26 [2024-12-02 06:18:32,363 INFO L396 AbstractCegarLoop]: === Iteration 28 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:32,363 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:32,364 INFO L85 PathProgramCache]: Analyzing trace with hash -37671733, now seen corresponding path program 1 times [2024-12-02 06:18:32,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:32,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [778181060] [2024-12-02 06:18:32,364 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:32,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:32,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:33,286 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2024-12-02 06:18:33,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:33,286 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [778181060] [2024-12-02 06:18:33,286 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [778181060] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:18:33,286 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:18:33,286 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-12-02 06:18:33,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55287714] [2024-12-02 06:18:33,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:33,287 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:18:33,287 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:33,288 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:18:33,288 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:18:33,288 INFO L87 Difference]: Start difference. First operand 3823 states and 5550 transitions. Second operand has 3 states, 3 states have (on average 233.66666666666666) internal successors, (701), 3 states have internal predecessors, (701), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:33,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:33,395 INFO L93 Difference]: Finished difference Result 6490 states and 9429 transitions. [2024-12-02 06:18:33,396 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:18:33,396 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 233.66666666666666) internal successors, (701), 3 states have internal predecessors, (701), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 776 [2024-12-02 06:18:33,397 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:33,401 INFO L225 Difference]: With dead ends: 6490 [2024-12-02 06:18:33,402 INFO L226 Difference]: Without dead ends: 3829 [2024-12-02 06:18:33,404 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-12-02 06:18:33,405 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:33,405 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:18:33,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3829 states. [2024-12-02 06:18:33,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3829 to 3826. [2024-12-02 06:18:33,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3826 states, 3770 states have (on average 1.4442970822281167) internal successors, (5445), 3770 states have internal predecessors, (5445), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:18:33,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3826 states to 3826 states and 5553 transitions. [2024-12-02 06:18:33,544 INFO L78 Accepts]: Start accepts. Automaton has 3826 states and 5553 transitions. Word has length 776 [2024-12-02 06:18:33,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:33,544 INFO L471 AbstractCegarLoop]: Abstraction has 3826 states and 5553 transitions. [2024-12-02 06:18:33,545 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 233.66666666666666) internal successors, (701), 3 states have internal predecessors, (701), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:33,545 INFO L276 IsEmpty]: Start isEmpty. Operand 3826 states and 5553 transitions. [2024-12-02 06:18:33,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 779 [2024-12-02 06:18:33,557 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:33,558 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:33,558 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable27 [2024-12-02 06:18:33,558 INFO L396 AbstractCegarLoop]: === Iteration 29 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:33,558 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:33,558 INFO L85 PathProgramCache]: Analyzing trace with hash 803660271, now seen corresponding path program 1 times [2024-12-02 06:18:33,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:33,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554771511] [2024-12-02 06:18:33,559 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:33,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:33,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:34,640 INFO L134 CoverageAnalysis]: Checked inductivity of 343 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2024-12-02 06:18:34,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:34,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554771511] [2024-12-02 06:18:34,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1554771511] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:34,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [717227419] [2024-12-02 06:18:34,641 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:34,641 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:34,641 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:34,642 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:34,645 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2024-12-02 06:18:36,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:36,030 INFO L256 TraceCheckSpWp]: Trace formula consists of 4053 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-12-02 06:18:36,038 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:36,062 INFO L134 CoverageAnalysis]: Checked inductivity of 343 backedges. 200 proven. 2 refuted. 0 times theorem prover too weak. 141 trivial. 0 not checked. [2024-12-02 06:18:36,062 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:36,108 INFO L134 CoverageAnalysis]: Checked inductivity of 343 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 243 trivial. 0 not checked. [2024-12-02 06:18:36,108 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [717227419] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:36,108 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:18:36,108 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:18:36,108 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1571604422] [2024-12-02 06:18:36,108 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:36,109 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:18:36,109 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:36,109 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:18:36,109 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:36,110 INFO L87 Difference]: Start difference. First operand 3826 states and 5553 transitions. Second operand has 3 states, 3 states have (on average 234.33333333333334) internal successors, (703), 3 states have internal predecessors, (703), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:36,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:36,214 INFO L93 Difference]: Finished difference Result 6493 states and 9432 transitions. [2024-12-02 06:18:36,214 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:18:36,215 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 234.33333333333334) internal successors, (703), 3 states have internal predecessors, (703), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 778 [2024-12-02 06:18:36,215 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:36,219 INFO L225 Difference]: With dead ends: 6493 [2024-12-02 06:18:36,219 INFO L226 Difference]: Without dead ends: 3829 [2024-12-02 06:18:36,222 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1558 GetRequests, 1553 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:36,223 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:36,223 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:18:36,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3829 states. [2024-12-02 06:18:36,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3829 to 3829. [2024-12-02 06:18:36,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3829 states, 3773 states have (on average 1.4439438112907501) internal successors, (5448), 3773 states have internal predecessors, (5448), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:18:36,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3829 states to 3829 states and 5556 transitions. [2024-12-02 06:18:36,341 INFO L78 Accepts]: Start accepts. Automaton has 3829 states and 5556 transitions. Word has length 778 [2024-12-02 06:18:36,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:36,342 INFO L471 AbstractCegarLoop]: Abstraction has 3829 states and 5556 transitions. [2024-12-02 06:18:36,342 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 234.33333333333334) internal successors, (703), 3 states have internal predecessors, (703), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:36,342 INFO L276 IsEmpty]: Start isEmpty. Operand 3829 states and 5556 transitions. [2024-12-02 06:18:36,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 781 [2024-12-02 06:18:36,351 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:36,352 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:36,367 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Ended with exit code 0 [2024-12-02 06:18:36,552 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 24 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable28 [2024-12-02 06:18:36,552 INFO L396 AbstractCegarLoop]: === Iteration 30 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:36,553 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:36,553 INFO L85 PathProgramCache]: Analyzing trace with hash 1569839027, now seen corresponding path program 1 times [2024-12-02 06:18:36,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:36,553 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [726420855] [2024-12-02 06:18:36,553 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:36,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:36,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:37,602 INFO L134 CoverageAnalysis]: Checked inductivity of 344 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 243 trivial. 0 not checked. [2024-12-02 06:18:37,602 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:37,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [726420855] [2024-12-02 06:18:37,603 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [726420855] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:37,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [786059067] [2024-12-02 06:18:37,603 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:37,603 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:37,603 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:37,604 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:37,605 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2024-12-02 06:18:39,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:39,088 INFO L256 TraceCheckSpWp]: Trace formula consists of 4062 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-12-02 06:18:39,096 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:39,119 INFO L134 CoverageAnalysis]: Checked inductivity of 344 backedges. 200 proven. 2 refuted. 0 times theorem prover too weak. 142 trivial. 0 not checked. [2024-12-02 06:18:39,119 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:39,166 INFO L134 CoverageAnalysis]: Checked inductivity of 344 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 244 trivial. 0 not checked. [2024-12-02 06:18:39,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [786059067] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:39,166 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:18:39,167 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:18:39,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946376619] [2024-12-02 06:18:39,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:39,168 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:18:39,168 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:39,168 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:18:39,168 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:39,168 INFO L87 Difference]: Start difference. First operand 3829 states and 5556 transitions. Second operand has 3 states, 3 states have (on average 235.0) internal successors, (705), 3 states have internal predecessors, (705), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:39,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:39,232 INFO L93 Difference]: Finished difference Result 6499 states and 9438 transitions. [2024-12-02 06:18:39,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:18:39,232 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 235.0) internal successors, (705), 3 states have internal predecessors, (705), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 780 [2024-12-02 06:18:39,233 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:39,236 INFO L225 Difference]: With dead ends: 6499 [2024-12-02 06:18:39,237 INFO L226 Difference]: Without dead ends: 3832 [2024-12-02 06:18:39,239 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1562 GetRequests, 1557 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:39,240 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:39,240 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:18:39,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3832 states. [2024-12-02 06:18:39,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3832 to 3832. [2024-12-02 06:18:39,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3832 states, 3776 states have (on average 1.4435911016949152) internal successors, (5451), 3776 states have internal predecessors, (5451), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:18:39,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3832 states to 3832 states and 5559 transitions. [2024-12-02 06:18:39,344 INFO L78 Accepts]: Start accepts. Automaton has 3832 states and 5559 transitions. Word has length 780 [2024-12-02 06:18:39,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:39,344 INFO L471 AbstractCegarLoop]: Abstraction has 3832 states and 5559 transitions. [2024-12-02 06:18:39,344 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 235.0) internal successors, (705), 3 states have internal predecessors, (705), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:39,344 INFO L276 IsEmpty]: Start isEmpty. Operand 3832 states and 5559 transitions. [2024-12-02 06:18:39,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 783 [2024-12-02 06:18:39,349 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:39,350 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:39,365 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Ended with exit code 0 [2024-12-02 06:18:39,550 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29,25 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:39,550 INFO L396 AbstractCegarLoop]: === Iteration 31 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:39,552 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:39,552 INFO L85 PathProgramCache]: Analyzing trace with hash -1168636393, now seen corresponding path program 1 times [2024-12-02 06:18:39,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:39,552 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664072240] [2024-12-02 06:18:39,552 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:39,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:39,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:40,521 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 244 trivial. 0 not checked. [2024-12-02 06:18:40,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:40,522 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [664072240] [2024-12-02 06:18:40,522 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [664072240] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:40,522 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1935473560] [2024-12-02 06:18:40,522 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:40,522 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:40,522 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:40,524 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:40,524 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2024-12-02 06:18:42,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:42,187 INFO L256 TraceCheckSpWp]: Trace formula consists of 4071 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-12-02 06:18:42,199 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:42,235 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 200 proven. 2 refuted. 0 times theorem prover too weak. 143 trivial. 0 not checked. [2024-12-02 06:18:42,235 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:42,291 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2024-12-02 06:18:42,291 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1935473560] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:42,291 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:18:42,291 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:18:42,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1279549244] [2024-12-02 06:18:42,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:42,292 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:18:42,292 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:42,293 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:18:42,293 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:42,293 INFO L87 Difference]: Start difference. First operand 3832 states and 5559 transitions. Second operand has 3 states, 3 states have (on average 235.66666666666666) internal successors, (707), 3 states have internal predecessors, (707), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:42,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:42,396 INFO L93 Difference]: Finished difference Result 6505 states and 9444 transitions. [2024-12-02 06:18:42,397 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:18:42,397 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 235.66666666666666) internal successors, (707), 3 states have internal predecessors, (707), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 782 [2024-12-02 06:18:42,398 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:42,402 INFO L225 Difference]: With dead ends: 6505 [2024-12-02 06:18:42,402 INFO L226 Difference]: Without dead ends: 3835 [2024-12-02 06:18:42,404 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1566 GetRequests, 1561 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:42,405 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:42,405 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:18:42,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3835 states. [2024-12-02 06:18:42,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3835 to 3835. [2024-12-02 06:18:42,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3835 states, 3779 states have (on average 1.4432389521037312) internal successors, (5454), 3779 states have internal predecessors, (5454), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:18:42,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3835 states to 3835 states and 5562 transitions. [2024-12-02 06:18:42,526 INFO L78 Accepts]: Start accepts. Automaton has 3835 states and 5562 transitions. Word has length 782 [2024-12-02 06:18:42,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:42,527 INFO L471 AbstractCegarLoop]: Abstraction has 3835 states and 5562 transitions. [2024-12-02 06:18:42,527 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 235.66666666666666) internal successors, (707), 3 states have internal predecessors, (707), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:42,527 INFO L276 IsEmpty]: Start isEmpty. Operand 3835 states and 5562 transitions. [2024-12-02 06:18:42,534 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 785 [2024-12-02 06:18:42,534 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:42,534 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:42,549 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Ended with exit code 0 [2024-12-02 06:18:42,734 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30,26 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:42,735 INFO L396 AbstractCegarLoop]: === Iteration 32 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:42,735 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:42,735 INFO L85 PathProgramCache]: Analyzing trace with hash 1506895131, now seen corresponding path program 1 times [2024-12-02 06:18:42,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:42,735 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1894353333] [2024-12-02 06:18:42,735 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:42,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:43,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:43,658 INFO L134 CoverageAnalysis]: Checked inductivity of 346 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2024-12-02 06:18:43,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:43,658 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1894353333] [2024-12-02 06:18:43,658 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1894353333] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:43,658 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1003048876] [2024-12-02 06:18:43,658 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:43,658 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:43,659 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:43,660 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:43,661 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2024-12-02 06:18:45,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:45,231 INFO L256 TraceCheckSpWp]: Trace formula consists of 4080 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-12-02 06:18:45,238 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:45,266 INFO L134 CoverageAnalysis]: Checked inductivity of 346 backedges. 200 proven. 2 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2024-12-02 06:18:45,266 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:45,315 INFO L134 CoverageAnalysis]: Checked inductivity of 346 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 246 trivial. 0 not checked. [2024-12-02 06:18:45,316 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1003048876] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:45,316 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:18:45,316 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:18:45,316 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1283511194] [2024-12-02 06:18:45,316 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:45,317 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:18:45,317 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:45,318 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:18:45,318 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:45,318 INFO L87 Difference]: Start difference. First operand 3835 states and 5562 transitions. Second operand has 3 states, 3 states have (on average 236.33333333333334) internal successors, (709), 3 states have internal predecessors, (709), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:45,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:45,385 INFO L93 Difference]: Finished difference Result 6511 states and 9450 transitions. [2024-12-02 06:18:45,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:18:45,386 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 236.33333333333334) internal successors, (709), 3 states have internal predecessors, (709), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 784 [2024-12-02 06:18:45,386 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:45,390 INFO L225 Difference]: With dead ends: 6511 [2024-12-02 06:18:45,390 INFO L226 Difference]: Without dead ends: 3838 [2024-12-02 06:18:45,392 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1570 GetRequests, 1565 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:45,393 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:45,393 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:18:45,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3838 states. [2024-12-02 06:18:45,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3838 to 3838. [2024-12-02 06:18:45,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3838 states, 3782 states have (on average 1.4428873611845585) internal successors, (5457), 3782 states have internal predecessors, (5457), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:18:45,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3838 states to 3838 states and 5565 transitions. [2024-12-02 06:18:45,471 INFO L78 Accepts]: Start accepts. Automaton has 3838 states and 5565 transitions. Word has length 784 [2024-12-02 06:18:45,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:45,471 INFO L471 AbstractCegarLoop]: Abstraction has 3838 states and 5565 transitions. [2024-12-02 06:18:45,472 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 236.33333333333334) internal successors, (709), 3 states have internal predecessors, (709), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:45,472 INFO L276 IsEmpty]: Start isEmpty. Operand 3838 states and 5565 transitions. [2024-12-02 06:18:45,478 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 787 [2024-12-02 06:18:45,478 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:45,478 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:45,495 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Ended with exit code 0 [2024-12-02 06:18:45,678 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable31,27 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:45,678 INFO L396 AbstractCegarLoop]: === Iteration 33 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:45,679 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:45,679 INFO L85 PathProgramCache]: Analyzing trace with hash -686297921, now seen corresponding path program 1 times [2024-12-02 06:18:45,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:45,679 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679072367] [2024-12-02 06:18:45,679 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:45,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:46,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:46,538 INFO L134 CoverageAnalysis]: Checked inductivity of 347 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 246 trivial. 0 not checked. [2024-12-02 06:18:46,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:46,538 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1679072367] [2024-12-02 06:18:46,539 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1679072367] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:46,539 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [177242776] [2024-12-02 06:18:46,539 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:46,539 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:46,539 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:46,540 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:46,541 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2024-12-02 06:18:48,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:48,232 INFO L256 TraceCheckSpWp]: Trace formula consists of 4089 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:18:48,239 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:48,262 INFO L134 CoverageAnalysis]: Checked inductivity of 347 backedges. 200 proven. 4 refuted. 0 times theorem prover too weak. 143 trivial. 0 not checked. [2024-12-02 06:18:48,263 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:48,312 INFO L134 CoverageAnalysis]: Checked inductivity of 347 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 247 trivial. 0 not checked. [2024-12-02 06:18:48,312 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [177242776] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:48,312 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:18:48,313 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:18:48,313 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [48864125] [2024-12-02 06:18:48,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:48,313 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:18:48,314 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:48,314 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:18:48,314 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:48,314 INFO L87 Difference]: Start difference. First operand 3838 states and 5565 transitions. Second operand has 3 states, 3 states have (on average 237.0) internal successors, (711), 3 states have internal predecessors, (711), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:48,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:48,380 INFO L93 Difference]: Finished difference Result 6517 states and 9456 transitions. [2024-12-02 06:18:48,380 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:18:48,380 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 237.0) internal successors, (711), 3 states have internal predecessors, (711), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 786 [2024-12-02 06:18:48,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:48,384 INFO L225 Difference]: With dead ends: 6517 [2024-12-02 06:18:48,384 INFO L226 Difference]: Without dead ends: 3841 [2024-12-02 06:18:48,387 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1574 GetRequests, 1569 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:48,387 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:48,387 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:18:48,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3841 states. [2024-12-02 06:18:48,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3841 to 3841. [2024-12-02 06:18:48,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3841 states, 3785 states have (on average 1.4425363276089829) internal successors, (5460), 3785 states have internal predecessors, (5460), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:18:48,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3841 states to 3841 states and 5568 transitions. [2024-12-02 06:18:48,494 INFO L78 Accepts]: Start accepts. Automaton has 3841 states and 5568 transitions. Word has length 786 [2024-12-02 06:18:48,494 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:48,494 INFO L471 AbstractCegarLoop]: Abstraction has 3841 states and 5568 transitions. [2024-12-02 06:18:48,494 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 237.0) internal successors, (711), 3 states have internal predecessors, (711), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:48,494 INFO L276 IsEmpty]: Start isEmpty. Operand 3841 states and 5568 transitions. [2024-12-02 06:18:48,500 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 789 [2024-12-02 06:18:48,500 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:48,500 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:48,517 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Ended with exit code 0 [2024-12-02 06:18:48,701 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable32,28 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:48,701 INFO L396 AbstractCegarLoop]: === Iteration 34 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:48,701 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:48,702 INFO L85 PathProgramCache]: Analyzing trace with hash -1853141277, now seen corresponding path program 1 times [2024-12-02 06:18:48,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:48,702 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026670690] [2024-12-02 06:18:48,702 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:48,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:49,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:49,643 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 247 trivial. 0 not checked. [2024-12-02 06:18:49,643 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:49,643 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1026670690] [2024-12-02 06:18:49,644 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1026670690] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:49,644 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [238283887] [2024-12-02 06:18:49,644 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:49,644 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:49,644 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:49,645 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:49,646 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2024-12-02 06:18:51,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:51,375 INFO L256 TraceCheckSpWp]: Trace formula consists of 4098 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:18:51,383 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:51,403 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 200 proven. 4 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2024-12-02 06:18:51,403 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:51,440 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 248 trivial. 0 not checked. [2024-12-02 06:18:51,440 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [238283887] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:51,440 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:18:51,441 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:18:51,441 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1553476714] [2024-12-02 06:18:51,441 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:51,441 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:18:51,441 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:51,442 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:18:51,442 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:51,442 INFO L87 Difference]: Start difference. First operand 3841 states and 5568 transitions. Second operand has 3 states, 3 states have (on average 237.66666666666666) internal successors, (713), 3 states have internal predecessors, (713), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:51,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:51,508 INFO L93 Difference]: Finished difference Result 6523 states and 9462 transitions. [2024-12-02 06:18:51,508 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:18:51,508 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 237.66666666666666) internal successors, (713), 3 states have internal predecessors, (713), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 788 [2024-12-02 06:18:51,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:51,512 INFO L225 Difference]: With dead ends: 6523 [2024-12-02 06:18:51,512 INFO L226 Difference]: Without dead ends: 3844 [2024-12-02 06:18:51,514 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1578 GetRequests, 1573 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:51,515 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:51,515 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:18:51,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3844 states. [2024-12-02 06:18:51,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3844 to 3844. [2024-12-02 06:18:51,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3844 states, 3788 states have (on average 1.4421858500527982) internal successors, (5463), 3788 states have internal predecessors, (5463), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:18:51,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3844 states to 3844 states and 5571 transitions. [2024-12-02 06:18:51,592 INFO L78 Accepts]: Start accepts. Automaton has 3844 states and 5571 transitions. Word has length 788 [2024-12-02 06:18:51,593 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:51,593 INFO L471 AbstractCegarLoop]: Abstraction has 3844 states and 5571 transitions. [2024-12-02 06:18:51,593 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 237.66666666666666) internal successors, (713), 3 states have internal predecessors, (713), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:51,593 INFO L276 IsEmpty]: Start isEmpty. Operand 3844 states and 5571 transitions. [2024-12-02 06:18:51,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 791 [2024-12-02 06:18:51,599 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:51,599 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:51,614 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Ended with exit code 0 [2024-12-02 06:18:51,799 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable33,29 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:51,799 INFO L396 AbstractCegarLoop]: === Iteration 35 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:51,800 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:51,800 INFO L85 PathProgramCache]: Analyzing trace with hash 72343303, now seen corresponding path program 1 times [2024-12-02 06:18:51,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:51,800 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [950598603] [2024-12-02 06:18:51,800 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:51,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:52,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:52,717 INFO L134 CoverageAnalysis]: Checked inductivity of 349 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 248 trivial. 0 not checked. [2024-12-02 06:18:52,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:52,717 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [950598603] [2024-12-02 06:18:52,718 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [950598603] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:52,718 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1697988208] [2024-12-02 06:18:52,718 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:52,718 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:52,718 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:52,719 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:52,720 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2024-12-02 06:18:54,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:54,463 INFO L256 TraceCheckSpWp]: Trace formula consists of 4107 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:18:54,471 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:54,491 INFO L134 CoverageAnalysis]: Checked inductivity of 349 backedges. 200 proven. 4 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2024-12-02 06:18:54,492 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:54,537 INFO L134 CoverageAnalysis]: Checked inductivity of 349 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2024-12-02 06:18:54,537 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1697988208] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:54,537 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:18:54,538 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:18:54,538 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1646023264] [2024-12-02 06:18:54,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:54,538 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:18:54,539 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:54,539 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:18:54,539 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:54,539 INFO L87 Difference]: Start difference. First operand 3844 states and 5571 transitions. Second operand has 3 states, 3 states have (on average 238.33333333333334) internal successors, (715), 3 states have internal predecessors, (715), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:54,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:54,608 INFO L93 Difference]: Finished difference Result 6529 states and 9468 transitions. [2024-12-02 06:18:54,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:18:54,609 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 238.33333333333334) internal successors, (715), 3 states have internal predecessors, (715), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 790 [2024-12-02 06:18:54,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:54,613 INFO L225 Difference]: With dead ends: 6529 [2024-12-02 06:18:54,613 INFO L226 Difference]: Without dead ends: 3847 [2024-12-02 06:18:54,615 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1582 GetRequests, 1577 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:54,616 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:54,616 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:18:54,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3847 states. [2024-12-02 06:18:54,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3847 to 3847. [2024-12-02 06:18:54,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3847 states, 3791 states have (on average 1.4418359271959904) internal successors, (5466), 3791 states have internal predecessors, (5466), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:18:54,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3847 states to 3847 states and 5574 transitions. [2024-12-02 06:18:54,692 INFO L78 Accepts]: Start accepts. Automaton has 3847 states and 5574 transitions. Word has length 790 [2024-12-02 06:18:54,693 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:54,693 INFO L471 AbstractCegarLoop]: Abstraction has 3847 states and 5574 transitions. [2024-12-02 06:18:54,693 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 238.33333333333334) internal successors, (715), 3 states have internal predecessors, (715), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:54,693 INFO L276 IsEmpty]: Start isEmpty. Operand 3847 states and 5574 transitions. [2024-12-02 06:18:54,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 793 [2024-12-02 06:18:54,699 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:54,700 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:54,721 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Ended with exit code 0 [2024-12-02 06:18:54,900 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 30 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable34 [2024-12-02 06:18:54,900 INFO L396 AbstractCegarLoop]: === Iteration 36 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:54,900 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:54,901 INFO L85 PathProgramCache]: Analyzing trace with hash -984268853, now seen corresponding path program 1 times [2024-12-02 06:18:54,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:54,901 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1360109098] [2024-12-02 06:18:54,901 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:54,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:55,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:56,004 INFO L134 CoverageAnalysis]: Checked inductivity of 350 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2024-12-02 06:18:56,004 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:56,004 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1360109098] [2024-12-02 06:18:56,004 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1360109098] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:56,004 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [568238579] [2024-12-02 06:18:56,005 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:56,005 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:56,005 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:56,006 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:56,007 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2024-12-02 06:18:57,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:57,815 INFO L256 TraceCheckSpWp]: Trace formula consists of 4116 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:18:57,822 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:18:57,840 INFO L134 CoverageAnalysis]: Checked inductivity of 350 backedges. 200 proven. 4 refuted. 0 times theorem prover too weak. 146 trivial. 0 not checked. [2024-12-02 06:18:57,840 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:18:57,883 INFO L134 CoverageAnalysis]: Checked inductivity of 350 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 250 trivial. 0 not checked. [2024-12-02 06:18:57,883 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [568238579] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:57,883 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:18:57,884 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:18:57,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [567751872] [2024-12-02 06:18:57,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:18:57,885 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:18:57,885 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:18:57,886 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:18:57,886 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:57,886 INFO L87 Difference]: Start difference. First operand 3847 states and 5574 transitions. Second operand has 3 states, 3 states have (on average 239.0) internal successors, (717), 3 states have internal predecessors, (717), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:57,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:18:57,955 INFO L93 Difference]: Finished difference Result 6535 states and 9474 transitions. [2024-12-02 06:18:57,955 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:18:57,956 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 239.0) internal successors, (717), 3 states have internal predecessors, (717), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 792 [2024-12-02 06:18:57,956 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:18:57,960 INFO L225 Difference]: With dead ends: 6535 [2024-12-02 06:18:57,960 INFO L226 Difference]: Without dead ends: 3850 [2024-12-02 06:18:57,962 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1586 GetRequests, 1581 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:18:57,962 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:18:57,962 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:18:57,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3850 states. [2024-12-02 06:18:58,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3850 to 3850. [2024-12-02 06:18:58,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3850 states, 3794 states have (on average 1.44148655772272) internal successors, (5469), 3794 states have internal predecessors, (5469), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:18:58,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3850 states to 3850 states and 5577 transitions. [2024-12-02 06:18:58,057 INFO L78 Accepts]: Start accepts. Automaton has 3850 states and 5577 transitions. Word has length 792 [2024-12-02 06:18:58,058 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:18:58,058 INFO L471 AbstractCegarLoop]: Abstraction has 3850 states and 5577 transitions. [2024-12-02 06:18:58,058 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 239.0) internal successors, (717), 3 states have internal predecessors, (717), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:18:58,058 INFO L276 IsEmpty]: Start isEmpty. Operand 3850 states and 5577 transitions. [2024-12-02 06:18:58,063 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 795 [2024-12-02 06:18:58,063 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:18:58,063 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:18:58,080 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Ended with exit code 0 [2024-12-02 06:18:58,264 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 31 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable35 [2024-12-02 06:18:58,264 INFO L396 AbstractCegarLoop]: === Iteration 37 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:18:58,265 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:18:58,265 INFO L85 PathProgramCache]: Analyzing trace with hash -1696765649, now seen corresponding path program 1 times [2024-12-02 06:18:58,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:18:58,265 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427357909] [2024-12-02 06:18:58,265 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:58,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:18:58,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:18:59,149 INFO L134 CoverageAnalysis]: Checked inductivity of 351 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 250 trivial. 0 not checked. [2024-12-02 06:18:59,149 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:18:59,149 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427357909] [2024-12-02 06:18:59,149 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [427357909] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:18:59,149 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [176026541] [2024-12-02 06:18:59,150 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:18:59,150 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:18:59,150 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:18:59,151 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:18:59,153 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2024-12-02 06:19:01,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:01,128 INFO L256 TraceCheckSpWp]: Trace formula consists of 4125 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:19:01,135 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:19:01,158 INFO L134 CoverageAnalysis]: Checked inductivity of 351 backedges. 200 proven. 4 refuted. 0 times theorem prover too weak. 147 trivial. 0 not checked. [2024-12-02 06:19:01,158 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:19:01,192 INFO L134 CoverageAnalysis]: Checked inductivity of 351 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 251 trivial. 0 not checked. [2024-12-02 06:19:01,193 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [176026541] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:01,193 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:19:01,193 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:19:01,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1864125104] [2024-12-02 06:19:01,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:19:01,194 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:19:01,194 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:01,195 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:19:01,195 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:19:01,195 INFO L87 Difference]: Start difference. First operand 3850 states and 5577 transitions. Second operand has 3 states, 3 states have (on average 239.66666666666666) internal successors, (719), 3 states have internal predecessors, (719), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:01,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:01,263 INFO L93 Difference]: Finished difference Result 6541 states and 9480 transitions. [2024-12-02 06:19:01,264 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:19:01,264 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 239.66666666666666) internal successors, (719), 3 states have internal predecessors, (719), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 794 [2024-12-02 06:19:01,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:01,268 INFO L225 Difference]: With dead ends: 6541 [2024-12-02 06:19:01,268 INFO L226 Difference]: Without dead ends: 3853 [2024-12-02 06:19:01,271 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1590 GetRequests, 1585 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:19:01,271 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:01,271 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:19:01,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3853 states. [2024-12-02 06:19:01,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3853 to 3853. [2024-12-02 06:19:01,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3853 states, 3797 states have (on average 1.4411377403213064) internal successors, (5472), 3797 states have internal predecessors, (5472), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:19:01,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3853 states to 3853 states and 5580 transitions. [2024-12-02 06:19:01,351 INFO L78 Accepts]: Start accepts. Automaton has 3853 states and 5580 transitions. Word has length 794 [2024-12-02 06:19:01,351 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:01,351 INFO L471 AbstractCegarLoop]: Abstraction has 3853 states and 5580 transitions. [2024-12-02 06:19:01,351 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 239.66666666666666) internal successors, (719), 3 states have internal predecessors, (719), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:01,351 INFO L276 IsEmpty]: Start isEmpty. Operand 3853 states and 5580 transitions. [2024-12-02 06:19:01,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 797 [2024-12-02 06:19:01,357 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:01,357 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:01,375 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Ended with exit code 0 [2024-12-02 06:19:01,557 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 32 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable36 [2024-12-02 06:19:01,558 INFO L396 AbstractCegarLoop]: === Iteration 38 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:01,558 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:01,558 INFO L85 PathProgramCache]: Analyzing trace with hash -2144578765, now seen corresponding path program 1 times [2024-12-02 06:19:01,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:01,558 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058610638] [2024-12-02 06:19:01,558 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:01,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:01,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:02,458 INFO L134 CoverageAnalysis]: Checked inductivity of 352 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 251 trivial. 0 not checked. [2024-12-02 06:19:02,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:02,458 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2058610638] [2024-12-02 06:19:02,458 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2058610638] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:02,458 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [796505830] [2024-12-02 06:19:02,459 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:02,459 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:02,459 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:19:02,460 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:19:02,461 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2024-12-02 06:19:04,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:04,382 INFO L256 TraceCheckSpWp]: Trace formula consists of 4134 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:19:04,389 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:19:04,410 INFO L134 CoverageAnalysis]: Checked inductivity of 352 backedges. 200 proven. 4 refuted. 0 times theorem prover too weak. 148 trivial. 0 not checked. [2024-12-02 06:19:04,410 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:19:04,449 INFO L134 CoverageAnalysis]: Checked inductivity of 352 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 252 trivial. 0 not checked. [2024-12-02 06:19:04,449 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [796505830] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:04,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:19:04,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:19:04,449 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [437770403] [2024-12-02 06:19:04,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:19:04,450 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:19:04,450 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:04,451 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:19:04,451 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:19:04,451 INFO L87 Difference]: Start difference. First operand 3853 states and 5580 transitions. Second operand has 3 states, 3 states have (on average 240.33333333333334) internal successors, (721), 3 states have internal predecessors, (721), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:04,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:04,524 INFO L93 Difference]: Finished difference Result 6547 states and 9486 transitions. [2024-12-02 06:19:04,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:19:04,525 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 240.33333333333334) internal successors, (721), 3 states have internal predecessors, (721), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 796 [2024-12-02 06:19:04,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:04,529 INFO L225 Difference]: With dead ends: 6547 [2024-12-02 06:19:04,529 INFO L226 Difference]: Without dead ends: 3856 [2024-12-02 06:19:04,531 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1594 GetRequests, 1589 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:19:04,531 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:04,531 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:19:04,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3856 states. [2024-12-02 06:19:04,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3856 to 3856. [2024-12-02 06:19:04,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3856 states, 3800 states have (on average 1.4407894736842106) internal successors, (5475), 3800 states have internal predecessors, (5475), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:19:04,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3856 states to 3856 states and 5583 transitions. [2024-12-02 06:19:04,613 INFO L78 Accepts]: Start accepts. Automaton has 3856 states and 5583 transitions. Word has length 796 [2024-12-02 06:19:04,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:04,613 INFO L471 AbstractCegarLoop]: Abstraction has 3856 states and 5583 transitions. [2024-12-02 06:19:04,614 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 240.33333333333334) internal successors, (721), 3 states have internal predecessors, (721), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:04,614 INFO L276 IsEmpty]: Start isEmpty. Operand 3856 states and 5583 transitions. [2024-12-02 06:19:04,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 799 [2024-12-02 06:19:04,619 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:04,620 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:04,638 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Ended with exit code 0 [2024-12-02 06:19:04,820 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 33 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable37 [2024-12-02 06:19:04,820 INFO L396 AbstractCegarLoop]: === Iteration 39 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:04,821 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:04,821 INFO L85 PathProgramCache]: Analyzing trace with hash 1690138103, now seen corresponding path program 1 times [2024-12-02 06:19:04,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:04,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924976299] [2024-12-02 06:19:04,821 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:04,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:05,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:05,731 INFO L134 CoverageAnalysis]: Checked inductivity of 353 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 252 trivial. 0 not checked. [2024-12-02 06:19:05,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:05,731 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [924976299] [2024-12-02 06:19:05,731 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [924976299] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:05,731 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [173914992] [2024-12-02 06:19:05,731 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:05,731 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:05,731 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:19:05,733 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:19:05,734 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2024-12-02 06:19:07,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:07,716 INFO L256 TraceCheckSpWp]: Trace formula consists of 4143 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:19:07,723 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:19:07,745 INFO L134 CoverageAnalysis]: Checked inductivity of 353 backedges. 200 proven. 4 refuted. 0 times theorem prover too weak. 149 trivial. 0 not checked. [2024-12-02 06:19:07,745 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:19:07,784 INFO L134 CoverageAnalysis]: Checked inductivity of 353 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 253 trivial. 0 not checked. [2024-12-02 06:19:07,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [173914992] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:07,784 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:19:07,785 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:19:07,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1511651218] [2024-12-02 06:19:07,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:19:07,785 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:19:07,785 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:07,786 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:19:07,786 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:19:07,786 INFO L87 Difference]: Start difference. First operand 3856 states and 5583 transitions. Second operand has 3 states, 3 states have (on average 241.0) internal successors, (723), 3 states have internal predecessors, (723), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:07,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:07,858 INFO L93 Difference]: Finished difference Result 6553 states and 9492 transitions. [2024-12-02 06:19:07,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:19:07,859 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 241.0) internal successors, (723), 3 states have internal predecessors, (723), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 798 [2024-12-02 06:19:07,860 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:07,863 INFO L225 Difference]: With dead ends: 6553 [2024-12-02 06:19:07,863 INFO L226 Difference]: Without dead ends: 3859 [2024-12-02 06:19:07,865 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1598 GetRequests, 1593 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:19:07,866 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:07,866 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:19:07,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3859 states. [2024-12-02 06:19:07,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3859 to 3859. [2024-12-02 06:19:07,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3859 states, 3803 states have (on average 1.44044175650802) internal successors, (5478), 3803 states have internal predecessors, (5478), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:19:07,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3859 states to 3859 states and 5586 transitions. [2024-12-02 06:19:07,987 INFO L78 Accepts]: Start accepts. Automaton has 3859 states and 5586 transitions. Word has length 798 [2024-12-02 06:19:07,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:07,987 INFO L471 AbstractCegarLoop]: Abstraction has 3859 states and 5586 transitions. [2024-12-02 06:19:07,987 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 241.0) internal successors, (723), 3 states have internal predecessors, (723), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:07,987 INFO L276 IsEmpty]: Start isEmpty. Operand 3859 states and 5586 transitions. [2024-12-02 06:19:07,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 801 [2024-12-02 06:19:07,992 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:07,993 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:08,010 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Ended with exit code 0 [2024-12-02 06:19:08,193 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 34 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable38 [2024-12-02 06:19:08,193 INFO L396 AbstractCegarLoop]: === Iteration 40 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:08,194 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:08,194 INFO L85 PathProgramCache]: Analyzing trace with hash -123098789, now seen corresponding path program 1 times [2024-12-02 06:19:08,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:08,194 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225274658] [2024-12-02 06:19:08,194 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:08,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:08,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:09,101 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 253 trivial. 0 not checked. [2024-12-02 06:19:09,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:09,101 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225274658] [2024-12-02 06:19:09,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1225274658] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:09,101 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [99754888] [2024-12-02 06:19:09,101 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:09,101 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:09,101 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:19:09,103 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:19:09,104 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2024-12-02 06:19:11,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:11,070 INFO L256 TraceCheckSpWp]: Trace formula consists of 4152 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-12-02 06:19:11,077 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:19:11,098 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 200 proven. 2 refuted. 0 times theorem prover too weak. 152 trivial. 0 not checked. [2024-12-02 06:19:11,099 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:19:11,132 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 254 trivial. 0 not checked. [2024-12-02 06:19:11,133 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [99754888] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:11,133 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:19:11,133 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:19:11,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [35963688] [2024-12-02 06:19:11,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:19:11,133 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:19:11,133 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:11,134 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:19:11,134 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:19:11,134 INFO L87 Difference]: Start difference. First operand 3859 states and 5586 transitions. Second operand has 3 states, 3 states have (on average 241.66666666666666) internal successors, (725), 3 states have internal predecessors, (725), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:11,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:11,240 INFO L93 Difference]: Finished difference Result 6559 states and 9498 transitions. [2024-12-02 06:19:11,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:19:11,240 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 241.66666666666666) internal successors, (725), 3 states have internal predecessors, (725), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 800 [2024-12-02 06:19:11,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:11,244 INFO L225 Difference]: With dead ends: 6559 [2024-12-02 06:19:11,244 INFO L226 Difference]: Without dead ends: 3862 [2024-12-02 06:19:11,245 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1602 GetRequests, 1597 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:19:11,246 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:11,246 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:19:11,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3862 states. [2024-12-02 06:19:11,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3862 to 3862. [2024-12-02 06:19:11,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3862 states, 3806 states have (on average 1.4400945874934314) internal successors, (5481), 3806 states have internal predecessors, (5481), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:19:11,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3862 states to 3862 states and 5589 transitions. [2024-12-02 06:19:11,326 INFO L78 Accepts]: Start accepts. Automaton has 3862 states and 5589 transitions. Word has length 800 [2024-12-02 06:19:11,327 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:11,327 INFO L471 AbstractCegarLoop]: Abstraction has 3862 states and 5589 transitions. [2024-12-02 06:19:11,327 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 241.66666666666666) internal successors, (725), 3 states have internal predecessors, (725), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:11,327 INFO L276 IsEmpty]: Start isEmpty. Operand 3862 states and 5589 transitions. [2024-12-02 06:19:11,332 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 803 [2024-12-02 06:19:11,332 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:11,333 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:11,352 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Ended with exit code 0 [2024-12-02 06:19:11,533 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 35 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable39 [2024-12-02 06:19:11,533 INFO L396 AbstractCegarLoop]: === Iteration 41 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:11,534 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:11,534 INFO L85 PathProgramCache]: Analyzing trace with hash -768983809, now seen corresponding path program 1 times [2024-12-02 06:19:11,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:11,534 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667355021] [2024-12-02 06:19:11,534 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:11,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:11,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:12,434 INFO L134 CoverageAnalysis]: Checked inductivity of 355 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 254 trivial. 0 not checked. [2024-12-02 06:19:12,435 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:12,435 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667355021] [2024-12-02 06:19:12,435 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1667355021] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:12,435 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1309707697] [2024-12-02 06:19:12,435 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:12,435 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:12,435 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:19:12,437 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:19:12,438 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2024-12-02 06:19:14,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:14,548 INFO L256 TraceCheckSpWp]: Trace formula consists of 4161 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:19:14,556 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:19:14,577 INFO L134 CoverageAnalysis]: Checked inductivity of 355 backedges. 200 proven. 4 refuted. 0 times theorem prover too weak. 151 trivial. 0 not checked. [2024-12-02 06:19:14,577 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:19:14,618 INFO L134 CoverageAnalysis]: Checked inductivity of 355 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 255 trivial. 0 not checked. [2024-12-02 06:19:14,618 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1309707697] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:14,618 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:19:14,618 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:19:14,618 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [710587658] [2024-12-02 06:19:14,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:19:14,619 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:19:14,619 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:14,619 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:19:14,619 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:19:14,619 INFO L87 Difference]: Start difference. First operand 3862 states and 5589 transitions. Second operand has 3 states, 3 states have (on average 242.33333333333334) internal successors, (727), 3 states have internal predecessors, (727), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:14,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:14,693 INFO L93 Difference]: Finished difference Result 6565 states and 9504 transitions. [2024-12-02 06:19:14,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:19:14,693 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 242.33333333333334) internal successors, (727), 3 states have internal predecessors, (727), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 802 [2024-12-02 06:19:14,694 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:14,697 INFO L225 Difference]: With dead ends: 6565 [2024-12-02 06:19:14,697 INFO L226 Difference]: Without dead ends: 3865 [2024-12-02 06:19:14,699 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1606 GetRequests, 1601 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:19:14,700 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:14,700 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:19:14,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3865 states. [2024-12-02 06:19:14,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3865 to 3865. [2024-12-02 06:19:14,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3865 states, 3809 states have (on average 1.439747965345235) internal successors, (5484), 3809 states have internal predecessors, (5484), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:19:14,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3865 states to 3865 states and 5592 transitions. [2024-12-02 06:19:14,785 INFO L78 Accepts]: Start accepts. Automaton has 3865 states and 5592 transitions. Word has length 802 [2024-12-02 06:19:14,785 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:14,785 INFO L471 AbstractCegarLoop]: Abstraction has 3865 states and 5592 transitions. [2024-12-02 06:19:14,785 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 242.33333333333334) internal successors, (727), 3 states have internal predecessors, (727), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:14,786 INFO L276 IsEmpty]: Start isEmpty. Operand 3865 states and 5592 transitions. [2024-12-02 06:19:14,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 805 [2024-12-02 06:19:14,791 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:14,792 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:14,811 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Ended with exit code 0 [2024-12-02 06:19:14,992 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable40,36 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:14,992 INFO L396 AbstractCegarLoop]: === Iteration 42 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:14,993 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:14,993 INFO L85 PathProgramCache]: Analyzing trace with hash -184454941, now seen corresponding path program 1 times [2024-12-02 06:19:14,993 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:14,993 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1191540339] [2024-12-02 06:19:14,993 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:14,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:15,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:15,900 INFO L134 CoverageAnalysis]: Checked inductivity of 356 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 255 trivial. 0 not checked. [2024-12-02 06:19:15,901 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:15,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1191540339] [2024-12-02 06:19:15,901 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1191540339] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:15,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1517268593] [2024-12-02 06:19:15,901 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:15,901 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:15,901 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:19:15,903 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:19:15,904 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2024-12-02 06:19:18,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:18,126 INFO L256 TraceCheckSpWp]: Trace formula consists of 4170 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-12-02 06:19:18,134 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:19:18,153 INFO L134 CoverageAnalysis]: Checked inductivity of 356 backedges. 200 proven. 4 refuted. 0 times theorem prover too weak. 152 trivial. 0 not checked. [2024-12-02 06:19:18,154 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:19:18,188 INFO L134 CoverageAnalysis]: Checked inductivity of 356 backedges. 100 proven. 0 refuted. 0 times theorem prover too weak. 256 trivial. 0 not checked. [2024-12-02 06:19:18,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1517268593] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:18,188 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 06:19:18,188 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-12-02 06:19:18,188 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2013069094] [2024-12-02 06:19:18,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:19:18,189 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-12-02 06:19:18,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:18,189 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-12-02 06:19:18,189 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:19:18,189 INFO L87 Difference]: Start difference. First operand 3865 states and 5592 transitions. Second operand has 3 states, 3 states have (on average 243.0) internal successors, (729), 3 states have internal predecessors, (729), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:18,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:18,267 INFO L93 Difference]: Finished difference Result 6571 states and 9510 transitions. [2024-12-02 06:19:18,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-12-02 06:19:18,268 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 243.0) internal successors, (729), 3 states have internal predecessors, (729), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 804 [2024-12-02 06:19:18,268 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:18,272 INFO L225 Difference]: With dead ends: 6571 [2024-12-02 06:19:18,272 INFO L226 Difference]: Without dead ends: 3868 [2024-12-02 06:19:18,275 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1610 GetRequests, 1605 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:19:18,275 INFO L435 NwaCegarLoop]: 1695 mSDtfsCounter, 1 mSDsluCounter, 1691 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 3386 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:18,275 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 3386 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:19:18,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3868 states. [2024-12-02 06:19:18,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3868 to 3868. [2024-12-02 06:19:18,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3868 states, 3812 states have (on average 1.439401888772298) internal successors, (5487), 3812 states have internal predecessors, (5487), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:19:18,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3868 states to 3868 states and 5595 transitions. [2024-12-02 06:19:18,360 INFO L78 Accepts]: Start accepts. Automaton has 3868 states and 5595 transitions. Word has length 804 [2024-12-02 06:19:18,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:18,360 INFO L471 AbstractCegarLoop]: Abstraction has 3868 states and 5595 transitions. [2024-12-02 06:19:18,361 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 243.0) internal successors, (729), 3 states have internal predecessors, (729), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:18,361 INFO L276 IsEmpty]: Start isEmpty. Operand 3868 states and 5595 transitions. [2024-12-02 06:19:18,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 807 [2024-12-02 06:19:18,368 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:18,368 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:18,388 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Ended with exit code 0 [2024-12-02 06:19:18,569 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 37 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable41 [2024-12-02 06:19:18,569 INFO L396 AbstractCegarLoop]: === Iteration 43 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:18,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:18,570 INFO L85 PathProgramCache]: Analyzing trace with hash 594904327, now seen corresponding path program 1 times [2024-12-02 06:19:18,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:18,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17883424] [2024-12-02 06:19:18,570 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:18,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:18,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:19,518 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 256 trivial. 0 not checked. [2024-12-02 06:19:19,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:19,518 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17883424] [2024-12-02 06:19:19,518 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17883424] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:19,518 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1022514177] [2024-12-02 06:19:19,518 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:19,518 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:19,519 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:19:19,520 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:19:19,521 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2024-12-02 06:19:21,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:21,783 INFO L256 TraceCheckSpWp]: Trace formula consists of 4179 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:19:21,790 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:19:21,829 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 200 proven. 7 refuted. 0 times theorem prover too weak. 150 trivial. 0 not checked. [2024-12-02 06:19:21,829 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:19:21,887 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 256 trivial. 0 not checked. [2024-12-02 06:19:21,887 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1022514177] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:19:21,887 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:19:21,888 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:19:21,888 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1505781728] [2024-12-02 06:19:21,888 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:19:21,889 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:19:21,889 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:21,890 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:19:21,890 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:19:21,890 INFO L87 Difference]: Start difference. First operand 3868 states and 5595 transitions. Second operand has 9 states, 9 states have (on average 82.88888888888889) internal successors, (746), 9 states have internal predecessors, (746), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:19:22,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:22,005 INFO L93 Difference]: Finished difference Result 6588 states and 9529 transitions. [2024-12-02 06:19:22,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:19:22,006 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 82.88888888888889) internal successors, (746), 9 states have internal predecessors, (746), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 806 [2024-12-02 06:19:22,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:22,010 INFO L225 Difference]: With dead ends: 6588 [2024-12-02 06:19:22,010 INFO L226 Difference]: Without dead ends: 3882 [2024-12-02 06:19:22,012 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1614 GetRequests, 1607 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:19:22,013 INFO L435 NwaCegarLoop]: 1699 mSDtfsCounter, 14 mSDsluCounter, 8463 mSDsCounter, 0 mSdLazyCounter, 59 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 14 SdHoareTripleChecker+Valid, 10162 SdHoareTripleChecker+Invalid, 60 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 59 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:22,013 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [14 Valid, 10162 Invalid, 60 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 59 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:19:22,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3882 states. [2024-12-02 06:19:22,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3882 to 3874. [2024-12-02 06:19:22,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3874 states, 3818 states have (on average 1.4387113672079623) internal successors, (5493), 3818 states have internal predecessors, (5493), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:19:22,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3874 states to 3874 states and 5601 transitions. [2024-12-02 06:19:22,098 INFO L78 Accepts]: Start accepts. Automaton has 3874 states and 5601 transitions. Word has length 806 [2024-12-02 06:19:22,099 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:22,099 INFO L471 AbstractCegarLoop]: Abstraction has 3874 states and 5601 transitions. [2024-12-02 06:19:22,099 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 82.88888888888889) internal successors, (746), 9 states have internal predecessors, (746), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:19:22,099 INFO L276 IsEmpty]: Start isEmpty. Operand 3874 states and 5601 transitions. [2024-12-02 06:19:22,105 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 809 [2024-12-02 06:19:22,105 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:22,105 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:22,125 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Ended with exit code 0 [2024-12-02 06:19:22,306 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 38 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable42 [2024-12-02 06:19:22,306 INFO L396 AbstractCegarLoop]: === Iteration 44 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:22,306 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:22,307 INFO L85 PathProgramCache]: Analyzing trace with hash 1294770987, now seen corresponding path program 2 times [2024-12-02 06:19:22,307 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:22,307 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139625383] [2024-12-02 06:19:22,307 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:19:22,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:22,524 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:19:22,524 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:19:22,756 INFO L134 CoverageAnalysis]: Checked inductivity of 360 backedges. 96 proven. 0 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2024-12-02 06:19:22,756 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:22,756 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139625383] [2024-12-02 06:19:22,756 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [139625383] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:19:22,756 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:19:22,756 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:19:22,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1329281837] [2024-12-02 06:19:22,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:19:22,757 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:19:22,757 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:22,757 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:19:22,757 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:19:22,757 INFO L87 Difference]: Start difference. First operand 3874 states and 5601 transitions. Second operand has 6 states, 6 states have (on average 121.33333333333333) internal successors, (728), 6 states have internal predecessors, (728), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:24,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:24,337 INFO L93 Difference]: Finished difference Result 8957 states and 12914 transitions. [2024-12-02 06:19:24,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:19:24,338 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 121.33333333333333) internal successors, (728), 6 states have internal predecessors, (728), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 808 [2024-12-02 06:19:24,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:24,342 INFO L225 Difference]: With dead ends: 8957 [2024-12-02 06:19:24,342 INFO L226 Difference]: Without dead ends: 5766 [2024-12-02 06:19:24,345 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:19:24,345 INFO L435 NwaCegarLoop]: 1483 mSDtfsCounter, 1667 mSDsluCounter, 3922 mSDsCounter, 0 mSdLazyCounter, 3058 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1672 SdHoareTripleChecker+Valid, 5405 SdHoareTripleChecker+Invalid, 3058 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 3058 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:24,345 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1672 Valid, 5405 Invalid, 3058 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 3058 Invalid, 0 Unknown, 0 Unchecked, 1.4s Time] [2024-12-02 06:19:24,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5766 states. [2024-12-02 06:19:24,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5766 to 3884. [2024-12-02 06:19:24,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3884 states, 3828 states have (on average 1.4375653082549635) internal successors, (5503), 3828 states have internal predecessors, (5503), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:19:24,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3884 states to 3884 states and 5611 transitions. [2024-12-02 06:19:24,467 INFO L78 Accepts]: Start accepts. Automaton has 3884 states and 5611 transitions. Word has length 808 [2024-12-02 06:19:24,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:24,468 INFO L471 AbstractCegarLoop]: Abstraction has 3884 states and 5611 transitions. [2024-12-02 06:19:24,468 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 121.33333333333333) internal successors, (728), 6 states have internal predecessors, (728), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:24,468 INFO L276 IsEmpty]: Start isEmpty. Operand 3884 states and 5611 transitions. [2024-12-02 06:19:24,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 809 [2024-12-02 06:19:24,473 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:24,473 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:24,474 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable43 [2024-12-02 06:19:24,474 INFO L396 AbstractCegarLoop]: === Iteration 45 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:24,474 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:24,474 INFO L85 PathProgramCache]: Analyzing trace with hash -983286891, now seen corresponding path program 1 times [2024-12-02 06:19:24,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:24,474 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218554944] [2024-12-02 06:19:24,474 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:24,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:24,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:25,470 INFO L134 CoverageAnalysis]: Checked inductivity of 360 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 259 trivial. 0 not checked. [2024-12-02 06:19:25,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:25,470 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1218554944] [2024-12-02 06:19:25,470 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1218554944] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:25,470 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2030319550] [2024-12-02 06:19:25,470 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:25,470 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:25,471 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:19:25,472 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:19:25,473 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2024-12-02 06:19:27,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:27,888 INFO L256 TraceCheckSpWp]: Trace formula consists of 4188 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:19:27,895 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:19:27,925 INFO L134 CoverageAnalysis]: Checked inductivity of 360 backedges. 200 proven. 7 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2024-12-02 06:19:27,925 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:19:27,969 INFO L134 CoverageAnalysis]: Checked inductivity of 360 backedges. 100 proven. 1 refuted. 0 times theorem prover too weak. 259 trivial. 0 not checked. [2024-12-02 06:19:27,969 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2030319550] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:19:27,969 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:19:27,969 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:19:27,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1698246677] [2024-12-02 06:19:27,969 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:19:27,970 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:19:27,970 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:27,970 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:19:27,971 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:19:27,971 INFO L87 Difference]: Start difference. First operand 3884 states and 5611 transitions. Second operand has 9 states, 9 states have (on average 82.88888888888889) internal successors, (746), 9 states have internal predecessors, (746), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:19:28,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:28,098 INFO L93 Difference]: Finished difference Result 6616 states and 9557 transitions. [2024-12-02 06:19:28,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:19:28,098 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 82.88888888888889) internal successors, (746), 9 states have internal predecessors, (746), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 808 [2024-12-02 06:19:28,099 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:28,104 INFO L225 Difference]: With dead ends: 6616 [2024-12-02 06:19:28,104 INFO L226 Difference]: Without dead ends: 3898 [2024-12-02 06:19:28,107 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1618 GetRequests, 1611 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:19:28,107 INFO L435 NwaCegarLoop]: 1699 mSDtfsCounter, 12 mSDsluCounter, 11853 mSDsCounter, 0 mSdLazyCounter, 75 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 12 SdHoareTripleChecker+Valid, 13552 SdHoareTripleChecker+Invalid, 76 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 75 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:28,107 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [12 Valid, 13552 Invalid, 76 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 75 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:19:28,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3898 states. [2024-12-02 06:19:28,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3898 to 3890. [2024-12-02 06:19:28,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3890 states, 3834 states have (on average 1.4368805425143454) internal successors, (5509), 3834 states have internal predecessors, (5509), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:19:28,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3890 states to 3890 states and 5617 transitions. [2024-12-02 06:19:28,254 INFO L78 Accepts]: Start accepts. Automaton has 3890 states and 5617 transitions. Word has length 808 [2024-12-02 06:19:28,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:28,255 INFO L471 AbstractCegarLoop]: Abstraction has 3890 states and 5617 transitions. [2024-12-02 06:19:28,255 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 82.88888888888889) internal successors, (746), 9 states have internal predecessors, (746), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:19:28,255 INFO L276 IsEmpty]: Start isEmpty. Operand 3890 states and 5617 transitions. [2024-12-02 06:19:28,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 811 [2024-12-02 06:19:28,263 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:28,264 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:28,286 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Ended with exit code 0 [2024-12-02 06:19:28,464 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 39 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable44 [2024-12-02 06:19:28,464 INFO L396 AbstractCegarLoop]: === Iteration 46 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:28,465 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:28,465 INFO L85 PathProgramCache]: Analyzing trace with hash 216219929, now seen corresponding path program 2 times [2024-12-02 06:19:28,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:28,465 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765295768] [2024-12-02 06:19:28,466 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:19:28,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:28,712 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:19:28,712 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:19:29,173 INFO L134 CoverageAnalysis]: Checked inductivity of 363 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 351 trivial. 0 not checked. [2024-12-02 06:19:29,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:29,173 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765295768] [2024-12-02 06:19:29,173 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [765295768] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:19:29,173 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:19:29,173 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:19:29,173 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [254628216] [2024-12-02 06:19:29,173 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:19:29,173 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:19:29,173 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:29,174 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:19:29,174 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:19:29,174 INFO L87 Difference]: Start difference. First operand 3890 states and 5617 transitions. Second operand has 5 states, 5 states have (on average 129.8) internal successors, (649), 5 states have internal predecessors, (649), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:19:29,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:29,290 INFO L93 Difference]: Finished difference Result 6704 states and 9682 transitions. [2024-12-02 06:19:29,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:19:29,291 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 129.8) internal successors, (649), 5 states have internal predecessors, (649), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 810 [2024-12-02 06:19:29,291 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:29,296 INFO L225 Difference]: With dead ends: 6704 [2024-12-02 06:19:29,297 INFO L226 Difference]: Without dead ends: 3974 [2024-12-02 06:19:29,299 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:19:29,299 INFO L435 NwaCegarLoop]: 1691 mSDtfsCounter, 10 mSDsluCounter, 5064 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 10 SdHoareTripleChecker+Valid, 6755 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:29,299 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [10 Valid, 6755 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 32 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:19:29,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3974 states. [2024-12-02 06:19:29,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3974 to 3960. [2024-12-02 06:19:29,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3960 states, 3904 states have (on average 1.436219262295082) internal successors, (5607), 3904 states have internal predecessors, (5607), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:19:29,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3960 states to 3960 states and 5715 transitions. [2024-12-02 06:19:29,432 INFO L78 Accepts]: Start accepts. Automaton has 3960 states and 5715 transitions. Word has length 810 [2024-12-02 06:19:29,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:29,433 INFO L471 AbstractCegarLoop]: Abstraction has 3960 states and 5715 transitions. [2024-12-02 06:19:29,433 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 129.8) internal successors, (649), 5 states have internal predecessors, (649), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:19:29,433 INFO L276 IsEmpty]: Start isEmpty. Operand 3960 states and 5715 transitions. [2024-12-02 06:19:29,438 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 812 [2024-12-02 06:19:29,438 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:29,439 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:29,439 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable45 [2024-12-02 06:19:29,439 INFO L396 AbstractCegarLoop]: === Iteration 47 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:29,440 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:29,440 INFO L85 PathProgramCache]: Analyzing trace with hash -720422800, now seen corresponding path program 1 times [2024-12-02 06:19:29,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:29,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631128766] [2024-12-02 06:19:29,440 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:29,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:29,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:30,379 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 101 proven. 1 refuted. 0 times theorem prover too weak. 262 trivial. 0 not checked. [2024-12-02 06:19:30,379 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:30,380 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [631128766] [2024-12-02 06:19:30,380 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [631128766] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:30,380 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1537031124] [2024-12-02 06:19:30,380 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:30,380 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:30,380 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:19:30,382 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:19:30,383 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2024-12-02 06:19:32,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:32,865 INFO L256 TraceCheckSpWp]: Trace formula consists of 4202 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:19:32,932 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:19:32,962 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 201 proven. 7 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2024-12-02 06:19:32,962 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:19:33,013 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 101 proven. 1 refuted. 0 times theorem prover too weak. 262 trivial. 0 not checked. [2024-12-02 06:19:33,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1537031124] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:19:33,013 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:19:33,013 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:19:33,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2041987285] [2024-12-02 06:19:33,013 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:19:33,014 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:19:33,014 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:33,014 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:19:33,014 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:19:33,015 INFO L87 Difference]: Start difference. First operand 3960 states and 5715 transitions. Second operand has 9 states, 9 states have (on average 83.0) internal successors, (747), 9 states have internal predecessors, (747), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:19:33,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:33,127 INFO L93 Difference]: Finished difference Result 6738 states and 9723 transitions. [2024-12-02 06:19:33,128 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:19:33,128 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 83.0) internal successors, (747), 9 states have internal predecessors, (747), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 811 [2024-12-02 06:19:33,129 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:33,132 INFO L225 Difference]: With dead ends: 6738 [2024-12-02 06:19:33,132 INFO L226 Difference]: Without dead ends: 3974 [2024-12-02 06:19:33,135 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1624 GetRequests, 1617 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:19:33,135 INFO L435 NwaCegarLoop]: 1699 mSDtfsCounter, 14 mSDsluCounter, 6768 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 14 SdHoareTripleChecker+Valid, 8467 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:33,135 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [14 Valid, 8467 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:19:33,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3974 states. [2024-12-02 06:19:33,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3974 to 3966. [2024-12-02 06:19:33,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3966 states, 3910 states have (on average 1.4355498721227622) internal successors, (5613), 3910 states have internal predecessors, (5613), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:19:33,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3966 states to 3966 states and 5721 transitions. [2024-12-02 06:19:33,227 INFO L78 Accepts]: Start accepts. Automaton has 3966 states and 5721 transitions. Word has length 811 [2024-12-02 06:19:33,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:33,227 INFO L471 AbstractCegarLoop]: Abstraction has 3966 states and 5721 transitions. [2024-12-02 06:19:33,227 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 83.0) internal successors, (747), 9 states have internal predecessors, (747), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:19:33,227 INFO L276 IsEmpty]: Start isEmpty. Operand 3966 states and 5721 transitions. [2024-12-02 06:19:33,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 814 [2024-12-02 06:19:33,233 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:33,234 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:33,265 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Ended with exit code 0 [2024-12-02 06:19:33,434 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 40 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable46 [2024-12-02 06:19:33,434 INFO L396 AbstractCegarLoop]: === Iteration 48 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:33,435 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:33,435 INFO L85 PathProgramCache]: Analyzing trace with hash 792913364, now seen corresponding path program 2 times [2024-12-02 06:19:33,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:33,435 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799029080] [2024-12-02 06:19:33,435 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:19:33,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:33,647 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:19:33,647 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:19:34,188 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 80 proven. 1 refuted. 0 times theorem prover too weak. 286 trivial. 0 not checked. [2024-12-02 06:19:34,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:34,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799029080] [2024-12-02 06:19:34,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [799029080] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:34,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1033702930] [2024-12-02 06:19:34,188 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:19:34,188 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:34,188 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:19:34,190 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:19:34,190 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2024-12-02 06:19:36,355 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:19:36,355 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:19:36,363 INFO L256 TraceCheckSpWp]: Trace formula consists of 1063 conjuncts, 62 conjuncts are in the unsatisfiable core [2024-12-02 06:19:36,372 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:19:38,083 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 196 proven. 0 refuted. 0 times theorem prover too weak. 171 trivial. 0 not checked. [2024-12-02 06:19:38,083 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:19:38,083 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1033702930] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:19:38,083 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:19:38,083 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [7] total 11 [2024-12-02 06:19:38,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1423230955] [2024-12-02 06:19:38,083 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:19:38,084 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:19:38,084 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:38,084 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:19:38,084 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:19:38,085 INFO L87 Difference]: Start difference. First operand 3966 states and 5721 transitions. Second operand has 6 states, 6 states have (on average 121.83333333333333) internal successors, (731), 6 states have internal predecessors, (731), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:39,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:39,457 INFO L93 Difference]: Finished difference Result 9245 states and 13313 transitions. [2024-12-02 06:19:39,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:19:39,458 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 121.83333333333333) internal successors, (731), 6 states have internal predecessors, (731), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 813 [2024-12-02 06:19:39,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:39,463 INFO L225 Difference]: With dead ends: 9245 [2024-12-02 06:19:39,463 INFO L226 Difference]: Without dead ends: 5849 [2024-12-02 06:19:39,466 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 819 GetRequests, 810 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:19:39,467 INFO L435 NwaCegarLoop]: 1462 mSDtfsCounter, 1640 mSDsluCounter, 2873 mSDsCounter, 0 mSdLazyCounter, 2550 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1645 SdHoareTripleChecker+Valid, 4335 SdHoareTripleChecker+Invalid, 2551 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 2550 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:39,467 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1645 Valid, 4335 Invalid, 2551 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 2550 Invalid, 0 Unknown, 0 Unchecked, 1.2s Time] [2024-12-02 06:19:39,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5849 states. [2024-12-02 06:19:39,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5849 to 4054. [2024-12-02 06:19:39,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4054 states, 3998 states have (on average 1.433966983491746) internal successors, (5733), 3998 states have internal predecessors, (5733), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:19:39,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4054 states to 4054 states and 5841 transitions. [2024-12-02 06:19:39,569 INFO L78 Accepts]: Start accepts. Automaton has 4054 states and 5841 transitions. Word has length 813 [2024-12-02 06:19:39,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:39,569 INFO L471 AbstractCegarLoop]: Abstraction has 4054 states and 5841 transitions. [2024-12-02 06:19:39,570 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 121.83333333333333) internal successors, (731), 6 states have internal predecessors, (731), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:39,570 INFO L276 IsEmpty]: Start isEmpty. Operand 4054 states and 5841 transitions. [2024-12-02 06:19:39,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 816 [2024-12-02 06:19:39,576 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:39,576 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:39,592 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Ended with exit code 0 [2024-12-02 06:19:39,776 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 41 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable47 [2024-12-02 06:19:39,777 INFO L396 AbstractCegarLoop]: === Iteration 49 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:39,777 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:39,777 INFO L85 PathProgramCache]: Analyzing trace with hash -79717106, now seen corresponding path program 1 times [2024-12-02 06:19:39,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:39,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [692345140] [2024-12-02 06:19:39,777 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:39,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:40,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:40,734 INFO L134 CoverageAnalysis]: Checked inductivity of 368 backedges. 102 proven. 1 refuted. 0 times theorem prover too weak. 265 trivial. 0 not checked. [2024-12-02 06:19:40,734 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:40,734 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [692345140] [2024-12-02 06:19:40,735 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [692345140] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:40,735 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1495481272] [2024-12-02 06:19:40,735 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:40,735 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:40,735 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:19:40,736 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:19:40,737 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2024-12-02 06:19:43,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:43,241 INFO L256 TraceCheckSpWp]: Trace formula consists of 4213 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:19:43,248 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:19:43,282 INFO L134 CoverageAnalysis]: Checked inductivity of 368 backedges. 202 proven. 7 refuted. 0 times theorem prover too weak. 159 trivial. 0 not checked. [2024-12-02 06:19:43,282 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:19:43,331 INFO L134 CoverageAnalysis]: Checked inductivity of 368 backedges. 102 proven. 1 refuted. 0 times theorem prover too weak. 265 trivial. 0 not checked. [2024-12-02 06:19:43,331 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1495481272] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:19:43,331 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:19:43,331 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:19:43,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [19125024] [2024-12-02 06:19:43,331 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:19:43,332 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:19:43,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:43,332 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:19:43,332 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:19:43,333 INFO L87 Difference]: Start difference. First operand 4054 states and 5841 transitions. Second operand has 9 states, 9 states have (on average 83.22222222222223) internal successors, (749), 9 states have internal predecessors, (749), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:19:43,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:43,453 INFO L93 Difference]: Finished difference Result 6904 states and 9945 transitions. [2024-12-02 06:19:43,453 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:19:43,453 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 83.22222222222223) internal successors, (749), 9 states have internal predecessors, (749), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 815 [2024-12-02 06:19:43,454 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:43,457 INFO L225 Difference]: With dead ends: 6904 [2024-12-02 06:19:43,457 INFO L226 Difference]: Without dead ends: 4068 [2024-12-02 06:19:43,460 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1632 GetRequests, 1625 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:19:43,460 INFO L435 NwaCegarLoop]: 1699 mSDtfsCounter, 14 mSDsluCounter, 6768 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 14 SdHoareTripleChecker+Valid, 8467 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:43,460 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [14 Valid, 8467 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:19:43,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4068 states. [2024-12-02 06:19:43,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4068 to 4060. [2024-12-02 06:19:43,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4060 states, 4004 states have (on average 1.4333166833166833) internal successors, (5739), 4004 states have internal predecessors, (5739), 54 states have call successors, (54), 1 states have call predecessors, (54), 1 states have return successors, (54), 54 states have call predecessors, (54), 54 states have call successors, (54) [2024-12-02 06:19:43,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4060 states to 4060 states and 5847 transitions. [2024-12-02 06:19:43,591 INFO L78 Accepts]: Start accepts. Automaton has 4060 states and 5847 transitions. Word has length 815 [2024-12-02 06:19:43,592 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:43,592 INFO L471 AbstractCegarLoop]: Abstraction has 4060 states and 5847 transitions. [2024-12-02 06:19:43,592 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 83.22222222222223) internal successors, (749), 9 states have internal predecessors, (749), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:19:43,592 INFO L276 IsEmpty]: Start isEmpty. Operand 4060 states and 5847 transitions. [2024-12-02 06:19:43,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 818 [2024-12-02 06:19:43,598 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:43,598 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:43,621 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Ended with exit code 0 [2024-12-02 06:19:43,799 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 42 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable48 [2024-12-02 06:19:43,799 INFO L396 AbstractCegarLoop]: === Iteration 50 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:43,799 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:43,800 INFO L85 PathProgramCache]: Analyzing trace with hash -1400049078, now seen corresponding path program 2 times [2024-12-02 06:19:43,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:43,800 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671106763] [2024-12-02 06:19:43,800 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:19:43,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:44,008 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:19:44,008 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:19:44,518 INFO L134 CoverageAnalysis]: Checked inductivity of 371 backedges. 80 proven. 1 refuted. 0 times theorem prover too weak. 290 trivial. 0 not checked. [2024-12-02 06:19:44,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:44,518 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671106763] [2024-12-02 06:19:44,518 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1671106763] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:44,518 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1504950140] [2024-12-02 06:19:44,518 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:19:44,518 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:44,518 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:19:44,520 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:19:44,520 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2024-12-02 06:19:46,759 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:19:46,759 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:19:46,766 INFO L256 TraceCheckSpWp]: Trace formula consists of 1064 conjuncts, 14 conjuncts are in the unsatisfiable core [2024-12-02 06:19:46,774 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:19:48,371 INFO L134 CoverageAnalysis]: Checked inductivity of 371 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2024-12-02 06:19:48,371 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:19:48,371 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1504950140] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:19:48,371 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:19:48,372 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [7] total 9 [2024-12-02 06:19:48,372 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [702920766] [2024-12-02 06:19:48,372 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:19:48,372 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:19:48,372 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:48,373 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:19:48,373 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:19:48,373 INFO L87 Difference]: Start difference. First operand 4060 states and 5847 transitions. Second operand has 4 states, 4 states have (on average 181.75) internal successors, (727), 4 states have internal predecessors, (727), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:49,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:49,263 INFO L93 Difference]: Finished difference Result 6092 states and 8770 transitions. [2024-12-02 06:19:49,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:19:49,263 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 181.75) internal successors, (727), 4 states have internal predecessors, (727), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 817 [2024-12-02 06:19:49,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:49,266 INFO L225 Difference]: With dead ends: 6092 [2024-12-02 06:19:49,266 INFO L226 Difference]: Without dead ends: 2612 [2024-12-02 06:19:49,268 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 824 GetRequests, 817 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:19:49,269 INFO L435 NwaCegarLoop]: 1005 mSDtfsCounter, 1052 mSDsluCounter, 1004 mSDsCounter, 0 mSdLazyCounter, 1387 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1052 SdHoareTripleChecker+Valid, 2009 SdHoareTripleChecker+Invalid, 1388 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1387 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:49,269 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1052 Valid, 2009 Invalid, 1388 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1387 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2024-12-02 06:19:49,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2612 states. [2024-12-02 06:19:49,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2612 to 2540. [2024-12-02 06:19:49,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2540 states, 2512 states have (on average 1.4359076433121019) internal successors, (3607), 2512 states have internal predecessors, (3607), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:19:49,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2540 states to 2540 states and 3659 transitions. [2024-12-02 06:19:49,321 INFO L78 Accepts]: Start accepts. Automaton has 2540 states and 3659 transitions. Word has length 817 [2024-12-02 06:19:49,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:49,321 INFO L471 AbstractCegarLoop]: Abstraction has 2540 states and 3659 transitions. [2024-12-02 06:19:49,321 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 181.75) internal successors, (727), 4 states have internal predecessors, (727), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:49,321 INFO L276 IsEmpty]: Start isEmpty. Operand 2540 states and 3659 transitions. [2024-12-02 06:19:49,325 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 818 [2024-12-02 06:19:49,326 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:49,326 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:49,348 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Ended with exit code 0 [2024-12-02 06:19:49,526 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 43 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable49 [2024-12-02 06:19:49,527 INFO L396 AbstractCegarLoop]: === Iteration 51 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:49,527 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:49,527 INFO L85 PathProgramCache]: Analyzing trace with hash -110229294, now seen corresponding path program 1 times [2024-12-02 06:19:49,527 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:49,527 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2067665697] [2024-12-02 06:19:49,527 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:49,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:49,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:50,520 INFO L134 CoverageAnalysis]: Checked inductivity of 371 backedges. 102 proven. 1 refuted. 0 times theorem prover too weak. 268 trivial. 0 not checked. [2024-12-02 06:19:50,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:50,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2067665697] [2024-12-02 06:19:50,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2067665697] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:50,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [109073912] [2024-12-02 06:19:50,520 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:50,520 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:50,521 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:19:50,522 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:19:50,523 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2024-12-02 06:19:53,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:53,234 INFO L256 TraceCheckSpWp]: Trace formula consists of 4222 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:19:53,242 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:19:53,273 INFO L134 CoverageAnalysis]: Checked inductivity of 371 backedges. 202 proven. 7 refuted. 0 times theorem prover too weak. 162 trivial. 0 not checked. [2024-12-02 06:19:53,273 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:19:53,327 INFO L134 CoverageAnalysis]: Checked inductivity of 371 backedges. 102 proven. 1 refuted. 0 times theorem prover too weak. 268 trivial. 0 not checked. [2024-12-02 06:19:53,327 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [109073912] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:19:53,327 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:19:53,327 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:19:53,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288133118] [2024-12-02 06:19:53,328 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:19:53,328 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:19:53,328 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:53,329 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:19:53,329 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:19:53,329 INFO L87 Difference]: Start difference. First operand 2540 states and 3659 transitions. Second operand has 9 states, 9 states have (on average 83.22222222222223) internal successors, (749), 9 states have internal predecessors, (749), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:19:53,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:53,425 INFO L93 Difference]: Finished difference Result 4209 states and 6058 transitions. [2024-12-02 06:19:53,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:19:53,426 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 83.22222222222223) internal successors, (749), 9 states have internal predecessors, (749), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 817 [2024-12-02 06:19:53,426 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:53,429 INFO L225 Difference]: With dead ends: 4209 [2024-12-02 06:19:53,429 INFO L226 Difference]: Without dead ends: 2551 [2024-12-02 06:19:53,430 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1636 GetRequests, 1629 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:19:53,430 INFO L435 NwaCegarLoop]: 1697 mSDtfsCounter, 13 mSDsluCounter, 8453 mSDsCounter, 0 mSdLazyCounter, 57 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 13 SdHoareTripleChecker+Valid, 10150 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 57 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:53,431 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [13 Valid, 10150 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 57 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:19:53,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2551 states. [2024-12-02 06:19:53,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2551 to 2544. [2024-12-02 06:19:53,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2544 states, 2516 states have (on average 1.435214626391097) internal successors, (3611), 2516 states have internal predecessors, (3611), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:19:53,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2544 states to 2544 states and 3663 transitions. [2024-12-02 06:19:53,486 INFO L78 Accepts]: Start accepts. Automaton has 2544 states and 3663 transitions. Word has length 817 [2024-12-02 06:19:53,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:53,486 INFO L471 AbstractCegarLoop]: Abstraction has 2544 states and 3663 transitions. [2024-12-02 06:19:53,486 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 83.22222222222223) internal successors, (749), 9 states have internal predecessors, (749), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:19:53,486 INFO L276 IsEmpty]: Start isEmpty. Operand 2544 states and 3663 transitions. [2024-12-02 06:19:53,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 820 [2024-12-02 06:19:53,491 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:53,491 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:53,514 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Ended with exit code 0 [2024-12-02 06:19:53,692 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable50,44 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:53,692 INFO L396 AbstractCegarLoop]: === Iteration 52 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:53,692 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:53,692 INFO L85 PathProgramCache]: Analyzing trace with hash 197677166, now seen corresponding path program 2 times [2024-12-02 06:19:53,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:53,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984320926] [2024-12-02 06:19:53,692 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:19:53,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:53,906 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:19:53,906 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:19:54,146 INFO L134 CoverageAnalysis]: Checked inductivity of 374 backedges. 97 proven. 0 refuted. 0 times theorem prover too weak. 277 trivial. 0 not checked. [2024-12-02 06:19:54,146 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:54,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [984320926] [2024-12-02 06:19:54,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [984320926] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:19:54,147 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:19:54,147 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:19:54,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [379529821] [2024-12-02 06:19:54,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:19:54,148 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:19:54,148 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:54,148 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:19:54,149 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:19:54,149 INFO L87 Difference]: Start difference. First operand 2544 states and 3663 transitions. Second operand has 6 states, 6 states have (on average 121.66666666666667) internal successors, (730), 6 states have internal predecessors, (730), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:55,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:55,801 INFO L93 Difference]: Finished difference Result 5892 states and 8454 transitions. [2024-12-02 06:19:55,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:19:55,802 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 121.66666666666667) internal successors, (730), 6 states have internal predecessors, (730), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 819 [2024-12-02 06:19:55,802 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:55,805 INFO L225 Difference]: With dead ends: 5892 [2024-12-02 06:19:55,805 INFO L226 Difference]: Without dead ends: 3918 [2024-12-02 06:19:55,807 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:19:55,807 INFO L435 NwaCegarLoop]: 1494 mSDtfsCounter, 1635 mSDsluCounter, 3942 mSDsCounter, 0 mSdLazyCounter, 3121 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1640 SdHoareTripleChecker+Valid, 5436 SdHoareTripleChecker+Invalid, 3122 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 3121 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:55,807 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1640 Valid, 5436 Invalid, 3122 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 3121 Invalid, 0 Unknown, 0 Unchecked, 1.5s Time] [2024-12-02 06:19:55,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3918 states. [2024-12-02 06:19:55,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3918 to 2544. [2024-12-02 06:19:55,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2544 states, 2516 states have (on average 1.435214626391097) internal successors, (3611), 2516 states have internal predecessors, (3611), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:19:55,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2544 states to 2544 states and 3663 transitions. [2024-12-02 06:19:55,871 INFO L78 Accepts]: Start accepts. Automaton has 2544 states and 3663 transitions. Word has length 819 [2024-12-02 06:19:55,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:55,871 INFO L471 AbstractCegarLoop]: Abstraction has 2544 states and 3663 transitions. [2024-12-02 06:19:55,871 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 121.66666666666667) internal successors, (730), 6 states have internal predecessors, (730), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:19:55,871 INFO L276 IsEmpty]: Start isEmpty. Operand 2544 states and 3663 transitions. [2024-12-02 06:19:55,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 822 [2024-12-02 06:19:55,876 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:55,876 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:55,877 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable51 [2024-12-02 06:19:55,877 INFO L396 AbstractCegarLoop]: === Iteration 53 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:19:55,877 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:19:55,877 INFO L85 PathProgramCache]: Analyzing trace with hash -1661105860, now seen corresponding path program 1 times [2024-12-02 06:19:55,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:19:55,877 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [392240893] [2024-12-02 06:19:55,877 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:55,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:19:56,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:56,819 INFO L134 CoverageAnalysis]: Checked inductivity of 375 backedges. 103 proven. 1 refuted. 0 times theorem prover too weak. 271 trivial. 0 not checked. [2024-12-02 06:19:56,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:19:56,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [392240893] [2024-12-02 06:19:56,819 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [392240893] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:19:56,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1667704499] [2024-12-02 06:19:56,819 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:19:56,819 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:19:56,820 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:19:56,821 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:19:56,822 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2024-12-02 06:19:59,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:19:59,636 INFO L256 TraceCheckSpWp]: Trace formula consists of 4233 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:19:59,644 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:19:59,681 INFO L134 CoverageAnalysis]: Checked inductivity of 375 backedges. 203 proven. 17 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2024-12-02 06:19:59,681 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:19:59,738 INFO L134 CoverageAnalysis]: Checked inductivity of 375 backedges. 103 proven. 1 refuted. 0 times theorem prover too weak. 271 trivial. 0 not checked. [2024-12-02 06:19:59,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1667704499] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:19:59,738 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:19:59,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:19:59,739 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1515067807] [2024-12-02 06:19:59,739 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:19:59,740 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:19:59,740 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:19:59,741 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:19:59,741 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:19:59,741 INFO L87 Difference]: Start difference. First operand 2544 states and 3663 transitions. Second operand has 9 states, 9 states have (on average 83.44444444444444) internal successors, (751), 9 states have internal predecessors, (751), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:19:59,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:19:59,850 INFO L93 Difference]: Finished difference Result 4218 states and 6069 transitions. [2024-12-02 06:19:59,850 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:19:59,850 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 83.44444444444444) internal successors, (751), 9 states have internal predecessors, (751), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 821 [2024-12-02 06:19:59,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:19:59,853 INFO L225 Difference]: With dead ends: 4218 [2024-12-02 06:19:59,853 INFO L226 Difference]: Without dead ends: 2556 [2024-12-02 06:19:59,854 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1645 GetRequests, 1637 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:19:59,855 INFO L435 NwaCegarLoop]: 1697 mSDtfsCounter, 15 mSDsluCounter, 8455 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 10152 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:19:59,855 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 10152 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:19:59,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2556 states. [2024-12-02 06:19:59,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2556 to 2556. [2024-12-02 06:19:59,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2556 states, 2528 states have (on average 1.4331487341772151) internal successors, (3623), 2528 states have internal predecessors, (3623), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:19:59,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2556 states to 2556 states and 3675 transitions. [2024-12-02 06:19:59,912 INFO L78 Accepts]: Start accepts. Automaton has 2556 states and 3675 transitions. Word has length 821 [2024-12-02 06:19:59,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:19:59,912 INFO L471 AbstractCegarLoop]: Abstraction has 2556 states and 3675 transitions. [2024-12-02 06:19:59,913 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 83.44444444444444) internal successors, (751), 9 states have internal predecessors, (751), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:19:59,913 INFO L276 IsEmpty]: Start isEmpty. Operand 2556 states and 3675 transitions. [2024-12-02 06:19:59,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 828 [2024-12-02 06:19:59,917 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:19:59,917 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:19:59,939 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Ended with exit code 0 [2024-12-02 06:20:00,117 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 45 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable52 [2024-12-02 06:20:00,117 INFO L396 AbstractCegarLoop]: === Iteration 54 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:20:00,118 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:20:00,118 INFO L85 PathProgramCache]: Analyzing trace with hash -560148952, now seen corresponding path program 2 times [2024-12-02 06:20:00,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:20:00,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747094277] [2024-12-02 06:20:00,119 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:20:00,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:20:00,334 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:20:00,334 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:20:00,668 INFO L134 CoverageAnalysis]: Checked inductivity of 390 backedges. 74 proven. 4 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2024-12-02 06:20:00,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:20:00,668 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [747094277] [2024-12-02 06:20:00,668 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [747094277] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:20:00,668 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [207443820] [2024-12-02 06:20:00,668 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:20:00,668 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:20:00,668 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:20:00,670 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:20:00,671 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2024-12-02 06:20:03,180 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:20:03,180 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:20:03,187 INFO L256 TraceCheckSpWp]: Trace formula consists of 1065 conjuncts, 16 conjuncts are in the unsatisfiable core [2024-12-02 06:20:03,195 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:20:04,924 INFO L134 CoverageAnalysis]: Checked inductivity of 390 backedges. 174 proven. 4 refuted. 0 times theorem prover too weak. 212 trivial. 0 not checked. [2024-12-02 06:20:04,924 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:20:06,917 INFO L134 CoverageAnalysis]: Checked inductivity of 390 backedges. 74 proven. 4 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2024-12-02 06:20:06,918 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [207443820] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:20:06,918 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:20:06,918 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 13 [2024-12-02 06:20:06,918 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [695265486] [2024-12-02 06:20:06,918 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:20:06,919 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2024-12-02 06:20:06,919 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:20:06,920 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-12-02 06:20:06,920 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:20:06,920 INFO L87 Difference]: Start difference. First operand 2556 states and 3675 transitions. Second operand has 13 states, 13 states have (on average 104.3076923076923) internal successors, (1356), 13 states have internal predecessors, (1356), 3 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 3 states have call predecessors, (20), 3 states have call successors, (20) [2024-12-02 06:20:08,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:20:08,669 INFO L93 Difference]: Finished difference Result 4510 states and 6473 transitions. [2024-12-02 06:20:08,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:20:08,669 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 104.3076923076923) internal successors, (1356), 13 states have internal predecessors, (1356), 3 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 3 states have call predecessors, (20), 3 states have call successors, (20) Word has length 827 [2024-12-02 06:20:08,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:20:08,672 INFO L225 Difference]: With dead ends: 4510 [2024-12-02 06:20:08,672 INFO L226 Difference]: Without dead ends: 2568 [2024-12-02 06:20:08,674 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1663 GetRequests, 1648 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=212, Unknown=0, NotChecked=0, Total=272 [2024-12-02 06:20:08,674 INFO L435 NwaCegarLoop]: 1000 mSDtfsCounter, 2108 mSDsluCounter, 3982 mSDsCounter, 0 mSdLazyCounter, 3496 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2108 SdHoareTripleChecker+Valid, 4982 SdHoareTripleChecker+Invalid, 3497 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 3496 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.6s IncrementalHoareTripleChecker+Time [2024-12-02 06:20:08,674 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2108 Valid, 4982 Invalid, 3497 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 3496 Invalid, 0 Unknown, 0 Unchecked, 1.6s Time] [2024-12-02 06:20:08,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2568 states. [2024-12-02 06:20:08,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2568 to 2562. [2024-12-02 06:20:08,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2562 states, 2534 states have (on average 1.4321231254932913) internal successors, (3629), 2534 states have internal predecessors, (3629), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:20:08,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2562 states to 2562 states and 3681 transitions. [2024-12-02 06:20:08,729 INFO L78 Accepts]: Start accepts. Automaton has 2562 states and 3681 transitions. Word has length 827 [2024-12-02 06:20:08,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:20:08,729 INFO L471 AbstractCegarLoop]: Abstraction has 2562 states and 3681 transitions. [2024-12-02 06:20:08,729 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 104.3076923076923) internal successors, (1356), 13 states have internal predecessors, (1356), 3 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 3 states have call predecessors, (20), 3 states have call successors, (20) [2024-12-02 06:20:08,729 INFO L276 IsEmpty]: Start isEmpty. Operand 2562 states and 3681 transitions. [2024-12-02 06:20:08,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 830 [2024-12-02 06:20:08,734 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:20:08,734 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:20:08,751 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Ended with exit code 0 [2024-12-02 06:20:08,935 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 46 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable53 [2024-12-02 06:20:08,935 INFO L396 AbstractCegarLoop]: === Iteration 55 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:20:08,935 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:20:08,935 INFO L85 PathProgramCache]: Analyzing trace with hash -695352586, now seen corresponding path program 1 times [2024-12-02 06:20:08,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:20:08,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1009499041] [2024-12-02 06:20:08,935 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:20:08,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:20:09,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:20:09,909 INFO L134 CoverageAnalysis]: Checked inductivity of 391 backedges. 104 proven. 1 refuted. 0 times theorem prover too weak. 286 trivial. 0 not checked. [2024-12-02 06:20:09,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:20:09,909 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1009499041] [2024-12-02 06:20:09,909 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1009499041] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:20:09,909 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1819201321] [2024-12-02 06:20:09,909 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:20:09,909 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:20:09,909 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:20:09,911 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:20:09,912 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2024-12-02 06:20:12,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:20:12,858 INFO L256 TraceCheckSpWp]: Trace formula consists of 4262 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:20:12,866 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:20:12,895 INFO L134 CoverageAnalysis]: Checked inductivity of 391 backedges. 204 proven. 17 refuted. 0 times theorem prover too weak. 170 trivial. 0 not checked. [2024-12-02 06:20:12,895 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:20:12,937 INFO L134 CoverageAnalysis]: Checked inductivity of 391 backedges. 104 proven. 1 refuted. 0 times theorem prover too weak. 286 trivial. 0 not checked. [2024-12-02 06:20:12,937 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1819201321] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:20:12,937 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:20:12,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:20:12,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [726911258] [2024-12-02 06:20:12,937 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:20:12,938 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:20:12,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:20:12,939 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:20:12,939 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:20:12,939 INFO L87 Difference]: Start difference. First operand 2562 states and 3681 transitions. Second operand has 9 states, 9 states have (on average 83.66666666666667) internal successors, (753), 9 states have internal predecessors, (753), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:20:13,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:20:13,078 INFO L93 Difference]: Finished difference Result 4252 states and 6103 transitions. [2024-12-02 06:20:13,078 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:20:13,078 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 83.66666666666667) internal successors, (753), 9 states have internal predecessors, (753), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 829 [2024-12-02 06:20:13,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:20:13,081 INFO L225 Difference]: With dead ends: 4252 [2024-12-02 06:20:13,081 INFO L226 Difference]: Without dead ends: 2574 [2024-12-02 06:20:13,082 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1661 GetRequests, 1653 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:20:13,083 INFO L435 NwaCegarLoop]: 1697 mSDtfsCounter, 16 mSDsluCounter, 6762 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 16 SdHoareTripleChecker+Valid, 8459 SdHoareTripleChecker+Invalid, 51 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:20:13,083 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [16 Valid, 8459 Invalid, 51 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:20:13,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2574 states. [2024-12-02 06:20:13,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2574 to 2574. [2024-12-02 06:20:13,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2574 states, 2546 states have (on average 1.4300864100549882) internal successors, (3641), 2546 states have internal predecessors, (3641), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:20:13,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2574 states to 2574 states and 3693 transitions. [2024-12-02 06:20:13,150 INFO L78 Accepts]: Start accepts. Automaton has 2574 states and 3693 transitions. Word has length 829 [2024-12-02 06:20:13,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:20:13,150 INFO L471 AbstractCegarLoop]: Abstraction has 2574 states and 3693 transitions. [2024-12-02 06:20:13,150 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 83.66666666666667) internal successors, (753), 9 states have internal predecessors, (753), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:20:13,150 INFO L276 IsEmpty]: Start isEmpty. Operand 2574 states and 3693 transitions. [2024-12-02 06:20:13,154 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 836 [2024-12-02 06:20:13,154 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:20:13,155 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:20:13,178 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Ended with exit code 0 [2024-12-02 06:20:13,355 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 47 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable54 [2024-12-02 06:20:13,356 INFO L396 AbstractCegarLoop]: === Iteration 56 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:20:13,356 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:20:13,356 INFO L85 PathProgramCache]: Analyzing trace with hash 1315002570, now seen corresponding path program 2 times [2024-12-02 06:20:13,356 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:20:13,357 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186893492] [2024-12-02 06:20:13,357 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:20:13,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:20:13,557 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:20:13,557 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:20:14,117 INFO L134 CoverageAnalysis]: Checked inductivity of 406 backedges. 81 proven. 1 refuted. 0 times theorem prover too weak. 324 trivial. 0 not checked. [2024-12-02 06:20:14,117 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:20:14,117 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186893492] [2024-12-02 06:20:14,117 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186893492] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:20:14,118 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1712267359] [2024-12-02 06:20:14,118 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:20:14,118 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:20:14,118 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:20:14,119 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:20:14,120 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2024-12-02 06:20:16,741 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:20:16,741 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:20:16,748 INFO L256 TraceCheckSpWp]: Trace formula consists of 1066 conjuncts, 34 conjuncts are in the unsatisfiable core [2024-12-02 06:20:16,756 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:20:18,564 INFO L134 CoverageAnalysis]: Checked inductivity of 406 backedges. 2 proven. 77 refuted. 0 times theorem prover too weak. 327 trivial. 0 not checked. [2024-12-02 06:20:18,564 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:20:19,928 INFO L134 CoverageAnalysis]: Checked inductivity of 406 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 393 trivial. 0 not checked. [2024-12-02 06:20:19,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1712267359] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:20:19,928 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:20:19,929 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 11, 10] total 24 [2024-12-02 06:20:19,929 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1237606929] [2024-12-02 06:20:19,929 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:20:19,930 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 24 states [2024-12-02 06:20:19,930 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:20:19,932 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2024-12-02 06:20:19,932 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=479, Unknown=0, NotChecked=0, Total=552 [2024-12-02 06:20:19,933 INFO L87 Difference]: Start difference. First operand 2574 states and 3693 transitions. Second operand has 24 states, 24 states have (on average 86.25) internal successors, (2070), 24 states have internal predecessors, (2070), 5 states have call successors, (25), 1 states have call predecessors, (25), 1 states have return successors, (25), 5 states have call predecessors, (25), 5 states have call successors, (25) [2024-12-02 06:20:24,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:20:24,740 INFO L93 Difference]: Finished difference Result 4618 states and 6605 transitions. [2024-12-02 06:20:24,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-12-02 06:20:24,741 INFO L78 Accepts]: Start accepts. Automaton has has 24 states, 24 states have (on average 86.25) internal successors, (2070), 24 states have internal predecessors, (2070), 5 states have call successors, (25), 1 states have call predecessors, (25), 1 states have return successors, (25), 5 states have call predecessors, (25), 5 states have call successors, (25) Word has length 835 [2024-12-02 06:20:24,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:20:24,743 INFO L225 Difference]: With dead ends: 4618 [2024-12-02 06:20:24,743 INFO L226 Difference]: Without dead ends: 2638 [2024-12-02 06:20:24,744 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1687 GetRequests, 1653 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 231 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=165, Invalid=1095, Unknown=0, NotChecked=0, Total=1260 [2024-12-02 06:20:24,744 INFO L435 NwaCegarLoop]: 989 mSDtfsCounter, 3215 mSDsluCounter, 15710 mSDsCounter, 0 mSdLazyCounter, 12119 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3215 SdHoareTripleChecker+Valid, 16699 SdHoareTripleChecker+Invalid, 12124 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 12119 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 4.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:20:24,744 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3215 Valid, 16699 Invalid, 12124 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 12119 Invalid, 0 Unknown, 0 Unchecked, 4.5s Time] [2024-12-02 06:20:24,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2638 states. [2024-12-02 06:20:24,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2638 to 2606. [2024-12-02 06:20:24,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2606 states, 2578 states have (on average 1.4278510473235067) internal successors, (3681), 2578 states have internal predecessors, (3681), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:20:24,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2606 states to 2606 states and 3733 transitions. [2024-12-02 06:20:24,797 INFO L78 Accepts]: Start accepts. Automaton has 2606 states and 3733 transitions. Word has length 835 [2024-12-02 06:20:24,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:20:24,798 INFO L471 AbstractCegarLoop]: Abstraction has 2606 states and 3733 transitions. [2024-12-02 06:20:24,798 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 24 states, 24 states have (on average 86.25) internal successors, (2070), 24 states have internal predecessors, (2070), 5 states have call successors, (25), 1 states have call predecessors, (25), 1 states have return successors, (25), 5 states have call predecessors, (25), 5 states have call successors, (25) [2024-12-02 06:20:24,798 INFO L276 IsEmpty]: Start isEmpty. Operand 2606 states and 3733 transitions. [2024-12-02 06:20:24,802 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 837 [2024-12-02 06:20:24,803 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:20:24,803 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:20:24,821 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Ended with exit code 0 [2024-12-02 06:20:25,003 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable55,48 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:20:25,003 INFO L396 AbstractCegarLoop]: === Iteration 57 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:20:25,004 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:20:25,004 INFO L85 PathProgramCache]: Analyzing trace with hash -1559229570, now seen corresponding path program 1 times [2024-12-02 06:20:25,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:20:25,004 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094427165] [2024-12-02 06:20:25,004 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:20:25,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:20:25,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:20:25,974 INFO L134 CoverageAnalysis]: Checked inductivity of 406 backedges. 104 proven. 1 refuted. 0 times theorem prover too weak. 301 trivial. 0 not checked. [2024-12-02 06:20:25,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:20:25,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1094427165] [2024-12-02 06:20:25,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1094427165] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:20:25,975 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2034620472] [2024-12-02 06:20:25,975 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:20:25,975 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:20:25,975 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:20:25,976 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:20:25,977 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2024-12-02 06:20:28,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:20:28,962 INFO L256 TraceCheckSpWp]: Trace formula consists of 4290 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:20:28,970 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:20:28,999 INFO L134 CoverageAnalysis]: Checked inductivity of 406 backedges. 204 proven. 17 refuted. 0 times theorem prover too weak. 185 trivial. 0 not checked. [2024-12-02 06:20:28,999 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:20:29,051 INFO L134 CoverageAnalysis]: Checked inductivity of 406 backedges. 104 proven. 1 refuted. 0 times theorem prover too weak. 301 trivial. 0 not checked. [2024-12-02 06:20:29,051 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2034620472] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:20:29,051 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:20:29,052 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:20:29,052 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [664737902] [2024-12-02 06:20:29,052 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:20:29,053 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:20:29,053 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:20:29,054 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:20:29,054 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:20:29,054 INFO L87 Difference]: Start difference. First operand 2606 states and 3733 transitions. Second operand has 9 states, 9 states have (on average 83.77777777777777) internal successors, (754), 9 states have internal predecessors, (754), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:20:29,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:20:29,162 INFO L93 Difference]: Finished difference Result 4334 states and 6199 transitions. [2024-12-02 06:20:29,163 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:20:29,163 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 83.77777777777777) internal successors, (754), 9 states have internal predecessors, (754), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 836 [2024-12-02 06:20:29,163 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:20:29,166 INFO L225 Difference]: With dead ends: 4334 [2024-12-02 06:20:29,166 INFO L226 Difference]: Without dead ends: 2618 [2024-12-02 06:20:29,167 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1675 GetRequests, 1667 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:20:29,167 INFO L435 NwaCegarLoop]: 1697 mSDtfsCounter, 16 mSDsluCounter, 6762 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 16 SdHoareTripleChecker+Valid, 8459 SdHoareTripleChecker+Invalid, 51 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:20:29,168 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [16 Valid, 8459 Invalid, 51 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:20:29,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2618 states. [2024-12-02 06:20:29,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2618 to 2618. [2024-12-02 06:20:29,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2618 states, 2590 states have (on average 1.425868725868726) internal successors, (3693), 2590 states have internal predecessors, (3693), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:20:29,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2618 states to 2618 states and 3745 transitions. [2024-12-02 06:20:29,228 INFO L78 Accepts]: Start accepts. Automaton has 2618 states and 3745 transitions. Word has length 836 [2024-12-02 06:20:29,228 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:20:29,228 INFO L471 AbstractCegarLoop]: Abstraction has 2618 states and 3745 transitions. [2024-12-02 06:20:29,229 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 83.77777777777777) internal successors, (754), 9 states have internal predecessors, (754), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:20:29,229 INFO L276 IsEmpty]: Start isEmpty. Operand 2618 states and 3745 transitions. [2024-12-02 06:20:29,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 843 [2024-12-02 06:20:29,233 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:20:29,233 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:20:29,258 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Ended with exit code 0 [2024-12-02 06:20:29,434 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 49 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable56 [2024-12-02 06:20:29,434 INFO L396 AbstractCegarLoop]: === Iteration 58 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:20:29,434 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:20:29,435 INFO L85 PathProgramCache]: Analyzing trace with hash -512250870, now seen corresponding path program 2 times [2024-12-02 06:20:29,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:20:29,435 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1704741512] [2024-12-02 06:20:29,435 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:20:29,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:20:29,670 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:20:29,671 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:20:31,070 INFO L134 CoverageAnalysis]: Checked inductivity of 421 backedges. 4 proven. 22 refuted. 0 times theorem prover too weak. 395 trivial. 0 not checked. [2024-12-02 06:20:31,070 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:20:31,070 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1704741512] [2024-12-02 06:20:31,070 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1704741512] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:20:31,070 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1215099622] [2024-12-02 06:20:31,070 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:20:31,070 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:20:31,070 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:20:31,072 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:20:31,072 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2024-12-02 06:20:33,866 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:20:33,866 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:20:33,874 INFO L256 TraceCheckSpWp]: Trace formula consists of 1067 conjuncts, 74 conjuncts are in the unsatisfiable core [2024-12-02 06:20:33,884 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:20:39,106 INFO L134 CoverageAnalysis]: Checked inductivity of 421 backedges. 72 proven. 22 refuted. 0 times theorem prover too weak. 327 trivial. 0 not checked. [2024-12-02 06:20:39,106 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:20:47,039 INFO L134 CoverageAnalysis]: Checked inductivity of 421 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 395 trivial. 0 not checked. [2024-12-02 06:20:47,039 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1215099622] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:20:47,039 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:20:47,040 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 16, 15] total 37 [2024-12-02 06:20:47,040 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1031276155] [2024-12-02 06:20:47,040 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:20:47,041 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2024-12-02 06:20:47,041 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:20:47,043 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2024-12-02 06:20:47,043 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=187, Invalid=1145, Unknown=0, NotChecked=0, Total=1332 [2024-12-02 06:20:47,043 INFO L87 Difference]: Start difference. First operand 2618 states and 3745 transitions. Second operand has 37 states, 37 states have (on average 55.32432432432432) internal successors, (2047), 37 states have internal predecessors, (2047), 4 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 4 states have call predecessors, (20), 4 states have call successors, (20) [2024-12-02 06:20:56,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:20:56,546 INFO L93 Difference]: Finished difference Result 6356 states and 9050 transitions. [2024-12-02 06:20:56,546 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2024-12-02 06:20:56,546 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 55.32432432432432) internal successors, (2047), 37 states have internal predecessors, (2047), 4 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 4 states have call predecessors, (20), 4 states have call successors, (20) Word has length 842 [2024-12-02 06:20:56,547 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:20:56,551 INFO L225 Difference]: With dead ends: 6356 [2024-12-02 06:20:56,551 INFO L226 Difference]: Without dead ends: 4628 [2024-12-02 06:20:56,553 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1718 GetRequests, 1657 SyntacticMatches, 1 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 965 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=528, Invalid=3254, Unknown=0, NotChecked=0, Total=3782 [2024-12-02 06:20:56,554 INFO L435 NwaCegarLoop]: 920 mSDtfsCounter, 5290 mSDsluCounter, 19099 mSDsCounter, 0 mSdLazyCounter, 17527 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 7.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5290 SdHoareTripleChecker+Valid, 20019 SdHoareTripleChecker+Invalid, 17542 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 17527 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 8.6s IncrementalHoareTripleChecker+Time [2024-12-02 06:20:56,554 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [5290 Valid, 20019 Invalid, 17542 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [15 Valid, 17527 Invalid, 0 Unknown, 0 Unchecked, 8.6s Time] [2024-12-02 06:20:56,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4628 states. [2024-12-02 06:20:56,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4628 to 2626. [2024-12-02 06:20:56,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2626 states, 2598 states have (on average 1.4253271747498075) internal successors, (3703), 2598 states have internal predecessors, (3703), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:20:56,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2626 states to 2626 states and 3755 transitions. [2024-12-02 06:20:56,632 INFO L78 Accepts]: Start accepts. Automaton has 2626 states and 3755 transitions. Word has length 842 [2024-12-02 06:20:56,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:20:56,633 INFO L471 AbstractCegarLoop]: Abstraction has 2626 states and 3755 transitions. [2024-12-02 06:20:56,633 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 55.32432432432432) internal successors, (2047), 37 states have internal predecessors, (2047), 4 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 4 states have call predecessors, (20), 4 states have call successors, (20) [2024-12-02 06:20:56,633 INFO L276 IsEmpty]: Start isEmpty. Operand 2626 states and 3755 transitions. [2024-12-02 06:20:56,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 843 [2024-12-02 06:20:56,638 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:20:56,638 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:20:56,656 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Ended with exit code 0 [2024-12-02 06:20:56,838 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 50 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable57 [2024-12-02 06:20:56,838 INFO L396 AbstractCegarLoop]: === Iteration 59 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:20:56,839 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:20:56,839 INFO L85 PathProgramCache]: Analyzing trace with hash -191677068, now seen corresponding path program 1 times [2024-12-02 06:20:56,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:20:56,839 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1181338953] [2024-12-02 06:20:56,839 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:20:56,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:20:57,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:20:57,850 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 103 proven. 1 refuted. 0 times theorem prover too weak. 316 trivial. 0 not checked. [2024-12-02 06:20:57,850 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:20:57,850 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1181338953] [2024-12-02 06:20:57,850 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1181338953] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:20:57,850 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [613326723] [2024-12-02 06:20:57,850 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:20:57,850 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:20:57,850 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:20:57,852 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:20:57,853 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2024-12-02 06:21:00,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:21:00,933 INFO L256 TraceCheckSpWp]: Trace formula consists of 4317 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:21:00,941 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:21:00,973 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 203 proven. 17 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2024-12-02 06:21:00,973 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:21:01,026 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 103 proven. 1 refuted. 0 times theorem prover too weak. 316 trivial. 0 not checked. [2024-12-02 06:21:01,026 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [613326723] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:21:01,026 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:21:01,026 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:21:01,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1317840552] [2024-12-02 06:21:01,026 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:21:01,027 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:21:01,027 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:21:01,027 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:21:01,027 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:21:01,028 INFO L87 Difference]: Start difference. First operand 2626 states and 3755 transitions. Second operand has 9 states, 9 states have (on average 83.77777777777777) internal successors, (754), 9 states have internal predecessors, (754), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:21:01,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:21:01,148 INFO L93 Difference]: Finished difference Result 4374 states and 6243 transitions. [2024-12-02 06:21:01,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:21:01,149 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 83.77777777777777) internal successors, (754), 9 states have internal predecessors, (754), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 842 [2024-12-02 06:21:01,149 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:21:01,152 INFO L225 Difference]: With dead ends: 4374 [2024-12-02 06:21:01,152 INFO L226 Difference]: Without dead ends: 2638 [2024-12-02 06:21:01,153 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1687 GetRequests, 1679 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:21:01,153 INFO L435 NwaCegarLoop]: 1697 mSDtfsCounter, 14 mSDsluCounter, 10148 mSDsCounter, 0 mSdLazyCounter, 64 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 14 SdHoareTripleChecker+Valid, 11845 SdHoareTripleChecker+Invalid, 66 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 64 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:21:01,154 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [14 Valid, 11845 Invalid, 66 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 64 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:21:01,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2638 states. [2024-12-02 06:21:01,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2638 to 2638. [2024-12-02 06:21:01,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2638 states, 2610 states have (on average 1.4233716475095786) internal successors, (3715), 2610 states have internal predecessors, (3715), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:21:01,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2638 states to 2638 states and 3767 transitions. [2024-12-02 06:21:01,248 INFO L78 Accepts]: Start accepts. Automaton has 2638 states and 3767 transitions. Word has length 842 [2024-12-02 06:21:01,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:21:01,248 INFO L471 AbstractCegarLoop]: Abstraction has 2638 states and 3767 transitions. [2024-12-02 06:21:01,249 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 83.77777777777777) internal successors, (754), 9 states have internal predecessors, (754), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:21:01,249 INFO L276 IsEmpty]: Start isEmpty. Operand 2638 states and 3767 transitions. [2024-12-02 06:21:01,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 849 [2024-12-02 06:21:01,253 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:21:01,253 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:21:01,278 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Ended with exit code 0 [2024-12-02 06:21:01,453 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 51 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable58 [2024-12-02 06:21:01,454 INFO L396 AbstractCegarLoop]: === Iteration 60 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:21:01,455 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:21:01,455 INFO L85 PathProgramCache]: Analyzing trace with hash 288215520, now seen corresponding path program 2 times [2024-12-02 06:21:01,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:21:01,456 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065596699] [2024-12-02 06:21:01,456 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:21:01,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:21:01,641 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-12-02 06:21:01,641 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:21:01,836 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 413 trivial. 0 not checked. [2024-12-02 06:21:01,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:21:01,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2065596699] [2024-12-02 06:21:01,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2065596699] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:21:01,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:21:01,837 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:21:01,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1086716286] [2024-12-02 06:21:01,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:21:01,837 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:21:01,837 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:21:01,838 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:21:01,838 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:21:01,838 INFO L87 Difference]: Start difference. First operand 2638 states and 3767 transitions. Second operand has 5 states, 5 states have (on average 132.8) internal successors, (664), 5 states have internal predecessors, (664), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:21:01,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:21:01,950 INFO L93 Difference]: Finished difference Result 4486 states and 6399 transitions. [2024-12-02 06:21:01,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:21:01,951 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 132.8) internal successors, (664), 5 states have internal predecessors, (664), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 848 [2024-12-02 06:21:01,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:21:01,955 INFO L225 Difference]: With dead ends: 4486 [2024-12-02 06:21:01,955 INFO L226 Difference]: Without dead ends: 2710 [2024-12-02 06:21:01,956 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:21:01,956 INFO L435 NwaCegarLoop]: 1692 mSDtfsCounter, 16 mSDsluCounter, 5064 mSDsCounter, 0 mSdLazyCounter, 23 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 16 SdHoareTripleChecker+Valid, 6756 SdHoareTripleChecker+Invalid, 23 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 23 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:21:01,956 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [16 Valid, 6756 Invalid, 23 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 23 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:21:01,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2710 states. [2024-12-02 06:21:02,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2710 to 2710. [2024-12-02 06:21:02,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2710 states, 2682 states have (on average 1.4239373601789709) internal successors, (3819), 2682 states have internal predecessors, (3819), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:21:02,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2710 states to 2710 states and 3871 transitions. [2024-12-02 06:21:02,020 INFO L78 Accepts]: Start accepts. Automaton has 2710 states and 3871 transitions. Word has length 848 [2024-12-02 06:21:02,020 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:21:02,020 INFO L471 AbstractCegarLoop]: Abstraction has 2710 states and 3871 transitions. [2024-12-02 06:21:02,021 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 132.8) internal successors, (664), 5 states have internal predecessors, (664), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:21:02,021 INFO L276 IsEmpty]: Start isEmpty. Operand 2710 states and 3871 transitions. [2024-12-02 06:21:02,025 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 850 [2024-12-02 06:21:02,025 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:21:02,026 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:21:02,026 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable59 [2024-12-02 06:21:02,026 INFO L396 AbstractCegarLoop]: === Iteration 61 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:21:02,026 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:21:02,026 INFO L85 PathProgramCache]: Analyzing trace with hash 561440369, now seen corresponding path program 1 times [2024-12-02 06:21:02,026 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:21:02,026 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [569236623] [2024-12-02 06:21:02,026 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:21:02,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:21:02,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:21:03,079 INFO L134 CoverageAnalysis]: Checked inductivity of 436 backedges. 104 proven. 1 refuted. 0 times theorem prover too weak. 331 trivial. 0 not checked. [2024-12-02 06:21:03,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:21:03,079 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [569236623] [2024-12-02 06:21:03,079 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [569236623] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:21:03,079 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1583564553] [2024-12-02 06:21:03,079 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:21:03,080 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:21:03,080 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:21:03,081 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:21:03,082 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2024-12-02 06:21:06,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:21:06,456 INFO L256 TraceCheckSpWp]: Trace formula consists of 4345 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:21:06,465 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:21:06,495 INFO L134 CoverageAnalysis]: Checked inductivity of 436 backedges. 204 proven. 17 refuted. 0 times theorem prover too weak. 215 trivial. 0 not checked. [2024-12-02 06:21:06,495 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:21:06,541 INFO L134 CoverageAnalysis]: Checked inductivity of 436 backedges. 104 proven. 1 refuted. 0 times theorem prover too weak. 331 trivial. 0 not checked. [2024-12-02 06:21:06,542 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1583564553] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:21:06,542 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:21:06,542 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:21:06,542 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1600109794] [2024-12-02 06:21:06,542 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:21:06,543 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:21:06,543 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:21:06,544 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:21:06,544 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:21:06,544 INFO L87 Difference]: Start difference. First operand 2710 states and 3871 transitions. Second operand has 9 states, 9 states have (on average 83.88888888888889) internal successors, (755), 9 states have internal predecessors, (755), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:21:06,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:21:06,663 INFO L93 Difference]: Finished difference Result 4506 states and 6423 transitions. [2024-12-02 06:21:06,664 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:21:06,664 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 83.88888888888889) internal successors, (755), 9 states have internal predecessors, (755), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 849 [2024-12-02 06:21:06,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:21:06,668 INFO L225 Difference]: With dead ends: 4506 [2024-12-02 06:21:06,668 INFO L226 Difference]: Without dead ends: 2722 [2024-12-02 06:21:06,669 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1701 GetRequests, 1693 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:21:06,669 INFO L435 NwaCegarLoop]: 1697 mSDtfsCounter, 15 mSDsluCounter, 8455 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 10152 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:21:06,669 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 10152 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:21:06,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2722 states. [2024-12-02 06:21:06,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2722 to 2722. [2024-12-02 06:21:06,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2722 states, 2694 states have (on average 1.4220489977728286) internal successors, (3831), 2694 states have internal predecessors, (3831), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:21:06,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2722 states to 2722 states and 3883 transitions. [2024-12-02 06:21:06,731 INFO L78 Accepts]: Start accepts. Automaton has 2722 states and 3883 transitions. Word has length 849 [2024-12-02 06:21:06,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:21:06,731 INFO L471 AbstractCegarLoop]: Abstraction has 2722 states and 3883 transitions. [2024-12-02 06:21:06,731 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 83.88888888888889) internal successors, (755), 9 states have internal predecessors, (755), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:21:06,732 INFO L276 IsEmpty]: Start isEmpty. Operand 2722 states and 3883 transitions. [2024-12-02 06:21:06,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 856 [2024-12-02 06:21:06,736 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:21:06,736 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:21:06,760 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Ended with exit code 0 [2024-12-02 06:21:06,936 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable60,52 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:21:06,936 INFO L396 AbstractCegarLoop]: === Iteration 62 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:21:06,937 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:21:06,937 INFO L85 PathProgramCache]: Analyzing trace with hash -101828699, now seen corresponding path program 2 times [2024-12-02 06:21:06,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:21:06,937 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1193809882] [2024-12-02 06:21:06,938 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:21:06,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:21:07,421 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:21:07,421 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:21:08,669 INFO L134 CoverageAnalysis]: Checked inductivity of 451 backedges. 104 proven. 0 refuted. 0 times theorem prover too weak. 347 trivial. 0 not checked. [2024-12-02 06:21:08,669 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:21:08,670 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1193809882] [2024-12-02 06:21:08,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1193809882] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:21:08,670 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:21:08,670 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:21:08,670 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [958936966] [2024-12-02 06:21:08,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:21:08,670 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:21:08,671 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:21:08,671 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:21:08,671 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:21:08,671 INFO L87 Difference]: Start difference. First operand 2722 states and 3883 transitions. Second operand has 4 states, 4 states have (on average 185.0) internal successors, (740), 4 states have internal predecessors, (740), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:21:08,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:21:08,927 INFO L93 Difference]: Finished difference Result 4518 states and 6429 transitions. [2024-12-02 06:21:08,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:21:08,928 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 185.0) internal successors, (740), 4 states have internal predecessors, (740), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 855 [2024-12-02 06:21:08,928 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:21:08,931 INFO L225 Difference]: With dead ends: 4518 [2024-12-02 06:21:08,931 INFO L226 Difference]: Without dead ends: 2722 [2024-12-02 06:21:08,932 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:21:08,933 INFO L435 NwaCegarLoop]: 1576 mSDtfsCounter, 1164 mSDsluCounter, 1578 mSDsCounter, 0 mSdLazyCounter, 238 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1164 SdHoareTripleChecker+Valid, 3154 SdHoareTripleChecker+Invalid, 239 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 238 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:21:08,933 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1164 Valid, 3154 Invalid, 239 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 238 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:21:08,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2722 states. [2024-12-02 06:21:08,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2722 to 2722. [2024-12-02 06:21:08,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2722 states, 2694 states have (on average 1.4205642167780252) internal successors, (3827), 2694 states have internal predecessors, (3827), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:21:08,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2722 states to 2722 states and 3879 transitions. [2024-12-02 06:21:08,997 INFO L78 Accepts]: Start accepts. Automaton has 2722 states and 3879 transitions. Word has length 855 [2024-12-02 06:21:08,997 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:21:08,997 INFO L471 AbstractCegarLoop]: Abstraction has 2722 states and 3879 transitions. [2024-12-02 06:21:08,997 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 185.0) internal successors, (740), 4 states have internal predecessors, (740), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:21:08,997 INFO L276 IsEmpty]: Start isEmpty. Operand 2722 states and 3879 transitions. [2024-12-02 06:21:09,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 858 [2024-12-02 06:21:09,002 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:21:09,003 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:21:09,003 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable61 [2024-12-02 06:21:09,003 INFO L396 AbstractCegarLoop]: === Iteration 63 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:21:09,003 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:21:09,003 INFO L85 PathProgramCache]: Analyzing trace with hash -1007319384, now seen corresponding path program 1 times [2024-12-02 06:21:09,003 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:21:09,003 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135790774] [2024-12-02 06:21:09,003 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:21:09,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:21:09,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:21:10,198 INFO L134 CoverageAnalysis]: Checked inductivity of 451 backedges. 104 proven. 0 refuted. 0 times theorem prover too weak. 347 trivial. 0 not checked. [2024-12-02 06:21:10,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:21:10,198 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135790774] [2024-12-02 06:21:10,198 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135790774] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:21:10,198 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:21:10,198 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:21:10,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [156922124] [2024-12-02 06:21:10,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:21:10,199 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:21:10,199 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:21:10,199 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:21:10,199 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:21:10,200 INFO L87 Difference]: Start difference. First operand 2722 states and 3879 transitions. Second operand has 5 states, 5 states have (on average 148.4) internal successors, (742), 5 states have internal predecessors, (742), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:21:10,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:21:10,470 INFO L93 Difference]: Finished difference Result 4518 states and 6421 transitions. [2024-12-02 06:21:10,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:21:10,471 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 148.4) internal successors, (742), 5 states have internal predecessors, (742), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 857 [2024-12-02 06:21:10,471 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:21:10,474 INFO L225 Difference]: With dead ends: 4518 [2024-12-02 06:21:10,474 INFO L226 Difference]: Without dead ends: 2722 [2024-12-02 06:21:10,475 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:21:10,475 INFO L435 NwaCegarLoop]: 1575 mSDtfsCounter, 2821 mSDsluCounter, 1577 mSDsCounter, 0 mSdLazyCounter, 238 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2826 SdHoareTripleChecker+Valid, 3152 SdHoareTripleChecker+Invalid, 239 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 238 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:21:10,475 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2826 Valid, 3152 Invalid, 239 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 238 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:21:10,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2722 states. [2024-12-02 06:21:10,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2722 to 2722. [2024-12-02 06:21:10,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2722 states, 2694 states have (on average 1.4198218262806237) internal successors, (3825), 2694 states have internal predecessors, (3825), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:21:10,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2722 states to 2722 states and 3877 transitions. [2024-12-02 06:21:10,548 INFO L78 Accepts]: Start accepts. Automaton has 2722 states and 3877 transitions. Word has length 857 [2024-12-02 06:21:10,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:21:10,549 INFO L471 AbstractCegarLoop]: Abstraction has 2722 states and 3877 transitions. [2024-12-02 06:21:10,549 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 148.4) internal successors, (742), 5 states have internal predecessors, (742), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:21:10,549 INFO L276 IsEmpty]: Start isEmpty. Operand 2722 states and 3877 transitions. [2024-12-02 06:21:10,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 859 [2024-12-02 06:21:10,553 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:21:10,553 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:21:10,553 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable62 [2024-12-02 06:21:10,553 INFO L396 AbstractCegarLoop]: === Iteration 64 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:21:10,554 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:21:10,554 INFO L85 PathProgramCache]: Analyzing trace with hash 1418528468, now seen corresponding path program 1 times [2024-12-02 06:21:10,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:21:10,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619703332] [2024-12-02 06:21:10,554 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:21:10,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:21:10,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:21:11,715 INFO L134 CoverageAnalysis]: Checked inductivity of 451 backedges. 104 proven. 1 refuted. 0 times theorem prover too weak. 346 trivial. 0 not checked. [2024-12-02 06:21:11,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:21:11,715 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619703332] [2024-12-02 06:21:11,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [619703332] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:21:11,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1117141149] [2024-12-02 06:21:11,716 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:21:11,716 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:21:11,716 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:21:11,717 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:21:11,718 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2024-12-02 06:21:15,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:21:15,342 INFO L256 TraceCheckSpWp]: Trace formula consists of 4379 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:21:15,351 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:21:15,384 INFO L134 CoverageAnalysis]: Checked inductivity of 451 backedges. 204 proven. 17 refuted. 0 times theorem prover too weak. 230 trivial. 0 not checked. [2024-12-02 06:21:15,385 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:21:15,439 INFO L134 CoverageAnalysis]: Checked inductivity of 451 backedges. 104 proven. 1 refuted. 0 times theorem prover too weak. 346 trivial. 0 not checked. [2024-12-02 06:21:15,439 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1117141149] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:21:15,439 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:21:15,440 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:21:15,440 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1960907856] [2024-12-02 06:21:15,440 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:21:15,441 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:21:15,441 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:21:15,442 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:21:15,442 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:21:15,442 INFO L87 Difference]: Start difference. First operand 2722 states and 3877 transitions. Second operand has 9 states, 9 states have (on average 84.22222222222223) internal successors, (758), 9 states have internal predecessors, (758), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:21:15,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:21:15,580 INFO L93 Difference]: Finished difference Result 4530 states and 6435 transitions. [2024-12-02 06:21:15,580 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:21:15,580 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 84.22222222222223) internal successors, (758), 9 states have internal predecessors, (758), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 858 [2024-12-02 06:21:15,581 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:21:15,585 INFO L225 Difference]: With dead ends: 4530 [2024-12-02 06:21:15,585 INFO L226 Difference]: Without dead ends: 2734 [2024-12-02 06:21:15,586 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1719 GetRequests, 1711 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:21:15,586 INFO L435 NwaCegarLoop]: 1694 mSDtfsCounter, 14 mSDsluCounter, 10130 mSDsCounter, 0 mSdLazyCounter, 65 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 14 SdHoareTripleChecker+Valid, 11824 SdHoareTripleChecker+Invalid, 67 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 65 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:21:15,587 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [14 Valid, 11824 Invalid, 67 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 65 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:21:15,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2734 states. [2024-12-02 06:21:15,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2734 to 2734. [2024-12-02 06:21:15,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2734 states, 2706 states have (on average 1.417960088691796) internal successors, (3837), 2706 states have internal predecessors, (3837), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:21:15,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2734 states to 2734 states and 3889 transitions. [2024-12-02 06:21:15,665 INFO L78 Accepts]: Start accepts. Automaton has 2734 states and 3889 transitions. Word has length 858 [2024-12-02 06:21:15,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:21:15,666 INFO L471 AbstractCegarLoop]: Abstraction has 2734 states and 3889 transitions. [2024-12-02 06:21:15,666 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 84.22222222222223) internal successors, (758), 9 states have internal predecessors, (758), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:21:15,666 INFO L276 IsEmpty]: Start isEmpty. Operand 2734 states and 3889 transitions. [2024-12-02 06:21:15,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 865 [2024-12-02 06:21:15,672 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:21:15,672 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:21:15,697 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Ended with exit code 0 [2024-12-02 06:21:15,873 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 53 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable63 [2024-12-02 06:21:15,873 INFO L396 AbstractCegarLoop]: === Iteration 65 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:21:15,873 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:21:15,873 INFO L85 PathProgramCache]: Analyzing trace with hash -1225954168, now seen corresponding path program 2 times [2024-12-02 06:21:15,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:21:15,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [512755969] [2024-12-02 06:21:15,874 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:21:15,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:21:16,319 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:21:16,319 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:21:16,998 INFO L134 CoverageAnalysis]: Checked inductivity of 466 backedges. 104 proven. 1 refuted. 0 times theorem prover too weak. 361 trivial. 0 not checked. [2024-12-02 06:21:16,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:21:16,998 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [512755969] [2024-12-02 06:21:16,998 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [512755969] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:21:16,998 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2065583461] [2024-12-02 06:21:16,998 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:21:16,998 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:21:16,998 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:21:17,000 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:21:17,000 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2024-12-02 06:21:20,577 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:21:20,577 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:21:20,599 INFO L256 TraceCheckSpWp]: Trace formula consists of 4406 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:21:20,607 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:21:20,639 INFO L134 CoverageAnalysis]: Checked inductivity of 466 backedges. 204 proven. 17 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2024-12-02 06:21:20,639 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:21:20,686 INFO L134 CoverageAnalysis]: Checked inductivity of 466 backedges. 104 proven. 1 refuted. 0 times theorem prover too weak. 361 trivial. 0 not checked. [2024-12-02 06:21:20,687 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2065583461] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:21:20,687 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:21:20,687 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:21:20,687 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96731365] [2024-12-02 06:21:20,687 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:21:20,688 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:21:20,688 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:21:20,688 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:21:20,688 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:21:20,688 INFO L87 Difference]: Start difference. First operand 2734 states and 3889 transitions. Second operand has 9 states, 9 states have (on average 84.22222222222223) internal successors, (758), 9 states have internal predecessors, (758), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:21:20,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:21:20,807 INFO L93 Difference]: Finished difference Result 4554 states and 6459 transitions. [2024-12-02 06:21:20,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:21:20,808 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 84.22222222222223) internal successors, (758), 9 states have internal predecessors, (758), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 864 [2024-12-02 06:21:20,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:21:20,811 INFO L225 Difference]: With dead ends: 4554 [2024-12-02 06:21:20,811 INFO L226 Difference]: Without dead ends: 2746 [2024-12-02 06:21:20,813 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1731 GetRequests, 1723 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:21:20,813 INFO L435 NwaCegarLoop]: 1694 mSDtfsCounter, 14 mSDsluCounter, 6750 mSDsCounter, 0 mSdLazyCounter, 51 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 14 SdHoareTripleChecker+Valid, 8444 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 51 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:21:20,813 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [14 Valid, 8444 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 51 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:21:20,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2746 states. [2024-12-02 06:21:20,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2746 to 2746. [2024-12-02 06:21:20,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2746 states, 2718 states have (on average 1.4161147902869757) internal successors, (3849), 2718 states have internal predecessors, (3849), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:21:20,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2746 states to 2746 states and 3901 transitions. [2024-12-02 06:21:20,884 INFO L78 Accepts]: Start accepts. Automaton has 2746 states and 3901 transitions. Word has length 864 [2024-12-02 06:21:20,884 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:21:20,884 INFO L471 AbstractCegarLoop]: Abstraction has 2746 states and 3901 transitions. [2024-12-02 06:21:20,885 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 84.22222222222223) internal successors, (758), 9 states have internal predecessors, (758), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:21:20,885 INFO L276 IsEmpty]: Start isEmpty. Operand 2746 states and 3901 transitions. [2024-12-02 06:21:20,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 871 [2024-12-02 06:21:20,889 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:21:20,890 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:21:20,916 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Ended with exit code 0 [2024-12-02 06:21:21,090 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 54 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable64 [2024-12-02 06:21:21,090 INFO L396 AbstractCegarLoop]: === Iteration 66 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:21:21,090 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:21:21,091 INFO L85 PathProgramCache]: Analyzing trace with hash -2090644900, now seen corresponding path program 3 times [2024-12-02 06:21:21,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:21:21,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117887620] [2024-12-02 06:21:21,091 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-12-02 06:21:21,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:21:22,897 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2024-12-02 06:21:22,897 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:21:23,963 INFO L134 CoverageAnalysis]: Checked inductivity of 481 backedges. 29 proven. 4 refuted. 0 times theorem prover too weak. 448 trivial. 0 not checked. [2024-12-02 06:21:23,963 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:21:23,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [117887620] [2024-12-02 06:21:23,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [117887620] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:21:23,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1246248393] [2024-12-02 06:21:23,963 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-12-02 06:21:23,963 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:21:23,963 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:21:23,965 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:21:23,990 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2024-12-02 06:21:27,919 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2024-12-02 06:21:27,919 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:21:27,938 INFO L256 TraceCheckSpWp]: Trace formula consists of 3553 conjuncts, 32 conjuncts are in the unsatisfiable core [2024-12-02 06:21:27,948 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:21:32,149 INFO L134 CoverageAnalysis]: Checked inductivity of 481 backedges. 65 proven. 75 refuted. 0 times theorem prover too weak. 341 trivial. 0 not checked. [2024-12-02 06:21:32,149 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:21:34,564 INFO L134 CoverageAnalysis]: Checked inductivity of 481 backedges. 29 proven. 4 refuted. 0 times theorem prover too weak. 448 trivial. 0 not checked. [2024-12-02 06:21:34,564 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1246248393] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:21:34,564 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:21:34,565 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 10, 6] total 17 [2024-12-02 06:21:34,565 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1245374065] [2024-12-02 06:21:34,565 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:21:34,566 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2024-12-02 06:21:34,566 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:21:34,567 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2024-12-02 06:21:34,567 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=219, Unknown=0, NotChecked=0, Total=272 [2024-12-02 06:21:34,567 INFO L87 Difference]: Start difference. First operand 2746 states and 3901 transitions. Second operand has 17 states, 17 states have (on average 111.6470588235294) internal successors, (1898), 17 states have internal predecessors, (1898), 4 states have call successors, (17), 2 states have call predecessors, (17), 2 states have return successors, (17), 4 states have call predecessors, (17), 4 states have call successors, (17) [2024-12-02 06:21:37,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:21:37,569 INFO L93 Difference]: Finished difference Result 4714 states and 6683 transitions. [2024-12-02 06:21:37,569 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:21:37,569 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 111.6470588235294) internal successors, (1898), 17 states have internal predecessors, (1898), 4 states have call successors, (17), 2 states have call predecessors, (17), 2 states have return successors, (17), 4 states have call predecessors, (17), 4 states have call successors, (17) Word has length 870 [2024-12-02 06:21:37,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:21:37,572 INFO L225 Difference]: With dead ends: 4714 [2024-12-02 06:21:37,573 INFO L226 Difference]: Without dead ends: 2754 [2024-12-02 06:21:37,574 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1752 GetRequests, 1732 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 79 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=95, Invalid=367, Unknown=0, NotChecked=0, Total=462 [2024-12-02 06:21:37,574 INFO L435 NwaCegarLoop]: 985 mSDtfsCounter, 1309 mSDsluCounter, 8792 mSDsCounter, 0 mSdLazyCounter, 7117 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1309 SdHoareTripleChecker+Valid, 9777 SdHoareTripleChecker+Invalid, 7118 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7117 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.8s IncrementalHoareTripleChecker+Time [2024-12-02 06:21:37,574 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1309 Valid, 9777 Invalid, 7118 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7117 Invalid, 0 Unknown, 0 Unchecked, 2.8s Time] [2024-12-02 06:21:37,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2754 states. [2024-12-02 06:21:37,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2754 to 2750. [2024-12-02 06:21:37,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2750 states, 2722 states have (on average 1.4155033063923586) internal successors, (3853), 2722 states have internal predecessors, (3853), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:21:37,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2750 states to 2750 states and 3905 transitions. [2024-12-02 06:21:37,649 INFO L78 Accepts]: Start accepts. Automaton has 2750 states and 3905 transitions. Word has length 870 [2024-12-02 06:21:37,649 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:21:37,650 INFO L471 AbstractCegarLoop]: Abstraction has 2750 states and 3905 transitions. [2024-12-02 06:21:37,650 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 17 states have (on average 111.6470588235294) internal successors, (1898), 17 states have internal predecessors, (1898), 4 states have call successors, (17), 2 states have call predecessors, (17), 2 states have return successors, (17), 4 states have call predecessors, (17), 4 states have call successors, (17) [2024-12-02 06:21:37,650 INFO L276 IsEmpty]: Start isEmpty. Operand 2750 states and 3905 transitions. [2024-12-02 06:21:37,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 873 [2024-12-02 06:21:37,655 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:21:37,655 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:21:37,682 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Ended with exit code 0 [2024-12-02 06:21:37,855 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 55 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable65 [2024-12-02 06:21:37,856 INFO L396 AbstractCegarLoop]: === Iteration 67 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:21:37,856 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:21:37,856 INFO L85 PathProgramCache]: Analyzing trace with hash 1099845788, now seen corresponding path program 1 times [2024-12-02 06:21:37,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:21:37,856 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049756175] [2024-12-02 06:21:37,857 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:21:37,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:21:38,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:21:38,983 INFO L134 CoverageAnalysis]: Checked inductivity of 482 backedges. 105 proven. 1 refuted. 0 times theorem prover too weak. 376 trivial. 0 not checked. [2024-12-02 06:21:38,983 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:21:38,983 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049756175] [2024-12-02 06:21:38,983 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049756175] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:21:38,983 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2063930535] [2024-12-02 06:21:38,983 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:21:38,983 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:21:38,983 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:21:38,985 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:21:38,985 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2024-12-02 06:21:42,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:21:42,566 INFO L256 TraceCheckSpWp]: Trace formula consists of 4435 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:21:42,575 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:21:42,605 INFO L134 CoverageAnalysis]: Checked inductivity of 482 backedges. 205 proven. 7 refuted. 0 times theorem prover too weak. 270 trivial. 0 not checked. [2024-12-02 06:21:42,605 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:21:42,656 INFO L134 CoverageAnalysis]: Checked inductivity of 482 backedges. 105 proven. 1 refuted. 0 times theorem prover too weak. 376 trivial. 0 not checked. [2024-12-02 06:21:42,656 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2063930535] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:21:42,656 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:21:42,656 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:21:42,656 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025028132] [2024-12-02 06:21:42,656 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:21:42,657 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:21:42,657 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:21:42,657 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:21:42,658 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:21:42,658 INFO L87 Difference]: Start difference. First operand 2750 states and 3905 transitions. Second operand has 9 states, 9 states have (on average 84.44444444444444) internal successors, (760), 9 states have internal predecessors, (760), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:21:42,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:21:42,767 INFO L93 Difference]: Finished difference Result 4583 states and 6486 transitions. [2024-12-02 06:21:42,767 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:21:42,768 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 84.44444444444444) internal successors, (760), 9 states have internal predecessors, (760), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 872 [2024-12-02 06:21:42,768 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:21:42,771 INFO L225 Difference]: With dead ends: 4583 [2024-12-02 06:21:42,771 INFO L226 Difference]: Without dead ends: 2761 [2024-12-02 06:21:42,773 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1746 GetRequests, 1739 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:21:42,773 INFO L435 NwaCegarLoop]: 1694 mSDtfsCounter, 14 mSDsluCounter, 8438 mSDsCounter, 0 mSdLazyCounter, 59 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 14 SdHoareTripleChecker+Valid, 10132 SdHoareTripleChecker+Invalid, 60 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 59 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:21:42,773 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [14 Valid, 10132 Invalid, 60 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 59 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:21:42,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2761 states. [2024-12-02 06:21:42,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2761 to 2754. [2024-12-02 06:21:42,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2754 states, 2726 states have (on average 1.4148936170212767) internal successors, (3857), 2726 states have internal predecessors, (3857), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:21:42,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2754 states to 2754 states and 3909 transitions. [2024-12-02 06:21:42,846 INFO L78 Accepts]: Start accepts. Automaton has 2754 states and 3909 transitions. Word has length 872 [2024-12-02 06:21:42,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:21:42,846 INFO L471 AbstractCegarLoop]: Abstraction has 2754 states and 3909 transitions. [2024-12-02 06:21:42,846 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 84.44444444444444) internal successors, (760), 9 states have internal predecessors, (760), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:21:42,846 INFO L276 IsEmpty]: Start isEmpty. Operand 2754 states and 3909 transitions. [2024-12-02 06:21:42,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 875 [2024-12-02 06:21:42,851 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:21:42,851 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:21:42,879 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Ended with exit code 0 [2024-12-02 06:21:43,052 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable66,56 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:21:43,052 INFO L396 AbstractCegarLoop]: === Iteration 68 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:21:43,052 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:21:43,052 INFO L85 PathProgramCache]: Analyzing trace with hash 1559898944, now seen corresponding path program 2 times [2024-12-02 06:21:43,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:21:43,052 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [887235335] [2024-12-02 06:21:43,053 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:21:43,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:21:43,551 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:21:43,551 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:21:44,172 INFO L134 CoverageAnalysis]: Checked inductivity of 485 backedges. 105 proven. 1 refuted. 0 times theorem prover too weak. 379 trivial. 0 not checked. [2024-12-02 06:21:44,172 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:21:44,172 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [887235335] [2024-12-02 06:21:44,172 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [887235335] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:21:44,172 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [52486676] [2024-12-02 06:21:44,173 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:21:44,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:21:44,173 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:21:44,174 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:21:44,175 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2024-12-02 06:21:47,899 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:21:47,899 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:21:47,925 INFO L256 TraceCheckSpWp]: Trace formula consists of 4444 conjuncts, 19 conjuncts are in the unsatisfiable core [2024-12-02 06:21:47,933 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:21:47,991 INFO L134 CoverageAnalysis]: Checked inductivity of 485 backedges. 206 proven. 0 refuted. 0 times theorem prover too weak. 279 trivial. 0 not checked. [2024-12-02 06:21:47,991 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:21:47,991 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [52486676] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:21:47,991 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:21:47,992 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [4] total 10 [2024-12-02 06:21:47,992 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [497313993] [2024-12-02 06:21:47,992 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:21:47,992 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:21:47,992 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:21:47,993 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:21:47,993 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:21:47,993 INFO L87 Difference]: Start difference. First operand 2754 states and 3909 transitions. Second operand has 8 states, 7 states have (on average 106.0) internal successors, (742), 8 states have internal predecessors, (742), 3 states have call successors, (10), 2 states have call predecessors, (10), 3 states have return successors, (10), 2 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:21:48,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:21:48,324 INFO L93 Difference]: Finished difference Result 6992 states and 9874 transitions. [2024-12-02 06:21:48,324 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:21:48,325 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 106.0) internal successors, (742), 8 states have internal predecessors, (742), 3 states have call successors, (10), 2 states have call predecessors, (10), 3 states have return successors, (10), 2 states have call predecessors, (10), 3 states have call successors, (10) Word has length 874 [2024-12-02 06:21:48,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:21:48,330 INFO L225 Difference]: With dead ends: 6992 [2024-12-02 06:21:48,330 INFO L226 Difference]: Without dead ends: 4856 [2024-12-02 06:21:48,332 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 877 GetRequests, 869 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:21:48,333 INFO L435 NwaCegarLoop]: 2533 mSDtfsCounter, 936 mSDsluCounter, 12679 mSDsCounter, 0 mSdLazyCounter, 254 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 941 SdHoareTripleChecker+Valid, 15212 SdHoareTripleChecker+Invalid, 254 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 254 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:21:48,333 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [941 Valid, 15212 Invalid, 254 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 254 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:21:48,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4856 states. [2024-12-02 06:21:48,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4856 to 2982. [2024-12-02 06:21:48,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2982 states, 2954 states have (on average 1.4031821259309412) internal successors, (4145), 2954 states have internal predecessors, (4145), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:21:48,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2982 states to 2982 states and 4197 transitions. [2024-12-02 06:21:48,419 INFO L78 Accepts]: Start accepts. Automaton has 2982 states and 4197 transitions. Word has length 874 [2024-12-02 06:21:48,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:21:48,419 INFO L471 AbstractCegarLoop]: Abstraction has 2982 states and 4197 transitions. [2024-12-02 06:21:48,419 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 106.0) internal successors, (742), 8 states have internal predecessors, (742), 3 states have call successors, (10), 2 states have call predecessors, (10), 3 states have return successors, (10), 2 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:21:48,419 INFO L276 IsEmpty]: Start isEmpty. Operand 2982 states and 4197 transitions. [2024-12-02 06:21:48,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 877 [2024-12-02 06:21:48,424 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:21:48,424 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:21:48,453 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Ended with exit code 0 [2024-12-02 06:21:48,625 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 57 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable67 [2024-12-02 06:21:48,625 INFO L396 AbstractCegarLoop]: === Iteration 69 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:21:48,625 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:21:48,626 INFO L85 PathProgramCache]: Analyzing trace with hash 1919094200, now seen corresponding path program 1 times [2024-12-02 06:21:48,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:21:48,626 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1416668806] [2024-12-02 06:21:48,626 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:21:48,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:21:49,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:21:49,698 INFO L134 CoverageAnalysis]: Checked inductivity of 486 backedges. 106 proven. 1 refuted. 0 times theorem prover too weak. 379 trivial. 0 not checked. [2024-12-02 06:21:49,698 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:21:49,698 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1416668806] [2024-12-02 06:21:49,699 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1416668806] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:21:49,699 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2028874893] [2024-12-02 06:21:49,699 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:21:49,699 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:21:49,699 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:21:49,700 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:21:49,701 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2024-12-02 06:21:53,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:21:53,594 INFO L256 TraceCheckSpWp]: Trace formula consists of 4450 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:21:53,603 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:21:53,637 INFO L134 CoverageAnalysis]: Checked inductivity of 486 backedges. 206 proven. 17 refuted. 0 times theorem prover too weak. 263 trivial. 0 not checked. [2024-12-02 06:21:53,637 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:21:53,689 INFO L134 CoverageAnalysis]: Checked inductivity of 486 backedges. 106 proven. 1 refuted. 0 times theorem prover too weak. 379 trivial. 0 not checked. [2024-12-02 06:21:53,689 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2028874893] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:21:53,689 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:21:53,689 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:21:53,689 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1225597726] [2024-12-02 06:21:53,689 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:21:53,690 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:21:53,690 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:21:53,690 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:21:53,691 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:21:53,691 INFO L87 Difference]: Start difference. First operand 2982 states and 4197 transitions. Second operand has 9 states, 9 states have (on average 84.66666666666667) internal successors, (762), 9 states have internal predecessors, (762), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:21:53,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:21:53,863 INFO L93 Difference]: Finished difference Result 4972 states and 6977 transitions. [2024-12-02 06:21:53,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:21:53,864 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 84.66666666666667) internal successors, (762), 9 states have internal predecessors, (762), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 876 [2024-12-02 06:21:53,864 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:21:53,867 INFO L225 Difference]: With dead ends: 4972 [2024-12-02 06:21:53,867 INFO L226 Difference]: Without dead ends: 2994 [2024-12-02 06:21:53,868 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1755 GetRequests, 1747 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:21:53,868 INFO L435 NwaCegarLoop]: 1694 mSDtfsCounter, 14 mSDsluCounter, 11820 mSDsCounter, 0 mSdLazyCounter, 72 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 14 SdHoareTripleChecker+Valid, 13514 SdHoareTripleChecker+Invalid, 74 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 72 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:21:53,868 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [14 Valid, 13514 Invalid, 74 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 72 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:21:53,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2994 states. [2024-12-02 06:21:53,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2994 to 2994. [2024-12-02 06:21:53,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2994 states, 2966 states have (on average 1.4015509103169252) internal successors, (4157), 2966 states have internal predecessors, (4157), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:21:53,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2994 states to 2994 states and 4209 transitions. [2024-12-02 06:21:53,950 INFO L78 Accepts]: Start accepts. Automaton has 2994 states and 4209 transitions. Word has length 876 [2024-12-02 06:21:53,951 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:21:53,951 INFO L471 AbstractCegarLoop]: Abstraction has 2994 states and 4209 transitions. [2024-12-02 06:21:53,951 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 84.66666666666667) internal successors, (762), 9 states have internal predecessors, (762), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:21:53,951 INFO L276 IsEmpty]: Start isEmpty. Operand 2994 states and 4209 transitions. [2024-12-02 06:21:53,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 883 [2024-12-02 06:21:53,956 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:21:53,956 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:21:53,985 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Ended with exit code 0 [2024-12-02 06:21:54,156 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 58 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable68 [2024-12-02 06:21:54,157 INFO L396 AbstractCegarLoop]: === Iteration 70 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:21:54,157 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:21:54,157 INFO L85 PathProgramCache]: Analyzing trace with hash 912903692, now seen corresponding path program 2 times [2024-12-02 06:21:54,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:21:54,157 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222603196] [2024-12-02 06:21:54,157 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:21:54,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:21:54,648 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:21:54,648 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:21:55,295 INFO L134 CoverageAnalysis]: Checked inductivity of 501 backedges. 106 proven. 1 refuted. 0 times theorem prover too weak. 394 trivial. 0 not checked. [2024-12-02 06:21:55,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:21:55,295 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [222603196] [2024-12-02 06:21:55,295 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [222603196] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:21:55,295 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [376388599] [2024-12-02 06:21:55,295 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 06:21:55,295 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:21:55,295 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:21:55,297 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:21:55,298 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2024-12-02 06:21:59,201 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 06:21:59,201 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:21:59,221 INFO L256 TraceCheckSpWp]: Trace formula consists of 4477 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-12-02 06:21:59,230 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:21:59,261 INFO L134 CoverageAnalysis]: Checked inductivity of 501 backedges. 206 proven. 17 refuted. 0 times theorem prover too weak. 278 trivial. 0 not checked. [2024-12-02 06:21:59,261 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:21:59,312 INFO L134 CoverageAnalysis]: Checked inductivity of 501 backedges. 106 proven. 1 refuted. 0 times theorem prover too weak. 394 trivial. 0 not checked. [2024-12-02 06:21:59,312 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [376388599] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:21:59,312 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:21:59,312 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-12-02 06:21:59,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114807653] [2024-12-02 06:21:59,313 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:21:59,313 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:21:59,313 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:21:59,314 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:21:59,314 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:21:59,314 INFO L87 Difference]: Start difference. First operand 2994 states and 4209 transitions. Second operand has 9 states, 9 states have (on average 84.66666666666667) internal successors, (762), 9 states have internal predecessors, (762), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:21:59,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:21:59,462 INFO L93 Difference]: Finished difference Result 4996 states and 7001 transitions. [2024-12-02 06:21:59,463 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:21:59,463 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 84.66666666666667) internal successors, (762), 9 states have internal predecessors, (762), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 882 [2024-12-02 06:21:59,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:21:59,467 INFO L225 Difference]: With dead ends: 4996 [2024-12-02 06:21:59,467 INFO L226 Difference]: Without dead ends: 3006 [2024-12-02 06:21:59,468 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1767 GetRequests, 1759 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:21:59,469 INFO L435 NwaCegarLoop]: 1694 mSDtfsCounter, 15 mSDsluCounter, 8440 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 10134 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:21:59,469 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 10134 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:21:59,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3006 states. [2024-12-02 06:21:59,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3006 to 3006. [2024-12-02 06:21:59,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3006 states, 2978 states have (on average 1.3999328408327736) internal successors, (4169), 2978 states have internal predecessors, (4169), 26 states have call successors, (26), 1 states have call predecessors, (26), 1 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-12-02 06:21:59,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3006 states to 3006 states and 4221 transitions. [2024-12-02 06:21:59,552 INFO L78 Accepts]: Start accepts. Automaton has 3006 states and 4221 transitions. Word has length 882 [2024-12-02 06:21:59,553 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:21:59,553 INFO L471 AbstractCegarLoop]: Abstraction has 3006 states and 4221 transitions. [2024-12-02 06:21:59,553 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 84.66666666666667) internal successors, (762), 9 states have internal predecessors, (762), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-12-02 06:21:59,553 INFO L276 IsEmpty]: Start isEmpty. Operand 3006 states and 4221 transitions. [2024-12-02 06:21:59,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 889 [2024-12-02 06:21:59,558 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:21:59,558 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:21:59,587 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Ended with exit code 0 [2024-12-02 06:21:59,758 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 59 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable69 [2024-12-02 06:21:59,759 INFO L396 AbstractCegarLoop]: === Iteration 71 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:21:59,759 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:21:59,759 INFO L85 PathProgramCache]: Analyzing trace with hash -646034528, now seen corresponding path program 3 times [2024-12-02 06:21:59,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:21:59,759 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264460830] [2024-12-02 06:21:59,760 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-12-02 06:21:59,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:22:03,758 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2024-12-02 06:22:03,758 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 06:22:05,428 INFO L134 CoverageAnalysis]: Checked inductivity of 516 backedges. 106 proven. 0 refuted. 0 times theorem prover too weak. 410 trivial. 0 not checked. [2024-12-02 06:22:05,428 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:22:05,428 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264460830] [2024-12-02 06:22:05,428 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264460830] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:22:05,429 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:22:05,429 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:22:05,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495646690] [2024-12-02 06:22:05,429 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:22:05,429 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:22:05,430 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:22:05,430 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:22:05,430 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:22:05,431 INFO L87 Difference]: Start difference. First operand 3006 states and 4221 transitions. Second operand has 7 states, 7 states have (on average 106.71428571428571) internal successors, (747), 7 states have internal predecessors, (747), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:22:05,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:22:05,690 INFO L93 Difference]: Finished difference Result 7090 states and 9924 transitions. [2024-12-02 06:22:05,690 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:22:05,691 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 106.71428571428571) internal successors, (747), 7 states have internal predecessors, (747), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 888 [2024-12-02 06:22:05,691 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:22:05,696 INFO L225 Difference]: With dead ends: 7090 [2024-12-02 06:22:05,696 INFO L226 Difference]: Without dead ends: 5088 [2024-12-02 06:22:05,698 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:22:05,698 INFO L435 NwaCegarLoop]: 2372 mSDtfsCounter, 489 mSDsluCounter, 9534 mSDsCounter, 0 mSdLazyCounter, 118 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 489 SdHoareTripleChecker+Valid, 11906 SdHoareTripleChecker+Invalid, 119 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 118 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:22:05,698 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [489 Valid, 11906 Invalid, 119 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 118 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:22:05,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5088 states. [2024-12-02 06:22:05,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5088 to 5048. [2024-12-02 06:22:05,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5048 states, 4994 states have (on average 1.396275530636764) internal successors, (6973), 4994 states have internal predecessors, (6973), 52 states have call successors, (52), 1 states have call predecessors, (52), 1 states have return successors, (52), 52 states have call predecessors, (52), 52 states have call successors, (52) [2024-12-02 06:22:05,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5048 states to 5048 states and 7077 transitions. [2024-12-02 06:22:05,826 INFO L78 Accepts]: Start accepts. Automaton has 5048 states and 7077 transitions. Word has length 888 [2024-12-02 06:22:05,826 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:22:05,826 INFO L471 AbstractCegarLoop]: Abstraction has 5048 states and 7077 transitions. [2024-12-02 06:22:05,827 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 106.71428571428571) internal successors, (747), 7 states have internal predecessors, (747), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:22:05,827 INFO L276 IsEmpty]: Start isEmpty. Operand 5048 states and 7077 transitions. [2024-12-02 06:22:05,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 890 [2024-12-02 06:22:05,833 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:22:05,833 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:22:05,833 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable70 [2024-12-02 06:22:05,833 INFO L396 AbstractCegarLoop]: === Iteration 72 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:22:05,834 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:22:05,834 INFO L85 PathProgramCache]: Analyzing trace with hash 1857841371, now seen corresponding path program 1 times [2024-12-02 06:22:05,834 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:22:05,834 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1198545409] [2024-12-02 06:22:05,834 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:22:05,834 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:22:06,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:22:07,491 INFO L134 CoverageAnalysis]: Checked inductivity of 516 backedges. 106 proven. 0 refuted. 0 times theorem prover too weak. 410 trivial. 0 not checked. [2024-12-02 06:22:07,491 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:22:07,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1198545409] [2024-12-02 06:22:07,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1198545409] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:22:07,491 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:22:07,491 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:22:07,491 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2114661358] [2024-12-02 06:22:07,491 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:22:07,491 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:22:07,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:22:07,492 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:22:07,492 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:22:07,492 INFO L87 Difference]: Start difference. First operand 5048 states and 7077 transitions. Second operand has 6 states, 6 states have (on average 124.66666666666667) internal successors, (748), 6 states have internal predecessors, (748), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:22:09,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:22:09,195 INFO L93 Difference]: Finished difference Result 10678 states and 14952 transitions. [2024-12-02 06:22:09,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:22:09,195 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 124.66666666666667) internal successors, (748), 6 states have internal predecessors, (748), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 889 [2024-12-02 06:22:09,196 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:22:09,202 INFO L225 Difference]: With dead ends: 10678 [2024-12-02 06:22:09,202 INFO L226 Difference]: Without dead ends: 7134 [2024-12-02 06:22:09,205 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:22:09,205 INFO L435 NwaCegarLoop]: 1178 mSDtfsCounter, 2554 mSDsluCounter, 3316 mSDsCounter, 0 mSdLazyCounter, 2989 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2559 SdHoareTripleChecker+Valid, 4494 SdHoareTripleChecker+Invalid, 2990 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 2989 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:22:09,205 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2559 Valid, 4494 Invalid, 2990 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 2989 Invalid, 0 Unknown, 0 Unchecked, 1.5s Time] [2024-12-02 06:22:09,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7134 states. [2024-12-02 06:22:09,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7134 to 6942. [2024-12-02 06:22:09,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6942 states, 6862 states have (on average 1.3936170212765957) internal successors, (9563), 6862 states have internal predecessors, (9563), 78 states have call successors, (78), 1 states have call predecessors, (78), 1 states have return successors, (78), 78 states have call predecessors, (78), 78 states have call successors, (78) [2024-12-02 06:22:09,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6942 states to 6942 states and 9719 transitions. [2024-12-02 06:22:09,414 INFO L78 Accepts]: Start accepts. Automaton has 6942 states and 9719 transitions. Word has length 889 [2024-12-02 06:22:09,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:22:09,415 INFO L471 AbstractCegarLoop]: Abstraction has 6942 states and 9719 transitions. [2024-12-02 06:22:09,415 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 124.66666666666667) internal successors, (748), 6 states have internal predecessors, (748), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:22:09,415 INFO L276 IsEmpty]: Start isEmpty. Operand 6942 states and 9719 transitions. [2024-12-02 06:22:09,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 890 [2024-12-02 06:22:09,423 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:22:09,423 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:22:09,423 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable71 [2024-12-02 06:22:09,423 INFO L396 AbstractCegarLoop]: === Iteration 73 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:22:09,424 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:22:09,424 INFO L85 PathProgramCache]: Analyzing trace with hash -968847965, now seen corresponding path program 1 times [2024-12-02 06:22:09,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:22:09,424 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1669439303] [2024-12-02 06:22:09,424 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:22:09,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:22:11,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:22:13,448 INFO L134 CoverageAnalysis]: Checked inductivity of 516 backedges. 106 proven. 0 refuted. 0 times theorem prover too weak. 410 trivial. 0 not checked. [2024-12-02 06:22:13,448 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:22:13,448 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1669439303] [2024-12-02 06:22:13,448 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1669439303] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:22:13,448 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:22:13,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:22:13,449 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1577583958] [2024-12-02 06:22:13,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:22:13,449 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:22:13,449 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:22:13,450 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:22:13,450 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:22:13,450 INFO L87 Difference]: Start difference. First operand 6942 states and 9719 transitions. Second operand has 6 states, 6 states have (on average 124.66666666666667) internal successors, (748), 6 states have internal predecessors, (748), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:22:13,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:22:13,741 INFO L93 Difference]: Finished difference Result 15595 states and 21895 transitions. [2024-12-02 06:22:13,742 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:22:13,742 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 124.66666666666667) internal successors, (748), 6 states have internal predecessors, (748), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 889 [2024-12-02 06:22:13,742 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:22:13,751 INFO L225 Difference]: With dead ends: 15595 [2024-12-02 06:22:13,751 INFO L226 Difference]: Without dead ends: 10657 [2024-12-02 06:22:13,755 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:22:13,756 INFO L435 NwaCegarLoop]: 1684 mSDtfsCounter, 1103 mSDsluCounter, 6729 mSDsCounter, 0 mSdLazyCounter, 46 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1103 SdHoareTripleChecker+Valid, 8413 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 46 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:22:13,756 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1103 Valid, 8413 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 46 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:22:13,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10657 states. [2024-12-02 06:22:13,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10657 to 8945. [2024-12-02 06:22:14,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8945 states, 8829 states have (on average 1.3916638350889114) internal successors, (12287), 8829 states have internal predecessors, (12287), 114 states have call successors, (114), 1 states have call predecessors, (114), 1 states have return successors, (114), 114 states have call predecessors, (114), 114 states have call successors, (114) [2024-12-02 06:22:14,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8945 states to 8945 states and 12515 transitions. [2024-12-02 06:22:14,013 INFO L78 Accepts]: Start accepts. Automaton has 8945 states and 12515 transitions. Word has length 889 [2024-12-02 06:22:14,013 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:22:14,013 INFO L471 AbstractCegarLoop]: Abstraction has 8945 states and 12515 transitions. [2024-12-02 06:22:14,014 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 124.66666666666667) internal successors, (748), 6 states have internal predecessors, (748), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:22:14,014 INFO L276 IsEmpty]: Start isEmpty. Operand 8945 states and 12515 transitions. [2024-12-02 06:22:14,022 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 891 [2024-12-02 06:22:14,022 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:22:14,023 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:22:14,023 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable72 [2024-12-02 06:22:14,023 INFO L396 AbstractCegarLoop]: === Iteration 74 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:22:14,023 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:22:14,023 INFO L85 PathProgramCache]: Analyzing trace with hash 147988985, now seen corresponding path program 1 times [2024-12-02 06:22:14,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:22:14,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [474956417] [2024-12-02 06:22:14,023 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:22:14,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:22:18,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:22:20,029 INFO L134 CoverageAnalysis]: Checked inductivity of 516 backedges. 98 proven. 0 refuted. 0 times theorem prover too weak. 418 trivial. 0 not checked. [2024-12-02 06:22:20,029 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:22:20,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [474956417] [2024-12-02 06:22:20,030 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [474956417] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:22:20,030 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:22:20,030 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:22:20,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489035347] [2024-12-02 06:22:20,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:22:20,031 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:22:20,031 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:22:20,031 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:22:20,031 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:22:20,032 INFO L87 Difference]: Start difference. First operand 8945 states and 12515 transitions. Second operand has 6 states, 6 states have (on average 123.66666666666667) internal successors, (742), 6 states have internal predecessors, (742), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:22:21,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:22:21,783 INFO L93 Difference]: Finished difference Result 20275 states and 28512 transitions. [2024-12-02 06:22:21,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:22:21,784 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 123.66666666666667) internal successors, (742), 6 states have internal predecessors, (742), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 890 [2024-12-02 06:22:21,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:22:21,796 INFO L225 Difference]: With dead ends: 20275 [2024-12-02 06:22:21,796 INFO L226 Difference]: Without dead ends: 13849 [2024-12-02 06:22:21,802 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:22:21,802 INFO L435 NwaCegarLoop]: 1010 mSDtfsCounter, 1966 mSDsluCounter, 3018 mSDsCounter, 0 mSdLazyCounter, 2748 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1969 SdHoareTripleChecker+Valid, 4028 SdHoareTripleChecker+Invalid, 2748 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 2748 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:22:21,803 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1969 Valid, 4028 Invalid, 2748 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 2748 Invalid, 0 Unknown, 0 Unchecked, 1.4s Time] [2024-12-02 06:22:21,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13849 states. [2024-12-02 06:22:22,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13849 to 8963. [2024-12-02 06:22:22,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8963 states, 8847 states have (on average 1.3908669605515993) internal successors, (12305), 8847 states have internal predecessors, (12305), 114 states have call successors, (114), 1 states have call predecessors, (114), 1 states have return successors, (114), 114 states have call predecessors, (114), 114 states have call successors, (114) [2024-12-02 06:22:22,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8963 states to 8963 states and 12533 transitions. [2024-12-02 06:22:22,027 INFO L78 Accepts]: Start accepts. Automaton has 8963 states and 12533 transitions. Word has length 890 [2024-12-02 06:22:22,027 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:22:22,027 INFO L471 AbstractCegarLoop]: Abstraction has 8963 states and 12533 transitions. [2024-12-02 06:22:22,027 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 123.66666666666667) internal successors, (742), 6 states have internal predecessors, (742), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:22:22,027 INFO L276 IsEmpty]: Start isEmpty. Operand 8963 states and 12533 transitions. [2024-12-02 06:22:22,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 891 [2024-12-02 06:22:22,037 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:22:22,037 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:22:22,038 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable73 [2024-12-02 06:22:22,038 INFO L396 AbstractCegarLoop]: === Iteration 75 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:22:22,038 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:22:22,039 INFO L85 PathProgramCache]: Analyzing trace with hash 1594807961, now seen corresponding path program 1 times [2024-12-02 06:22:22,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:22:22,039 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389261806] [2024-12-02 06:22:22,039 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:22:22,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:22:22,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:22:23,671 INFO L134 CoverageAnalysis]: Checked inductivity of 516 backedges. 106 proven. 0 refuted. 0 times theorem prover too weak. 410 trivial. 0 not checked. [2024-12-02 06:22:23,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:22:23,671 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [389261806] [2024-12-02 06:22:23,672 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [389261806] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:22:23,672 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:22:23,672 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:22:23,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [806516372] [2024-12-02 06:22:23,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:22:23,672 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:22:23,672 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:22:23,673 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:22:23,673 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:22:23,673 INFO L87 Difference]: Start difference. First operand 8963 states and 12533 transitions. Second operand has 6 states, 6 states have (on average 124.83333333333333) internal successors, (749), 6 states have internal predecessors, (749), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:22:25,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:22:25,708 INFO L93 Difference]: Finished difference Result 20200 states and 28278 transitions. [2024-12-02 06:22:25,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:22:25,709 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 124.83333333333333) internal successors, (749), 6 states have internal predecessors, (749), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 890 [2024-12-02 06:22:25,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:22:25,719 INFO L225 Difference]: With dead ends: 20200 [2024-12-02 06:22:25,719 INFO L226 Difference]: Without dead ends: 15256 [2024-12-02 06:22:25,723 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:22:25,723 INFO L435 NwaCegarLoop]: 1795 mSDtfsCounter, 2551 mSDsluCounter, 4545 mSDsCounter, 0 mSdLazyCounter, 3288 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2556 SdHoareTripleChecker+Valid, 6340 SdHoareTripleChecker+Invalid, 3289 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 3288 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.7s IncrementalHoareTripleChecker+Time [2024-12-02 06:22:25,723 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2556 Valid, 6340 Invalid, 3289 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 3288 Invalid, 0 Unknown, 0 Unchecked, 1.7s Time] [2024-12-02 06:22:25,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15256 states. [2024-12-02 06:22:25,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15256 to 12818. [2024-12-02 06:22:26,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12818 states, 12618 states have (on average 1.3846092883182755) internal successors, (17471), 12618 states have internal predecessors, (17471), 198 states have call successors, (198), 1 states have call predecessors, (198), 1 states have return successors, (198), 198 states have call predecessors, (198), 198 states have call successors, (198) [2024-12-02 06:22:26,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12818 states to 12818 states and 17867 transitions. [2024-12-02 06:22:26,018 INFO L78 Accepts]: Start accepts. Automaton has 12818 states and 17867 transitions. Word has length 890 [2024-12-02 06:22:26,018 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:22:26,018 INFO L471 AbstractCegarLoop]: Abstraction has 12818 states and 17867 transitions. [2024-12-02 06:22:26,018 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 124.83333333333333) internal successors, (749), 6 states have internal predecessors, (749), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:22:26,018 INFO L276 IsEmpty]: Start isEmpty. Operand 12818 states and 17867 transitions. [2024-12-02 06:22:26,031 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 892 [2024-12-02 06:22:26,031 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:22:26,032 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:22:26,032 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable74 [2024-12-02 06:22:26,032 INFO L396 AbstractCegarLoop]: === Iteration 76 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:22:26,032 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:22:26,033 INFO L85 PathProgramCache]: Analyzing trace with hash 1713435910, now seen corresponding path program 1 times [2024-12-02 06:22:26,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:22:26,033 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276983774] [2024-12-02 06:22:26,033 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:22:26,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:22:31,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:22:33,011 INFO L134 CoverageAnalysis]: Checked inductivity of 515 backedges. 63 proven. 4 refuted. 0 times theorem prover too weak. 448 trivial. 0 not checked. [2024-12-02 06:22:33,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:22:33,011 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276983774] [2024-12-02 06:22:33,011 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1276983774] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:22:33,011 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1598099367] [2024-12-02 06:22:33,011 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:22:33,011 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:22:33,011 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:22:33,013 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:22:33,013 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2024-12-02 06:22:37,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:22:37,192 INFO L256 TraceCheckSpWp]: Trace formula consists of 4511 conjuncts, 33 conjuncts are in the unsatisfiable core [2024-12-02 06:22:37,201 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:22:37,936 INFO L134 CoverageAnalysis]: Checked inductivity of 515 backedges. 78 proven. 0 refuted. 0 times theorem prover too weak. 437 trivial. 0 not checked. [2024-12-02 06:22:37,936 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:22:37,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1598099367] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:22:37,936 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:22:37,936 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 9 [2024-12-02 06:22:37,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [54283124] [2024-12-02 06:22:37,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:22:37,937 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:22:37,937 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:22:37,937 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:22:37,937 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:22:37,937 INFO L87 Difference]: Start difference. First operand 12818 states and 17867 transitions. Second operand has 6 states, 6 states have (on average 116.5) internal successors, (699), 6 states have internal predecessors, (699), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:22:39,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:22:39,431 INFO L93 Difference]: Finished difference Result 12851 states and 17898 transitions. [2024-12-02 06:22:39,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:22:39,432 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 116.5) internal successors, (699), 6 states have internal predecessors, (699), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 891 [2024-12-02 06:22:39,432 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:22:39,439 INFO L225 Difference]: With dead ends: 12851 [2024-12-02 06:22:39,439 INFO L226 Difference]: Without dead ends: 8027 [2024-12-02 06:22:39,444 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 899 GetRequests, 892 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:22:39,444 INFO L435 NwaCegarLoop]: 997 mSDtfsCounter, 1408 mSDsluCounter, 2962 mSDsCounter, 0 mSdLazyCounter, 2796 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1412 SdHoareTripleChecker+Valid, 3959 SdHoareTripleChecker+Invalid, 2796 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 2796 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2024-12-02 06:22:39,444 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1412 Valid, 3959 Invalid, 2796 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 2796 Invalid, 0 Unknown, 0 Unchecked, 1.3s Time] [2024-12-02 06:22:39,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8027 states. [2024-12-02 06:22:39,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8027 to 8000. [2024-12-02 06:22:39,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8000 states, 7890 states have (on average 1.378960709759189) internal successors, (10880), 7890 states have internal predecessors, (10880), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:22:39,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8000 states to 8000 states and 11096 transitions. [2024-12-02 06:22:39,660 INFO L78 Accepts]: Start accepts. Automaton has 8000 states and 11096 transitions. Word has length 891 [2024-12-02 06:22:39,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:22:39,661 INFO L471 AbstractCegarLoop]: Abstraction has 8000 states and 11096 transitions. [2024-12-02 06:22:39,661 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 116.5) internal successors, (699), 6 states have internal predecessors, (699), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:22:39,661 INFO L276 IsEmpty]: Start isEmpty. Operand 8000 states and 11096 transitions. [2024-12-02 06:22:39,669 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 894 [2024-12-02 06:22:39,669 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:22:39,670 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:22:39,707 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Forceful destruction successful, exit code 0 [2024-12-02 06:22:39,870 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 60 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable75 [2024-12-02 06:22:39,871 INFO L396 AbstractCegarLoop]: === Iteration 77 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:22:39,871 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:22:39,871 INFO L85 PathProgramCache]: Analyzing trace with hash 2057113762, now seen corresponding path program 1 times [2024-12-02 06:22:39,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:22:39,871 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703581839] [2024-12-02 06:22:39,871 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:22:39,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:22:45,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:22:46,408 INFO L134 CoverageAnalysis]: Checked inductivity of 516 backedges. 98 proven. 0 refuted. 0 times theorem prover too weak. 418 trivial. 0 not checked. [2024-12-02 06:22:46,409 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:22:46,409 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1703581839] [2024-12-02 06:22:46,409 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1703581839] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:22:46,409 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:22:46,409 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:22:46,409 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1982810090] [2024-12-02 06:22:46,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:22:46,410 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:22:46,410 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:22:46,410 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:22:46,410 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:22:46,410 INFO L87 Difference]: Start difference. First operand 8000 states and 11096 transitions. Second operand has 6 states, 6 states have (on average 124.16666666666667) internal successors, (745), 6 states have internal predecessors, (745), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:22:48,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:22:48,286 INFO L93 Difference]: Finished difference Result 13297 states and 18527 transitions. [2024-12-02 06:22:48,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:22:48,287 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 124.16666666666667) internal successors, (745), 6 states have internal predecessors, (745), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 893 [2024-12-02 06:22:48,287 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:22:48,295 INFO L225 Difference]: With dead ends: 13297 [2024-12-02 06:22:48,295 INFO L226 Difference]: Without dead ends: 9220 [2024-12-02 06:22:48,299 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:22:48,299 INFO L435 NwaCegarLoop]: 1795 mSDtfsCounter, 1961 mSDsluCounter, 4570 mSDsCounter, 0 mSdLazyCounter, 3285 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1964 SdHoareTripleChecker+Valid, 6365 SdHoareTripleChecker+Invalid, 3286 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 3285 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.5s IncrementalHoareTripleChecker+Time [2024-12-02 06:22:48,299 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1964 Valid, 6365 Invalid, 3286 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 3285 Invalid, 0 Unknown, 0 Unchecked, 1.5s Time] [2024-12-02 06:22:48,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9220 states. [2024-12-02 06:22:48,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9220 to 8000. [2024-12-02 06:22:48,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8000 states, 7890 states have (on average 1.3766793409378961) internal successors, (10862), 7890 states have internal predecessors, (10862), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:22:48,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8000 states to 8000 states and 11078 transitions. [2024-12-02 06:22:48,577 INFO L78 Accepts]: Start accepts. Automaton has 8000 states and 11078 transitions. Word has length 893 [2024-12-02 06:22:48,578 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:22:48,578 INFO L471 AbstractCegarLoop]: Abstraction has 8000 states and 11078 transitions. [2024-12-02 06:22:48,578 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 124.16666666666667) internal successors, (745), 6 states have internal predecessors, (745), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:22:48,578 INFO L276 IsEmpty]: Start isEmpty. Operand 8000 states and 11078 transitions. [2024-12-02 06:22:48,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 895 [2024-12-02 06:22:48,586 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:22:48,586 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:22:48,587 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable76 [2024-12-02 06:22:48,587 INFO L396 AbstractCegarLoop]: === Iteration 78 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:22:48,587 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:22:48,588 INFO L85 PathProgramCache]: Analyzing trace with hash 198121689, now seen corresponding path program 1 times [2024-12-02 06:22:48,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:22:48,588 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581919838] [2024-12-02 06:22:48,588 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:22:48,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:22:52,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:22:54,655 INFO L134 CoverageAnalysis]: Checked inductivity of 518 backedges. 39 proven. 0 refuted. 0 times theorem prover too weak. 479 trivial. 0 not checked. [2024-12-02 06:22:54,655 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:22:54,655 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [581919838] [2024-12-02 06:22:54,655 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [581919838] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:22:54,656 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:22:54,656 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:22:54,656 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [570007670] [2024-12-02 06:22:54,656 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:22:54,656 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:22:54,656 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:22:54,657 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:22:54,657 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:22:54,657 INFO L87 Difference]: Start difference. First operand 8000 states and 11078 transitions. Second operand has 7 states, 7 states have (on average 98.85714285714286) internal successors, (692), 7 states have internal predecessors, (692), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:22:55,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:22:55,024 INFO L93 Difference]: Finished difference Result 13355 states and 18510 transitions. [2024-12-02 06:22:55,024 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:22:55,024 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 98.85714285714286) internal successors, (692), 7 states have internal predecessors, (692), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 894 [2024-12-02 06:22:55,025 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:22:55,033 INFO L225 Difference]: With dead ends: 13355 [2024-12-02 06:22:55,033 INFO L226 Difference]: Without dead ends: 8216 [2024-12-02 06:22:55,038 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:22:55,039 INFO L435 NwaCegarLoop]: 1666 mSDtfsCounter, 1418 mSDsluCounter, 6646 mSDsCounter, 0 mSdLazyCounter, 156 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1422 SdHoareTripleChecker+Valid, 8312 SdHoareTripleChecker+Invalid, 157 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 156 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:22:55,039 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1422 Valid, 8312 Invalid, 157 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 156 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:22:55,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8216 states. [2024-12-02 06:22:55,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8216 to 8135. [2024-12-02 06:22:55,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8135 states, 8025 states have (on average 1.3737071651090342) internal successors, (11024), 8025 states have internal predecessors, (11024), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:22:55,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8135 states to 8135 states and 11240 transitions. [2024-12-02 06:22:55,251 INFO L78 Accepts]: Start accepts. Automaton has 8135 states and 11240 transitions. Word has length 894 [2024-12-02 06:22:55,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:22:55,251 INFO L471 AbstractCegarLoop]: Abstraction has 8135 states and 11240 transitions. [2024-12-02 06:22:55,251 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 98.85714285714286) internal successors, (692), 7 states have internal predecessors, (692), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:22:55,252 INFO L276 IsEmpty]: Start isEmpty. Operand 8135 states and 11240 transitions. [2024-12-02 06:22:55,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 895 [2024-12-02 06:22:55,263 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:22:55,264 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:22:55,264 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable77 [2024-12-02 06:22:55,264 INFO L396 AbstractCegarLoop]: === Iteration 79 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:22:55,265 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:22:55,265 INFO L85 PathProgramCache]: Analyzing trace with hash 783033561, now seen corresponding path program 1 times [2024-12-02 06:22:55,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:22:55,265 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2122993311] [2024-12-02 06:22:55,265 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:22:55,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:00,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:02,261 INFO L134 CoverageAnalysis]: Checked inductivity of 518 backedges. 55 proven. 0 refuted. 0 times theorem prover too weak. 463 trivial. 0 not checked. [2024-12-02 06:23:02,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:02,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2122993311] [2024-12-02 06:23:02,261 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2122993311] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:02,261 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:02,262 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 06:23:02,262 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [705659901] [2024-12-02 06:23:02,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:02,262 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 06:23:02,262 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:02,263 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 06:23:02,263 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:23:02,263 INFO L87 Difference]: Start difference. First operand 8135 states and 11240 transitions. Second operand has 7 states, 7 states have (on average 101.0) internal successors, (707), 7 states have internal predecessors, (707), 2 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) [2024-12-02 06:23:02,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:02,606 INFO L93 Difference]: Finished difference Result 13067 states and 18099 transitions. [2024-12-02 06:23:02,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:23:02,607 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 101.0) internal successors, (707), 7 states have internal predecessors, (707), 2 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) Word has length 894 [2024-12-02 06:23:02,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:02,615 INFO L225 Difference]: With dead ends: 13067 [2024-12-02 06:23:02,615 INFO L226 Difference]: Without dead ends: 8279 [2024-12-02 06:23:02,619 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:23:02,620 INFO L435 NwaCegarLoop]: 1666 mSDtfsCounter, 1403 mSDsluCounter, 6646 mSDsCounter, 0 mSdLazyCounter, 156 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1406 SdHoareTripleChecker+Valid, 8312 SdHoareTripleChecker+Invalid, 157 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 156 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:02,620 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1406 Valid, 8312 Invalid, 157 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 156 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:23:02,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8279 states. [2024-12-02 06:23:02,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8279 to 8225. [2024-12-02 06:23:02,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8225 states, 8115 states have (on average 1.371780653111522) internal successors, (11132), 8115 states have internal predecessors, (11132), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:23:02,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8225 states to 8225 states and 11348 transitions. [2024-12-02 06:23:02,838 INFO L78 Accepts]: Start accepts. Automaton has 8225 states and 11348 transitions. Word has length 894 [2024-12-02 06:23:02,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:02,838 INFO L471 AbstractCegarLoop]: Abstraction has 8225 states and 11348 transitions. [2024-12-02 06:23:02,839 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 101.0) internal successors, (707), 7 states have internal predecessors, (707), 2 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) [2024-12-02 06:23:02,839 INFO L276 IsEmpty]: Start isEmpty. Operand 8225 states and 11348 transitions. [2024-12-02 06:23:02,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 895 [2024-12-02 06:23:02,848 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:02,848 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:02,848 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable78 [2024-12-02 06:23:02,848 INFO L396 AbstractCegarLoop]: === Iteration 80 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:02,849 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:02,849 INFO L85 PathProgramCache]: Analyzing trace with hash 562507993, now seen corresponding path program 1 times [2024-12-02 06:23:02,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:02,849 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2104750052] [2024-12-02 06:23:02,849 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:02,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:07,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:09,522 INFO L134 CoverageAnalysis]: Checked inductivity of 518 backedges. 108 proven. 0 refuted. 0 times theorem prover too weak. 410 trivial. 0 not checked. [2024-12-02 06:23:09,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:09,522 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2104750052] [2024-12-02 06:23:09,522 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2104750052] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:09,522 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:09,522 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-12-02 06:23:09,522 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [783378562] [2024-12-02 06:23:09,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:09,523 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 06:23:09,523 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:09,524 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 06:23:09,524 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:23:09,524 INFO L87 Difference]: Start difference. First operand 8225 states and 11348 transitions. Second operand has 9 states, 9 states have (on average 83.66666666666667) internal successors, (753), 9 states have internal predecessors, (753), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:23:10,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:10,078 INFO L93 Difference]: Finished difference Result 13484 states and 18739 transitions. [2024-12-02 06:23:10,078 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-12-02 06:23:10,079 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 83.66666666666667) internal successors, (753), 9 states have internal predecessors, (753), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 894 [2024-12-02 06:23:10,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:10,087 INFO L225 Difference]: With dead ends: 13484 [2024-12-02 06:23:10,087 INFO L226 Difference]: Without dead ends: 9129 [2024-12-02 06:23:10,092 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=35, Invalid=147, Unknown=0, NotChecked=0, Total=182 [2024-12-02 06:23:10,092 INFO L435 NwaCegarLoop]: 1673 mSDtfsCounter, 1753 mSDsluCounter, 11606 mSDsCounter, 0 mSdLazyCounter, 256 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1753 SdHoareTripleChecker+Valid, 13279 SdHoareTripleChecker+Invalid, 265 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 256 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:10,092 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1753 Valid, 13279 Invalid, 265 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 256 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:23:10,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9129 states. [2024-12-02 06:23:10,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9129 to 8243. [2024-12-02 06:23:10,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8243 states, 8133 states have (on average 1.3716955612934956) internal successors, (11156), 8133 states have internal predecessors, (11156), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:23:10,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8243 states to 8243 states and 11372 transitions. [2024-12-02 06:23:10,320 INFO L78 Accepts]: Start accepts. Automaton has 8243 states and 11372 transitions. Word has length 894 [2024-12-02 06:23:10,320 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:10,320 INFO L471 AbstractCegarLoop]: Abstraction has 8243 states and 11372 transitions. [2024-12-02 06:23:10,320 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 83.66666666666667) internal successors, (753), 9 states have internal predecessors, (753), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:23:10,320 INFO L276 IsEmpty]: Start isEmpty. Operand 8243 states and 11372 transitions. [2024-12-02 06:23:10,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 895 [2024-12-02 06:23:10,329 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:10,330 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:10,330 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable79 [2024-12-02 06:23:10,330 INFO L396 AbstractCegarLoop]: === Iteration 81 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:10,330 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:10,331 INFO L85 PathProgramCache]: Analyzing trace with hash -933180882, now seen corresponding path program 1 times [2024-12-02 06:23:10,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:10,331 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161116156] [2024-12-02 06:23:10,331 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:10,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:12,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:13,569 INFO L134 CoverageAnalysis]: Checked inductivity of 518 backedges. 108 proven. 0 refuted. 0 times theorem prover too weak. 410 trivial. 0 not checked. [2024-12-02 06:23:13,569 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:13,569 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [161116156] [2024-12-02 06:23:13,569 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [161116156] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:13,569 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:13,569 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 06:23:13,569 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869135898] [2024-12-02 06:23:13,569 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:13,570 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 06:23:13,570 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:13,571 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 06:23:13,571 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:23:13,571 INFO L87 Difference]: Start difference. First operand 8243 states and 11372 transitions. Second operand has 4 states, 4 states have (on average 188.25) internal successors, (753), 4 states have internal predecessors, (753), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:23:13,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:13,775 INFO L93 Difference]: Finished difference Result 11633 states and 16065 transitions. [2024-12-02 06:23:13,776 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 06:23:13,776 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 188.25) internal successors, (753), 4 states have internal predecessors, (753), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 894 [2024-12-02 06:23:13,777 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:13,784 INFO L225 Difference]: With dead ends: 11633 [2024-12-02 06:23:13,784 INFO L226 Difference]: Without dead ends: 8243 [2024-12-02 06:23:13,787 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 06:23:13,787 INFO L435 NwaCegarLoop]: 1687 mSDtfsCounter, 97 mSDsluCounter, 3199 mSDsCounter, 0 mSdLazyCounter, 14 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 97 SdHoareTripleChecker+Valid, 4886 SdHoareTripleChecker+Invalid, 14 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 14 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:13,787 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [97 Valid, 4886 Invalid, 14 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 14 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:23:13,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8243 states. [2024-12-02 06:23:13,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8243 to 8243. [2024-12-02 06:23:14,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8243 states, 8133 states have (on average 1.3709578261404156) internal successors, (11150), 8133 states have internal predecessors, (11150), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:23:14,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8243 states to 8243 states and 11366 transitions. [2024-12-02 06:23:14,013 INFO L78 Accepts]: Start accepts. Automaton has 8243 states and 11366 transitions. Word has length 894 [2024-12-02 06:23:14,013 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:14,014 INFO L471 AbstractCegarLoop]: Abstraction has 8243 states and 11366 transitions. [2024-12-02 06:23:14,014 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 188.25) internal successors, (753), 4 states have internal predecessors, (753), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:23:14,014 INFO L276 IsEmpty]: Start isEmpty. Operand 8243 states and 11366 transitions. [2024-12-02 06:23:14,023 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 896 [2024-12-02 06:23:14,023 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:14,023 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:14,023 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable80 [2024-12-02 06:23:14,024 INFO L396 AbstractCegarLoop]: === Iteration 82 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:14,024 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:14,024 INFO L85 PathProgramCache]: Analyzing trace with hash 1978984070, now seen corresponding path program 1 times [2024-12-02 06:23:14,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:14,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [930953928] [2024-12-02 06:23:14,025 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:14,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:19,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:20,668 INFO L134 CoverageAnalysis]: Checked inductivity of 518 backedges. 108 proven. 0 refuted. 0 times theorem prover too weak. 410 trivial. 0 not checked. [2024-12-02 06:23:20,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:20,668 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [930953928] [2024-12-02 06:23:20,669 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [930953928] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:20,669 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:20,669 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:23:20,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1764829251] [2024-12-02 06:23:20,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:20,670 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:23:20,670 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:20,670 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:23:20,670 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:23:20,670 INFO L87 Difference]: Start difference. First operand 8243 states and 11366 transitions. Second operand has 5 states, 5 states have (on average 150.8) internal successors, (754), 5 states have internal predecessors, (754), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:21,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:21,072 INFO L93 Difference]: Finished difference Result 11651 states and 16083 transitions. [2024-12-02 06:23:21,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:23:21,072 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 150.8) internal successors, (754), 5 states have internal predecessors, (754), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 895 [2024-12-02 06:23:21,073 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:21,080 INFO L225 Difference]: With dead ends: 11651 [2024-12-02 06:23:21,080 INFO L226 Difference]: Without dead ends: 8261 [2024-12-02 06:23:21,083 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:23:21,084 INFO L435 NwaCegarLoop]: 1578 mSDtfsCounter, 1338 mSDsluCounter, 3130 mSDsCounter, 0 mSdLazyCounter, 357 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1338 SdHoareTripleChecker+Valid, 4708 SdHoareTripleChecker+Invalid, 358 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 357 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:21,084 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1338 Valid, 4708 Invalid, 358 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 357 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 06:23:21,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8261 states. [2024-12-02 06:23:21,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8261 to 8261. [2024-12-02 06:23:21,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8261 states, 8151 states have (on average 1.3708747392957918) internal successors, (11174), 8151 states have internal predecessors, (11174), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-12-02 06:23:21,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8261 states to 8261 states and 11390 transitions. [2024-12-02 06:23:21,337 INFO L78 Accepts]: Start accepts. Automaton has 8261 states and 11390 transitions. Word has length 895 [2024-12-02 06:23:21,338 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:21,338 INFO L471 AbstractCegarLoop]: Abstraction has 8261 states and 11390 transitions. [2024-12-02 06:23:21,338 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 150.8) internal successors, (754), 5 states have internal predecessors, (754), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:23:21,338 INFO L276 IsEmpty]: Start isEmpty. Operand 8261 states and 11390 transitions. [2024-12-02 06:23:21,347 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 896 [2024-12-02 06:23:21,347 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:21,347 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:21,348 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable81 [2024-12-02 06:23:21,348 INFO L396 AbstractCegarLoop]: === Iteration 83 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:21,348 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:21,348 INFO L85 PathProgramCache]: Analyzing trace with hash -1095671446, now seen corresponding path program 1 times [2024-12-02 06:23:21,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:21,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [410070888] [2024-12-02 06:23:21,348 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:21,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:28,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:34,254 INFO L134 CoverageAnalysis]: Checked inductivity of 518 backedges. 108 proven. 0 refuted. 0 times theorem prover too weak. 410 trivial. 0 not checked. [2024-12-02 06:23:34,254 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:34,254 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [410070888] [2024-12-02 06:23:34,254 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [410070888] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:34,254 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:34,254 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [16] imperfect sequences [] total 16 [2024-12-02 06:23:34,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [439335523] [2024-12-02 06:23:34,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:34,255 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2024-12-02 06:23:34,255 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:34,256 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2024-12-02 06:23:34,256 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=191, Unknown=0, NotChecked=0, Total=240 [2024-12-02 06:23:34,256 INFO L87 Difference]: Start difference. First operand 8261 states and 11390 transitions. Second operand has 16 states, 16 states have (on average 47.125) internal successors, (754), 16 states have internal predecessors, (754), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:23:39,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:39,123 INFO L93 Difference]: Finished difference Result 13788 states and 19040 transitions. [2024-12-02 06:23:39,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2024-12-02 06:23:39,123 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 47.125) internal successors, (754), 16 states have internal predecessors, (754), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 895 [2024-12-02 06:23:39,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:39,132 INFO L225 Difference]: With dead ends: 13788 [2024-12-02 06:23:39,132 INFO L226 Difference]: Without dead ends: 10380 [2024-12-02 06:23:39,136 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=70, Invalid=310, Unknown=0, NotChecked=0, Total=380 [2024-12-02 06:23:39,136 INFO L435 NwaCegarLoop]: 1087 mSDtfsCounter, 3006 mSDsluCounter, 11343 mSDsCounter, 0 mSdLazyCounter, 9369 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3016 SdHoareTripleChecker+Valid, 12430 SdHoareTripleChecker+Invalid, 9377 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 9369 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 4.4s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:39,137 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3016 Valid, 12430 Invalid, 9377 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 9369 Invalid, 0 Unknown, 0 Unchecked, 4.4s Time] [2024-12-02 06:23:39,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10380 states. [2024-12-02 06:23:39,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10380 to 9458. [2024-12-02 06:23:39,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9458 states, 9312 states have (on average 1.3671606529209621) internal successors, (12731), 9312 states have internal predecessors, (12731), 144 states have call successors, (144), 1 states have call predecessors, (144), 1 states have return successors, (144), 144 states have call predecessors, (144), 144 states have call successors, (144) [2024-12-02 06:23:39,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9458 states to 9458 states and 13019 transitions. [2024-12-02 06:23:39,395 INFO L78 Accepts]: Start accepts. Automaton has 9458 states and 13019 transitions. Word has length 895 [2024-12-02 06:23:39,395 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:39,396 INFO L471 AbstractCegarLoop]: Abstraction has 9458 states and 13019 transitions. [2024-12-02 06:23:39,396 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 47.125) internal successors, (754), 16 states have internal predecessors, (754), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:23:39,396 INFO L276 IsEmpty]: Start isEmpty. Operand 9458 states and 13019 transitions. [2024-12-02 06:23:39,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 896 [2024-12-02 06:23:39,405 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:39,406 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:39,406 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable82 [2024-12-02 06:23:39,406 INFO L396 AbstractCegarLoop]: === Iteration 84 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:39,406 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:39,407 INFO L85 PathProgramCache]: Analyzing trace with hash 2114761467, now seen corresponding path program 1 times [2024-12-02 06:23:39,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:39,407 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [904429304] [2024-12-02 06:23:39,407 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:39,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:39,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:40,916 INFO L134 CoverageAnalysis]: Checked inductivity of 516 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 494 trivial. 0 not checked. [2024-12-02 06:23:40,916 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:40,916 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [904429304] [2024-12-02 06:23:40,917 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [904429304] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:40,917 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:40,917 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:23:40,917 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [321078278] [2024-12-02 06:23:40,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:40,917 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:23:40,917 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:40,918 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:23:40,918 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:23:40,918 INFO L87 Difference]: Start difference. First operand 9458 states and 13019 transitions. Second operand has 5 states, 5 states have (on average 136.2) internal successors, (681), 5 states have internal predecessors, (681), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:42,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:42,070 INFO L93 Difference]: Finished difference Result 15668 states and 21600 transitions. [2024-12-02 06:23:42,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:23:42,070 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 136.2) internal successors, (681), 5 states have internal predecessors, (681), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 895 [2024-12-02 06:23:42,070 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:42,079 INFO L225 Difference]: With dead ends: 15668 [2024-12-02 06:23:42,079 INFO L226 Difference]: Without dead ends: 9566 [2024-12-02 06:23:42,083 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:23:42,084 INFO L435 NwaCegarLoop]: 1018 mSDtfsCounter, 1668 mSDsluCounter, 2017 mSDsCounter, 0 mSdLazyCounter, 2037 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1673 SdHoareTripleChecker+Valid, 3035 SdHoareTripleChecker+Invalid, 2039 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 2037 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:42,084 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1673 Valid, 3035 Invalid, 2039 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 2037 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-12-02 06:23:42,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9566 states. [2024-12-02 06:23:42,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9566 to 9566. [2024-12-02 06:23:42,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9566 states, 9420 states have (on average 1.3629511677282378) internal successors, (12839), 9420 states have internal predecessors, (12839), 144 states have call successors, (144), 1 states have call predecessors, (144), 1 states have return successors, (144), 144 states have call predecessors, (144), 144 states have call successors, (144) [2024-12-02 06:23:42,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9566 states to 9566 states and 13127 transitions. [2024-12-02 06:23:42,370 INFO L78 Accepts]: Start accepts. Automaton has 9566 states and 13127 transitions. Word has length 895 [2024-12-02 06:23:42,370 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:42,370 INFO L471 AbstractCegarLoop]: Abstraction has 9566 states and 13127 transitions. [2024-12-02 06:23:42,370 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 136.2) internal successors, (681), 5 states have internal predecessors, (681), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:23:42,370 INFO L276 IsEmpty]: Start isEmpty. Operand 9566 states and 13127 transitions. [2024-12-02 06:23:42,380 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 896 [2024-12-02 06:23:42,380 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:42,380 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:42,381 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable83 [2024-12-02 06:23:42,381 INFO L396 AbstractCegarLoop]: === Iteration 85 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:42,381 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:42,382 INFO L85 PathProgramCache]: Analyzing trace with hash -600507496, now seen corresponding path program 1 times [2024-12-02 06:23:42,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:42,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1139613365] [2024-12-02 06:23:42,382 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:42,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:23:49,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:23:51,810 INFO L134 CoverageAnalysis]: Checked inductivity of 518 backedges. 37 proven. 0 refuted. 0 times theorem prover too weak. 481 trivial. 0 not checked. [2024-12-02 06:23:51,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:23:51,811 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1139613365] [2024-12-02 06:23:51,811 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1139613365] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:23:51,811 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:23:51,811 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:23:51,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1111739289] [2024-12-02 06:23:51,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:23:51,812 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:23:51,812 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:23:51,812 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:23:51,813 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:23:51,813 INFO L87 Difference]: Start difference. First operand 9566 states and 13127 transitions. Second operand has 8 states, 8 states have (on average 86.375) internal successors, (691), 8 states have internal predecessors, (691), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:23:52,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:23:52,537 INFO L93 Difference]: Finished difference Result 17243 states and 23753 transitions. [2024-12-02 06:23:52,537 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:23:52,537 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 86.375) internal successors, (691), 8 states have internal predecessors, (691), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 895 [2024-12-02 06:23:52,538 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:23:52,549 INFO L225 Difference]: With dead ends: 17243 [2024-12-02 06:23:52,549 INFO L226 Difference]: Without dead ends: 12908 [2024-12-02 06:23:52,553 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=42, Invalid=114, Unknown=0, NotChecked=0, Total=156 [2024-12-02 06:23:52,554 INFO L435 NwaCegarLoop]: 2852 mSDtfsCounter, 2687 mSDsluCounter, 10161 mSDsCounter, 0 mSdLazyCounter, 556 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2692 SdHoareTripleChecker+Valid, 13013 SdHoareTripleChecker+Invalid, 560 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 556 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-12-02 06:23:52,554 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2692 Valid, 13013 Invalid, 560 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 556 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-12-02 06:23:52,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12908 states. [2024-12-02 06:23:52,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12908 to 10972. [2024-12-02 06:23:52,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10972 states, 10817 states have (on average 1.3619302949061662) internal successors, (14732), 10817 states have internal predecessors, (14732), 153 states have call successors, (153), 1 states have call predecessors, (153), 1 states have return successors, (153), 153 states have call predecessors, (153), 153 states have call successors, (153) [2024-12-02 06:23:52,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10972 states to 10972 states and 15038 transitions. [2024-12-02 06:23:52,878 INFO L78 Accepts]: Start accepts. Automaton has 10972 states and 15038 transitions. Word has length 895 [2024-12-02 06:23:52,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:23:52,879 INFO L471 AbstractCegarLoop]: Abstraction has 10972 states and 15038 transitions. [2024-12-02 06:23:52,879 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 86.375) internal successors, (691), 8 states have internal predecessors, (691), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:23:52,879 INFO L276 IsEmpty]: Start isEmpty. Operand 10972 states and 15038 transitions. [2024-12-02 06:23:52,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 897 [2024-12-02 06:23:52,889 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:23:52,889 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:23:52,890 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable84 [2024-12-02 06:23:52,890 INFO L396 AbstractCegarLoop]: === Iteration 86 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:23:52,890 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:23:52,890 INFO L85 PathProgramCache]: Analyzing trace with hash -965672746, now seen corresponding path program 1 times [2024-12-02 06:23:52,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:23:52,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466565795] [2024-12-02 06:23:52,890 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:23:52,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:00,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:02,823 INFO L134 CoverageAnalysis]: Checked inductivity of 518 backedges. 108 proven. 0 refuted. 0 times theorem prover too weak. 410 trivial. 0 not checked. [2024-12-02 06:24:02,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:02,823 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1466565795] [2024-12-02 06:24:02,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1466565795] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:24:02,823 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:24:02,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:24:02,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993753597] [2024-12-02 06:24:02,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:02,823 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:24:02,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:02,824 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:24:02,824 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:24:02,825 INFO L87 Difference]: Start difference. First operand 10972 states and 15038 transitions. Second operand has 8 states, 8 states have (on average 94.375) internal successors, (755), 8 states have internal predecessors, (755), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:03,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:03,350 INFO L93 Difference]: Finished difference Result 23024 states and 31616 transitions. [2024-12-02 06:24:03,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:24:03,351 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 94.375) internal successors, (755), 8 states have internal predecessors, (755), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 896 [2024-12-02 06:24:03,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:03,366 INFO L225 Difference]: With dead ends: 23024 [2024-12-02 06:24:03,366 INFO L226 Difference]: Without dead ends: 19580 [2024-12-02 06:24:03,372 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=81, Unknown=0, NotChecked=0, Total=110 [2024-12-02 06:24:03,373 INFO L435 NwaCegarLoop]: 1679 mSDtfsCounter, 2539 mSDsluCounter, 8368 mSDsCounter, 0 mSdLazyCounter, 137 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2544 SdHoareTripleChecker+Valid, 10047 SdHoareTripleChecker+Invalid, 137 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 137 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:03,373 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2544 Valid, 10047 Invalid, 137 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 137 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:24:03,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19580 states. [2024-12-02 06:24:03,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19580 to 19575. [2024-12-02 06:24:03,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19575 states, 19303 states have (on average 1.363674040304616) internal successors, (26323), 19303 states have internal predecessors, (26323), 270 states have call successors, (270), 1 states have call predecessors, (270), 1 states have return successors, (270), 270 states have call predecessors, (270), 270 states have call successors, (270) [2024-12-02 06:24:03,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19575 states to 19575 states and 26863 transitions. [2024-12-02 06:24:03,876 INFO L78 Accepts]: Start accepts. Automaton has 19575 states and 26863 transitions. Word has length 896 [2024-12-02 06:24:03,876 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:03,876 INFO L471 AbstractCegarLoop]: Abstraction has 19575 states and 26863 transitions. [2024-12-02 06:24:03,877 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 94.375) internal successors, (755), 8 states have internal predecessors, (755), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:03,877 INFO L276 IsEmpty]: Start isEmpty. Operand 19575 states and 26863 transitions. [2024-12-02 06:24:03,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 898 [2024-12-02 06:24:03,893 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:03,893 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:03,893 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable85 [2024-12-02 06:24:03,893 INFO L396 AbstractCegarLoop]: === Iteration 87 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:03,893 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:03,894 INFO L85 PathProgramCache]: Analyzing trace with hash 1257671042, now seen corresponding path program 1 times [2024-12-02 06:24:03,894 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:03,894 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669074056] [2024-12-02 06:24:03,894 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:03,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:08,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:10,121 INFO L134 CoverageAnalysis]: Checked inductivity of 518 backedges. 108 proven. 0 refuted. 0 times theorem prover too weak. 410 trivial. 0 not checked. [2024-12-02 06:24:10,121 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:10,121 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669074056] [2024-12-02 06:24:10,121 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669074056] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:24:10,121 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:24:10,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:24:10,122 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821112625] [2024-12-02 06:24:10,122 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:10,122 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:24:10,122 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:10,123 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:24:10,123 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:24:10,123 INFO L87 Difference]: Start difference. First operand 19575 states and 26863 transitions. Second operand has 8 states, 8 states have (on average 94.5) internal successors, (756), 8 states have internal predecessors, (756), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:13,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:13,042 INFO L93 Difference]: Finished difference Result 28208 states and 38639 transitions. [2024-12-02 06:24:13,042 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:24:13,042 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 94.5) internal successors, (756), 8 states have internal predecessors, (756), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 897 [2024-12-02 06:24:13,042 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:13,061 INFO L225 Difference]: With dead ends: 28208 [2024-12-02 06:24:13,061 INFO L226 Difference]: Without dead ends: 24662 [2024-12-02 06:24:13,067 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:24:13,067 INFO L435 NwaCegarLoop]: 1937 mSDtfsCounter, 2870 mSDsluCounter, 7321 mSDsCounter, 0 mSdLazyCounter, 4656 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2880 SdHoareTripleChecker+Valid, 9258 SdHoareTripleChecker+Invalid, 4658 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 4656 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.3s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:13,068 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2880 Valid, 9258 Invalid, 4658 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 4656 Invalid, 0 Unknown, 0 Unchecked, 2.3s Time] [2024-12-02 06:24:13,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24662 states. [2024-12-02 06:24:13,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24662 to 24483. [2024-12-02 06:24:13,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24483 states, 24121 states have (on average 1.3582770200240455) internal successors, (32763), 24121 states have internal predecessors, (32763), 360 states have call successors, (360), 1 states have call predecessors, (360), 1 states have return successors, (360), 360 states have call predecessors, (360), 360 states have call successors, (360) [2024-12-02 06:24:13,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24483 states to 24483 states and 33483 transitions. [2024-12-02 06:24:13,671 INFO L78 Accepts]: Start accepts. Automaton has 24483 states and 33483 transitions. Word has length 897 [2024-12-02 06:24:13,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:13,672 INFO L471 AbstractCegarLoop]: Abstraction has 24483 states and 33483 transitions. [2024-12-02 06:24:13,672 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 94.5) internal successors, (756), 8 states have internal predecessors, (756), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:13,672 INFO L276 IsEmpty]: Start isEmpty. Operand 24483 states and 33483 transitions. [2024-12-02 06:24:13,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 898 [2024-12-02 06:24:13,692 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:13,692 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:13,693 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable86 [2024-12-02 06:24:13,693 INFO L396 AbstractCegarLoop]: === Iteration 88 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:13,693 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:13,693 INFO L85 PathProgramCache]: Analyzing trace with hash -1427840670, now seen corresponding path program 1 times [2024-12-02 06:24:13,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:13,693 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1561909878] [2024-12-02 06:24:13,693 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:13,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:19,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:20,814 INFO L134 CoverageAnalysis]: Checked inductivity of 516 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 500 trivial. 0 not checked. [2024-12-02 06:24:20,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:20,814 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1561909878] [2024-12-02 06:24:20,814 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1561909878] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:24:20,814 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:24:20,814 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 06:24:20,814 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1525187034] [2024-12-02 06:24:20,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:20,815 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:24:20,815 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:20,815 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:24:20,815 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:24:20,815 INFO L87 Difference]: Start difference. First operand 24483 states and 33483 transitions. Second operand has 6 states, 6 states have (on average 112.5) internal successors, (675), 6 states have internal predecessors, (675), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:24:22,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:22,708 INFO L93 Difference]: Finished difference Result 39806 states and 54480 transitions. [2024-12-02 06:24:22,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:24:22,709 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 112.5) internal successors, (675), 6 states have internal predecessors, (675), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 897 [2024-12-02 06:24:22,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:22,728 INFO L225 Difference]: With dead ends: 39806 [2024-12-02 06:24:22,728 INFO L226 Difference]: Without dead ends: 24483 [2024-12-02 06:24:22,738 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:24:22,739 INFO L435 NwaCegarLoop]: 1008 mSDtfsCounter, 2000 mSDsluCounter, 2543 mSDsCounter, 0 mSdLazyCounter, 2604 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2005 SdHoareTripleChecker+Valid, 3551 SdHoareTripleChecker+Invalid, 2612 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 2604 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:22,739 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2005 Valid, 3551 Invalid, 2612 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 2604 Invalid, 0 Unknown, 0 Unchecked, 1.3s Time] [2024-12-02 06:24:22,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24483 states. [2024-12-02 06:24:23,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24483 to 23181. [2024-12-02 06:24:23,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23181 states, 22819 states have (on average 1.358473202156098) internal successors, (30999), 22819 states have internal predecessors, (30999), 360 states have call successors, (360), 1 states have call predecessors, (360), 1 states have return successors, (360), 360 states have call predecessors, (360), 360 states have call successors, (360) [2024-12-02 06:24:23,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23181 states to 23181 states and 31719 transitions. [2024-12-02 06:24:23,350 INFO L78 Accepts]: Start accepts. Automaton has 23181 states and 31719 transitions. Word has length 897 [2024-12-02 06:24:23,351 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:23,351 INFO L471 AbstractCegarLoop]: Abstraction has 23181 states and 31719 transitions. [2024-12-02 06:24:23,351 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 112.5) internal successors, (675), 6 states have internal predecessors, (675), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-12-02 06:24:23,351 INFO L276 IsEmpty]: Start isEmpty. Operand 23181 states and 31719 transitions. [2024-12-02 06:24:23,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 898 [2024-12-02 06:24:23,370 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:23,371 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:23,371 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable87 [2024-12-02 06:24:23,371 INFO L396 AbstractCegarLoop]: === Iteration 89 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:23,371 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:23,372 INFO L85 PathProgramCache]: Analyzing trace with hash -974885164, now seen corresponding path program 1 times [2024-12-02 06:24:23,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:23,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386090103] [2024-12-02 06:24:23,372 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:23,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:28,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:31,788 INFO L134 CoverageAnalysis]: Checked inductivity of 518 backedges. 108 proven. 0 refuted. 0 times theorem prover too weak. 410 trivial. 0 not checked. [2024-12-02 06:24:31,788 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:31,788 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [386090103] [2024-12-02 06:24:31,788 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [386090103] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:24:31,788 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:24:31,788 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 06:24:31,788 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213772723] [2024-12-02 06:24:31,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:31,789 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:24:31,789 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:31,790 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:24:31,790 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2024-12-02 06:24:31,790 INFO L87 Difference]: Start difference. First operand 23181 states and 31719 transitions. Second operand has 8 states, 8 states have (on average 94.5) internal successors, (756), 8 states have internal predecessors, (756), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:34,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:34,227 INFO L93 Difference]: Finished difference Result 27366 states and 37489 transitions. [2024-12-02 06:24:34,227 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 06:24:34,228 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 94.5) internal successors, (756), 8 states have internal predecessors, (756), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 897 [2024-12-02 06:24:34,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:34,248 INFO L225 Difference]: With dead ends: 27366 [2024-12-02 06:24:34,248 INFO L226 Difference]: Without dead ends: 23181 [2024-12-02 06:24:34,255 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=61, Unknown=0, NotChecked=0, Total=90 [2024-12-02 06:24:34,256 INFO L435 NwaCegarLoop]: 997 mSDtfsCounter, 1617 mSDsluCounter, 4336 mSDsCounter, 0 mSdLazyCounter, 3971 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1617 SdHoareTripleChecker+Valid, 5333 SdHoareTripleChecker+Invalid, 3973 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3971 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.9s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:34,256 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1617 Valid, 5333 Invalid, 3973 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3971 Invalid, 0 Unknown, 0 Unchecked, 1.9s Time] [2024-12-02 06:24:34,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23181 states. [2024-12-02 06:24:34,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23181 to 22978. [2024-12-02 06:24:34,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22978 states, 22616 states have (on average 1.3574460558896357) internal successors, (30700), 22616 states have internal predecessors, (30700), 360 states have call successors, (360), 1 states have call predecessors, (360), 1 states have return successors, (360), 360 states have call predecessors, (360), 360 states have call successors, (360) [2024-12-02 06:24:34,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22978 states to 22978 states and 31420 transitions. [2024-12-02 06:24:34,976 INFO L78 Accepts]: Start accepts. Automaton has 22978 states and 31420 transitions. Word has length 897 [2024-12-02 06:24:34,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:34,977 INFO L471 AbstractCegarLoop]: Abstraction has 22978 states and 31420 transitions. [2024-12-02 06:24:34,977 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 94.5) internal successors, (756), 8 states have internal predecessors, (756), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:24:34,977 INFO L276 IsEmpty]: Start isEmpty. Operand 22978 states and 31420 transitions. [2024-12-02 06:24:34,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 898 [2024-12-02 06:24:34,996 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:34,997 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:34,997 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable88 [2024-12-02 06:24:34,997 INFO L396 AbstractCegarLoop]: === Iteration 90 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:34,998 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:34,998 INFO L85 PathProgramCache]: Analyzing trace with hash -112617734, now seen corresponding path program 1 times [2024-12-02 06:24:34,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:34,998 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [30401550] [2024-12-02 06:24:34,998 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:34,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:43,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:44,392 INFO L134 CoverageAnalysis]: Checked inductivity of 518 backedges. 48 proven. 24 refuted. 0 times theorem prover too weak. 446 trivial. 0 not checked. [2024-12-02 06:24:44,392 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:44,392 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [30401550] [2024-12-02 06:24:44,392 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [30401550] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:24:44,392 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [969367959] [2024-12-02 06:24:44,393 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:44,393 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:24:44,393 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:24:44,394 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:24:44,395 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2024-12-02 06:24:53,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:53,431 INFO L256 TraceCheckSpWp]: Trace formula consists of 4519 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 06:24:53,440 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:24:53,476 INFO L134 CoverageAnalysis]: Checked inductivity of 518 backedges. 151 proven. 0 refuted. 0 times theorem prover too weak. 367 trivial. 0 not checked. [2024-12-02 06:24:53,476 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:24:53,476 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [969367959] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:24:53,476 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:24:53,477 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 9 [2024-12-02 06:24:53,477 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1950184004] [2024-12-02 06:24:53,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:53,477 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:24:53,477 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:53,478 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:24:53,478 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:24:53,478 INFO L87 Difference]: Start difference. First operand 22978 states and 31420 transitions. Second operand has 6 states, 5 states have (on average 144.2) internal successors, (721), 6 states have internal predecessors, (721), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) [2024-12-02 06:24:54,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:54,076 INFO L93 Difference]: Finished difference Result 33725 states and 46447 transitions. [2024-12-02 06:24:54,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:24:54,077 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 144.2) internal successors, (721), 6 states have internal predecessors, (721), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) Word has length 897 [2024-12-02 06:24:54,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:54,096 INFO L225 Difference]: With dead ends: 33725 [2024-12-02 06:24:54,097 INFO L226 Difference]: Without dead ends: 22978 [2024-12-02 06:24:54,107 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 902 GetRequests, 895 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:24:54,107 INFO L435 NwaCegarLoop]: 1681 mSDtfsCounter, 0 mSDsluCounter, 6705 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 8386 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:54,107 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 8386 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:24:54,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22978 states. [2024-12-02 06:24:54,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22978 to 22978. [2024-12-02 06:24:54,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22978 states, 22616 states have (on average 1.3549699327909444) internal successors, (30644), 22616 states have internal predecessors, (30644), 360 states have call successors, (360), 1 states have call predecessors, (360), 1 states have return successors, (360), 360 states have call predecessors, (360), 360 states have call successors, (360) [2024-12-02 06:24:54,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22978 states to 22978 states and 31364 transitions. [2024-12-02 06:24:54,782 INFO L78 Accepts]: Start accepts. Automaton has 22978 states and 31364 transitions. Word has length 897 [2024-12-02 06:24:54,782 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:54,783 INFO L471 AbstractCegarLoop]: Abstraction has 22978 states and 31364 transitions. [2024-12-02 06:24:54,783 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 144.2) internal successors, (721), 6 states have internal predecessors, (721), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) [2024-12-02 06:24:54,783 INFO L276 IsEmpty]: Start isEmpty. Operand 22978 states and 31364 transitions. [2024-12-02 06:24:54,802 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 900 [2024-12-02 06:24:54,803 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:54,803 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:54,857 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Forceful destruction successful, exit code 0 [2024-12-02 06:24:55,003 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 61 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable89 [2024-12-02 06:24:55,003 INFO L396 AbstractCegarLoop]: === Iteration 91 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:55,004 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:55,004 INFO L85 PathProgramCache]: Analyzing trace with hash -1664882956, now seen corresponding path program 1 times [2024-12-02 06:24:55,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:55,004 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473661403] [2024-12-02 06:24:55,004 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:55,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:24:55,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:24:56,343 INFO L134 CoverageAnalysis]: Checked inductivity of 519 backedges. 51 proven. 0 refuted. 0 times theorem prover too weak. 468 trivial. 0 not checked. [2024-12-02 06:24:56,343 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:24:56,343 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473661403] [2024-12-02 06:24:56,343 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1473661403] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:24:56,343 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:24:56,344 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:24:56,344 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1726420258] [2024-12-02 06:24:56,344 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:24:56,344 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:24:56,344 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:24:56,345 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:24:56,345 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:24:56,345 INFO L87 Difference]: Start difference. First operand 22978 states and 31364 transitions. Second operand has 5 states, 5 states have (on average 141.4) internal successors, (707), 5 states have internal predecessors, (707), 2 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) [2024-12-02 06:24:57,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:24:57,396 INFO L93 Difference]: Finished difference Result 54226 states and 73882 transitions. [2024-12-02 06:24:57,397 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:24:57,397 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 141.4) internal successors, (707), 5 states have internal predecessors, (707), 2 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) Word has length 899 [2024-12-02 06:24:57,397 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:24:57,429 INFO L225 Difference]: With dead ends: 54226 [2024-12-02 06:24:57,429 INFO L226 Difference]: Without dead ends: 42679 [2024-12-02 06:24:57,443 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:24:57,443 INFO L435 NwaCegarLoop]: 1690 mSDtfsCounter, 917 mSDsluCounter, 5038 mSDsCounter, 0 mSdLazyCounter, 67 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 920 SdHoareTripleChecker+Valid, 6728 SdHoareTripleChecker+Invalid, 67 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 67 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:24:57,443 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [920 Valid, 6728 Invalid, 67 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 67 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:24:57,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42679 states. [2024-12-02 06:24:58,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42679 to 32546. [2024-12-02 06:24:58,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32546 states, 31992 states have (on average 1.330207551887972) internal successors, (42556), 31992 states have internal predecessors, (42556), 552 states have call successors, (552), 1 states have call predecessors, (552), 1 states have return successors, (552), 552 states have call predecessors, (552), 552 states have call successors, (552) [2024-12-02 06:24:58,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32546 states to 32546 states and 43660 transitions. [2024-12-02 06:24:58,330 INFO L78 Accepts]: Start accepts. Automaton has 32546 states and 43660 transitions. Word has length 899 [2024-12-02 06:24:58,330 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:24:58,330 INFO L471 AbstractCegarLoop]: Abstraction has 32546 states and 43660 transitions. [2024-12-02 06:24:58,381 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 141.4) internal successors, (707), 5 states have internal predecessors, (707), 2 states have call successors, (7), 1 states have call predecessors, (7), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) [2024-12-02 06:24:58,382 INFO L276 IsEmpty]: Start isEmpty. Operand 32546 states and 43660 transitions. [2024-12-02 06:24:58,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 900 [2024-12-02 06:24:58,403 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:24:58,404 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:24:58,404 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable90 [2024-12-02 06:24:58,404 INFO L396 AbstractCegarLoop]: === Iteration 92 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:24:58,404 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:24:58,404 INFO L85 PathProgramCache]: Analyzing trace with hash -1974329772, now seen corresponding path program 1 times [2024-12-02 06:24:58,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:24:58,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [846907794] [2024-12-02 06:24:58,404 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:24:58,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:07,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:08,186 INFO L134 CoverageAnalysis]: Checked inductivity of 519 backedges. 48 proven. 24 refuted. 0 times theorem prover too weak. 447 trivial. 0 not checked. [2024-12-02 06:25:08,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:08,187 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [846907794] [2024-12-02 06:25:08,187 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [846907794] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:25:08,187 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1885766138] [2024-12-02 06:25:08,187 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:08,187 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:25:08,187 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:25:08,188 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:25:08,189 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2024-12-02 06:25:16,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:16,590 INFO L256 TraceCheckSpWp]: Trace formula consists of 4525 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-12-02 06:25:16,599 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:25:17,135 INFO L134 CoverageAnalysis]: Checked inductivity of 519 backedges. 203 proven. 0 refuted. 0 times theorem prover too weak. 316 trivial. 0 not checked. [2024-12-02 06:25:17,136 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:25:17,136 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1885766138] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:17,136 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:25:17,136 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [6] total 12 [2024-12-02 06:25:17,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1199183786] [2024-12-02 06:25:17,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:17,136 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 06:25:17,136 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:17,137 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 06:25:17,137 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:25:17,137 INFO L87 Difference]: Start difference. First operand 32546 states and 43660 transitions. Second operand has 8 states, 8 states have (on average 94.75) internal successors, (758), 8 states have internal predecessors, (758), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:20,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:20,466 INFO L93 Difference]: Finished difference Result 68165 states and 91533 transitions. [2024-12-02 06:25:20,466 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 06:25:20,466 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 94.75) internal successors, (758), 8 states have internal predecessors, (758), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 899 [2024-12-02 06:25:20,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:20,514 INFO L225 Difference]: With dead ends: 68165 [2024-12-02 06:25:20,514 INFO L226 Difference]: Without dead ends: 61114 [2024-12-02 06:25:20,528 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 906 GetRequests, 894 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=37, Invalid=145, Unknown=0, NotChecked=0, Total=182 [2024-12-02 06:25:20,528 INFO L435 NwaCegarLoop]: 1020 mSDtfsCounter, 3866 mSDsluCounter, 5059 mSDsCounter, 0 mSdLazyCounter, 4078 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3876 SdHoareTripleChecker+Valid, 6079 SdHoareTripleChecker+Invalid, 4083 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 4078 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:20,528 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3876 Valid, 6079 Invalid, 4083 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 4078 Invalid, 0 Unknown, 0 Unchecked, 2.0s Time] [2024-12-02 06:25:20,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61114 states. [2024-12-02 06:25:21,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61114 to 57644. [2024-12-02 06:25:21,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57644 states, 56610 states have (on average 1.3268327150680093) internal successors, (75112), 56610 states have internal predecessors, (75112), 1032 states have call successors, (1032), 1 states have call predecessors, (1032), 1 states have return successors, (1032), 1032 states have call predecessors, (1032), 1032 states have call successors, (1032) [2024-12-02 06:25:22,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57644 states to 57644 states and 77176 transitions. [2024-12-02 06:25:22,039 INFO L78 Accepts]: Start accepts. Automaton has 57644 states and 77176 transitions. Word has length 899 [2024-12-02 06:25:22,039 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:22,039 INFO L471 AbstractCegarLoop]: Abstraction has 57644 states and 77176 transitions. [2024-12-02 06:25:22,039 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 94.75) internal successors, (758), 8 states have internal predecessors, (758), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-12-02 06:25:22,039 INFO L276 IsEmpty]: Start isEmpty. Operand 57644 states and 77176 transitions. [2024-12-02 06:25:22,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 901 [2024-12-02 06:25:22,093 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:22,093 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:22,153 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Ended with exit code 0 [2024-12-02 06:25:22,293 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable91,62 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:25:22,294 INFO L396 AbstractCegarLoop]: === Iteration 93 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:22,294 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:22,294 INFO L85 PathProgramCache]: Analyzing trace with hash -1283070514, now seen corresponding path program 1 times [2024-12-02 06:25:22,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:22,294 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097234179] [2024-12-02 06:25:22,294 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:22,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:30,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:31,481 INFO L134 CoverageAnalysis]: Checked inductivity of 519 backedges. 48 proven. 24 refuted. 0 times theorem prover too weak. 447 trivial. 0 not checked. [2024-12-02 06:25:31,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:31,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097234179] [2024-12-02 06:25:31,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1097234179] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:25:31,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1286441683] [2024-12-02 06:25:31,481 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:31,482 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:25:31,482 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:25:31,483 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:25:31,484 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2024-12-02 06:25:40,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:40,728 INFO L256 TraceCheckSpWp]: Trace formula consists of 4528 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 06:25:40,736 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:25:40,775 INFO L134 CoverageAnalysis]: Checked inductivity of 519 backedges. 97 proven. 0 refuted. 0 times theorem prover too weak. 422 trivial. 0 not checked. [2024-12-02 06:25:40,775 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:25:40,775 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1286441683] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:25:40,775 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:25:40,775 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 9 [2024-12-02 06:25:40,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2086094056] [2024-12-02 06:25:40,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:25:40,776 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:25:40,776 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:25:40,776 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:25:40,776 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:25:40,776 INFO L87 Difference]: Start difference. First operand 57644 states and 77176 transitions. Second operand has 6 states, 5 states have (on average 139.4) internal successors, (697), 6 states have internal predecessors, (697), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) [2024-12-02 06:25:41,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:25:41,988 INFO L93 Difference]: Finished difference Result 72439 states and 97867 transitions. [2024-12-02 06:25:41,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:25:41,988 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 139.4) internal successors, (697), 6 states have internal predecessors, (697), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) Word has length 900 [2024-12-02 06:25:41,989 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:25:42,046 INFO L225 Difference]: With dead ends: 72439 [2024-12-02 06:25:42,046 INFO L226 Difference]: Without dead ends: 57644 [2024-12-02 06:25:42,068 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 905 GetRequests, 898 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-12-02 06:25:42,069 INFO L435 NwaCegarLoop]: 1680 mSDtfsCounter, 0 mSDsluCounter, 6701 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 8381 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:25:42,069 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 8381 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:25:42,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57644 states. [2024-12-02 06:25:43,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57644 to 57644. [2024-12-02 06:25:43,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57644 states, 56610 states have (on average 1.3249955838191132) internal successors, (75008), 56610 states have internal predecessors, (75008), 1032 states have call successors, (1032), 1 states have call predecessors, (1032), 1 states have return successors, (1032), 1032 states have call predecessors, (1032), 1032 states have call successors, (1032) [2024-12-02 06:25:43,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57644 states to 57644 states and 77072 transitions. [2024-12-02 06:25:43,562 INFO L78 Accepts]: Start accepts. Automaton has 57644 states and 77072 transitions. Word has length 900 [2024-12-02 06:25:43,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:25:43,563 INFO L471 AbstractCegarLoop]: Abstraction has 57644 states and 77072 transitions. [2024-12-02 06:25:43,563 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 139.4) internal successors, (697), 6 states have internal predecessors, (697), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) [2024-12-02 06:25:43,563 INFO L276 IsEmpty]: Start isEmpty. Operand 57644 states and 77072 transitions. [2024-12-02 06:25:43,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 901 [2024-12-02 06:25:43,616 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:25:43,616 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:25:43,661 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Ended with exit code 0 [2024-12-02 06:25:43,816 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable92,63 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:25:43,817 INFO L396 AbstractCegarLoop]: === Iteration 94 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:25:43,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:25:43,817 INFO L85 PathProgramCache]: Analyzing trace with hash 687124750, now seen corresponding path program 1 times [2024-12-02 06:25:43,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:25:43,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773373234] [2024-12-02 06:25:43,817 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:43,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:25:48,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:51,323 INFO L134 CoverageAnalysis]: Checked inductivity of 519 backedges. 44 proven. 1 refuted. 0 times theorem prover too weak. 474 trivial. 0 not checked. [2024-12-02 06:25:51,323 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:25:51,323 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [773373234] [2024-12-02 06:25:51,324 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [773373234] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:25:51,324 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [382387687] [2024-12-02 06:25:51,324 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:25:51,324 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:25:51,324 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:25:51,325 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:25:51,326 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2024-12-02 06:25:58,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:25:58,044 INFO L256 TraceCheckSpWp]: Trace formula consists of 4528 conjuncts, 145 conjuncts are in the unsatisfiable core [2024-12-02 06:25:58,058 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:25:59,737 INFO L134 CoverageAnalysis]: Checked inductivity of 519 backedges. 152 proven. 19 refuted. 0 times theorem prover too weak. 348 trivial. 0 not checked. [2024-12-02 06:25:59,738 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:26:01,834 INFO L134 CoverageAnalysis]: Checked inductivity of 519 backedges. 127 proven. 9 refuted. 0 times theorem prover too weak. 383 trivial. 0 not checked. [2024-12-02 06:26:01,835 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [382387687] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:26:01,835 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:26:01,835 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 17, 21] total 41 [2024-12-02 06:26:01,835 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1431521226] [2024-12-02 06:26:01,835 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:26:01,836 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 41 states [2024-12-02 06:26:01,836 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:26:01,837 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2024-12-02 06:26:01,837 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=196, Invalid=1444, Unknown=0, NotChecked=0, Total=1640 [2024-12-02 06:26:01,838 INFO L87 Difference]: Start difference. First operand 57644 states and 77072 transitions. Second operand has 41 states, 40 states have (on average 52.375) internal successors, (2095), 41 states have internal predecessors, (2095), 9 states have call successors, (23), 2 states have call predecessors, (23), 3 states have return successors, (23), 8 states have call predecessors, (23), 9 states have call successors, (23) [2024-12-02 06:26:16,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:26:16,092 INFO L93 Difference]: Finished difference Result 91801 states and 124577 transitions. [2024-12-02 06:26:16,092 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2024-12-02 06:26:16,093 INFO L78 Accepts]: Start accepts. Automaton has has 41 states, 40 states have (on average 52.375) internal successors, (2095), 41 states have internal predecessors, (2095), 9 states have call successors, (23), 2 states have call predecessors, (23), 3 states have return successors, (23), 8 states have call predecessors, (23), 9 states have call successors, (23) Word has length 900 [2024-12-02 06:26:16,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:26:16,143 INFO L225 Difference]: With dead ends: 91801 [2024-12-02 06:26:16,143 INFO L226 Difference]: Without dead ends: 75774 [2024-12-02 06:26:16,161 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1842 GetRequests, 1766 SyntacticMatches, 0 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1461 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=765, Invalid=5241, Unknown=0, NotChecked=0, Total=6006 [2024-12-02 06:26:16,161 INFO L435 NwaCegarLoop]: 1488 mSDtfsCounter, 4011 mSDsluCounter, 38326 mSDsCounter, 0 mSdLazyCounter, 25493 mSolverCounterSat, 38 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 9.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4018 SdHoareTripleChecker+Valid, 39814 SdHoareTripleChecker+Invalid, 25531 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 38 IncrementalHoareTripleChecker+Valid, 25493 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 11.2s IncrementalHoareTripleChecker+Time [2024-12-02 06:26:16,161 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4018 Valid, 39814 Invalid, 25531 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [38 Valid, 25493 Invalid, 0 Unknown, 0 Unchecked, 11.2s Time] [2024-12-02 06:26:16,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75774 states. [2024-12-02 06:26:18,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75774 to 74640. [2024-12-02 06:26:18,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74640 states, 73206 states have (on average 1.3355462666994509) internal successors, (97770), 73206 states have internal predecessors, (97770), 1432 states have call successors, (1432), 1 states have call predecessors, (1432), 1 states have return successors, (1432), 1432 states have call predecessors, (1432), 1432 states have call successors, (1432) [2024-12-02 06:26:18,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74640 states to 74640 states and 100634 transitions. [2024-12-02 06:26:18,341 INFO L78 Accepts]: Start accepts. Automaton has 74640 states and 100634 transitions. Word has length 900 [2024-12-02 06:26:18,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:26:18,341 INFO L471 AbstractCegarLoop]: Abstraction has 74640 states and 100634 transitions. [2024-12-02 06:26:18,341 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 41 states, 40 states have (on average 52.375) internal successors, (2095), 41 states have internal predecessors, (2095), 9 states have call successors, (23), 2 states have call predecessors, (23), 3 states have return successors, (23), 8 states have call predecessors, (23), 9 states have call successors, (23) [2024-12-02 06:26:18,341 INFO L276 IsEmpty]: Start isEmpty. Operand 74640 states and 100634 transitions. [2024-12-02 06:26:18,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 903 [2024-12-02 06:26:18,400 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:26:18,400 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:26:18,439 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Ended with exit code 0 [2024-12-02 06:26:18,600 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable93,64 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:26:18,600 INFO L396 AbstractCegarLoop]: === Iteration 95 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:26:18,601 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:26:18,601 INFO L85 PathProgramCache]: Analyzing trace with hash -497627218, now seen corresponding path program 1 times [2024-12-02 06:26:18,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:26:18,601 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [875255471] [2024-12-02 06:26:18,601 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:18,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:26:26,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:27,659 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 48 proven. 24 refuted. 0 times theorem prover too weak. 448 trivial. 0 not checked. [2024-12-02 06:26:27,659 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:26:27,659 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [875255471] [2024-12-02 06:26:27,659 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [875255471] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:26:27,659 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2093186407] [2024-12-02 06:26:27,659 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:27,659 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:26:27,659 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:26:27,661 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:26:27,661 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2024-12-02 06:26:40,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:40,523 INFO L256 TraceCheckSpWp]: Trace formula consists of 4534 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 06:26:40,532 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:26:40,552 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2024-12-02 06:26:40,552 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:26:40,552 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2093186407] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:26:40,552 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:26:40,552 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 7 [2024-12-02 06:26:40,552 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1859995129] [2024-12-02 06:26:40,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:26:40,553 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:26:40,553 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:26:40,553 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:26:40,553 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:26:40,553 INFO L87 Difference]: Start difference. First operand 74640 states and 100634 transitions. Second operand has 6 states, 5 states have (on average 142.0) internal successors, (710), 6 states have internal predecessors, (710), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) [2024-12-02 06:26:42,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:26:42,465 INFO L93 Difference]: Finished difference Result 112607 states and 152895 transitions. [2024-12-02 06:26:42,465 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:26:42,466 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 142.0) internal successors, (710), 6 states have internal predecessors, (710), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) Word has length 902 [2024-12-02 06:26:42,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:26:42,534 INFO L225 Difference]: With dead ends: 112607 [2024-12-02 06:26:42,534 INFO L226 Difference]: Without dead ends: 74640 [2024-12-02 06:26:42,564 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 907 GetRequests, 902 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:26:42,564 INFO L435 NwaCegarLoop]: 1679 mSDtfsCounter, 0 mSDsluCounter, 6697 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 8376 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:26:42,564 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 8376 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:26:42,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74640 states. [2024-12-02 06:26:44,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74640 to 74640. [2024-12-02 06:26:44,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74640 states, 73206 states have (on average 1.3312843209572987) internal successors, (97458), 73206 states have internal predecessors, (97458), 1432 states have call successors, (1432), 1 states have call predecessors, (1432), 1 states have return successors, (1432), 1432 states have call predecessors, (1432), 1432 states have call successors, (1432) [2024-12-02 06:26:44,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74640 states to 74640 states and 100322 transitions. [2024-12-02 06:26:44,613 INFO L78 Accepts]: Start accepts. Automaton has 74640 states and 100322 transitions. Word has length 902 [2024-12-02 06:26:44,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:26:44,613 INFO L471 AbstractCegarLoop]: Abstraction has 74640 states and 100322 transitions. [2024-12-02 06:26:44,613 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 142.0) internal successors, (710), 6 states have internal predecessors, (710), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) [2024-12-02 06:26:44,613 INFO L276 IsEmpty]: Start isEmpty. Operand 74640 states and 100322 transitions. [2024-12-02 06:26:44,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 904 [2024-12-02 06:26:44,672 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:26:44,672 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:26:44,714 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Ended with exit code 0 [2024-12-02 06:26:44,872 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable94,65 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:26:44,872 INFO L396 AbstractCegarLoop]: === Iteration 96 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:26:44,873 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:26:44,873 INFO L85 PathProgramCache]: Analyzing trace with hash -1660398245, now seen corresponding path program 1 times [2024-12-02 06:26:44,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:26:44,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952902210] [2024-12-02 06:26:44,873 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:44,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:26:45,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:26:46,295 INFO L134 CoverageAnalysis]: Checked inductivity of 519 backedges. 35 proven. 0 refuted. 0 times theorem prover too weak. 484 trivial. 0 not checked. [2024-12-02 06:26:46,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:26:46,295 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952902210] [2024-12-02 06:26:46,295 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952902210] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:26:46,295 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 06:26:46,296 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 06:26:46,296 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1574358750] [2024-12-02 06:26:46,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:26:46,296 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 06:26:46,296 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:26:46,296 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 06:26:46,296 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 06:26:46,297 INFO L87 Difference]: Start difference. First operand 74640 states and 100322 transitions. Second operand has 5 states, 5 states have (on average 139.8) internal successors, (699), 5 states have internal predecessors, (699), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:26:48,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:26:48,281 INFO L93 Difference]: Finished difference Result 91224 states and 122962 transitions. [2024-12-02 06:26:48,281 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 06:26:48,282 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 139.8) internal successors, (699), 5 states have internal predecessors, (699), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 903 [2024-12-02 06:26:48,282 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:26:48,348 INFO L225 Difference]: With dead ends: 91224 [2024-12-02 06:26:48,348 INFO L226 Difference]: Without dead ends: 74659 [2024-12-02 06:26:48,365 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-12-02 06:26:48,366 INFO L435 NwaCegarLoop]: 2163 mSDtfsCounter, 736 mSDsluCounter, 5983 mSDsCounter, 0 mSdLazyCounter, 64 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 740 SdHoareTripleChecker+Valid, 8146 SdHoareTripleChecker+Invalid, 64 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 64 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 06:26:48,366 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [740 Valid, 8146 Invalid, 64 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 64 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 06:26:48,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74659 states. [2024-12-02 06:26:50,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74659 to 74250. [2024-12-02 06:26:50,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74250 states, 72816 states have (on average 1.328444297956493) internal successors, (96732), 72816 states have internal predecessors, (96732), 1432 states have call successors, (1432), 1 states have call predecessors, (1432), 1 states have return successors, (1432), 1432 states have call predecessors, (1432), 1432 states have call successors, (1432) [2024-12-02 06:26:50,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74250 states to 74250 states and 99596 transitions. [2024-12-02 06:26:50,524 INFO L78 Accepts]: Start accepts. Automaton has 74250 states and 99596 transitions. Word has length 903 [2024-12-02 06:26:50,524 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:26:50,524 INFO L471 AbstractCegarLoop]: Abstraction has 74250 states and 99596 transitions. [2024-12-02 06:26:50,524 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 139.8) internal successors, (699), 5 states have internal predecessors, (699), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:26:50,524 INFO L276 IsEmpty]: Start isEmpty. Operand 74250 states and 99596 transitions. [2024-12-02 06:26:50,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 905 [2024-12-02 06:26:50,657 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:26:50,657 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:26:50,657 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable95 [2024-12-02 06:26:50,657 INFO L396 AbstractCegarLoop]: === Iteration 97 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:26:50,658 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:26:50,658 INFO L85 PathProgramCache]: Analyzing trace with hash 737297480, now seen corresponding path program 1 times [2024-12-02 06:26:50,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:26:50,658 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829380233] [2024-12-02 06:26:50,658 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:26:50,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:26:59,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:02,514 INFO L134 CoverageAnalysis]: Checked inductivity of 521 backedges. 33 proven. 78 refuted. 0 times theorem prover too weak. 410 trivial. 0 not checked. [2024-12-02 06:27:02,514 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:27:02,514 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [829380233] [2024-12-02 06:27:02,514 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [829380233] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:27:02,514 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [245977681] [2024-12-02 06:27:02,515 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:27:02,515 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:27:02,515 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:27:02,516 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:27:02,517 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2024-12-02 06:27:17,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:17,448 INFO L256 TraceCheckSpWp]: Trace formula consists of 4540 conjuncts, 92 conjuncts are in the unsatisfiable core [2024-12-02 06:27:17,459 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:27:20,257 INFO L134 CoverageAnalysis]: Checked inductivity of 521 backedges. 69 proven. 83 refuted. 0 times theorem prover too weak. 369 trivial. 0 not checked. [2024-12-02 06:27:20,257 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:27:26,166 INFO L134 CoverageAnalysis]: Checked inductivity of 521 backedges. 34 proven. 77 refuted. 0 times theorem prover too weak. 410 trivial. 0 not checked. [2024-12-02 06:27:26,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [245977681] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:27:26,166 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:27:26,167 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 21, 16] total 36 [2024-12-02 06:27:26,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1689643966] [2024-12-02 06:27:26,167 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:27:26,168 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2024-12-02 06:27:26,168 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:27:26,169 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2024-12-02 06:27:26,169 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=184, Invalid=1076, Unknown=0, NotChecked=0, Total=1260 [2024-12-02 06:27:26,170 INFO L87 Difference]: Start difference. First operand 74250 states and 99596 transitions. Second operand has 36 states, 36 states have (on average 56.94444444444444) internal successors, (2050), 36 states have internal predecessors, (2050), 6 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 6 states have call predecessors, (20), 6 states have call successors, (20) [2024-12-02 06:27:34,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:27:34,437 INFO L93 Difference]: Finished difference Result 92431 states and 124532 transitions. [2024-12-02 06:27:34,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2024-12-02 06:27:34,438 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 36 states have (on average 56.94444444444444) internal successors, (2050), 36 states have internal predecessors, (2050), 6 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 6 states have call predecessors, (20), 6 states have call successors, (20) Word has length 904 [2024-12-02 06:27:34,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:27:34,495 INFO L225 Difference]: With dead ends: 92431 [2024-12-02 06:27:34,495 INFO L226 Difference]: Without dead ends: 84820 [2024-12-02 06:27:34,511 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1837 GetRequests, 1780 SyntacticMatches, 0 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 832 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=550, Invalid=2872, Unknown=0, NotChecked=0, Total=3422 [2024-12-02 06:27:34,512 INFO L435 NwaCegarLoop]: 1069 mSDtfsCounter, 4344 mSDsluCounter, 16041 mSDsCounter, 0 mSdLazyCounter, 13012 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 4.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4349 SdHoareTripleChecker+Valid, 17110 SdHoareTripleChecker+Invalid, 13024 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 13012 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 5.7s IncrementalHoareTripleChecker+Time [2024-12-02 06:27:34,512 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4349 Valid, 17110 Invalid, 13024 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [12 Valid, 13012 Invalid, 0 Unknown, 0 Unchecked, 5.7s Time] [2024-12-02 06:27:34,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84820 states. [2024-12-02 06:27:36,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84820 to 84532. [2024-12-02 06:27:36,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84532 states, 83026 states have (on average 1.3334015850456484) internal successors, (110707), 83026 states have internal predecessors, (110707), 1504 states have call successors, (1504), 1 states have call predecessors, (1504), 1 states have return successors, (1504), 1504 states have call predecessors, (1504), 1504 states have call successors, (1504) [2024-12-02 06:27:36,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84532 states to 84532 states and 113715 transitions. [2024-12-02 06:27:36,932 INFO L78 Accepts]: Start accepts. Automaton has 84532 states and 113715 transitions. Word has length 904 [2024-12-02 06:27:36,933 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:27:36,933 INFO L471 AbstractCegarLoop]: Abstraction has 84532 states and 113715 transitions. [2024-12-02 06:27:36,933 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 36 states have (on average 56.94444444444444) internal successors, (2050), 36 states have internal predecessors, (2050), 6 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 6 states have call predecessors, (20), 6 states have call successors, (20) [2024-12-02 06:27:36,933 INFO L276 IsEmpty]: Start isEmpty. Operand 84532 states and 113715 transitions. [2024-12-02 06:27:36,995 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 905 [2024-12-02 06:27:36,995 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:27:36,995 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:27:37,038 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Ended with exit code 0 [2024-12-02 06:27:37,195 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable96,66 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:27:37,196 INFO L396 AbstractCegarLoop]: === Iteration 98 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:27:37,196 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:27:37,196 INFO L85 PathProgramCache]: Analyzing trace with hash 1488007848, now seen corresponding path program 1 times [2024-12-02 06:27:37,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:27:37,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68626622] [2024-12-02 06:27:37,196 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:27:37,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:27:43,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:46,246 INFO L134 CoverageAnalysis]: Checked inductivity of 519 backedges. 41 proven. 3 refuted. 0 times theorem prover too weak. 475 trivial. 0 not checked. [2024-12-02 06:27:46,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:27:46,247 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [68626622] [2024-12-02 06:27:46,247 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [68626622] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:27:46,247 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1512592945] [2024-12-02 06:27:46,247 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:27:46,247 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:27:46,247 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:27:46,248 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:27:46,249 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2024-12-02 06:27:58,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:27:58,218 INFO L256 TraceCheckSpWp]: Trace formula consists of 4540 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 06:27:58,225 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:27:58,268 INFO L134 CoverageAnalysis]: Checked inductivity of 519 backedges. 56 proven. 0 refuted. 0 times theorem prover too weak. 463 trivial. 0 not checked. [2024-12-02 06:27:58,268 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:27:58,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1512592945] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:27:58,268 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:27:58,269 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 12 [2024-12-02 06:27:58,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1422505415] [2024-12-02 06:27:58,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:27:58,269 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:27:58,269 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:27:58,269 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:27:58,270 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=109, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:27:58,270 INFO L87 Difference]: Start difference. First operand 84532 states and 113715 transitions. Second operand has 6 states, 5 states have (on average 138.4) internal successors, (692), 6 states have internal predecessors, (692), 2 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:28:00,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:28:00,515 INFO L93 Difference]: Finished difference Result 118719 states and 161753 transitions. [2024-12-02 06:28:00,516 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:28:00,516 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 138.4) internal successors, (692), 6 states have internal predecessors, (692), 2 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 904 [2024-12-02 06:28:00,517 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:28:00,584 INFO L225 Difference]: With dead ends: 118719 [2024-12-02 06:28:00,584 INFO L226 Difference]: Without dead ends: 84532 [2024-12-02 06:28:00,614 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 911 GetRequests, 901 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=109, Unknown=0, NotChecked=0, Total=132 [2024-12-02 06:28:00,614 INFO L435 NwaCegarLoop]: 1680 mSDtfsCounter, 0 mSDsluCounter, 6697 mSDsCounter, 0 mSdLazyCounter, 53 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 8377 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 53 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:28:00,614 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 8377 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 53 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:28:00,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84532 states. [2024-12-02 06:28:03,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84532 to 84532. [2024-12-02 06:28:03,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84532 states, 83026 states have (on average 1.3308963457230265) internal successors, (110499), 83026 states have internal predecessors, (110499), 1504 states have call successors, (1504), 1 states have call predecessors, (1504), 1 states have return successors, (1504), 1504 states have call predecessors, (1504), 1504 states have call successors, (1504) [2024-12-02 06:28:03,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84532 states to 84532 states and 113507 transitions. [2024-12-02 06:28:03,172 INFO L78 Accepts]: Start accepts. Automaton has 84532 states and 113507 transitions. Word has length 904 [2024-12-02 06:28:03,173 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:28:03,173 INFO L471 AbstractCegarLoop]: Abstraction has 84532 states and 113507 transitions. [2024-12-02 06:28:03,173 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 138.4) internal successors, (692), 6 states have internal predecessors, (692), 2 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 06:28:03,173 INFO L276 IsEmpty]: Start isEmpty. Operand 84532 states and 113507 transitions. [2024-12-02 06:28:03,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 905 [2024-12-02 06:28:03,238 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:28:03,239 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:28:03,281 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Ended with exit code 0 [2024-12-02 06:28:03,439 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 67 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable97 [2024-12-02 06:28:03,439 INFO L396 AbstractCegarLoop]: === Iteration 99 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:28:03,439 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:28:03,440 INFO L85 PathProgramCache]: Analyzing trace with hash 900928263, now seen corresponding path program 1 times [2024-12-02 06:28:03,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:28:03,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892644986] [2024-12-02 06:28:03,440 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:28:03,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:28:11,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:28:12,852 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 95 proven. 12 refuted. 0 times theorem prover too weak. 413 trivial. 0 not checked. [2024-12-02 06:28:12,852 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:28:12,852 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1892644986] [2024-12-02 06:28:12,853 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1892644986] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:28:12,853 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1351136037] [2024-12-02 06:28:12,853 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:28:12,853 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:28:12,853 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:28:12,855 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:28:12,855 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2024-12-02 06:28:25,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:28:25,141 INFO L256 TraceCheckSpWp]: Trace formula consists of 4540 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 06:28:25,148 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:28:25,167 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 329 trivial. 0 not checked. [2024-12-02 06:28:25,168 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 06:28:25,168 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1351136037] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 06:28:25,168 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 06:28:25,168 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 7 [2024-12-02 06:28:25,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2045746430] [2024-12-02 06:28:25,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 06:28:25,168 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 06:28:25,168 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:28:25,169 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 06:28:25,169 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:28:25,169 INFO L87 Difference]: Start difference. First operand 84532 states and 113507 transitions. Second operand has 6 states, 5 states have (on average 148.2) internal successors, (741), 6 states have internal predecessors, (741), 3 states have call successors, (10), 2 states have call predecessors, (10), 3 states have return successors, (10), 2 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:28:27,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:28:27,731 INFO L93 Difference]: Finished difference Result 140455 states and 189489 transitions. [2024-12-02 06:28:27,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 06:28:27,732 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 148.2) internal successors, (741), 6 states have internal predecessors, (741), 3 states have call successors, (10), 2 states have call predecessors, (10), 3 states have return successors, (10), 2 states have call predecessors, (10), 3 states have call successors, (10) Word has length 904 [2024-12-02 06:28:27,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:28:27,798 INFO L225 Difference]: With dead ends: 140455 [2024-12-02 06:28:27,798 INFO L226 Difference]: Without dead ends: 84532 [2024-12-02 06:28:27,829 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 909 GetRequests, 904 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 06:28:27,829 INFO L435 NwaCegarLoop]: 1679 mSDtfsCounter, 0 mSDsluCounter, 6693 mSDsCounter, 0 mSdLazyCounter, 53 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 8372 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 53 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 06:28:27,829 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 8372 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 53 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 06:28:27,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84532 states. [2024-12-02 06:28:30,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84532 to 74644. [2024-12-02 06:28:30,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74644 states, 73138 states have (on average 1.3385517788290628) internal successors, (97899), 73138 states have internal predecessors, (97899), 1504 states have call successors, (1504), 1 states have call predecessors, (1504), 1 states have return successors, (1504), 1504 states have call predecessors, (1504), 1504 states have call successors, (1504) [2024-12-02 06:28:30,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74644 states to 74644 states and 100907 transitions. [2024-12-02 06:28:30,432 INFO L78 Accepts]: Start accepts. Automaton has 74644 states and 100907 transitions. Word has length 904 [2024-12-02 06:28:30,432 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:28:30,432 INFO L471 AbstractCegarLoop]: Abstraction has 74644 states and 100907 transitions. [2024-12-02 06:28:30,432 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 148.2) internal successors, (741), 6 states have internal predecessors, (741), 3 states have call successors, (10), 2 states have call predecessors, (10), 3 states have return successors, (10), 2 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 06:28:30,433 INFO L276 IsEmpty]: Start isEmpty. Operand 74644 states and 100907 transitions. [2024-12-02 06:28:30,494 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 906 [2024-12-02 06:28:30,494 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:28:30,495 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:28:30,540 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Ended with exit code 0 [2024-12-02 06:28:30,695 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 68 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable98 [2024-12-02 06:28:30,695 INFO L396 AbstractCegarLoop]: === Iteration 100 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:28:30,696 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:28:30,696 INFO L85 PathProgramCache]: Analyzing trace with hash -486340545, now seen corresponding path program 1 times [2024-12-02 06:28:30,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:28:30,696 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152415686] [2024-12-02 06:28:30,696 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:28:30,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:28:38,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:28:41,738 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 29 proven. 4 refuted. 0 times theorem prover too weak. 487 trivial. 0 not checked. [2024-12-02 06:28:41,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 06:28:41,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152415686] [2024-12-02 06:28:41,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [152415686] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 06:28:41,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [892032080] [2024-12-02 06:28:41,738 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:28:41,738 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 06:28:41,738 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 06:28:41,740 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 06:28:41,740 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2024-12-02 06:29:01,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 06:29:01,887 INFO L256 TraceCheckSpWp]: Trace formula consists of 4543 conjuncts, 135 conjuncts are in the unsatisfiable core [2024-12-02 06:29:01,901 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 06:29:01,991 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-12-02 06:29:02,070 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2024-12-02 06:29:02,154 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2024-12-02 06:29:02,227 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2024-12-02 06:29:07,976 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 3 [2024-12-02 06:29:08,016 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 201 proven. 61 refuted. 0 times theorem prover too weak. 258 trivial. 0 not checked. [2024-12-02 06:29:08,017 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 06:29:13,957 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 41 [2024-12-02 06:29:13,961 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 714 treesize of output 710 [2024-12-02 06:29:14,202 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 129 proven. 42 refuted. 0 times theorem prover too weak. 349 trivial. 0 not checked. [2024-12-02 06:29:14,202 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [892032080] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 06:29:14,202 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 06:29:14,203 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 22, 26] total 50 [2024-12-02 06:29:14,203 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127568197] [2024-12-02 06:29:14,203 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 06:29:14,204 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 50 states [2024-12-02 06:29:14,204 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 06:29:14,204 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2024-12-02 06:29:14,205 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=304, Invalid=2146, Unknown=0, NotChecked=0, Total=2450 [2024-12-02 06:29:14,205 INFO L87 Difference]: Start difference. First operand 74644 states and 100907 transitions. Second operand has 50 states, 49 states have (on average 43.816326530612244) internal successors, (2147), 50 states have internal predecessors, (2147), 7 states have call successors, (25), 3 states have call predecessors, (25), 4 states have return successors, (25), 6 states have call predecessors, (25), 7 states have call successors, (25) [2024-12-02 06:29:31,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 06:29:31,374 INFO L93 Difference]: Finished difference Result 174648 states and 237768 transitions. [2024-12-02 06:29:31,375 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2024-12-02 06:29:31,375 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 49 states have (on average 43.816326530612244) internal successors, (2147), 50 states have internal predecessors, (2147), 7 states have call successors, (25), 3 states have call predecessors, (25), 4 states have return successors, (25), 6 states have call predecessors, (25), 7 states have call successors, (25) Word has length 905 [2024-12-02 06:29:31,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 06:29:31,472 INFO L225 Difference]: With dead ends: 174648 [2024-12-02 06:29:31,473 INFO L226 Difference]: Without dead ends: 140493 [2024-12-02 06:29:31,495 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1835 GetRequests, 1759 SyntacticMatches, 9 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1365 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=524, Invalid=4168, Unknown=0, NotChecked=0, Total=4692 [2024-12-02 06:29:31,496 INFO L435 NwaCegarLoop]: 910 mSDtfsCounter, 5476 mSDsluCounter, 24023 mSDsCounter, 0 mSdLazyCounter, 25209 mSolverCounterSat, 18 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 10.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5476 SdHoareTripleChecker+Valid, 24933 SdHoareTripleChecker+Invalid, 25227 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 18 IncrementalHoareTripleChecker+Valid, 25209 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 12.3s IncrementalHoareTripleChecker+Time [2024-12-02 06:29:31,496 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [5476 Valid, 24933 Invalid, 25227 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [18 Valid, 25209 Invalid, 0 Unknown, 0 Unchecked, 12.3s Time] [2024-12-02 06:29:31,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140493 states. [2024-12-02 06:29:35,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140493 to 124682. [2024-12-02 06:29:35,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124682 states, 121831 states have (on average 1.330646551370341) internal successors, (162114), 121831 states have internal predecessors, (162114), 2848 states have call successors, (2848), 2 states have call predecessors, (2848), 2 states have return successors, (2848), 2848 states have call predecessors, (2848), 2848 states have call successors, (2848) [2024-12-02 06:29:35,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124682 states to 124682 states and 167810 transitions. [2024-12-02 06:29:35,709 INFO L78 Accepts]: Start accepts. Automaton has 124682 states and 167810 transitions. Word has length 905 [2024-12-02 06:29:35,709 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 06:29:35,709 INFO L471 AbstractCegarLoop]: Abstraction has 124682 states and 167810 transitions. [2024-12-02 06:29:35,710 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 50 states, 49 states have (on average 43.816326530612244) internal successors, (2147), 50 states have internal predecessors, (2147), 7 states have call successors, (25), 3 states have call predecessors, (25), 4 states have return successors, (25), 6 states have call predecessors, (25), 7 states have call successors, (25) [2024-12-02 06:29:35,710 INFO L276 IsEmpty]: Start isEmpty. Operand 124682 states and 167810 transitions. [2024-12-02 06:29:35,816 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 906 [2024-12-02 06:29:35,816 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 06:29:35,817 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:29:35,861 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Forceful destruction successful, exit code 0 [2024-12-02 06:29:36,017 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 69 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable99 [2024-12-02 06:29:36,017 INFO L396 AbstractCegarLoop]: === Iteration 101 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 06:29:36,017 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 06:29:36,018 INFO L85 PathProgramCache]: Analyzing trace with hash -1311013943, now seen corresponding path program 1 times [2024-12-02 06:29:36,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 06:29:36,018 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [269184453] [2024-12-02 06:29:36,018 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 06:29:36,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 06:29:48,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 06:29:48,990 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 06:30:04,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 06:30:05,214 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-12-02 06:30:05,214 INFO L340 BasicCegarLoop]: Counterexample is feasible [2024-12-02 06:30:05,215 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-12-02 06:30:05,216 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable100 [2024-12-02 06:30:05,218 INFO L422 BasicCegarLoop]: Path program histogram: [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 06:30:05,756 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-12-02 06:30:05,759 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.12 06:30:05 BoogieIcfgContainer [2024-12-02 06:30:05,759 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-12-02 06:30:05,760 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-12-02 06:30:05,760 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-12-02 06:30:05,760 INFO L274 PluginConnector]: Witness Printer initialized [2024-12-02 06:30:05,761 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:17:04" (3/4) ... [2024-12-02 06:30:05,763 INFO L149 WitnessPrinter]: No result that supports witness generation found [2024-12-02 06:30:05,764 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-12-02 06:30:05,764 INFO L158 Benchmark]: Toolchain (without parser) took 787022.68ms. Allocated memory was 142.6MB in the beginning and 4.9GB in the end (delta: 4.7GB). Free memory was 114.6MB in the beginning and 1.4GB in the end (delta: -1.3GB). Peak memory consumption was 3.4GB. Max. memory is 16.1GB. [2024-12-02 06:30:05,765 INFO L158 Benchmark]: CDTParser took 0.37ms. Allocated memory is still 142.6MB. Free memory is still 83.1MB. There was no memory consumed. Max. memory is 16.1GB. [2024-12-02 06:30:05,765 INFO L158 Benchmark]: CACSL2BoogieTranslator took 551.12ms. Allocated memory is still 142.6MB. Free memory was 114.6MB in the beginning and 58.8MB in the end (delta: 55.8MB). Peak memory consumption was 58.7MB. Max. memory is 16.1GB. [2024-12-02 06:30:05,765 INFO L158 Benchmark]: Boogie Procedure Inliner took 335.06ms. Allocated memory was 142.6MB in the beginning and 159.4MB in the end (delta: 16.8MB). Free memory was 58.8MB in the beginning and 74.3MB in the end (delta: -15.5MB). Peak memory consumption was 51.1MB. Max. memory is 16.1GB. [2024-12-02 06:30:05,765 INFO L158 Benchmark]: Boogie Preprocessor took 423.45ms. Allocated memory was 159.4MB in the beginning and 427.8MB in the end (delta: 268.4MB). Free memory was 74.3MB in the beginning and 328.4MB in the end (delta: -254.1MB). Peak memory consumption was 46.0MB. Max. memory is 16.1GB. [2024-12-02 06:30:05,765 INFO L158 Benchmark]: RCFGBuilder took 4155.08ms. Allocated memory is still 427.8MB. Free memory was 328.0MB in the beginning and 139.3MB in the end (delta: 188.7MB). Peak memory consumption was 212.7MB. Max. memory is 16.1GB. [2024-12-02 06:30:05,765 INFO L158 Benchmark]: TraceAbstraction took 781547.19ms. Allocated memory was 427.8MB in the beginning and 4.9GB in the end (delta: 4.4GB). Free memory was 139.3MB in the beginning and 1.4GB in the end (delta: -1.3GB). Peak memory consumption was 3.8GB. Max. memory is 16.1GB. [2024-12-02 06:30:05,765 INFO L158 Benchmark]: Witness Printer took 4.30ms. Allocated memory is still 4.9GB. Free memory was 1.4GB in the beginning and 1.4GB in the end (delta: 4.4MB). There was no memory consumed. Max. memory is 16.1GB. [2024-12-02 06:30:05,766 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.37ms. Allocated memory is still 142.6MB. Free memory is still 83.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 551.12ms. Allocated memory is still 142.6MB. Free memory was 114.6MB in the beginning and 58.8MB in the end (delta: 55.8MB). Peak memory consumption was 58.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 335.06ms. Allocated memory was 142.6MB in the beginning and 159.4MB in the end (delta: 16.8MB). Free memory was 58.8MB in the beginning and 74.3MB in the end (delta: -15.5MB). Peak memory consumption was 51.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 423.45ms. Allocated memory was 159.4MB in the beginning and 427.8MB in the end (delta: 268.4MB). Free memory was 74.3MB in the beginning and 328.4MB in the end (delta: -254.1MB). Peak memory consumption was 46.0MB. Max. memory is 16.1GB. * RCFGBuilder took 4155.08ms. Allocated memory is still 427.8MB. Free memory was 328.0MB in the beginning and 139.3MB in the end (delta: 188.7MB). Peak memory consumption was 212.7MB. Max. memory is 16.1GB. * TraceAbstraction took 781547.19ms. Allocated memory was 427.8MB in the beginning and 4.9GB in the end (delta: 4.4GB). Free memory was 139.3MB in the beginning and 1.4GB in the end (delta: -1.3GB). Peak memory consumption was 3.8GB. Max. memory is 16.1GB. * Witness Printer took 4.30ms. Allocated memory is still 4.9GB. Free memory was 1.4GB in the beginning and 1.4GB in the end (delta: 4.4MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 21]: Unable to prove that a call to reach_error is unreachable Unable to prove that a call to reach_error is unreachable Reason: overapproximation of bitwiseOr at line 322, overapproximation of bitwiseOr at line 346, overapproximation of bitwiseOr at line 300, overapproximation of bitwiseOr at line 362, overapproximation of bitwiseOr at line 883, overapproximation of bitwiseOr at line 436, overapproximation of bitwiseAnd at line 449, overapproximation of bitwiseAnd at line 333, overapproximation of bitwiseAnd at line 374, overapproximation of bitwiseAnd at line 441, overapproximation of bitwiseAnd at line 286, overapproximation of bitwiseAnd at line 861, overapproximation of bitwiseAnd at line 281. Possible FailurePath: [L26] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L27] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L29] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 8); [L30] const SORT_3 msb_SORT_3 = (SORT_3)1 << (8 - 1); [L32] const SORT_11 mask_SORT_11 = (SORT_11)-1 >> (sizeof(SORT_11) * 8 - 2); [L33] const SORT_11 msb_SORT_11 = (SORT_11)1 << (2 - 1); [L37] const SORT_19 mask_SORT_19 = (SORT_19)-1 >> (sizeof(SORT_19) * 8 - 3); [L38] const SORT_19 msb_SORT_19 = (SORT_19)1 << (3 - 1); [L40] const SORT_156 mask_SORT_156 = (SORT_156)-1 >> (sizeof(SORT_156) * 8 - 32); [L41] const SORT_156 msb_SORT_156 = (SORT_156)1 << (32 - 1); [L43] const SORT_191 mask_SORT_191 = (SORT_191)-1 >> (sizeof(SORT_191) * 8 - 4); [L44] const SORT_191 msb_SORT_191 = (SORT_191)1 << (4 - 1); [L46] const SORT_193 mask_SORT_193 = (SORT_193)-1 >> (sizeof(SORT_193) * 8 - 5); [L47] const SORT_193 msb_SORT_193 = (SORT_193)1 << (5 - 1); [L49] const SORT_195 mask_SORT_195 = (SORT_195)-1 >> (sizeof(SORT_195) * 8 - 6); [L50] const SORT_195 msb_SORT_195 = (SORT_195)1 << (6 - 1); [L52] const SORT_197 mask_SORT_197 = (SORT_197)-1 >> (sizeof(SORT_197) * 8 - 7); [L53] const SORT_197 msb_SORT_197 = (SORT_197)1 << (7 - 1); [L55] const SORT_200 mask_SORT_200 = (SORT_200)-1 >> (sizeof(SORT_200) * 8 - 9); [L56] const SORT_200 msb_SORT_200 = (SORT_200)1 << (9 - 1); [L58] const SORT_202 mask_SORT_202 = (SORT_202)-1 >> (sizeof(SORT_202) * 8 - 10); [L59] const SORT_202 msb_SORT_202 = (SORT_202)1 << (10 - 1); [L61] const SORT_204 mask_SORT_204 = (SORT_204)-1 >> (sizeof(SORT_204) * 8 - 11); [L62] const SORT_204 msb_SORT_204 = (SORT_204)1 << (11 - 1); [L64] const SORT_206 mask_SORT_206 = (SORT_206)-1 >> (sizeof(SORT_206) * 8 - 12); [L65] const SORT_206 msb_SORT_206 = (SORT_206)1 << (12 - 1); [L67] const SORT_208 mask_SORT_208 = (SORT_208)-1 >> (sizeof(SORT_208) * 8 - 13); [L68] const SORT_208 msb_SORT_208 = (SORT_208)1 << (13 - 1); [L70] const SORT_210 mask_SORT_210 = (SORT_210)-1 >> (sizeof(SORT_210) * 8 - 14); [L71] const SORT_210 msb_SORT_210 = (SORT_210)1 << (14 - 1); [L73] const SORT_212 mask_SORT_212 = (SORT_212)-1 >> (sizeof(SORT_212) * 8 - 15); [L74] const SORT_212 msb_SORT_212 = (SORT_212)1 << (15 - 1); [L76] const SORT_214 mask_SORT_214 = (SORT_214)-1 >> (sizeof(SORT_214) * 8 - 16); [L77] const SORT_214 msb_SORT_214 = (SORT_214)1 << (16 - 1); [L79] const SORT_216 mask_SORT_216 = (SORT_216)-1 >> (sizeof(SORT_216) * 8 - 17); [L80] const SORT_216 msb_SORT_216 = (SORT_216)1 << (17 - 1); [L82] const SORT_218 mask_SORT_218 = (SORT_218)-1 >> (sizeof(SORT_218) * 8 - 18); [L83] const SORT_218 msb_SORT_218 = (SORT_218)1 << (18 - 1); [L85] const SORT_220 mask_SORT_220 = (SORT_220)-1 >> (sizeof(SORT_220) * 8 - 19); [L86] const SORT_220 msb_SORT_220 = (SORT_220)1 << (19 - 1); [L88] const SORT_222 mask_SORT_222 = (SORT_222)-1 >> (sizeof(SORT_222) * 8 - 20); [L89] const SORT_222 msb_SORT_222 = (SORT_222)1 << (20 - 1); [L91] const SORT_224 mask_SORT_224 = (SORT_224)-1 >> (sizeof(SORT_224) * 8 - 21); [L92] const SORT_224 msb_SORT_224 = (SORT_224)1 << (21 - 1); [L94] const SORT_226 mask_SORT_226 = (SORT_226)-1 >> (sizeof(SORT_226) * 8 - 22); [L95] const SORT_226 msb_SORT_226 = (SORT_226)1 << (22 - 1); [L97] const SORT_228 mask_SORT_228 = (SORT_228)-1 >> (sizeof(SORT_228) * 8 - 23); [L98] const SORT_228 msb_SORT_228 = (SORT_228)1 << (23 - 1); [L100] const SORT_230 mask_SORT_230 = (SORT_230)-1 >> (sizeof(SORT_230) * 8 - 24); [L101] const SORT_230 msb_SORT_230 = (SORT_230)1 << (24 - 1); [L103] const SORT_232 mask_SORT_232 = (SORT_232)-1 >> (sizeof(SORT_232) * 8 - 25); [L104] const SORT_232 msb_SORT_232 = (SORT_232)1 << (25 - 1); [L106] const SORT_234 mask_SORT_234 = (SORT_234)-1 >> (sizeof(SORT_234) * 8 - 26); [L107] const SORT_234 msb_SORT_234 = (SORT_234)1 << (26 - 1); [L109] const SORT_236 mask_SORT_236 = (SORT_236)-1 >> (sizeof(SORT_236) * 8 - 27); [L110] const SORT_236 msb_SORT_236 = (SORT_236)1 << (27 - 1); [L112] const SORT_238 mask_SORT_238 = (SORT_238)-1 >> (sizeof(SORT_238) * 8 - 28); [L113] const SORT_238 msb_SORT_238 = (SORT_238)1 << (28 - 1); [L115] const SORT_240 mask_SORT_240 = (SORT_240)-1 >> (sizeof(SORT_240) * 8 - 29); [L116] const SORT_240 msb_SORT_240 = (SORT_240)1 << (29 - 1); [L118] const SORT_242 mask_SORT_242 = (SORT_242)-1 >> (sizeof(SORT_242) * 8 - 30); [L119] const SORT_242 msb_SORT_242 = (SORT_242)1 << (30 - 1); [L121] const SORT_244 mask_SORT_244 = (SORT_244)-1 >> (sizeof(SORT_244) * 8 - 31); [L122] const SORT_244 msb_SORT_244 = (SORT_244)1 << (31 - 1); [L125] const SORT_19 var_29 = 4; [L126] const SORT_19 var_49 = 0; [L127] const SORT_1 var_59 = 1; [L128] const SORT_1 var_60 = 0; [L129] const SORT_11 var_401 = 0; [L130] const SORT_3 var_508 = 0; [L131] const SORT_11 var_513 = 3; [L132] const SORT_11 var_519 = 2; [L133] const SORT_11 var_531 = 1; [L135] SORT_1 input_2; [L136] SORT_3 input_4; [L137] SORT_1 input_5; [L138] SORT_1 input_6; [L139] SORT_1 input_7; [L140] SORT_1 input_8; [L141] SORT_1 input_9; [L142] SORT_1 input_10; [L144] SORT_12 state_13; [L145] unsigned char i = 0; VAL [i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L145] COND TRUE i < (1 << 2) VAL [i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L145] EXPR __VERIFIER_nondet_uchar() & mask_SORT_3 VAL [i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L145] state_13[i] = __VERIFIER_nondet_uchar() & mask_SORT_3 [L145] ++i VAL [i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L145] COND TRUE i < (1 << 2) VAL [i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L145] EXPR __VERIFIER_nondet_uchar() & mask_SORT_3 VAL [i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L145] state_13[i] = __VERIFIER_nondet_uchar() & mask_SORT_3 [L145] ++i VAL [i=2, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L145] COND TRUE i < (1 << 2) VAL [i=2, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L145] EXPR __VERIFIER_nondet_uchar() & mask_SORT_3 VAL [i=2, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L145] state_13[i] = __VERIFIER_nondet_uchar() & mask_SORT_3 [L145] ++i VAL [i=3, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L145] COND TRUE i < (1 << 2) VAL [i=3, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L145] EXPR __VERIFIER_nondet_uchar() & mask_SORT_3 VAL [i=3, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L145] state_13[i] = __VERIFIER_nondet_uchar() & mask_SORT_3 [L145] ++i VAL [i=4, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L145] COND FALSE !(i < (1 << 2)) VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L146] SORT_14 state_15; [L147] unsigned char i = 0; VAL [i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L147] COND TRUE i < (1 << 1) VAL [i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L147] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L147] state_15[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L147] ++i VAL [i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L147] COND TRUE i < (1 << 1) VAL [i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L147] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L147] state_15[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L147] ++i VAL [i=2, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L147] COND FALSE !(i < (1 << 1)) VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L148] EXPR __VERIFIER_nondet_uchar() & mask_SORT_19 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L148] SORT_19 state_20 = __VERIFIER_nondet_uchar() & mask_SORT_19; [L149] EXPR __VERIFIER_nondet_uchar() & mask_SORT_19 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, state_20=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L149] SORT_19 state_23 = __VERIFIER_nondet_uchar() & mask_SORT_19; [L150] EXPR __VERIFIER_nondet_uchar() & mask_SORT_19 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, state_20=0, state_23=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L150] SORT_19 state_28 = __VERIFIER_nondet_uchar() & mask_SORT_19; [L151] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, state_20=0, state_23=0, state_28=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L151] SORT_1 state_32 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L152] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L152] SORT_1 state_33 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L153] EXPR __VERIFIER_nondet_uchar() & mask_SORT_19 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L153] SORT_19 state_36 = __VERIFIER_nondet_uchar() & mask_SORT_19; [L154] EXPR __VERIFIER_nondet_uchar() & mask_SORT_3 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L154] SORT_3 state_55 = __VERIFIER_nondet_uchar() & mask_SORT_3; [L155] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L155] SORT_1 state_61 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L156] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L156] SORT_11 state_148 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L157] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L157] SORT_11 state_153 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L158] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L158] SORT_1 state_157 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L159] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L159] SORT_1 state_158 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L160] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L160] SORT_1 state_159 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L161] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L161] SORT_1 state_160 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L162] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L162] SORT_1 state_161 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L163] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L163] SORT_1 state_162 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L164] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L164] SORT_1 state_163 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L165] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L165] SORT_1 state_164 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L166] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L166] SORT_1 state_165 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L167] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L167] SORT_1 state_166 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L168] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L168] SORT_1 state_167 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L169] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L169] SORT_1 state_168 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L170] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L170] SORT_1 state_169 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L171] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L171] SORT_1 state_170 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L172] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L172] SORT_1 state_171 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L173] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L173] SORT_1 state_172 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L174] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L174] SORT_1 state_173 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L175] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L175] SORT_1 state_174 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L176] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L176] SORT_1 state_175 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L177] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L177] SORT_1 state_176 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L178] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L178] SORT_1 state_177 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L179] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L179] SORT_1 state_178 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L180] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L180] SORT_1 state_179 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L181] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L181] SORT_1 state_180 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L182] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L182] SORT_1 state_181 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L183] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L183] SORT_1 state_182 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L184] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L184] SORT_1 state_183 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L185] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L185] SORT_1 state_184 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L186] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L186] SORT_1 state_185 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L187] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L187] SORT_1 state_186 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L188] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L188] SORT_1 state_187 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L189] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L189] SORT_1 state_188 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L190] SORT_248 state_249; [L191] unsigned char i = 0; VAL [i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L191] COND TRUE i < (1 << 2) VAL [i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L191] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L191] state_249[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L191] ++i VAL [i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L191] COND TRUE i < (1 << 2) VAL [i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L191] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L191] state_249[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L191] ++i VAL [i=2, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L191] COND TRUE i < (1 << 2) VAL [i=2, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L191] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=2, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L191] state_249[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L191] ++i VAL [i=3, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L191] COND TRUE i < (1 << 2) VAL [i=3, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L191] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=3, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L191] state_249[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L191] ++i VAL [i=4, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L191] COND FALSE !(i < (1 << 2)) VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L192] EXPR __VERIFIER_nondet_uchar() & mask_SORT_19 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L192] SORT_19 state_254 = __VERIFIER_nondet_uchar() & mask_SORT_19; [L193] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L193] SORT_1 state_263 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L194] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L194] SORT_1 state_264 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L195] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L195] SORT_1 state_265 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L196] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L196] SORT_1 state_266 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L197] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L197] SORT_1 state_267 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L198] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L198] SORT_1 state_268 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L199] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L199] SORT_1 state_269 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L200] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L200] SORT_1 state_270 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L201] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L201] SORT_1 state_271 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L202] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L202] SORT_1 state_272 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L203] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L203] SORT_1 state_273 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L204] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L204] SORT_1 state_274 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L205] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L205] SORT_1 state_275 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L206] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L206] SORT_1 state_276 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L207] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L207] SORT_1 state_277 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L208] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L208] SORT_1 state_278 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L209] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L209] SORT_1 state_279 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L210] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L210] SORT_1 state_280 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L211] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L211] SORT_1 state_281 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L212] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L212] SORT_1 state_282 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L213] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L213] SORT_1 state_283 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L214] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L214] SORT_1 state_284 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L215] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L215] SORT_1 state_285 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L216] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L216] SORT_1 state_286 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L217] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L217] SORT_1 state_287 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L218] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L218] SORT_1 state_288 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L219] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L219] SORT_11 state_289 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L220] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L220] SORT_1 state_290 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L221] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L221] SORT_11 state_291 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L222] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L222] SORT_1 state_292 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L223] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L223] SORT_11 state_329 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L224] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L224] SORT_11 state_330 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L225] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L225] SORT_1 state_331 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L226] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L226] SORT_1 state_332 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L227] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L227] SORT_1 state_333 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L228] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L228] SORT_1 state_334 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L229] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L229] SORT_1 state_335 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L230] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L230] SORT_1 state_336 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L231] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L231] SORT_1 state_337 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L232] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L232] SORT_1 state_338 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L233] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L233] SORT_1 state_339 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L234] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L234] SORT_1 state_340 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L235] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L235] SORT_1 state_341 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L236] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L236] SORT_1 state_342 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L237] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L237] SORT_1 state_343 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L238] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L238] SORT_1 state_344 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L239] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L239] SORT_1 state_345 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L240] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L240] SORT_1 state_346 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L241] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L241] SORT_1 state_347 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L242] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L242] SORT_1 state_348 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L243] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L243] SORT_1 state_349 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L244] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L244] SORT_1 state_350 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L245] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L245] SORT_1 state_351 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L246] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L246] SORT_1 state_352 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L247] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L247] SORT_1 state_353 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L248] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L248] SORT_1 state_354 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L249] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L249] SORT_1 state_355 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L250] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L250] SORT_1 state_356 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L251] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L251] SORT_1 state_357 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L252] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L252] SORT_1 state_358 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L253] EXPR __VERIFIER_nondet_uchar() & mask_SORT_19 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L253] SORT_19 state_359 = __VERIFIER_nondet_uchar() & mask_SORT_19; [L254] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L254] SORT_1 state_360 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L255] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L255] SORT_1 state_392 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L256] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L256] SORT_1 state_393 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L257] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L257] SORT_11 state_564 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L259] SORT_1 init_62_arg_1 = var_59; [L260] state_61 = init_62_arg_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L263] input_2 = __VERIFIER_nondet_uchar() [L264] input_4 = __VERIFIER_nondet_uchar() [L265] input_5 = __VERIFIER_nondet_uchar() [L266] EXPR input_5 & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L266] input_5 = input_5 & mask_SORT_1 [L267] input_6 = __VERIFIER_nondet_uchar() [L268] EXPR input_6 & mask_SORT_1 VAL [input_5=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L268] input_6 = input_6 & mask_SORT_1 [L269] input_7 = __VERIFIER_nondet_uchar() [L270] EXPR input_7 & mask_SORT_1 VAL [input_5=0, input_6=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L270] input_7 = input_7 & mask_SORT_1 [L271] input_8 = __VERIFIER_nondet_uchar() [L272] EXPR input_8 & mask_SORT_1 VAL [input_5=0, input_6=0, input_7=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L272] input_8 = input_8 & mask_SORT_1 [L273] input_9 = __VERIFIER_nondet_uchar() [L274] EXPR input_9 & mask_SORT_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L274] input_9 = input_9 & mask_SORT_1 [L275] input_10 = __VERIFIER_nondet_uchar() [L277] SORT_19 var_21_arg_0 = state_20; [L278] SORT_1 var_21 = var_21_arg_0 != 0; [L279] SORT_1 var_22_arg_0 = var_21; [L280] SORT_1 var_22 = ~var_22_arg_0; VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=-1, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L281] EXPR var_22 & mask_SORT_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L281] var_22 = var_22 & mask_SORT_1 [L282] SORT_1 var_67_arg_0 = var_22; [L283] SORT_1 var_67 = ~var_67_arg_0; [L284] SORT_1 var_45_arg_0 = input_6; [L285] SORT_1 var_45 = ~var_45_arg_0; VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_29=4, var_401=0, var_45=-1, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_67=-1] [L286] EXPR var_45 & mask_SORT_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_67=-1] [L286] var_45 = var_45 & mask_SORT_1 [L287] SORT_1 var_46_arg_0 = input_5; [L288] SORT_1 var_46_arg_1 = var_45; VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_29=4, var_401=0, var_45=1, var_46_arg_0=0, var_46_arg_1=1, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_67=-1] [L289] EXPR var_46_arg_0 & var_46_arg_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_29=4, var_401=0, var_45=1, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_67=-1] [L289] SORT_1 var_46 = var_46_arg_0 & var_46_arg_1; [L290] EXPR var_46 & mask_SORT_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_29=4, var_401=0, var_45=1, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_67=-1] [L290] var_46 = var_46 & mask_SORT_1 [L291] SORT_1 var_68_arg_0 = var_46; [L292] SORT_1 var_68 = ~var_68_arg_0; [L293] SORT_1 var_69_arg_0 = var_67; [L294] SORT_1 var_69_arg_1 = var_68; VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_69_arg_0=-1, var_69_arg_1=-1] [L295] EXPR var_69_arg_0 | var_69_arg_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L295] SORT_1 var_69 = var_69_arg_0 | var_69_arg_1; [L296] SORT_1 var_70_arg_0 = var_59; [L297] SORT_1 var_70 = ~var_70_arg_0; [L298] SORT_1 var_71_arg_0 = var_69; [L299] SORT_1 var_71_arg_1 = var_70; VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_71_arg_0=255, var_71_arg_1=-2] [L300] EXPR var_71_arg_0 | var_71_arg_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L300] SORT_1 var_71 = var_71_arg_0 | var_71_arg_1; [L301] EXPR var_71 & mask_SORT_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L301] var_71 = var_71 & mask_SORT_1 [L302] SORT_1 constr_72_arg_0 = var_71; VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L303] CALL assume_abort_if_not(constr_72_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L303] RET assume_abort_if_not(constr_72_arg_0) VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L304] SORT_19 var_24_arg_0 = state_23; [L305] SORT_1 var_24 = var_24_arg_0 != 0; [L306] SORT_1 var_25_arg_0 = var_24; [L307] SORT_1 var_25 = ~var_25_arg_0; [L308] SORT_1 var_73_arg_0 = var_25; [L309] SORT_1 var_73 = ~var_73_arg_0; [L310] SORT_1 var_74_arg_0 = input_5; [L311] SORT_1 var_74_arg_1 = input_6; VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_73=-256, var_74_arg_0=0, var_74_arg_1=0] [L312] EXPR var_74_arg_0 & var_74_arg_1 VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_73=-256] [L312] SORT_1 var_74 = var_74_arg_0 & var_74_arg_1; [L313] SORT_1 var_75_arg_0 = var_74; [L314] SORT_1 var_75 = ~var_75_arg_0; [L315] SORT_1 var_76_arg_0 = var_73; [L316] SORT_1 var_76_arg_1 = var_75; VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_76_arg_0=-256, var_76_arg_1=-1] [L317] EXPR var_76_arg_0 | var_76_arg_1 VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0] [L317] SORT_1 var_76 = var_76_arg_0 | var_76_arg_1; [L318] SORT_1 var_77_arg_0 = var_59; [L319] SORT_1 var_77 = ~var_77_arg_0; [L320] SORT_1 var_78_arg_0 = var_76; [L321] SORT_1 var_78_arg_1 = var_77; VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_78_arg_0=255, var_78_arg_1=-2] [L322] EXPR var_78_arg_0 | var_78_arg_1 VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0] [L322] SORT_1 var_78 = var_78_arg_0 | var_78_arg_1; [L323] EXPR var_78 & mask_SORT_1 VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0] [L323] var_78 = var_78 & mask_SORT_1 [L324] SORT_1 constr_79_arg_0 = var_78; VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0] [L325] CALL assume_abort_if_not(constr_79_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L325] RET assume_abort_if_not(constr_79_arg_0) VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0] [L326] SORT_19 var_30_arg_0 = state_28; [L327] SORT_19 var_30_arg_1 = var_29; [L328] SORT_1 var_30 = var_30_arg_0 == var_30_arg_1; [L329] SORT_1 var_80_arg_0 = var_30; [L330] SORT_1 var_80 = ~var_80_arg_0; [L331] SORT_1 var_39_arg_0 = input_8; [L332] SORT_1 var_39 = ~var_39_arg_0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=-1, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L333] EXPR var_39 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L333] var_39 = var_39 & mask_SORT_1 [L334] SORT_1 var_40_arg_0 = input_7; [L335] SORT_1 var_40_arg_1 = var_39; VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40_arg_0=0, var_40_arg_1=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L336] EXPR var_40_arg_0 & var_40_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L336] SORT_1 var_40 = var_40_arg_0 & var_40_arg_1; [L337] SORT_1 var_81_arg_0 = var_40; [L338] SORT_1 var_81 = ~var_81_arg_0; [L339] SORT_1 var_82_arg_0 = var_80; [L340] SORT_1 var_82_arg_1 = var_81; VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1, var_82_arg_0=-1, var_82_arg_1=-1] [L341] EXPR var_82_arg_0 | var_82_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L341] SORT_1 var_82 = var_82_arg_0 | var_82_arg_1; [L342] SORT_1 var_83_arg_0 = var_59; [L343] SORT_1 var_83 = ~var_83_arg_0; [L344] SORT_1 var_84_arg_0 = var_82; [L345] SORT_1 var_84_arg_1 = var_83; VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1, var_84_arg_0=255, var_84_arg_1=-2] [L346] EXPR var_84_arg_0 | var_84_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L346] SORT_1 var_84 = var_84_arg_0 | var_84_arg_1; [L347] EXPR var_84 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L347] var_84 = var_84 & mask_SORT_1 [L348] SORT_1 constr_85_arg_0 = var_84; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L349] CALL assume_abort_if_not(constr_85_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L349] RET assume_abort_if_not(constr_85_arg_0) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L350] SORT_1 var_86_arg_0 = input_7; [L351] SORT_1 var_86_arg_1 = input_8; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1, var_86_arg_0=0, var_86_arg_1=0] [L352] EXPR var_86_arg_0 & var_86_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L352] SORT_1 var_86 = var_86_arg_0 & var_86_arg_1; [L353] SORT_1 var_87_arg_0 = var_86; [L354] SORT_1 var_87 = ~var_87_arg_0; [L355] SORT_1 var_88_arg_0 = var_80; [L356] SORT_1 var_88_arg_1 = var_87; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0, var_88_arg_0=-1, var_88_arg_1=-1] [L357] EXPR var_88_arg_0 | var_88_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L357] SORT_1 var_88 = var_88_arg_0 | var_88_arg_1; [L358] SORT_1 var_89_arg_0 = var_59; [L359] SORT_1 var_89 = ~var_89_arg_0; [L360] SORT_1 var_90_arg_0 = var_88; [L361] SORT_1 var_90_arg_1 = var_89; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0, var_90_arg_0=255, var_90_arg_1=-2] [L362] EXPR var_90_arg_0 | var_90_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L362] SORT_1 var_90 = var_90_arg_0 | var_90_arg_1; [L363] EXPR var_90 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L363] var_90 = var_90 & mask_SORT_1 [L364] SORT_1 constr_91_arg_0 = var_90; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L365] CALL assume_abort_if_not(constr_91_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L365] RET assume_abort_if_not(constr_91_arg_0) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L366] SORT_1 var_92_arg_0 = state_61; [L367] SORT_1 var_92_arg_1 = input_9; [L368] SORT_1 var_92 = var_92_arg_0 == var_92_arg_1; [L369] SORT_1 var_93_arg_0 = var_59; [L370] SORT_1 var_93 = ~var_93_arg_0; [L371] SORT_1 var_94_arg_0 = var_92; [L372] SORT_1 var_94_arg_1 = var_93; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0, var_94_arg_0=0, var_94_arg_1=-2] [L373] EXPR var_94_arg_0 | var_94_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L373] SORT_1 var_94 = var_94_arg_0 | var_94_arg_1; [L374] EXPR var_94 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L374] var_94 = var_94 & mask_SORT_1 [L375] SORT_1 constr_95_arg_0 = var_94; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L376] CALL assume_abort_if_not(constr_95_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L376] RET assume_abort_if_not(constr_95_arg_0) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=1, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L378] SORT_1 var_63_arg_0 = state_61; [L379] SORT_1 var_63_arg_1 = var_60; [L380] SORT_1 var_63_arg_2 = var_59; [L381] SORT_1 var_63 = var_63_arg_0 ? var_63_arg_1 : var_63_arg_2; [L382] SORT_1 var_34_arg_0 = state_33; [L383] SORT_1 var_34 = ~var_34_arg_0; [L384] SORT_1 var_35_arg_0 = state_32; [L385] SORT_1 var_35_arg_1 = var_34; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_35_arg_0=0, var_35_arg_1=-1, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L386] EXPR var_35_arg_0 & var_35_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L386] SORT_1 var_35 = var_35_arg_0 & var_35_arg_1; [L387] SORT_19 var_37_arg_0 = state_36; [L388] SORT_1 var_37 = var_37_arg_0 != 0; [L389] SORT_1 var_38_arg_0 = var_35; [L390] SORT_1 var_38_arg_1 = var_37; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38_arg_0=0, var_38_arg_1=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L391] EXPR var_38_arg_0 & var_38_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L391] SORT_1 var_38 = var_38_arg_0 & var_38_arg_1; [L392] SORT_1 var_41_arg_0 = state_32; [L393] SORT_1 var_41 = ~var_41_arg_0; [L394] SORT_1 var_42_arg_0 = var_40; [L395] SORT_1 var_42_arg_1 = var_41; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_42_arg_0=0, var_42_arg_1=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L396] EXPR var_42_arg_0 & var_42_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L396] SORT_1 var_42 = var_42_arg_0 & var_42_arg_1; [L397] SORT_1 var_43_arg_0 = var_42; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_43_arg_0=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L398] EXPR var_43_arg_0 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L398] var_43_arg_0 = var_43_arg_0 & mask_SORT_1 [L399] SORT_19 var_43 = var_43_arg_0; [L400] SORT_19 var_44_arg_0 = state_36; [L401] SORT_19 var_44_arg_1 = var_43; [L402] SORT_19 var_44 = var_44_arg_0 + var_44_arg_1; [L403] SORT_1 var_47_arg_0 = var_46; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_44=0, var_45=1, var_46=0, var_47_arg_0=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L404] EXPR var_47_arg_0 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_44=0, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L404] var_47_arg_0 = var_47_arg_0 & mask_SORT_1 [L405] SORT_19 var_47 = var_47_arg_0; [L406] SORT_19 var_48_arg_0 = var_44; [L407] SORT_19 var_48_arg_1 = var_47; [L408] SORT_19 var_48 = var_48_arg_0 - var_48_arg_1; [L409] SORT_1 var_50_arg_0 = input_9; [L410] SORT_19 var_50_arg_1 = var_49; [L411] SORT_19 var_50_arg_2 = var_48; [L412] SORT_19 var_50 = var_50_arg_0 ? var_50_arg_1 : var_50_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L413] EXPR var_50 & mask_SORT_19 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L413] var_50 = var_50 & mask_SORT_19 [L414] SORT_19 var_51_arg_0 = var_50; [L415] SORT_1 var_51 = var_51_arg_0 != 0; [L416] SORT_1 var_52_arg_0 = var_51; [L417] SORT_1 var_52 = ~var_52_arg_0; [L418] SORT_1 var_53_arg_0 = var_38; [L419] SORT_1 var_53_arg_1 = var_52; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53_arg_0=0, var_53_arg_1=-1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L420] EXPR var_53_arg_0 & var_53_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L420] SORT_1 var_53 = var_53_arg_0 & var_53_arg_1; [L421] SORT_1 var_54_arg_0 = var_53; [L422] SORT_1 var_54 = ~var_54_arg_0; [L423] SORT_11* var_16_arg_0 = state_15; [L424] SORT_1 var_16_arg_1 = input_6; [L425] EXPR var_16_arg_0[(unsigned char) var_16_arg_1] [L425] SORT_11 var_16 = var_16_arg_0[(unsigned char) var_16_arg_1]; [L426] EXPR var_16 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_54=-1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L426] var_16 = var_16 & mask_SORT_11 [L427] SORT_3* var_17_arg_0 = state_13; [L428] SORT_11 var_17_arg_1 = var_16; [L429] EXPR var_17_arg_0[(unsigned char) var_17_arg_1] [L429] SORT_3 var_17 = var_17_arg_0[(unsigned char) var_17_arg_1]; [L430] EXPR var_17 & mask_SORT_3 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_54=-1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L430] var_17 = var_17 & mask_SORT_3 [L431] SORT_3 var_56_arg_0 = state_55; [L432] SORT_3 var_56_arg_1 = var_17; [L433] SORT_1 var_56 = var_56_arg_0 == var_56_arg_1; [L434] SORT_1 var_57_arg_0 = var_54; [L435] SORT_1 var_57_arg_1 = var_56; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_57_arg_0=-1, var_57_arg_1=1, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L436] EXPR var_57_arg_0 | var_57_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_63=0, var_74=0, var_86=0] [L436] SORT_1 var_57 = var_57_arg_0 | var_57_arg_1; [L437] SORT_1 var_64_arg_0 = var_57; [L438] SORT_1 var_64 = ~var_64_arg_0; [L439] SORT_1 var_65_arg_0 = var_63; [L440] SORT_1 var_65_arg_1 = var_64; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_65_arg_0=0, var_65_arg_1=-256, var_74=0, var_86=0] [L441] EXPR var_65_arg_0 & var_65_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L441] SORT_1 var_65 = var_65_arg_0 & var_65_arg_1; [L442] EXPR var_65 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L442] var_65 = var_65 & mask_SORT_1 [L443] SORT_1 bad_66_arg_0 = var_65; [L444] CALL __VERIFIER_assert(!(bad_66_arg_0)) [L21] COND FALSE !(!(cond)) [L444] RET __VERIFIER_assert(!(bad_66_arg_0)) [L446] SORT_1 var_26_arg_0 = var_25; [L447] SORT_1 var_26_arg_1 = var_22; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_26_arg_0=-1, var_26_arg_1=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L448] EXPR ((SORT_11)var_26_arg_0 << 1) | var_26_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L448] SORT_11 var_26 = ((SORT_11)var_26_arg_0 << 1) | var_26_arg_1; [L449] EXPR var_26 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L449] var_26 = var_26 & mask_SORT_11 [L450] SORT_1 var_444_arg_0 = input_8; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_26=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_444_arg_0=0, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L451] EXPR var_444_arg_0 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_26=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L451] var_444_arg_0 = var_444_arg_0 & mask_SORT_1 [L452] SORT_11 var_444 = var_444_arg_0; [L453] SORT_11 var_445_arg_0 = var_26; [L454] SORT_11 var_445_arg_1 = var_444; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_445_arg_0=0, var_445_arg_1=0, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L455] EXPR var_445_arg_0 >> var_445_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L455] SORT_11 var_445 = var_445_arg_0 >> var_445_arg_1; [L456] SORT_11 var_446_arg_0 = var_445; [L457] SORT_1 var_446 = var_446_arg_0 >> 0; [L458] SORT_1 var_447_arg_0 = input_7; [L459] SORT_1 var_447_arg_1 = var_446; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_447_arg_0=0, var_447_arg_1=0, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L460] EXPR var_447_arg_0 & var_447_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L460] SORT_1 var_447 = var_447_arg_0 & var_447_arg_1; [L461] EXPR var_447 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L461] var_447 = var_447 & mask_SORT_1 [L462] SORT_1 var_448_arg_0 = var_447; [L463] SORT_1 var_448_arg_1 = var_59; [L464] SORT_1 var_448_arg_2 = var_60; [L465] SORT_1 var_448 = var_448_arg_0 ? var_448_arg_1 : var_448_arg_2; [L466] SORT_1 var_449_arg_0 = input_9; [L467] SORT_1 var_449_arg_1 = var_60; [L468] SORT_1 var_449_arg_2 = var_448; [L469] SORT_1 var_449 = var_449_arg_0 ? var_449_arg_1 : var_449_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_449=0, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L470] EXPR var_449 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L470] var_449 = var_449 & mask_SORT_1 [L471] SORT_1 var_450_arg_0 = var_449; [L472] SORT_1 var_450_arg_1 = var_449; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_450_arg_0=0, var_450_arg_1=0, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L473] EXPR ((SORT_11)var_450_arg_0 << 1) | var_450_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L473] SORT_11 var_450 = ((SORT_11)var_450_arg_0 << 1) | var_450_arg_1; [L474] EXPR var_450 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L474] var_450 = var_450 & mask_SORT_11 [L475] SORT_11 var_457_arg_0 = var_450; [L476] SORT_1 var_457 = var_457_arg_0 != 0; [L477] SORT_1 var_252_arg_0 = input_8; [L478] SORT_1 var_252_arg_1 = input_6; [L479] SORT_1 var_252 = var_252_arg_0 == var_252_arg_1; [L480] SORT_1 var_253_arg_0 = input_7; [L481] SORT_1 var_253_arg_1 = var_252; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_253_arg_0=0, var_253_arg_1=1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_450=0, var_457=0, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L482] EXPR var_253_arg_0 & var_253_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_450=0, var_457=0, var_45=1, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L482] SORT_1 var_253 = var_253_arg_0 & var_253_arg_1; [L483] SORT_1 var_255_arg_0 = input_6; [L484] SORT_19 var_255_arg_1 = state_23; [L485] SORT_19 var_255_arg_2 = state_254; [L486] SORT_19 var_255 = var_255_arg_0 ? var_255_arg_1 : var_255_arg_2; [L487] SORT_1 var_256_arg_0 = var_45; [L488] SORT_19 var_256_arg_1 = state_20; [L489] SORT_19 var_256_arg_2 = var_255; [L490] SORT_19 var_256 = var_256_arg_0 ? var_256_arg_1 : var_256_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_253=0, var_256=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L491] EXPR var_256 & mask_SORT_19 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_253=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L491] var_256 = var_256 & mask_SORT_19 [L492] SORT_1 var_257_arg_0 = var_59; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_253=0, var_256=0, var_257_arg_0=1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L493] EXPR var_257_arg_0 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_253=0, var_256=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L493] var_257_arg_0 = var_257_arg_0 & mask_SORT_1 [L494] SORT_19 var_257 = var_257_arg_0; [L495] SORT_19 var_258_arg_0 = var_256; [L496] SORT_19 var_258_arg_1 = var_257; [L497] SORT_1 var_258 = var_258_arg_0 == var_258_arg_1; [L498] SORT_1 var_259_arg_0 = var_253; [L499] SORT_1 var_259_arg_1 = var_258; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_259_arg_0=0, var_259_arg_1=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L500] EXPR var_259_arg_0 & var_259_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L500] SORT_1 var_259 = var_259_arg_0 & var_259_arg_1; [L501] EXPR var_259 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L501] var_259 = var_259 & mask_SORT_1 [L502] SORT_1 var_432_arg_0 = var_259; [L503] SORT_1 var_432_arg_1 = var_60; [L504] SORT_1 var_432_arg_2 = var_59; [L505] SORT_1 var_432 = var_432_arg_0 ? var_432_arg_1 : var_432_arg_2; [L506] SORT_1 var_433_arg_0 = input_5; [L507] SORT_1 var_433_arg_1 = var_432; [L508] SORT_1 var_433_arg_2 = var_60; [L509] SORT_1 var_433 = var_433_arg_0 ? var_433_arg_1 : var_433_arg_2; [L510] SORT_1 var_434_arg_0 = input_9; [L511] SORT_1 var_434_arg_1 = var_60; [L512] SORT_1 var_434_arg_2 = var_433; [L513] SORT_1 var_434 = var_434_arg_0 ? var_434_arg_1 : var_434_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_259=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_434=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L514] EXPR var_434 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_259=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L514] var_434 = var_434 & mask_SORT_1 [L515] SORT_1 var_435_arg_0 = var_434; [L516] SORT_1 var_435_arg_1 = var_434; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_259=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_435_arg_0=0, var_435_arg_1=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L517] EXPR ((SORT_11)var_435_arg_0 << 1) | var_435_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_259=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L517] SORT_11 var_435 = ((SORT_11)var_435_arg_0 << 1) | var_435_arg_1; [L518] EXPR var_435 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_259=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L518] var_435 = var_435 & mask_SORT_11 [L519] SORT_11 var_442_arg_0 = var_435; [L520] SORT_1 var_442 = var_442_arg_0 != 0; [L521] SORT_1 var_420_arg_0 = var_259; [L522] SORT_1 var_420_arg_1 = var_59; [L523] SORT_1 var_420_arg_2 = var_60; [L524] SORT_1 var_420 = var_420_arg_0 ? var_420_arg_1 : var_420_arg_2; [L525] SORT_1 var_421_arg_0 = input_5; [L526] SORT_1 var_421_arg_1 = var_420; [L527] SORT_1 var_421_arg_2 = var_60; [L528] SORT_1 var_421 = var_421_arg_0 ? var_421_arg_1 : var_421_arg_2; [L529] SORT_1 var_422_arg_0 = input_9; [L530] SORT_1 var_422_arg_1 = var_60; [L531] SORT_1 var_422_arg_2 = var_421; [L532] SORT_1 var_422 = var_422_arg_0 ? var_422_arg_1 : var_422_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_422=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L533] EXPR var_422 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L533] var_422 = var_422 & mask_SORT_1 [L534] SORT_1 var_423_arg_0 = var_422; [L535] SORT_1 var_423_arg_1 = var_422; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_423_arg_0=0, var_423_arg_1=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L536] EXPR ((SORT_11)var_423_arg_0 << 1) | var_423_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L536] SORT_11 var_423 = ((SORT_11)var_423_arg_0 << 1) | var_423_arg_1; [L537] EXPR var_423 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L537] var_423 = var_423 & mask_SORT_11 [L538] SORT_11 var_430_arg_0 = var_423; [L539] SORT_1 var_430 = var_430_arg_0 != 0; [L540] SORT_1 var_402_arg_0 = input_9; [L541] SORT_1 var_402_arg_1 = var_59; [L542] SORT_1 var_402_arg_2 = var_60; [L543] SORT_1 var_402 = var_402_arg_0 ? var_402_arg_1 : var_402_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_402=0, var_40=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L544] EXPR var_402 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L544] var_402 = var_402 & mask_SORT_1 [L545] SORT_1 var_403_arg_0 = var_402; [L546] SORT_1 var_403_arg_1 = var_402; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403_arg_0=0, var_403_arg_1=0, var_40=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L547] EXPR ((SORT_11)var_403_arg_0 << 1) | var_403_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L547] SORT_11 var_403 = ((SORT_11)var_403_arg_0 << 1) | var_403_arg_1; [L548] EXPR var_403 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L548] var_403 = var_403 & mask_SORT_11 [L549] SORT_11 var_418_arg_0 = var_403; [L550] SORT_1 var_418 = var_418_arg_0 != 0; [L551] SORT_11 var_410_arg_0 = var_403; [L552] SORT_1 var_410 = var_410_arg_0 != 0; [L553] SORT_11 var_407_arg_0 = var_401; [L554] SORT_11 var_407_arg_1 = var_403; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_407_arg_0=0, var_407_arg_1=0, var_40=0, var_410=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L555] EXPR var_407_arg_0 & var_407_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_40=0, var_410=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L555] SORT_11 var_407 = var_407_arg_0 & var_407_arg_1; [L556] SORT_11* var_404_arg_0 = state_15; [L557] SORT_1 var_404_arg_1 = var_60; [L558] EXPR var_404_arg_0[(unsigned char) var_404_arg_1] [L558] SORT_11 var_404 = var_404_arg_0[(unsigned char) var_404_arg_1]; [L559] SORT_11 var_405_arg_0 = var_403; [L560] SORT_11 var_405 = ~var_405_arg_0; [L561] SORT_11 var_406_arg_0 = var_404; [L562] SORT_11 var_406_arg_1 = var_405; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_406_arg_0=0, var_406_arg_1=-1, var_407=0, var_40=0, var_410=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L563] EXPR var_406_arg_0 & var_406_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_407=0, var_40=0, var_410=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L563] SORT_11 var_406 = var_406_arg_0 & var_406_arg_1; [L564] SORT_11 var_408_arg_0 = var_407; [L565] SORT_11 var_408_arg_1 = var_406; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_408_arg_0=0, var_408_arg_1=0, var_40=0, var_410=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L566] EXPR var_408_arg_0 | var_408_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_40=0, var_410=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L566] SORT_11 var_408 = var_408_arg_0 | var_408_arg_1; [L567] SORT_11* var_409_arg_0 = state_15; [L568] SORT_1 var_409_arg_1 = var_60; [L569] SORT_11 var_409_arg_2 = var_408; [L570] SORT_14 var_409; [L571] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409={9:0}, var_409_arg_0={7:0}, var_409_arg_1=0, var_409_arg_2=0, var_40=0, var_410=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L571] COND TRUE i < (1 << 1) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409={9:0}, var_409_arg_0={7:0}, var_409_arg_1=0, var_409_arg_2=0, var_40=0, var_410=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L571] EXPR var_409_arg_0[i] [L571] var_409[i] = var_409_arg_0[i] [L571] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409={9:0}, var_409_arg_0={7:0}, var_409_arg_1=0, var_409_arg_2=0, var_40=0, var_410=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L571] COND TRUE i < (1 << 1) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409={9:0}, var_409_arg_0={7:0}, var_409_arg_1=0, var_409_arg_2=0, var_40=0, var_410=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L571] EXPR var_409_arg_0[i] [L571] var_409[i] = var_409_arg_0[i] [L571] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409={9:0}, var_409_arg_0={7:0}, var_409_arg_1=0, var_409_arg_2=0, var_40=0, var_410=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L571] COND FALSE !(i < (1 << 1)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409={9:0}, var_409_arg_0={7:0}, var_409_arg_1=0, var_409_arg_2=0, var_40=0, var_410=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L572] var_409[(unsigned char) var_409_arg_1] = var_409_arg_2 [L573] SORT_1 var_411_arg_0 = var_410; [L574] SORT_11* var_411_arg_1 = var_409; [L575] SORT_11* var_411_arg_2 = state_15; [L576] SORT_11* var_411 = var_411_arg_0 ? var_411_arg_1 : var_411_arg_2; [L577] SORT_11 var_415_arg_0 = var_401; [L578] SORT_11 var_415_arg_1 = var_403; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_411={7:0}, var_415_arg_0=0, var_415_arg_1=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L579] EXPR var_415_arg_0 & var_415_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_411={7:0}, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L579] SORT_11 var_415 = var_415_arg_0 & var_415_arg_1; [L580] SORT_11* var_412_arg_0 = var_411; [L581] SORT_1 var_412_arg_1 = var_59; [L582] EXPR var_412_arg_0[(unsigned char) var_412_arg_1] [L582] SORT_11 var_412 = var_412_arg_0[(unsigned char) var_412_arg_1]; [L583] SORT_11 var_413_arg_0 = var_403; [L584] SORT_11 var_413 = ~var_413_arg_0; [L585] SORT_11 var_414_arg_0 = var_412; [L586] SORT_11 var_414_arg_1 = var_413; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_411={7:0}, var_414_arg_0=0, var_414_arg_1=-1, var_415=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L587] EXPR var_414_arg_0 & var_414_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_411={7:0}, var_415=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L587] SORT_11 var_414 = var_414_arg_0 & var_414_arg_1; [L588] SORT_11 var_416_arg_0 = var_415; [L589] SORT_11 var_416_arg_1 = var_414; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_411={7:0}, var_416_arg_0=0, var_416_arg_1=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L590] EXPR var_416_arg_0 | var_416_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_411={7:0}, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L590] SORT_11 var_416 = var_416_arg_0 | var_416_arg_1; [L591] SORT_11* var_417_arg_0 = var_411; [L592] SORT_1 var_417_arg_1 = var_59; [L593] SORT_11 var_417_arg_2 = var_416; [L594] SORT_14 var_417; [L595] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_411={7:0}, var_417={32:0}, var_417_arg_0={7:0}, var_417_arg_1=1, var_417_arg_2=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L595] COND TRUE i < (1 << 1) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_411={7:0}, var_417={32:0}, var_417_arg_0={7:0}, var_417_arg_1=1, var_417_arg_2=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L595] EXPR var_417_arg_0[i] [L595] var_417[i] = var_417_arg_0[i] [L595] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_411={7:0}, var_417={32:0}, var_417_arg_0={7:0}, var_417_arg_1=1, var_417_arg_2=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L595] COND TRUE i < (1 << 1) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_411={7:0}, var_417={32:0}, var_417_arg_0={7:0}, var_417_arg_1=1, var_417_arg_2=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L595] EXPR var_417_arg_0[i] [L595] var_417[i] = var_417_arg_0[i] [L595] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_411={7:0}, var_417={32:0}, var_417_arg_0={7:0}, var_417_arg_1=1, var_417_arg_2=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L595] COND FALSE !(i < (1 << 1)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_411={7:0}, var_417={32:0}, var_417_arg_0={7:0}, var_417_arg_1=1, var_417_arg_2=0, var_418=0, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L596] var_417[(unsigned char) var_417_arg_1] = var_417_arg_2 [L597] SORT_1 var_419_arg_0 = var_418; [L598] SORT_11* var_419_arg_1 = var_417; [L599] SORT_11* var_419_arg_2 = var_411; [L600] SORT_11* var_419 = var_419_arg_0 ? var_419_arg_1 : var_419_arg_2; [L601] SORT_11 var_427_arg_0 = state_148; [L602] SORT_11 var_427_arg_1 = var_423; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_419={7:0}, var_41=-1, var_423=0, var_427_arg_0=0, var_427_arg_1=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L603] EXPR var_427_arg_0 & var_427_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_419={7:0}, var_41=-1, var_423=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L603] SORT_11 var_427 = var_427_arg_0 & var_427_arg_1; [L604] SORT_11* var_424_arg_0 = var_419; [L605] SORT_1 var_424_arg_1 = input_6; [L606] EXPR var_424_arg_0[(unsigned char) var_424_arg_1] [L606] SORT_11 var_424 = var_424_arg_0[(unsigned char) var_424_arg_1]; [L607] SORT_11 var_425_arg_0 = var_423; [L608] SORT_11 var_425 = ~var_425_arg_0; [L609] SORT_11 var_426_arg_0 = var_424; [L610] SORT_11 var_426_arg_1 = var_425; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_419={7:0}, var_41=-1, var_426_arg_0=0, var_426_arg_1=-1, var_427=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L611] EXPR var_426_arg_0 & var_426_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_419={7:0}, var_41=-1, var_427=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L611] SORT_11 var_426 = var_426_arg_0 & var_426_arg_1; [L612] SORT_11 var_428_arg_0 = var_427; [L613] SORT_11 var_428_arg_1 = var_426; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_419={7:0}, var_41=-1, var_428_arg_0=0, var_428_arg_1=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L614] EXPR var_428_arg_0 | var_428_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_419={7:0}, var_41=-1, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L614] SORT_11 var_428 = var_428_arg_0 | var_428_arg_1; [L615] SORT_11* var_429_arg_0 = var_419; [L616] SORT_1 var_429_arg_1 = input_6; [L617] SORT_11 var_429_arg_2 = var_428; [L618] SORT_14 var_429; [L619] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_419={7:0}, var_41=-1, var_429={11:0}, var_429_arg_0={7:0}, var_429_arg_1=0, var_429_arg_2=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L619] COND TRUE i < (1 << 1) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_419={7:0}, var_41=-1, var_429={11:0}, var_429_arg_0={7:0}, var_429_arg_1=0, var_429_arg_2=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L619] EXPR var_429_arg_0[i] [L619] var_429[i] = var_429_arg_0[i] [L619] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_419={7:0}, var_41=-1, var_429={11:0}, var_429_arg_0={7:0}, var_429_arg_1=0, var_429_arg_2=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L619] COND TRUE i < (1 << 1) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_419={7:0}, var_41=-1, var_429={11:0}, var_429_arg_0={7:0}, var_429_arg_1=0, var_429_arg_2=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L619] EXPR var_429_arg_0[i] [L619] var_429[i] = var_429_arg_0[i] [L619] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_419={7:0}, var_41=-1, var_429={11:0}, var_429_arg_0={7:0}, var_429_arg_1=0, var_429_arg_2=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L619] COND FALSE !(i < (1 << 1)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_419={7:0}, var_41=-1, var_429={11:0}, var_429_arg_0={7:0}, var_429_arg_1=0, var_429_arg_2=0, var_430=0, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L620] var_429[(unsigned char) var_429_arg_1] = var_429_arg_2 [L621] SORT_1 var_431_arg_0 = var_430; [L622] SORT_11* var_431_arg_1 = var_429; [L623] SORT_11* var_431_arg_2 = var_419; [L624] SORT_11* var_431 = var_431_arg_0 ? var_431_arg_1 : var_431_arg_2; [L625] SORT_11* var_250_arg_0 = state_249; [L626] SORT_11 var_250_arg_1 = var_16; [L627] EXPR var_250_arg_0[(unsigned char) var_250_arg_1] [L627] SORT_11 var_250 = var_250_arg_0[(unsigned char) var_250_arg_1]; [L628] SORT_11 var_439_arg_0 = var_250; [L629] SORT_11 var_439_arg_1 = var_435; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_431={7:0}, var_435=0, var_439_arg_0=0, var_439_arg_1=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L630] EXPR var_439_arg_0 & var_439_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_431={7:0}, var_435=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L630] SORT_11 var_439 = var_439_arg_0 & var_439_arg_1; [L631] SORT_11* var_436_arg_0 = var_431; [L632] SORT_1 var_436_arg_1 = input_6; [L633] EXPR var_436_arg_0[(unsigned char) var_436_arg_1] [L633] SORT_11 var_436 = var_436_arg_0[(unsigned char) var_436_arg_1]; [L634] SORT_11 var_437_arg_0 = var_435; [L635] SORT_11 var_437 = ~var_437_arg_0; [L636] SORT_11 var_438_arg_0 = var_436; [L637] SORT_11 var_438_arg_1 = var_437; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_431={7:0}, var_438_arg_0=0, var_438_arg_1=-1, var_439=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L638] EXPR var_438_arg_0 & var_438_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_431={7:0}, var_439=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L638] SORT_11 var_438 = var_438_arg_0 & var_438_arg_1; [L639] SORT_11 var_440_arg_0 = var_439; [L640] SORT_11 var_440_arg_1 = var_438; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_431={7:0}, var_440_arg_0=0, var_440_arg_1=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L641] EXPR var_440_arg_0 | var_440_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_431={7:0}, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L641] SORT_11 var_440 = var_440_arg_0 | var_440_arg_1; [L642] SORT_11* var_441_arg_0 = var_431; [L643] SORT_1 var_441_arg_1 = input_6; [L644] SORT_11 var_441_arg_2 = var_440; [L645] SORT_14 var_441; [L646] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_431={7:0}, var_441={10:0}, var_441_arg_0={7:0}, var_441_arg_1=0, var_441_arg_2=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L646] COND TRUE i < (1 << 1) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_431={7:0}, var_441={10:0}, var_441_arg_0={7:0}, var_441_arg_1=0, var_441_arg_2=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L646] EXPR var_441_arg_0[i] [L646] var_441[i] = var_441_arg_0[i] [L646] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_431={7:0}, var_441={10:0}, var_441_arg_0={7:0}, var_441_arg_1=0, var_441_arg_2=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L646] COND TRUE i < (1 << 1) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_431={7:0}, var_441={10:0}, var_441_arg_0={7:0}, var_441_arg_1=0, var_441_arg_2=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L646] EXPR var_441_arg_0[i] [L646] var_441[i] = var_441_arg_0[i] [L646] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_431={7:0}, var_441={10:0}, var_441_arg_0={7:0}, var_441_arg_1=0, var_441_arg_2=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L646] COND FALSE !(i < (1 << 1)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_431={7:0}, var_441={10:0}, var_441_arg_0={7:0}, var_441_arg_1=0, var_441_arg_2=0, var_442=0, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L647] var_441[(unsigned char) var_441_arg_1] = var_441_arg_2 [L648] SORT_1 var_443_arg_0 = var_442; [L649] SORT_11* var_443_arg_1 = var_441; [L650] SORT_11* var_443_arg_2 = var_431; [L651] SORT_11* var_443 = var_443_arg_0 ? var_443_arg_1 : var_443_arg_2; [L652] SORT_11 var_454_arg_0 = state_148; [L653] SORT_11 var_454_arg_1 = var_450; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_443={7:0}, var_446=0, var_450=0, var_454_arg_0=0, var_454_arg_1=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L654] EXPR var_454_arg_0 & var_454_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_443={7:0}, var_446=0, var_450=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L654] SORT_11 var_454 = var_454_arg_0 & var_454_arg_1; [L655] SORT_11* var_451_arg_0 = var_443; [L656] SORT_1 var_451_arg_1 = input_8; [L657] EXPR var_451_arg_0[(unsigned char) var_451_arg_1] [L657] SORT_11 var_451 = var_451_arg_0[(unsigned char) var_451_arg_1]; [L658] SORT_11 var_452_arg_0 = var_450; [L659] SORT_11 var_452 = ~var_452_arg_0; [L660] SORT_11 var_453_arg_0 = var_451; [L661] SORT_11 var_453_arg_1 = var_452; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_443={7:0}, var_446=0, var_453_arg_0=0, var_453_arg_1=-1, var_454=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L662] EXPR var_453_arg_0 & var_453_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_443={7:0}, var_446=0, var_454=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L662] SORT_11 var_453 = var_453_arg_0 & var_453_arg_1; [L663] SORT_11 var_455_arg_0 = var_454; [L664] SORT_11 var_455_arg_1 = var_453; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_443={7:0}, var_446=0, var_455_arg_0=0, var_455_arg_1=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L665] EXPR var_455_arg_0 | var_455_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_443={7:0}, var_446=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L665] SORT_11 var_455 = var_455_arg_0 | var_455_arg_1; [L666] SORT_11* var_456_arg_0 = var_443; [L667] SORT_1 var_456_arg_1 = input_8; [L668] SORT_11 var_456_arg_2 = var_455; [L669] SORT_14 var_456; [L670] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_443={7:0}, var_446=0, var_456={14:0}, var_456_arg_0={7:0}, var_456_arg_1=0, var_456_arg_2=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L670] COND TRUE i < (1 << 1) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_443={7:0}, var_446=0, var_456={14:0}, var_456_arg_0={7:0}, var_456_arg_1=0, var_456_arg_2=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L670] EXPR var_456_arg_0[i] [L670] var_456[i] = var_456_arg_0[i] [L670] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_443={7:0}, var_446=0, var_456={14:0}, var_456_arg_0={7:0}, var_456_arg_1=0, var_456_arg_2=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L670] COND TRUE i < (1 << 1) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_443={7:0}, var_446=0, var_456={14:0}, var_456_arg_0={7:0}, var_456_arg_1=0, var_456_arg_2=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L670] EXPR var_456_arg_0[i] [L670] var_456[i] = var_456_arg_0[i] [L670] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_443={7:0}, var_446=0, var_456={14:0}, var_456_arg_0={7:0}, var_456_arg_1=0, var_456_arg_2=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L670] COND FALSE !(i < (1 << 1)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_443={7:0}, var_446=0, var_456={14:0}, var_456_arg_0={7:0}, var_456_arg_1=0, var_456_arg_2=0, var_457=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L671] var_456[(unsigned char) var_456_arg_1] = var_456_arg_2 [L672] SORT_1 var_458_arg_0 = var_457; [L673] SORT_11* var_458_arg_1 = var_456; [L674] SORT_11* var_458_arg_2 = var_443; [L675] SORT_11* var_458 = var_458_arg_0 ? var_458_arg_1 : var_458_arg_2; [L676] SORT_11* next_459_arg_1 = var_458; [L677] SORT_1 var_460_arg_0 = input_7; [L678] SORT_1 var_460_arg_1 = var_59; [L679] SORT_1 var_460_arg_2 = var_60; [L680] SORT_1 var_460 = var_460_arg_0 ? var_460_arg_1 : var_460_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L681] EXPR var_460 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L681] var_460 = var_460 & mask_SORT_1 [L682] SORT_1 var_461_arg_0 = var_460; [L683] SORT_1 var_461_arg_1 = var_460; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_461_arg_0=0, var_461_arg_1=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L684] EXPR ((SORT_11)var_461_arg_0 << 1) | var_461_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L684] SORT_11 var_461 = ((SORT_11)var_461_arg_0 << 1) | var_461_arg_1; [L685] EXPR var_461 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L685] var_461 = var_461 & mask_SORT_11 [L686] SORT_1 var_462_arg_0 = var_460; [L687] SORT_11 var_462_arg_1 = var_461; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_462_arg_0=0, var_462_arg_1=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L688] EXPR ((SORT_19)var_462_arg_0 << 2) | var_462_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L688] SORT_19 var_462 = ((SORT_19)var_462_arg_0 << 2) | var_462_arg_1; [L689] EXPR var_462 & mask_SORT_19 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L689] var_462 = var_462 & mask_SORT_19 [L690] SORT_1 var_463_arg_0 = var_460; [L691] SORT_19 var_463_arg_1 = var_462; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_463_arg_0=0, var_463_arg_1=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L692] EXPR ((SORT_191)var_463_arg_0 << 3) | var_463_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L692] SORT_191 var_463 = ((SORT_191)var_463_arg_0 << 3) | var_463_arg_1; [L693] EXPR var_463 & mask_SORT_191 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L693] var_463 = var_463 & mask_SORT_191 [L694] SORT_1 var_464_arg_0 = var_460; [L695] SORT_191 var_464_arg_1 = var_463; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_464_arg_0=0, var_464_arg_1=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L696] EXPR ((SORT_193)var_464_arg_0 << 4) | var_464_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L696] SORT_193 var_464 = ((SORT_193)var_464_arg_0 << 4) | var_464_arg_1; [L697] EXPR var_464 & mask_SORT_193 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L697] var_464 = var_464 & mask_SORT_193 [L698] SORT_1 var_465_arg_0 = var_460; [L699] SORT_193 var_465_arg_1 = var_464; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_465_arg_0=0, var_465_arg_1=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L700] EXPR ((SORT_195)var_465_arg_0 << 5) | var_465_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L700] SORT_195 var_465 = ((SORT_195)var_465_arg_0 << 5) | var_465_arg_1; [L701] EXPR var_465 & mask_SORT_195 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L701] var_465 = var_465 & mask_SORT_195 [L702] SORT_1 var_466_arg_0 = var_460; [L703] SORT_195 var_466_arg_1 = var_465; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_466_arg_0=0, var_466_arg_1=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L704] EXPR ((SORT_197)var_466_arg_0 << 6) | var_466_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L704] SORT_197 var_466 = ((SORT_197)var_466_arg_0 << 6) | var_466_arg_1; [L705] EXPR var_466 & mask_SORT_197 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_460=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L705] var_466 = var_466 & mask_SORT_197 [L706] SORT_1 var_467_arg_0 = var_460; [L707] SORT_197 var_467_arg_1 = var_466; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_467_arg_0=0, var_467_arg_1=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L708] EXPR ((SORT_3)var_467_arg_0 << 7) | var_467_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L708] SORT_3 var_467 = ((SORT_3)var_467_arg_0 << 7) | var_467_arg_1; [L709] EXPR var_467 & mask_SORT_3 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L709] var_467 = var_467 & mask_SORT_3 [L710] SORT_3 var_474_arg_0 = var_467; [L711] SORT_1 var_474 = var_474_arg_0 != 0; [L712] SORT_3 var_471_arg_0 = input_4; [L713] SORT_3 var_471_arg_1 = var_467; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_467=0, var_46=0, var_471_arg_0=0, var_471_arg_1=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L714] EXPR var_471_arg_0 & var_471_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_467=0, var_46=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L714] SORT_3 var_471 = var_471_arg_0 & var_471_arg_1; [L715] SORT_3* var_468_arg_0 = state_13; [L716] SORT_11 var_468_arg_1 = state_148; [L717] EXPR var_468_arg_0[(unsigned char) var_468_arg_1] [L717] SORT_3 var_468 = var_468_arg_0[(unsigned char) var_468_arg_1]; [L718] SORT_3 var_469_arg_0 = var_467; [L719] SORT_3 var_469 = ~var_469_arg_0; [L720] SORT_3 var_470_arg_0 = var_468; [L721] SORT_3 var_470_arg_1 = var_469; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_470_arg_0=0, var_470_arg_1=-1, var_471=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L722] EXPR var_470_arg_0 & var_470_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_471=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L722] SORT_3 var_470 = var_470_arg_0 & var_470_arg_1; [L723] SORT_3 var_472_arg_0 = var_471; [L724] SORT_3 var_472_arg_1 = var_470; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_472_arg_0=0, var_472_arg_1=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L725] EXPR var_472_arg_0 | var_472_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L725] SORT_3 var_472 = var_472_arg_0 | var_472_arg_1; [L726] SORT_3* var_473_arg_0 = state_13; [L727] SORT_11 var_473_arg_1 = state_148; [L728] SORT_3 var_473_arg_2 = var_472; [L729] SORT_12 var_473; [L730] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473={16:0}, var_473_arg_0={6:0}, var_473_arg_1=0, var_473_arg_2=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L730] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473={16:0}, var_473_arg_0={6:0}, var_473_arg_1=0, var_473_arg_2=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L730] EXPR var_473_arg_0[i] [L730] var_473[i] = var_473_arg_0[i] [L730] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473={16:0}, var_473_arg_0={6:0}, var_473_arg_1=0, var_473_arg_2=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L730] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473={16:0}, var_473_arg_0={6:0}, var_473_arg_1=0, var_473_arg_2=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L730] EXPR var_473_arg_0[i] [L730] var_473[i] = var_473_arg_0[i] [L730] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473={16:0}, var_473_arg_0={6:0}, var_473_arg_1=0, var_473_arg_2=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L730] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473={16:0}, var_473_arg_0={6:0}, var_473_arg_1=0, var_473_arg_2=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L730] EXPR var_473_arg_0[i] [L730] var_473[i] = var_473_arg_0[i] [L730] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473={16:0}, var_473_arg_0={6:0}, var_473_arg_1=0, var_473_arg_2=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L730] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473={16:0}, var_473_arg_0={6:0}, var_473_arg_1=0, var_473_arg_2=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L730] EXPR var_473_arg_0[i] [L730] var_473[i] = var_473_arg_0[i] [L730] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=4, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473={16:0}, var_473_arg_0={6:0}, var_473_arg_1=0, var_473_arg_2=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L730] COND FALSE !(i < (1 << 2)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473={16:0}, var_473_arg_0={6:0}, var_473_arg_1=0, var_473_arg_2=0, var_474=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L731] var_473[(unsigned char) var_473_arg_1] = var_473_arg_2 [L732] SORT_1 var_475_arg_0 = var_474; [L733] SORT_3* var_475_arg_1 = var_473; [L734] SORT_3* var_475_arg_2 = state_13; [L735] SORT_3* var_475 = var_475_arg_0 ? var_475_arg_1 : var_475_arg_2; [L736] SORT_3* next_476_arg_1 = var_475; [L737] SORT_1 var_477_arg_0 = input_8; [L738] SORT_1 var_477 = ~var_477_arg_0; [L739] SORT_1 var_478_arg_0 = input_7; [L740] SORT_1 var_478_arg_1 = var_477; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_478_arg_0=0, var_478_arg_1=-1, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L741] EXPR var_478_arg_0 & var_478_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L741] SORT_1 var_478 = var_478_arg_0 & var_478_arg_1; [L742] SORT_1 var_479_arg_0 = var_478; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_479_arg_0=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L743] EXPR var_479_arg_0 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L743] var_479_arg_0 = var_479_arg_0 & mask_SORT_1 [L744] SORT_19 var_479 = var_479_arg_0; [L745] SORT_19 var_480_arg_0 = state_20; [L746] SORT_19 var_480_arg_1 = var_479; [L747] SORT_19 var_480 = var_480_arg_0 + var_480_arg_1; [L748] SORT_1 var_481_arg_0 = input_6; [L749] SORT_1 var_481 = ~var_481_arg_0; [L750] SORT_1 var_482_arg_0 = input_5; [L751] SORT_1 var_482_arg_1 = var_481; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_480=0, var_482_arg_0=0, var_482_arg_1=-1, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L752] EXPR var_482_arg_0 & var_482_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_480=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L752] SORT_1 var_482 = var_482_arg_0 & var_482_arg_1; [L753] SORT_1 var_483_arg_0 = var_482; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_480=0, var_483_arg_0=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L754] EXPR var_483_arg_0 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_480=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L754] var_483_arg_0 = var_483_arg_0 & mask_SORT_1 [L755] SORT_19 var_483 = var_483_arg_0; [L756] SORT_19 var_484_arg_0 = var_480; [L757] SORT_19 var_484_arg_1 = var_483; [L758] SORT_19 var_484 = var_484_arg_0 - var_484_arg_1; [L759] SORT_1 var_485_arg_0 = input_9; [L760] SORT_19 var_485_arg_1 = var_49; [L761] SORT_19 var_485_arg_2 = var_484; [L762] SORT_19 var_485 = var_485_arg_0 ? var_485_arg_1 : var_485_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_485=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L763] EXPR var_485 & mask_SORT_19 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L763] var_485 = var_485 & mask_SORT_19 [L764] SORT_19 next_486_arg_1 = var_485; [L765] SORT_1 var_487_arg_0 = var_86; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_487_arg_0=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0] [L766] EXPR var_487_arg_0 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0] [L766] var_487_arg_0 = var_487_arg_0 & mask_SORT_1 [L767] SORT_19 var_487 = var_487_arg_0; [L768] SORT_19 var_488_arg_0 = state_23; [L769] SORT_19 var_488_arg_1 = var_487; [L770] SORT_19 var_488 = var_488_arg_0 + var_488_arg_1; [L771] SORT_1 var_489_arg_0 = var_74; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_488=0, var_489_arg_0=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L772] EXPR var_489_arg_0 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_488=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L772] var_489_arg_0 = var_489_arg_0 & mask_SORT_1 [L773] SORT_19 var_489 = var_489_arg_0; [L774] SORT_19 var_490_arg_0 = var_488; [L775] SORT_19 var_490_arg_1 = var_489; [L776] SORT_19 var_490 = var_490_arg_0 - var_490_arg_1; [L777] SORT_1 var_491_arg_0 = input_9; [L778] SORT_19 var_491_arg_1 = var_49; [L779] SORT_19 var_491_arg_2 = var_490; [L780] SORT_19 var_491 = var_491_arg_0 ? var_491_arg_1 : var_491_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_491=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L781] EXPR var_491 & mask_SORT_19 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L781] var_491 = var_491 & mask_SORT_19 [L782] SORT_19 next_492_arg_1 = var_491; [L783] SORT_1 var_493_arg_0 = input_7; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_493_arg_0=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L784] EXPR var_493_arg_0 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L784] var_493_arg_0 = var_493_arg_0 & mask_SORT_1 [L785] SORT_19 var_493 = var_493_arg_0; [L786] SORT_19 var_494_arg_0 = state_28; [L787] SORT_19 var_494_arg_1 = var_493; [L788] SORT_19 var_494 = var_494_arg_0 + var_494_arg_1; [L789] SORT_1 var_495_arg_0 = input_5; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_494=0, var_495_arg_0=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L790] EXPR var_495_arg_0 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_494=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L790] var_495_arg_0 = var_495_arg_0 & mask_SORT_1 [L791] SORT_19 var_495 = var_495_arg_0; [L792] SORT_19 var_496_arg_0 = var_494; [L793] SORT_19 var_496_arg_1 = var_495; [L794] SORT_19 var_496 = var_496_arg_0 - var_496_arg_1; [L795] SORT_1 var_497_arg_0 = input_9; [L796] SORT_19 var_497_arg_1 = var_49; [L797] SORT_19 var_497_arg_2 = var_496; [L798] SORT_19 var_497 = var_497_arg_0 ? var_497_arg_1 : var_497_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_497=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L799] EXPR var_497 & mask_SORT_19 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L799] var_497 = var_497 & mask_SORT_19 [L800] SORT_19 next_498_arg_1 = var_497; [L801] SORT_1 var_103_arg_0 = input_10; [L802] SORT_1 var_103_arg_1 = var_40; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_103_arg_0=0, var_103_arg_1=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L803] EXPR var_103_arg_0 & var_103_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L803] SORT_1 var_103 = var_103_arg_0 & var_103_arg_1; [L804] SORT_1 var_104_arg_0 = state_32; [L805] SORT_1 var_104_arg_1 = var_103; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_103=0, var_104_arg_0=0, var_104_arg_1=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L806] EXPR var_104_arg_0 | var_104_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_103=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L806] SORT_1 var_104 = var_104_arg_0 | var_104_arg_1; [L807] SORT_1 var_499_arg_0 = state_32; [L808] SORT_1 var_499_arg_1 = var_59; [L809] SORT_1 var_499_arg_2 = var_104; [L810] SORT_1 var_499 = var_499_arg_0 ? var_499_arg_1 : var_499_arg_2; [L811] SORT_1 var_500_arg_0 = input_9; [L812] SORT_1 var_500_arg_1 = var_60; [L813] SORT_1 var_500_arg_2 = var_499; [L814] SORT_1 var_500 = var_500_arg_0 ? var_500_arg_1 : var_500_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_103=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_500=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L815] EXPR var_500 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_103=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0] [L815] var_500 = var_500 & mask_SORT_1 [L816] SORT_1 next_501_arg_1 = var_500; [L817] SORT_1 var_114_arg_0 = var_53; [L818] SORT_1 var_114_arg_1 = state_33; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_36=0, state_55=0, state_564=0, var_103=0, var_114_arg_0=0, var_114_arg_1=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L819] EXPR var_114_arg_0 | var_114_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_36=0, state_55=0, state_564=0, var_103=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_40=0, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_46=0, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L819] SORT_1 var_114 = var_114_arg_0 | var_114_arg_1; [L820] SORT_1 var_502_arg_0 = input_9; [L821] SORT_1 var_502_arg_1 = var_60; [L822] SORT_1 var_502_arg_2 = var_114; [L823] SORT_1 var_502 = var_502_arg_0 ? var_502_arg_1 : var_502_arg_2; [L824] SORT_1 next_503_arg_1 = var_502; [L825] SORT_1 var_126_arg_0 = var_40; [L826] SORT_1 var_126_arg_1 = var_46; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_36=0, state_55=0, state_564=0, var_103=0, var_126_arg_0=0, var_126_arg_1=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L827] EXPR var_126_arg_0 | var_126_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_36=0, state_55=0, state_564=0, var_103=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L827] SORT_1 var_126 = var_126_arg_0 | var_126_arg_1; [L828] SORT_1 var_127_arg_0 = var_126; [L829] SORT_1 var_127_arg_1 = input_9; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_36=0, state_55=0, state_564=0, var_103=0, var_127_arg_0=0, var_127_arg_1=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L830] EXPR var_127_arg_0 | var_127_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_36=0, state_55=0, state_564=0, var_103=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L830] SORT_1 var_127 = var_127_arg_0 | var_127_arg_1; [L831] SORT_1 var_128_arg_0 = var_127; [L832] SORT_1 var_128_arg_1 = state_32; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_36=0, state_55=0, state_564=0, var_103=0, var_128_arg_0=0, var_128_arg_1=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L833] EXPR var_128_arg_0 | var_128_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_36=0, state_55=0, state_564=0, var_103=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L833] SORT_1 var_128 = var_128_arg_0 | var_128_arg_1; [L834] EXPR var_128 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_36=0, state_55=0, state_564=0, var_103=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L834] var_128 = var_128 & mask_SORT_1 [L835] SORT_1 var_504_arg_0 = var_128; [L836] SORT_19 var_504_arg_1 = var_50; [L837] SORT_19 var_504_arg_2 = state_36; [L838] SORT_19 var_504 = var_504_arg_0 ? var_504_arg_1 : var_504_arg_2; [L839] SORT_1 var_505_arg_0 = input_9; [L840] SORT_19 var_505_arg_1 = var_49; [L841] SORT_19 var_505_arg_2 = var_504; [L842] SORT_19 var_505 = var_505_arg_0 ? var_505_arg_1 : var_505_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_55=0, state_564=0, var_103=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_505=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L843] EXPR var_505 & mask_SORT_19 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_55=0, state_564=0, var_103=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_41=-1, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L843] var_505 = var_505 & mask_SORT_19 [L844] SORT_19 next_506_arg_1 = var_505; [L845] SORT_1 var_111_arg_0 = var_103; [L846] SORT_1 var_111_arg_1 = var_41; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_55=0, state_564=0, var_111_arg_0=0, var_111_arg_1=-1, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L847] EXPR var_111_arg_0 & var_111_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L847] SORT_1 var_111 = var_111_arg_0 & var_111_arg_1; [L848] EXPR var_111 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_4=0, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_55=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L848] var_111 = var_111 & mask_SORT_1 [L849] SORT_1 var_507_arg_0 = var_111; [L850] SORT_3 var_507_arg_1 = input_4; [L851] SORT_3 var_507_arg_2 = state_55; [L852] SORT_3 var_507 = var_507_arg_0 ? var_507_arg_1 : var_507_arg_2; [L853] SORT_1 var_509_arg_0 = input_9; [L854] SORT_3 var_509_arg_1 = var_508; [L855] SORT_3 var_509_arg_2 = var_507; [L856] SORT_3 var_509 = var_509_arg_0 ? var_509_arg_1 : var_509_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_509=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L857] EXPR var_509 & mask_SORT_3 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L857] var_509 = var_509 & mask_SORT_3 [L858] SORT_3 next_510_arg_1 = var_509; [L859] SORT_1 next_511_arg_1 = var_60; [L860] SORT_11 var_520_arg_0 = var_519; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_520_arg_0=2, var_531=1, var_59=1, var_60=0] [L861] EXPR var_520_arg_0 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L861] var_520_arg_0 = var_520_arg_0 & mask_SORT_11 [L862] SORT_19 var_520 = var_520_arg_0; [L863] SORT_19 var_521_arg_0 = state_28; [L864] SORT_19 var_521_arg_1 = var_520; [L865] SORT_1 var_521 = var_521_arg_0 >= var_521_arg_1; [L866] SORT_1 var_522_arg_0 = input_7; [L867] SORT_1 var_522_arg_1 = var_521; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_522_arg_0=0, var_522_arg_1=0, var_531=1, var_59=1, var_60=0] [L868] EXPR var_522_arg_0 & var_522_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L868] SORT_1 var_522 = var_522_arg_0 & var_522_arg_1; [L869] SORT_1 var_523_arg_0 = var_30; [L870] SORT_1 var_523_arg_1 = var_522; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_523_arg_0=0, var_523_arg_1=0, var_531=1, var_59=1, var_60=0] [L871] EXPR var_523_arg_0 | var_523_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L871] SORT_1 var_523 = var_523_arg_0 | var_523_arg_1; [L872] EXPR var_523 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L872] var_523 = var_523 & mask_SORT_1 [L873] SORT_1 var_512_arg_0 = input_5; [L874] SORT_1 var_512 = ~var_512_arg_0; [L875] SORT_11 var_514_arg_0 = var_513; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_512=-1, var_513=3, var_514_arg_0=3, var_519=2, var_523=0, var_531=1, var_59=1, var_60=0] [L876] EXPR var_514_arg_0 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_512=-1, var_513=3, var_519=2, var_523=0, var_531=1, var_59=1, var_60=0] [L876] var_514_arg_0 = var_514_arg_0 & mask_SORT_11 [L877] SORT_19 var_514 = var_514_arg_0; [L878] SORT_19 var_515_arg_0 = state_28; [L879] SORT_19 var_515_arg_1 = var_514; [L880] SORT_1 var_515 = var_515_arg_0 < var_515_arg_1; [L881] SORT_1 var_516_arg_0 = var_512; [L882] SORT_1 var_516_arg_1 = var_515; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_516_arg_0=-1, var_516_arg_1=1, var_519=2, var_523=0, var_531=1, var_59=1, var_60=0] [L883] EXPR var_516_arg_0 | var_516_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_523=0, var_531=1, var_59=1, var_60=0] [L883] SORT_1 var_516 = var_516_arg_0 | var_516_arg_1; [L884] SORT_1 var_517_arg_0 = input_7; [L885] SORT_1 var_517_arg_1 = var_516; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_517_arg_0=0, var_517_arg_1=256, var_519=2, var_523=0, var_531=1, var_59=1, var_60=0] [L886] EXPR var_517_arg_0 & var_517_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_523=0, var_531=1, var_59=1, var_60=0] [L886] SORT_1 var_517 = var_517_arg_0 & var_517_arg_1; [L887] EXPR var_517 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_523=0, var_531=1, var_59=1, var_60=0] [L887] var_517 = var_517 & mask_SORT_1 [L888] SORT_11* var_251_arg_0 = state_249; [L889] SORT_11 var_251_arg_1 = state_148; [L890] EXPR var_251_arg_0[(unsigned char) var_251_arg_1] [L890] SORT_11 var_251 = var_251_arg_0[(unsigned char) var_251_arg_1]; [L891] SORT_1 var_518_arg_0 = var_517; [L892] SORT_11 var_518_arg_1 = var_251; [L893] SORT_11 var_518_arg_2 = state_148; [L894] SORT_11 var_518 = var_518_arg_0 ? var_518_arg_1 : var_518_arg_2; [L895] SORT_1 var_524_arg_0 = var_523; [L896] SORT_11 var_524_arg_1 = var_16; [L897] SORT_11 var_524_arg_2 = var_518; [L898] SORT_11 var_524 = var_524_arg_0 ? var_524_arg_1 : var_524_arg_2; [L899] SORT_1 var_525_arg_0 = input_5; [L900] SORT_11 var_525_arg_1 = var_524; [L901] SORT_11 var_525_arg_2 = var_518; [L902] SORT_11 var_525 = var_525_arg_0 ? var_525_arg_1 : var_525_arg_2; [L903] SORT_1 var_526_arg_0 = input_9; [L904] SORT_11 var_526_arg_1 = var_401; [L905] SORT_11 var_526_arg_2 = var_525; [L906] SORT_11 var_526 = var_526_arg_0 ? var_526_arg_1 : var_526_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_526=0, var_531=1, var_59=1, var_60=0] [L907] EXPR var_526 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L907] var_526 = var_526 & mask_SORT_11 [L908] SORT_11 next_527_arg_1 = var_526; [L909] SORT_1 var_528_arg_0 = input_5; [L910] SORT_11 var_528_arg_1 = var_16; [L911] SORT_11 var_528_arg_2 = state_153; [L912] SORT_11 var_528 = var_528_arg_0 ? var_528_arg_1 : var_528_arg_2; [L913] SORT_1 var_529_arg_0 = input_9; [L914] SORT_11 var_529_arg_1 = var_513; [L915] SORT_11 var_529_arg_2 = var_528; [L916] SORT_11 var_529 = var_529_arg_0 ? var_529_arg_1 : var_529_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_529=0, var_531=1, var_59=1, var_60=0] [L917] EXPR var_529 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_30=0, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L917] var_529 = var_529 & mask_SORT_11 [L918] SORT_11 next_530_arg_1 = var_529; [L919] SORT_1 var_580_arg_0 = var_30; [L920] SORT_1 var_580 = ~var_580_arg_0; [L921] SORT_1 var_581_arg_0 = input_5; [L922] SORT_1 var_581_arg_1 = var_580; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_581_arg_0=0, var_581_arg_1=-1, var_59=1, var_60=0] [L923] EXPR var_581_arg_0 & var_581_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L923] SORT_1 var_581 = var_581_arg_0 & var_581_arg_1; [L924] EXPR var_581 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L924] var_581 = var_581 & mask_SORT_1 [L925] SORT_1 var_582_arg_0 = var_581; [L926] SORT_1 var_582_arg_1 = var_59; [L927] SORT_1 var_582_arg_2 = var_60; [L928] SORT_1 var_582 = var_582_arg_0 ? var_582_arg_1 : var_582_arg_2; [L929] SORT_1 var_583_arg_0 = input_9; [L930] SORT_1 var_583_arg_1 = var_60; [L931] SORT_1 var_583_arg_2 = var_582; [L932] SORT_1 var_583 = var_583_arg_0 ? var_583_arg_1 : var_583_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_583=0, var_59=1, var_60=0] [L933] EXPR var_583 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L933] var_583 = var_583 & mask_SORT_1 [L934] SORT_1 var_584_arg_0 = var_583; [L935] SORT_1 var_584_arg_1 = var_583; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_584_arg_0=0, var_584_arg_1=0, var_59=1, var_60=0] [L936] EXPR ((SORT_11)var_584_arg_0 << 1) | var_584_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L936] SORT_11 var_584 = ((SORT_11)var_584_arg_0 << 1) | var_584_arg_1; [L937] EXPR var_584 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_446=0, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L937] var_584 = var_584 & mask_SORT_11 [L938] SORT_11 var_591_arg_0 = var_584; [L939] SORT_1 var_591 = var_591_arg_0 != 0; [L940] SORT_1 var_567_arg_0 = var_446; [L941] SORT_1 var_567 = ~var_567_arg_0; [L942] SORT_1 var_568_arg_0 = input_7; [L943] SORT_1 var_568_arg_1 = var_567; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_568_arg_0=0, var_568_arg_1=-1, var_584=0, var_591=0, var_59=1, var_60=0] [L944] EXPR var_568_arg_0 & var_568_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_584=0, var_591=0, var_59=1, var_60=0] [L944] SORT_1 var_568 = var_568_arg_0 & var_568_arg_1; [L945] EXPR var_568 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_584=0, var_591=0, var_59=1, var_60=0] [L945] var_568 = var_568 & mask_SORT_1 [L946] SORT_1 var_569_arg_0 = var_568; [L947] SORT_1 var_569_arg_1 = var_59; [L948] SORT_1 var_569_arg_2 = var_60; [L949] SORT_1 var_569 = var_569_arg_0 ? var_569_arg_1 : var_569_arg_2; [L950] SORT_1 var_570_arg_0 = input_9; [L951] SORT_1 var_570_arg_1 = var_60; [L952] SORT_1 var_570_arg_2 = var_569; [L953] SORT_1 var_570 = var_570_arg_0 ? var_570_arg_1 : var_570_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_570=0, var_584=0, var_591=0, var_59=1, var_60=0] [L954] EXPR var_570 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_584=0, var_591=0, var_59=1, var_60=0] [L954] var_570 = var_570 & mask_SORT_1 [L955] SORT_1 var_571_arg_0 = var_570; [L956] SORT_1 var_571_arg_1 = var_570; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_571_arg_0=0, var_571_arg_1=0, var_584=0, var_591=0, var_59=1, var_60=0] [L957] EXPR ((SORT_11)var_571_arg_0 << 1) | var_571_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_584=0, var_591=0, var_59=1, var_60=0] [L957] SORT_11 var_571 = ((SORT_11)var_571_arg_0 << 1) | var_571_arg_1; [L958] EXPR var_571 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_584=0, var_591=0, var_59=1, var_60=0] [L958] var_571 = var_571 & mask_SORT_11 [L959] SORT_11 var_578_arg_0 = var_571; [L960] SORT_1 var_578 = var_578_arg_0 != 0; [L961] SORT_11 var_562_arg_0 = var_403; [L962] SORT_1 var_562 = var_562_arg_0 != 0; [L963] SORT_11 var_554_arg_0 = var_403; [L964] SORT_1 var_554 = var_554_arg_0 != 0; [L965] SORT_11 var_546_arg_0 = var_403; [L966] SORT_1 var_546 = var_546_arg_0 != 0; [L967] SORT_11 var_538_arg_0 = var_403; [L968] SORT_1 var_538 = var_538_arg_0 != 0; [L969] SORT_11 var_535_arg_0 = var_531; [L970] SORT_11 var_535_arg_1 = var_403; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_535_arg_0=1, var_535_arg_1=0, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L971] EXPR var_535_arg_0 & var_535_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L971] SORT_11 var_535 = var_535_arg_0 & var_535_arg_1; [L972] SORT_11* var_532_arg_0 = state_249; [L973] SORT_11 var_532_arg_1 = var_401; [L974] EXPR var_532_arg_0[(unsigned char) var_532_arg_1] [L974] SORT_11 var_532 = var_532_arg_0[(unsigned char) var_532_arg_1]; [L975] SORT_11 var_533_arg_0 = var_403; [L976] SORT_11 var_533 = ~var_533_arg_0; [L977] SORT_11 var_534_arg_0 = var_532; [L978] SORT_11 var_534_arg_1 = var_533; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_534_arg_0=0, var_534_arg_1=-1, var_535=0, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L979] EXPR var_534_arg_0 & var_534_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_535=0, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L979] SORT_11 var_534 = var_534_arg_0 & var_534_arg_1; [L980] SORT_11 var_536_arg_0 = var_535; [L981] SORT_11 var_536_arg_1 = var_534; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_536_arg_0=0, var_536_arg_1=0, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L982] EXPR var_536_arg_0 | var_536_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L982] SORT_11 var_536 = var_536_arg_0 | var_536_arg_1; [L983] SORT_11* var_537_arg_0 = state_249; [L984] SORT_11 var_537_arg_1 = var_401; [L985] SORT_11 var_537_arg_2 = var_536; [L986] SORT_248 var_537; [L987] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537={22:0}, var_537_arg_0={27:0}, var_537_arg_1=0, var_537_arg_2=0, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L987] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537={22:0}, var_537_arg_0={27:0}, var_537_arg_1=0, var_537_arg_2=0, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L987] EXPR var_537_arg_0[i] [L987] var_537[i] = var_537_arg_0[i] [L987] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537={22:0}, var_537_arg_0={27:0}, var_537_arg_1=0, var_537_arg_2=0, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L987] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537={22:0}, var_537_arg_0={27:0}, var_537_arg_1=0, var_537_arg_2=0, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L987] EXPR var_537_arg_0[i] [L987] var_537[i] = var_537_arg_0[i] [L987] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537={22:0}, var_537_arg_0={27:0}, var_537_arg_1=0, var_537_arg_2=0, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L987] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537={22:0}, var_537_arg_0={27:0}, var_537_arg_1=0, var_537_arg_2=0, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L987] EXPR var_537_arg_0[i] [L987] var_537[i] = var_537_arg_0[i] [L987] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537={22:0}, var_537_arg_0={27:0}, var_537_arg_1=0, var_537_arg_2=0, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L987] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537={22:0}, var_537_arg_0={27:0}, var_537_arg_1=0, var_537_arg_2=0, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L987] EXPR var_537_arg_0[i] [L987] var_537[i] = var_537_arg_0[i] [L987] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=4, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537={22:0}, var_537_arg_0={27:0}, var_537_arg_1=0, var_537_arg_2=0, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L987] COND FALSE !(i < (1 << 2)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537={22:0}, var_537_arg_0={27:0}, var_537_arg_1=0, var_537_arg_2=0, var_538=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L988] var_537[(unsigned char) var_537_arg_1] = var_537_arg_2 [L989] SORT_1 var_539_arg_0 = var_538; [L990] SORT_11* var_539_arg_1 = var_537; [L991] SORT_11* var_539_arg_2 = state_249; [L992] SORT_11* var_539 = var_539_arg_0 ? var_539_arg_1 : var_539_arg_2; [L993] SORT_11 var_543_arg_0 = var_519; [L994] SORT_11 var_543_arg_1 = var_403; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_543_arg_0=2, var_543_arg_1=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L995] EXPR var_543_arg_0 & var_543_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L995] SORT_11 var_543 = var_543_arg_0 & var_543_arg_1; [L996] SORT_11* var_540_arg_0 = var_539; [L997] SORT_11 var_540_arg_1 = var_531; [L998] EXPR var_540_arg_0[(unsigned char) var_540_arg_1] [L998] SORT_11 var_540 = var_540_arg_0[(unsigned char) var_540_arg_1]; [L999] SORT_11 var_541_arg_0 = var_403; [L1000] SORT_11 var_541 = ~var_541_arg_0; [L1001] SORT_11 var_542_arg_0 = var_540; [L1002] SORT_11 var_542_arg_1 = var_541; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_542_arg_0=0, var_542_arg_1=-1, var_543=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1003] EXPR var_542_arg_0 & var_542_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_543=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1003] SORT_11 var_542 = var_542_arg_0 & var_542_arg_1; [L1004] SORT_11 var_544_arg_0 = var_543; [L1005] SORT_11 var_544_arg_1 = var_542; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_544_arg_0=0, var_544_arg_1=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1006] EXPR var_544_arg_0 | var_544_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1006] SORT_11 var_544 = var_544_arg_0 | var_544_arg_1; [L1007] SORT_11* var_545_arg_0 = var_539; [L1008] SORT_11 var_545_arg_1 = var_531; [L1009] SORT_11 var_545_arg_2 = var_544; [L1010] SORT_248 var_545; [L1011] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_545={18:0}, var_545_arg_0={27:0}, var_545_arg_1=1, var_545_arg_2=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1011] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_545={18:0}, var_545_arg_0={27:0}, var_545_arg_1=1, var_545_arg_2=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1011] EXPR var_545_arg_0[i] [L1011] var_545[i] = var_545_arg_0[i] [L1011] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_545={18:0}, var_545_arg_0={27:0}, var_545_arg_1=1, var_545_arg_2=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1011] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_545={18:0}, var_545_arg_0={27:0}, var_545_arg_1=1, var_545_arg_2=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1011] EXPR var_545_arg_0[i] [L1011] var_545[i] = var_545_arg_0[i] [L1011] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_545={18:0}, var_545_arg_0={27:0}, var_545_arg_1=1, var_545_arg_2=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1011] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_545={18:0}, var_545_arg_0={27:0}, var_545_arg_1=1, var_545_arg_2=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1011] EXPR var_545_arg_0[i] [L1011] var_545[i] = var_545_arg_0[i] [L1011] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_545={18:0}, var_545_arg_0={27:0}, var_545_arg_1=1, var_545_arg_2=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1011] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_545={18:0}, var_545_arg_0={27:0}, var_545_arg_1=1, var_545_arg_2=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1011] EXPR var_545_arg_0[i] [L1011] var_545[i] = var_545_arg_0[i] [L1011] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=4, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_545={18:0}, var_545_arg_0={27:0}, var_545_arg_1=1, var_545_arg_2=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1011] COND FALSE !(i < (1 << 2)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_539={27:0}, var_545={18:0}, var_545_arg_0={27:0}, var_545_arg_1=1, var_545_arg_2=0, var_546=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1012] var_545[(unsigned char) var_545_arg_1] = var_545_arg_2 [L1013] SORT_1 var_547_arg_0 = var_546; [L1014] SORT_11* var_547_arg_1 = var_545; [L1015] SORT_11* var_547_arg_2 = var_539; [L1016] SORT_11* var_547 = var_547_arg_0 ? var_547_arg_1 : var_547_arg_2; [L1017] SORT_11 var_551_arg_0 = var_513; [L1018] SORT_11 var_551_arg_1 = var_403; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_551_arg_0=3, var_551_arg_1=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1019] EXPR var_551_arg_0 & var_551_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1019] SORT_11 var_551 = var_551_arg_0 & var_551_arg_1; [L1020] SORT_11* var_548_arg_0 = var_547; [L1021] SORT_11 var_548_arg_1 = var_519; [L1022] EXPR var_548_arg_0[(unsigned char) var_548_arg_1] [L1022] SORT_11 var_548 = var_548_arg_0[(unsigned char) var_548_arg_1]; [L1023] SORT_11 var_549_arg_0 = var_403; [L1024] SORT_11 var_549 = ~var_549_arg_0; [L1025] SORT_11 var_550_arg_0 = var_548; [L1026] SORT_11 var_550_arg_1 = var_549; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_550_arg_0=0, var_550_arg_1=-1, var_551=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1027] EXPR var_550_arg_0 & var_550_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_551=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1027] SORT_11 var_550 = var_550_arg_0 & var_550_arg_1; [L1028] SORT_11 var_552_arg_0 = var_551; [L1029] SORT_11 var_552_arg_1 = var_550; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_552_arg_0=0, var_552_arg_1=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1030] EXPR var_552_arg_0 | var_552_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1030] SORT_11 var_552 = var_552_arg_0 | var_552_arg_1; [L1031] SORT_11* var_553_arg_0 = var_547; [L1032] SORT_11 var_553_arg_1 = var_519; [L1033] SORT_11 var_553_arg_2 = var_552; [L1034] SORT_248 var_553; [L1035] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_553={24:0}, var_553_arg_0={27:0}, var_553_arg_1=2, var_553_arg_2=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1035] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_553={24:0}, var_553_arg_0={27:0}, var_553_arg_1=2, var_553_arg_2=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1035] EXPR var_553_arg_0[i] [L1035] var_553[i] = var_553_arg_0[i] [L1035] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_553={24:0}, var_553_arg_0={27:0}, var_553_arg_1=2, var_553_arg_2=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1035] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_553={24:0}, var_553_arg_0={27:0}, var_553_arg_1=2, var_553_arg_2=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1035] EXPR var_553_arg_0[i] [L1035] var_553[i] = var_553_arg_0[i] [L1035] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_553={24:0}, var_553_arg_0={27:0}, var_553_arg_1=2, var_553_arg_2=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1035] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_553={24:0}, var_553_arg_0={27:0}, var_553_arg_1=2, var_553_arg_2=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1035] EXPR var_553_arg_0[i] [L1035] var_553[i] = var_553_arg_0[i] [L1035] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_553={24:0}, var_553_arg_0={27:0}, var_553_arg_1=2, var_553_arg_2=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1035] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_553={24:0}, var_553_arg_0={27:0}, var_553_arg_1=2, var_553_arg_2=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1035] EXPR var_553_arg_0[i] [L1035] var_553[i] = var_553_arg_0[i] [L1035] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=4, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_553={24:0}, var_553_arg_0={27:0}, var_553_arg_1=2, var_553_arg_2=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1035] COND FALSE !(i < (1 << 2)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_547={27:0}, var_553={24:0}, var_553_arg_0={27:0}, var_553_arg_1=2, var_553_arg_2=0, var_554=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1036] var_553[(unsigned char) var_553_arg_1] = var_553_arg_2 [L1037] SORT_1 var_555_arg_0 = var_554; [L1038] SORT_11* var_555_arg_1 = var_553; [L1039] SORT_11* var_555_arg_2 = var_547; [L1040] SORT_11* var_555 = var_555_arg_0 ? var_555_arg_1 : var_555_arg_2; [L1041] SORT_11 var_559_arg_0 = var_401; [L1042] SORT_11 var_559_arg_1 = var_403; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_559_arg_0=0, var_559_arg_1=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1043] EXPR var_559_arg_0 & var_559_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_403=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1043] SORT_11 var_559 = var_559_arg_0 & var_559_arg_1; [L1044] SORT_11* var_556_arg_0 = var_555; [L1045] SORT_11 var_556_arg_1 = var_513; [L1046] EXPR var_556_arg_0[(unsigned char) var_556_arg_1] [L1046] SORT_11 var_556 = var_556_arg_0[(unsigned char) var_556_arg_1]; [L1047] SORT_11 var_557_arg_0 = var_403; [L1048] SORT_11 var_557 = ~var_557_arg_0; [L1049] SORT_11 var_558_arg_0 = var_556; [L1050] SORT_11 var_558_arg_1 = var_557; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_558_arg_0=0, var_558_arg_1=-1, var_559=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1051] EXPR var_558_arg_0 & var_558_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_559=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1051] SORT_11 var_558 = var_558_arg_0 & var_558_arg_1; [L1052] SORT_11 var_560_arg_0 = var_559; [L1053] SORT_11 var_560_arg_1 = var_558; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_560_arg_0=0, var_560_arg_1=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1054] EXPR var_560_arg_0 | var_560_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1054] SORT_11 var_560 = var_560_arg_0 | var_560_arg_1; [L1055] SORT_11* var_561_arg_0 = var_555; [L1056] SORT_11 var_561_arg_1 = var_513; [L1057] SORT_11 var_561_arg_2 = var_560; [L1058] SORT_248 var_561; [L1059] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_561={19:0}, var_561_arg_0={27:0}, var_561_arg_1=3, var_561_arg_2=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1059] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_561={19:0}, var_561_arg_0={27:0}, var_561_arg_1=3, var_561_arg_2=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1059] EXPR var_561_arg_0[i] [L1059] var_561[i] = var_561_arg_0[i] [L1059] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_561={19:0}, var_561_arg_0={27:0}, var_561_arg_1=3, var_561_arg_2=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1059] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_561={19:0}, var_561_arg_0={27:0}, var_561_arg_1=3, var_561_arg_2=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1059] EXPR var_561_arg_0[i] [L1059] var_561[i] = var_561_arg_0[i] [L1059] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_561={19:0}, var_561_arg_0={27:0}, var_561_arg_1=3, var_561_arg_2=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1059] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_561={19:0}, var_561_arg_0={27:0}, var_561_arg_1=3, var_561_arg_2=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1059] EXPR var_561_arg_0[i] [L1059] var_561[i] = var_561_arg_0[i] [L1059] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_561={19:0}, var_561_arg_0={27:0}, var_561_arg_1=3, var_561_arg_2=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1059] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_561={19:0}, var_561_arg_0={27:0}, var_561_arg_1=3, var_561_arg_2=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1059] EXPR var_561_arg_0[i] [L1059] var_561[i] = var_561_arg_0[i] [L1059] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=4, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_561={19:0}, var_561_arg_0={27:0}, var_561_arg_1=3, var_561_arg_2=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1059] COND FALSE !(i < (1 << 2)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_39=0, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_555={27:0}, var_561={19:0}, var_561_arg_0={27:0}, var_561_arg_1=3, var_561_arg_2=0, var_562=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1060] var_561[(unsigned char) var_561_arg_1] = var_561_arg_2 [L1061] SORT_1 var_563_arg_0 = var_562; [L1062] SORT_11* var_563_arg_1 = var_561; [L1063] SORT_11* var_563_arg_2 = var_555; [L1064] SORT_11* var_563 = var_563_arg_0 ? var_563_arg_1 : var_563_arg_2; [L1065] SORT_1 var_565_arg_0 = input_8; [L1066] SORT_11 var_565_arg_1 = state_330; [L1067] SORT_11 var_565_arg_2 = state_564; [L1068] SORT_11 var_565 = var_565_arg_0 ? var_565_arg_1 : var_565_arg_2; [L1069] SORT_1 var_566_arg_0 = var_39; [L1070] SORT_11 var_566_arg_1 = state_329; [L1071] SORT_11 var_566_arg_2 = var_565; [L1072] SORT_11 var_566 = var_566_arg_0 ? var_566_arg_1 : var_566_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_566=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1073] EXPR var_566 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1073] var_566 = var_566 & mask_SORT_11 [L1074] SORT_11 var_575_arg_0 = state_148; [L1075] SORT_11 var_575_arg_1 = var_571; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_566=0, var_571=0, var_575_arg_0=0, var_575_arg_1=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1076] EXPR var_575_arg_0 & var_575_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_566=0, var_571=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1076] SORT_11 var_575 = var_575_arg_0 & var_575_arg_1; [L1077] SORT_11* var_572_arg_0 = var_563; [L1078] SORT_11 var_572_arg_1 = var_566; [L1079] EXPR var_572_arg_0[(unsigned char) var_572_arg_1] [L1079] SORT_11 var_572 = var_572_arg_0[(unsigned char) var_572_arg_1]; [L1080] SORT_11 var_573_arg_0 = var_571; [L1081] SORT_11 var_573 = ~var_573_arg_0; [L1082] SORT_11 var_574_arg_0 = var_572; [L1083] SORT_11 var_574_arg_1 = var_573; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_566=0, var_574_arg_0=0, var_574_arg_1=-1, var_575=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1084] EXPR var_574_arg_0 & var_574_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_566=0, var_575=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1084] SORT_11 var_574 = var_574_arg_0 & var_574_arg_1; [L1085] SORT_11 var_576_arg_0 = var_575; [L1086] SORT_11 var_576_arg_1 = var_574; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_566=0, var_576_arg_0=0, var_576_arg_1=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1087] EXPR var_576_arg_0 | var_576_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_566=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1087] SORT_11 var_576 = var_576_arg_0 | var_576_arg_1; [L1088] SORT_11* var_577_arg_0 = var_563; [L1089] SORT_11 var_577_arg_1 = var_566; [L1090] SORT_11 var_577_arg_2 = var_576; [L1091] SORT_248 var_577; [L1092] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_577={20:0}, var_577_arg_0={27:0}, var_577_arg_1=0, var_577_arg_2=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1092] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_577={20:0}, var_577_arg_0={27:0}, var_577_arg_1=0, var_577_arg_2=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1092] EXPR var_577_arg_0[i] [L1092] var_577[i] = var_577_arg_0[i] [L1092] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_577={20:0}, var_577_arg_0={27:0}, var_577_arg_1=0, var_577_arg_2=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1092] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_577={20:0}, var_577_arg_0={27:0}, var_577_arg_1=0, var_577_arg_2=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1092] EXPR var_577_arg_0[i] [L1092] var_577[i] = var_577_arg_0[i] [L1092] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_577={20:0}, var_577_arg_0={27:0}, var_577_arg_1=0, var_577_arg_2=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1092] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_577={20:0}, var_577_arg_0={27:0}, var_577_arg_1=0, var_577_arg_2=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1092] EXPR var_577_arg_0[i] [L1092] var_577[i] = var_577_arg_0[i] [L1092] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_577={20:0}, var_577_arg_0={27:0}, var_577_arg_1=0, var_577_arg_2=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1092] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_577={20:0}, var_577_arg_0={27:0}, var_577_arg_1=0, var_577_arg_2=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1092] EXPR var_577_arg_0[i] [L1092] var_577[i] = var_577_arg_0[i] [L1092] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=4, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_577={20:0}, var_577_arg_0={27:0}, var_577_arg_1=0, var_577_arg_2=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1092] COND FALSE !(i < (1 << 2)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_16=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_563={27:0}, var_577={20:0}, var_577_arg_0={27:0}, var_577_arg_1=0, var_577_arg_2=0, var_578=0, var_584=0, var_591=0, var_59=1, var_60=0] [L1093] var_577[(unsigned char) var_577_arg_1] = var_577_arg_2 [L1094] SORT_1 var_579_arg_0 = var_578; [L1095] SORT_11* var_579_arg_1 = var_577; [L1096] SORT_11* var_579_arg_2 = var_563; [L1097] SORT_11* var_579 = var_579_arg_0 ? var_579_arg_1 : var_579_arg_2; [L1098] SORT_11 var_588_arg_0 = var_16; [L1099] SORT_11 var_588_arg_1 = var_584; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_584=0, var_588_arg_0=0, var_588_arg_1=0, var_591=0, var_59=1, var_60=0] [L1100] EXPR var_588_arg_0 & var_588_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_584=0, var_591=0, var_59=1, var_60=0] [L1100] SORT_11 var_588 = var_588_arg_0 & var_588_arg_1; [L1101] SORT_11* var_585_arg_0 = var_579; [L1102] SORT_11 var_585_arg_1 = state_153; [L1103] EXPR var_585_arg_0[(unsigned char) var_585_arg_1] [L1103] SORT_11 var_585 = var_585_arg_0[(unsigned char) var_585_arg_1]; [L1104] SORT_11 var_586_arg_0 = var_584; [L1105] SORT_11 var_586 = ~var_586_arg_0; [L1106] SORT_11 var_587_arg_0 = var_585; [L1107] SORT_11 var_587_arg_1 = var_586; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_587_arg_0=0, var_587_arg_1=-1, var_588=0, var_591=0, var_59=1, var_60=0] [L1108] EXPR var_587_arg_0 & var_587_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_588=0, var_591=0, var_59=1, var_60=0] [L1108] SORT_11 var_587 = var_587_arg_0 & var_587_arg_1; [L1109] SORT_11 var_589_arg_0 = var_588; [L1110] SORT_11 var_589_arg_1 = var_587; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_589_arg_0=0, var_589_arg_1=0, var_591=0, var_59=1, var_60=0] [L1111] EXPR var_589_arg_0 | var_589_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_591=0, var_59=1, var_60=0] [L1111] SORT_11 var_589 = var_589_arg_0 | var_589_arg_1; [L1112] SORT_11* var_590_arg_0 = var_579; [L1113] SORT_11 var_590_arg_1 = state_153; [L1114] SORT_11 var_590_arg_2 = var_589; [L1115] SORT_248 var_590; [L1116] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_590={28:0}, var_590_arg_0={27:0}, var_590_arg_1=0, var_590_arg_2=0, var_591=0, var_59=1, var_60=0] [L1116] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_590={28:0}, var_590_arg_0={27:0}, var_590_arg_1=0, var_590_arg_2=0, var_591=0, var_59=1, var_60=0] [L1116] EXPR var_590_arg_0[i] [L1116] var_590[i] = var_590_arg_0[i] [L1116] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_590={28:0}, var_590_arg_0={27:0}, var_590_arg_1=0, var_590_arg_2=0, var_591=0, var_59=1, var_60=0] [L1116] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_590={28:0}, var_590_arg_0={27:0}, var_590_arg_1=0, var_590_arg_2=0, var_591=0, var_59=1, var_60=0] [L1116] EXPR var_590_arg_0[i] [L1116] var_590[i] = var_590_arg_0[i] [L1116] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_590={28:0}, var_590_arg_0={27:0}, var_590_arg_1=0, var_590_arg_2=0, var_591=0, var_59=1, var_60=0] [L1116] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_590={28:0}, var_590_arg_0={27:0}, var_590_arg_1=0, var_590_arg_2=0, var_591=0, var_59=1, var_60=0] [L1116] EXPR var_590_arg_0[i] [L1116] var_590[i] = var_590_arg_0[i] [L1116] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_590={28:0}, var_590_arg_0={27:0}, var_590_arg_1=0, var_590_arg_2=0, var_591=0, var_59=1, var_60=0] [L1116] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_590={28:0}, var_590_arg_0={27:0}, var_590_arg_1=0, var_590_arg_2=0, var_591=0, var_59=1, var_60=0] [L1116] EXPR var_590_arg_0[i] [L1116] var_590[i] = var_590_arg_0[i] [L1116] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=4, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_590={28:0}, var_590_arg_0={27:0}, var_590_arg_1=0, var_590_arg_2=0, var_591=0, var_59=1, var_60=0] [L1116] COND FALSE !(i < (1 << 2)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_7=0, input_8=0, input_9=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, state_13={6:0}, state_148=0, state_15={7:0}, state_249={27:0}, state_254=0, state_329=0, state_330=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_579={27:0}, var_590={28:0}, var_590_arg_0={27:0}, var_590_arg_1=0, var_590_arg_2=0, var_591=0, var_59=1, var_60=0] [L1117] var_590[(unsigned char) var_590_arg_1] = var_590_arg_2 [L1118] SORT_1 var_592_arg_0 = var_591; [L1119] SORT_11* var_592_arg_1 = var_590; [L1120] SORT_11* var_592_arg_2 = var_579; [L1121] SORT_11* var_592 = var_592_arg_0 ? var_592_arg_1 : var_592_arg_2; [L1122] SORT_11* next_593_arg_1 = var_592; [L1123] SORT_1 var_594_arg_0 = input_8; [L1124] SORT_11 var_594_arg_1 = state_329; [L1125] SORT_11 var_594_arg_2 = state_148; [L1126] SORT_11 var_594 = var_594_arg_0 ? var_594_arg_1 : var_594_arg_2; [L1127] SORT_1 var_595_arg_0 = input_7; [L1128] SORT_11 var_595_arg_1 = var_594; [L1129] SORT_11 var_595_arg_2 = state_329; [L1130] SORT_11 var_595 = var_595_arg_0 ? var_595_arg_1 : var_595_arg_2; [L1131] SORT_1 var_596_arg_0 = input_9; [L1132] SORT_11 var_596_arg_1 = var_401; [L1133] SORT_11 var_596_arg_2 = var_595; [L1134] SORT_11 var_596 = var_596_arg_0 ? var_596_arg_1 : var_596_arg_2; [L1135] SORT_11 next_597_arg_1 = var_596; [L1136] SORT_1 var_598_arg_0 = input_8; [L1137] SORT_11 var_598_arg_1 = state_148; [L1138] SORT_11 var_598_arg_2 = state_330; [L1139] SORT_11 var_598 = var_598_arg_0 ? var_598_arg_1 : var_598_arg_2; [L1140] SORT_1 var_599_arg_0 = input_7; [L1141] SORT_11 var_599_arg_1 = var_598; [L1142] SORT_11 var_599_arg_2 = state_330; [L1143] SORT_11 var_599 = var_599_arg_0 ? var_599_arg_1 : var_599_arg_2; [L1144] SORT_1 var_600_arg_0 = input_9; [L1145] SORT_11 var_600_arg_1 = var_401; [L1146] SORT_11 var_600_arg_2 = var_599; [L1147] SORT_11 var_600 = var_600_arg_0 ? var_600_arg_1 : var_600_arg_2; [L1148] SORT_11 next_601_arg_1 = var_600; [L1150] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1150] COND TRUE i < (1 << 1) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1150] EXPR next_459_arg_1[i] [L1150] state_15[i] = next_459_arg_1[i] [L1150] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1150] COND TRUE i < (1 << 1) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1150] EXPR next_459_arg_1[i] [L1150] state_15[i] = next_459_arg_1[i] [L1150] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1150] COND FALSE !(i < (1 << 1)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1151] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1151] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1151] EXPR next_476_arg_1[i] [L1151] state_13[i] = next_476_arg_1[i] [L1151] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1151] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1151] EXPR next_476_arg_1[i] [L1151] state_13[i] = next_476_arg_1[i] [L1151] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1151] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1151] EXPR next_476_arg_1[i] [L1151] state_13[i] = next_476_arg_1[i] [L1151] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1151] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1151] EXPR next_476_arg_1[i] [L1151] state_13[i] = next_476_arg_1[i] [L1151] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=4, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1151] COND FALSE !(i < (1 << 2)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_486_arg_1=0, next_492_arg_1=0, next_498_arg_1=0, next_501_arg_1=0, next_503_arg_1=0, next_506_arg_1=0, next_510_arg_1=0, next_511_arg_1=0, next_527_arg_1=0, next_530_arg_1=0, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_15={7:0}, state_249={27:0}, state_254=0, state_564=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1152] state_20 = next_486_arg_1 [L1153] state_23 = next_492_arg_1 [L1154] state_28 = next_498_arg_1 [L1155] state_32 = next_501_arg_1 [L1156] state_33 = next_503_arg_1 [L1157] state_36 = next_506_arg_1 [L1158] state_55 = next_510_arg_1 [L1159] state_61 = next_511_arg_1 [L1160] state_148 = next_527_arg_1 [L1161] state_153 = next_530_arg_1 [L1162] unsigned char i = 0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1162] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1162] EXPR next_593_arg_1[i] [L1162] state_249[i] = next_593_arg_1[i] [L1162] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1162] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1162] EXPR next_593_arg_1[i] [L1162] state_249[i] = next_593_arg_1[i] [L1162] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1162] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=2, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1162] EXPR next_593_arg_1[i] [L1162] state_249[i] = next_593_arg_1[i] [L1162] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1162] COND TRUE i < (1 << 2) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=3, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1162] EXPR next_593_arg_1[i] [L1162] state_249[i] = next_593_arg_1[i] [L1162] ++i VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, i=4, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1162] COND FALSE !(i < (1 << 2)) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, next_459_arg_1={7:0}, next_476_arg_1={6:0}, next_593_arg_1={27:0}, next_597_arg_1=0, next_601_arg_1=0, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_32=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_409_arg_0={7:0}, var_417_arg_0={7:0}, var_429_arg_0={7:0}, var_441_arg_0={7:0}, var_456_arg_0={7:0}, var_473_arg_0={6:0}, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_537_arg_0={27:0}, var_545_arg_0={27:0}, var_553_arg_0={27:0}, var_561_arg_0={27:0}, var_577_arg_0={27:0}, var_590_arg_0={27:0}, var_59=1, var_60=0] [L1163] state_329 = next_597_arg_1 [L1164] state_330 = next_601_arg_1 [L263] input_2 = __VERIFIER_nondet_uchar() [L264] input_4 = __VERIFIER_nondet_uchar() [L265] input_5 = __VERIFIER_nondet_uchar() [L266] EXPR input_5 & mask_SORT_1 VAL [mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L266] input_5 = input_5 & mask_SORT_1 [L267] input_6 = __VERIFIER_nondet_uchar() [L268] EXPR input_6 & mask_SORT_1 VAL [input_5=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L268] input_6 = input_6 & mask_SORT_1 [L269] input_7 = __VERIFIER_nondet_uchar() [L270] EXPR input_7 & mask_SORT_1 VAL [input_5=0, input_6=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L270] input_7 = input_7 & mask_SORT_1 [L271] input_8 = __VERIFIER_nondet_uchar() [L272] EXPR input_8 & mask_SORT_1 VAL [input_5=0, input_6=0, input_7=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L272] input_8 = input_8 & mask_SORT_1 [L273] input_9 = __VERIFIER_nondet_uchar() [L274] EXPR input_9 & mask_SORT_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L274] input_9 = input_9 & mask_SORT_1 [L275] input_10 = __VERIFIER_nondet_uchar() [L277] SORT_19 var_21_arg_0 = state_20; [L278] SORT_1 var_21 = var_21_arg_0 != 0; [L279] SORT_1 var_22_arg_0 = var_21; [L280] SORT_1 var_22 = ~var_22_arg_0; VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=-1, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L281] EXPR var_22 & mask_SORT_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L281] var_22 = var_22 & mask_SORT_1 [L282] SORT_1 var_67_arg_0 = var_22; [L283] SORT_1 var_67 = ~var_67_arg_0; [L284] SORT_1 var_45_arg_0 = input_6; [L285] SORT_1 var_45 = ~var_45_arg_0; VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_29=4, var_401=0, var_45=-1, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_67=-1] [L286] EXPR var_45 & mask_SORT_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_29=4, var_401=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_67=-1] [L286] var_45 = var_45 & mask_SORT_1 [L287] SORT_1 var_46_arg_0 = input_5; [L288] SORT_1 var_46_arg_1 = var_45; VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_29=4, var_401=0, var_45=0, var_46_arg_0=0, var_46_arg_1=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_67=-1] [L289] EXPR var_46_arg_0 & var_46_arg_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_29=4, var_401=0, var_45=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_67=-1] [L289] SORT_1 var_46 = var_46_arg_0 & var_46_arg_1; [L290] EXPR var_46 & mask_SORT_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_29=4, var_401=0, var_45=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_67=-1] [L290] var_46 = var_46 & mask_SORT_1 [L291] SORT_1 var_68_arg_0 = var_46; [L292] SORT_1 var_68 = ~var_68_arg_0; [L293] SORT_1 var_69_arg_0 = var_67; [L294] SORT_1 var_69_arg_1 = var_68; VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_69_arg_0=-1, var_69_arg_1=-1] [L295] EXPR var_69_arg_0 | var_69_arg_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L295] SORT_1 var_69 = var_69_arg_0 | var_69_arg_1; [L296] SORT_1 var_70_arg_0 = var_59; [L297] SORT_1 var_70 = ~var_70_arg_0; [L298] SORT_1 var_71_arg_0 = var_69; [L299] SORT_1 var_71_arg_1 = var_70; VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_71_arg_0=255, var_71_arg_1=-2] [L300] EXPR var_71_arg_0 | var_71_arg_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L300] SORT_1 var_71 = var_71_arg_0 | var_71_arg_1; [L301] EXPR var_71 & mask_SORT_1 VAL [input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L301] var_71 = var_71 & mask_SORT_1 [L302] SORT_1 constr_72_arg_0 = var_71; VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L303] CALL assume_abort_if_not(constr_72_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L303] RET assume_abort_if_not(constr_72_arg_0) VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0] [L304] SORT_19 var_24_arg_0 = state_23; [L305] SORT_1 var_24 = var_24_arg_0 != 0; [L306] SORT_1 var_25_arg_0 = var_24; [L307] SORT_1 var_25 = ~var_25_arg_0; [L308] SORT_1 var_73_arg_0 = var_25; [L309] SORT_1 var_73 = ~var_73_arg_0; [L310] SORT_1 var_74_arg_0 = input_5; [L311] SORT_1 var_74_arg_1 = input_6; VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_73=-256, var_74_arg_0=0, var_74_arg_1=0] [L312] EXPR var_74_arg_0 & var_74_arg_1 VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_73=-256] [L312] SORT_1 var_74 = var_74_arg_0 & var_74_arg_1; [L313] SORT_1 var_75_arg_0 = var_74; [L314] SORT_1 var_75 = ~var_75_arg_0; [L315] SORT_1 var_76_arg_0 = var_73; [L316] SORT_1 var_76_arg_1 = var_75; VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_76_arg_0=-256, var_76_arg_1=-1] [L317] EXPR var_76_arg_0 | var_76_arg_1 VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0] [L317] SORT_1 var_76 = var_76_arg_0 | var_76_arg_1; [L318] SORT_1 var_77_arg_0 = var_59; [L319] SORT_1 var_77 = ~var_77_arg_0; [L320] SORT_1 var_78_arg_0 = var_76; [L321] SORT_1 var_78_arg_1 = var_77; VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_78_arg_0=255, var_78_arg_1=-2] [L322] EXPR var_78_arg_0 | var_78_arg_1 VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0] [L322] SORT_1 var_78 = var_78_arg_0 | var_78_arg_1; [L323] EXPR var_78 & mask_SORT_1 VAL [constr_72_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0] [L323] var_78 = var_78 & mask_SORT_1 [L324] SORT_1 constr_79_arg_0 = var_78; VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0] [L325] CALL assume_abort_if_not(constr_79_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L325] RET assume_abort_if_not(constr_79_arg_0) VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0] [L326] SORT_19 var_30_arg_0 = state_28; [L327] SORT_19 var_30_arg_1 = var_29; [L328] SORT_1 var_30 = var_30_arg_0 == var_30_arg_1; [L329] SORT_1 var_80_arg_0 = var_30; [L330] SORT_1 var_80 = ~var_80_arg_0; [L331] SORT_1 var_39_arg_0 = input_8; [L332] SORT_1 var_39 = ~var_39_arg_0; VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=-1, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L333] EXPR var_39 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L333] var_39 = var_39 & mask_SORT_1 [L334] SORT_1 var_40_arg_0 = input_7; [L335] SORT_1 var_40_arg_1 = var_39; VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40_arg_0=0, var_40_arg_1=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L336] EXPR var_40_arg_0 & var_40_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L336] SORT_1 var_40 = var_40_arg_0 & var_40_arg_1; [L337] SORT_1 var_81_arg_0 = var_40; [L338] SORT_1 var_81 = ~var_81_arg_0; [L339] SORT_1 var_82_arg_0 = var_80; [L340] SORT_1 var_82_arg_1 = var_81; VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1, var_82_arg_0=-1, var_82_arg_1=-1] [L341] EXPR var_82_arg_0 | var_82_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L341] SORT_1 var_82 = var_82_arg_0 | var_82_arg_1; [L342] SORT_1 var_83_arg_0 = var_59; [L343] SORT_1 var_83 = ~var_83_arg_0; [L344] SORT_1 var_84_arg_0 = var_82; [L345] SORT_1 var_84_arg_1 = var_83; VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1, var_84_arg_0=255, var_84_arg_1=-2] [L346] EXPR var_84_arg_0 | var_84_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L346] SORT_1 var_84 = var_84_arg_0 | var_84_arg_1; [L347] EXPR var_84 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L347] var_84 = var_84 & mask_SORT_1 [L348] SORT_1 constr_85_arg_0 = var_84; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L349] CALL assume_abort_if_not(constr_85_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L349] RET assume_abort_if_not(constr_85_arg_0) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L350] SORT_1 var_86_arg_0 = input_7; [L351] SORT_1 var_86_arg_1 = input_8; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1, var_86_arg_0=0, var_86_arg_1=0] [L352] EXPR var_86_arg_0 & var_86_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_80=-1] [L352] SORT_1 var_86 = var_86_arg_0 & var_86_arg_1; [L353] SORT_1 var_87_arg_0 = var_86; [L354] SORT_1 var_87 = ~var_87_arg_0; [L355] SORT_1 var_88_arg_0 = var_80; [L356] SORT_1 var_88_arg_1 = var_87; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0, var_88_arg_0=-1, var_88_arg_1=-1] [L357] EXPR var_88_arg_0 | var_88_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L357] SORT_1 var_88 = var_88_arg_0 | var_88_arg_1; [L358] SORT_1 var_89_arg_0 = var_59; [L359] SORT_1 var_89 = ~var_89_arg_0; [L360] SORT_1 var_90_arg_0 = var_88; [L361] SORT_1 var_90_arg_1 = var_89; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0, var_90_arg_0=255, var_90_arg_1=-2] [L362] EXPR var_90_arg_0 | var_90_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L362] SORT_1 var_90 = var_90_arg_0 | var_90_arg_1; [L363] EXPR var_90 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L363] var_90 = var_90 & mask_SORT_1 [L364] SORT_1 constr_91_arg_0 = var_90; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L365] CALL assume_abort_if_not(constr_91_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L365] RET assume_abort_if_not(constr_91_arg_0) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L366] SORT_1 var_92_arg_0 = state_61; [L367] SORT_1 var_92_arg_1 = input_9; [L368] SORT_1 var_92 = var_92_arg_0 == var_92_arg_1; [L369] SORT_1 var_93_arg_0 = var_59; [L370] SORT_1 var_93 = ~var_93_arg_0; [L371] SORT_1 var_94_arg_0 = var_92; [L372] SORT_1 var_94_arg_1 = var_93; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0, var_94_arg_0=0, var_94_arg_1=-2] [L373] EXPR var_94_arg_0 | var_94_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L373] SORT_1 var_94 = var_94_arg_0 | var_94_arg_1; [L374] EXPR var_94 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L374] var_94 = var_94 & mask_SORT_1 [L375] SORT_1 constr_95_arg_0 = var_94; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L376] CALL assume_abort_if_not(constr_95_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L376] RET assume_abort_if_not(constr_95_arg_0) VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, state_61=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_74=0, var_86=0] [L378] SORT_1 var_63_arg_0 = state_61; [L379] SORT_1 var_63_arg_1 = var_60; [L380] SORT_1 var_63_arg_2 = var_59; [L381] SORT_1 var_63 = var_63_arg_0 ? var_63_arg_1 : var_63_arg_2; [L382] SORT_1 var_34_arg_0 = state_33; [L383] SORT_1 var_34 = ~var_34_arg_0; [L384] SORT_1 var_35_arg_0 = state_32; [L385] SORT_1 var_35_arg_1 = var_34; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_35_arg_0=0, var_35_arg_1=-1, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L386] EXPR var_35_arg_0 & var_35_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L386] SORT_1 var_35 = var_35_arg_0 & var_35_arg_1; [L387] SORT_19 var_37_arg_0 = state_36; [L388] SORT_1 var_37 = var_37_arg_0 != 0; [L389] SORT_1 var_38_arg_0 = var_35; [L390] SORT_1 var_38_arg_1 = var_37; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38_arg_0=0, var_38_arg_1=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L391] EXPR var_38_arg_0 & var_38_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L391] SORT_1 var_38 = var_38_arg_0 & var_38_arg_1; [L392] SORT_1 var_41_arg_0 = state_32; [L393] SORT_1 var_41 = ~var_41_arg_0; [L394] SORT_1 var_42_arg_0 = var_40; [L395] SORT_1 var_42_arg_1 = var_41; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_42_arg_0=0, var_42_arg_1=-1, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L396] EXPR var_42_arg_0 & var_42_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L396] SORT_1 var_42 = var_42_arg_0 & var_42_arg_1; [L397] SORT_1 var_43_arg_0 = var_42; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_43_arg_0=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L398] EXPR var_43_arg_0 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L398] var_43_arg_0 = var_43_arg_0 & mask_SORT_1 [L399] SORT_19 var_43 = var_43_arg_0; [L400] SORT_19 var_44_arg_0 = state_36; [L401] SORT_19 var_44_arg_1 = var_43; [L402] SORT_19 var_44 = var_44_arg_0 + var_44_arg_1; [L403] SORT_1 var_47_arg_0 = var_46; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_44=0, var_45=0, var_46=0, var_47_arg_0=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L404] EXPR var_47_arg_0 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_44=0, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L404] var_47_arg_0 = var_47_arg_0 & mask_SORT_1 [L405] SORT_19 var_47 = var_47_arg_0; [L406] SORT_19 var_48_arg_0 = var_44; [L407] SORT_19 var_48_arg_1 = var_47; [L408] SORT_19 var_48 = var_48_arg_0 - var_48_arg_1; [L409] SORT_1 var_50_arg_0 = input_9; [L410] SORT_19 var_50_arg_1 = var_49; [L411] SORT_19 var_50_arg_2 = var_48; [L412] SORT_19 var_50 = var_50_arg_0 ? var_50_arg_1 : var_50_arg_2; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L413] EXPR var_50 & mask_SORT_19 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_38=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=0, var_46=0, var_49=0, var_508=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L413] var_50 = var_50 & mask_SORT_19 [L414] SORT_19 var_51_arg_0 = var_50; [L415] SORT_1 var_51 = var_51_arg_0 != 0; [L416] SORT_1 var_52_arg_0 = var_51; [L417] SORT_1 var_52 = ~var_52_arg_0; [L418] SORT_1 var_53_arg_0 = var_38; [L419] SORT_1 var_53_arg_1 = var_52; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53_arg_0=0, var_53_arg_1=-1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L420] EXPR var_53_arg_0 & var_53_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L420] SORT_1 var_53 = var_53_arg_0 & var_53_arg_1; [L421] SORT_1 var_54_arg_0 = var_53; [L422] SORT_1 var_54 = ~var_54_arg_0; [L423] SORT_11* var_16_arg_0 = state_15; [L424] SORT_1 var_16_arg_1 = input_6; [L425] EXPR var_16_arg_0[(unsigned char) var_16_arg_1] [L425] SORT_11 var_16 = var_16_arg_0[(unsigned char) var_16_arg_1]; [L426] EXPR var_16 & mask_SORT_11 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_54=-1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L426] var_16 = var_16 & mask_SORT_11 [L427] SORT_3* var_17_arg_0 = state_13; [L428] SORT_11 var_17_arg_1 = var_16; [L429] EXPR var_17_arg_0[(unsigned char) var_17_arg_1] [L429] SORT_3 var_17 = var_17_arg_0[(unsigned char) var_17_arg_1]; [L430] EXPR var_17 & mask_SORT_3 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_54=-1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L430] var_17 = var_17 & mask_SORT_3 [L431] SORT_3 var_56_arg_0 = state_55; [L432] SORT_3 var_56_arg_1 = var_17; [L433] SORT_1 var_56 = var_56_arg_0 == var_56_arg_1; [L434] SORT_1 var_57_arg_0 = var_54; [L435] SORT_1 var_57_arg_1 = var_56; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_57_arg_0=-1, var_57_arg_1=1, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L436] EXPR var_57_arg_0 | var_57_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_63=1, var_74=0, var_86=0] [L436] SORT_1 var_57 = var_57_arg_0 | var_57_arg_1; [L437] SORT_1 var_64_arg_0 = var_57; [L438] SORT_1 var_64 = ~var_64_arg_0; [L439] SORT_1 var_65_arg_0 = var_63; [L440] SORT_1 var_65_arg_1 = var_64; VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_65_arg_0=1, var_65_arg_1=-1, var_74=0, var_86=0] [L441] EXPR var_65_arg_0 & var_65_arg_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L441] SORT_1 var_65 = var_65_arg_0 & var_65_arg_1; [L442] EXPR var_65 & mask_SORT_1 VAL [constr_72_arg_0=1, constr_79_arg_0=1, constr_85_arg_0=1, constr_91_arg_0=1, constr_95_arg_0=1, input_5=0, input_6=0, input_7=0, input_8=0, input_9=1, mask_SORT_11=3, mask_SORT_191=15, mask_SORT_193=31, mask_SORT_195=63, mask_SORT_197=127, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=255, state_13={6:0}, state_148=0, state_153=0, state_15={7:0}, state_20=0, state_23=0, state_249={27:0}, state_254=0, state_28=0, state_329=0, state_32=0, state_330=0, state_33=0, state_36=0, state_55=0, state_564=0, var_16=0, var_22=0, var_25=-1, var_29=4, var_30=0, var_39=0, var_401=0, var_40=0, var_41=-1, var_45=0, var_46=0, var_49=0, var_508=0, var_50=0, var_513=3, var_519=2, var_531=1, var_53=0, var_59=1, var_60=0, var_74=0, var_86=0] [L442] var_65 = var_65 & mask_SORT_1 [L443] SORT_1 bad_66_arg_0 = var_65; [L444] CALL __VERIFIER_assert(!(bad_66_arg_0)) [L21] COND TRUE !(cond) [L21] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 1149 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 780.9s, OverallIterations: 101, TraceHistogramMax: 10, PathProgramHistogramMax: 3, EmptinessCheckTime: 1.3s, AutomataDifference: 147.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 155177 SdHoareTripleChecker+Valid, 106.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 154973 mSDsluCounter, 779254 SdHoareTripleChecker+Invalid, 91.8s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 621030 mSDsCounter, 717 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 216398 IncrementalHoareTripleChecker+Invalid, 217115 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 717 mSolverCounterUnsat, 158224 mSDtfsCounter, 216398 mSolverCounterSat, 1.6s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 83461 GetRequests, 82336 SyntacticMatches, 11 SemanticMatches, 1114 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7402 ImplicationChecksByTransitivity, 14.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=124682occurred in iteration=100, InterpolantAutomatonStates: 767, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 33.5s AutomataMinimizationTime, 100 MinimizatonAttempts, 72041 StatesRemovedByMinimization, 57 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 15.6s SsaConstructionTime, 251.5s SatisfiabilityAnalysisTime, 170.1s InterpolantComputationTime, 120177 NumberOfCodeBlocks, 111712 NumberOfCodeBlocksAsserted, 179 NumberOfCheckSat, 155134 ConstructedInterpolants, 32 QuantifiedInterpolants, 420087 SizeOfPredicates, 164 NumberOfNonLiveVariables, 210707 ConjunctsInSsa, 1916 ConjunctsInUnsatCore, 221 InterpolantComputations, 74 PerfectInterpolantSequences, 70515/71825 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2024-12-02 06:30:05,830 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_402eabc9-3fd6-4754-8e27-2cc91ab33193/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request...