./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version a0165632 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/config/KojakReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/config/svcomp-Reach-32bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- This is Ultimate 0.2.5-dev-a016563 [2024-11-08 19:44:45,745 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-08 19:44:45,846 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/config/svcomp-Reach-32bit-Kojak_Default.epf [2024-11-08 19:44:45,851 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-08 19:44:45,855 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck.Interpolating solver [2024-11-08 19:44:45,885 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-08 19:44:45,886 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-08 19:44:45,886 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ALWAYS [2024-11-08 19:44:45,887 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-08 19:44:45,887 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-08 19:44:45,888 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-08 19:44:45,888 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-08 19:44:45,889 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-08 19:44:45,889 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-08 19:44:45,889 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-08 19:44:45,890 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-08 19:44:45,890 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-08 19:44:45,890 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-08 19:44:45,891 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-08 19:44:45,891 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-08 19:44:45,892 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-08 19:44:45,892 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-08 19:44:45,892 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-08 19:44:45,893 INFO L151 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2024-11-08 19:44:45,893 INFO L153 SettingsManager]: * Timeout in seconds=1000000 [2024-11-08 19:44:45,893 INFO L153 SettingsManager]: * Theory for external solver=ALL [2024-11-08 19:44:45,894 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-08 19:44:45,894 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2024-11-08 19:44:45,894 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-08 19:44:45,895 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-08 19:44:45,895 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-08 19:44:45,895 INFO L153 SettingsManager]: * Trace refinement strategy=PENGUIN [2024-11-08 19:44:45,900 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-08 19:44:45,900 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2024-11-08 19:44:46,217 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-08 19:44:46,249 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-08 19:44:46,252 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-08 19:44:46,254 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-08 19:44:46,254 INFO L274 PluginConnector]: CDTParser initialized [2024-11-08 19:44:46,256 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/../../sv-benchmarks/c/systemc/transmitter.15.cil.c Unable to find full path for "g++" [2024-11-08 19:44:48,251 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-08 19:44:48,513 INFO L384 CDTParser]: Found 1 translation units. [2024-11-08 19:44:48,514 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/sv-benchmarks/c/systemc/transmitter.15.cil.c [2024-11-08 19:44:48,532 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/data/1b5b01ffc/fd0994633d404f2db10b05161582fdbf/FLAG9bf3a94b6 [2024-11-08 19:44:48,550 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/data/1b5b01ffc/fd0994633d404f2db10b05161582fdbf [2024-11-08 19:44:48,553 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-08 19:44:48,554 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-08 19:44:48,555 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-08 19:44:48,556 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-08 19:44:48,561 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-08 19:44:48,562 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 07:44:48" (1/1) ... [2024-11-08 19:44:48,564 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@559d4676 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 07:44:48, skipping insertion in model container [2024-11-08 19:44:48,564 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 07:44:48" (1/1) ... [2024-11-08 19:44:48,623 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-08 19:44:48,809 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2024-11-08 19:44:49,034 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 19:44:49,048 INFO L200 MainTranslator]: Completed pre-run [2024-11-08 19:44:49,062 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2024-11-08 19:44:49,150 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 19:44:49,190 INFO L204 MainTranslator]: Completed translation [2024-11-08 19:44:49,191 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 07:44:49 WrapperNode [2024-11-08 19:44:49,191 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-08 19:44:49,192 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-08 19:44:49,192 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-08 19:44:49,192 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-08 19:44:49,197 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 07:44:49" (1/1) ... [2024-11-08 19:44:49,211 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 07:44:49" (1/1) ... [2024-11-08 19:44:49,263 INFO L138 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 38, calls inlined = 38, statements flattened = 901 [2024-11-08 19:44:49,263 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-08 19:44:49,264 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-08 19:44:49,264 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-08 19:44:49,264 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-08 19:44:49,274 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 07:44:49" (1/1) ... [2024-11-08 19:44:49,274 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 07:44:49" (1/1) ... [2024-11-08 19:44:49,278 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 07:44:49" (1/1) ... [2024-11-08 19:44:49,278 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 07:44:49" (1/1) ... [2024-11-08 19:44:49,291 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 07:44:49" (1/1) ... [2024-11-08 19:44:49,303 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 07:44:49" (1/1) ... [2024-11-08 19:44:49,306 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 07:44:49" (1/1) ... [2024-11-08 19:44:49,310 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 07:44:49" (1/1) ... [2024-11-08 19:44:49,315 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-08 19:44:49,316 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-08 19:44:49,316 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-08 19:44:49,316 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-08 19:44:49,317 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 07:44:49" (1/1) ... [2024-11-08 19:44:49,323 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2024-11-08 19:44:49,336 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/z3 [2024-11-08 19:44:49,350 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) [2024-11-08 19:44:49,352 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Waiting until timeout for monitored process [2024-11-08 19:44:49,381 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-08 19:44:49,381 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2024-11-08 19:44:49,382 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2024-11-08 19:44:49,382 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2024-11-08 19:44:49,382 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2024-11-08 19:44:49,382 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2024-11-08 19:44:49,382 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2024-11-08 19:44:49,383 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2024-11-08 19:44:49,383 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2024-11-08 19:44:49,383 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2024-11-08 19:44:49,383 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2024-11-08 19:44:49,383 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2024-11-08 19:44:49,383 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2024-11-08 19:44:49,384 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2024-11-08 19:44:49,384 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-08 19:44:49,384 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-08 19:44:49,516 INFO L238 CfgBuilder]: Building ICFG [2024-11-08 19:44:49,518 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-08 19:44:50,653 INFO L? ?]: Removed 103 outVars from TransFormulas that were not future-live. [2024-11-08 19:44:50,653 INFO L287 CfgBuilder]: Performing block encoding [2024-11-08 19:44:51,277 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-08 19:44:51,277 INFO L316 CfgBuilder]: Removed 17 assume(true) statements. [2024-11-08 19:44:51,278 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 07:44:51 BoogieIcfgContainer [2024-11-08 19:44:51,278 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-08 19:44:51,279 INFO L112 PluginConnector]: ------------------------CodeCheck---------------------------- [2024-11-08 19:44:51,279 INFO L270 PluginConnector]: Initializing CodeCheck... [2024-11-08 19:44:51,291 INFO L274 PluginConnector]: CodeCheck initialized [2024-11-08 19:44:51,291 INFO L184 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 07:44:51" (1/1) ... [2024-11-08 19:44:51,303 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 19:44:51,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:51,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312 states to 206 states and 312 transitions. [2024-11-08 19:44:51,378 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 312 transitions. [2024-11-08 19:44:51,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:51,383 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:51,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:51,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:52,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:52,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:52,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 247 states and 392 transitions. [2024-11-08 19:44:52,318 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 392 transitions. [2024-11-08 19:44:52,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:52,324 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:52,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:52,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:52,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:52,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:52,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 248 states and 392 transitions. [2024-11-08 19:44:52,632 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 392 transitions. [2024-11-08 19:44:52,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:52,638 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:52,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:52,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:52,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:52,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:52,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 249 states and 392 transitions. [2024-11-08 19:44:52,904 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 392 transitions. [2024-11-08 19:44:52,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:52,908 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:52,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:52,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:53,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:53,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:53,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 250 states and 392 transitions. [2024-11-08 19:44:53,134 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 392 transitions. [2024-11-08 19:44:53,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:53,136 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:53,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:53,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:53,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:53,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:53,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 251 states and 392 transitions. [2024-11-08 19:44:53,360 INFO L276 IsEmpty]: Start isEmpty. Operand 251 states and 392 transitions. [2024-11-08 19:44:53,362 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:53,365 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:53,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:53,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:53,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:53,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:53,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 252 states and 392 transitions. [2024-11-08 19:44:53,547 INFO L276 IsEmpty]: Start isEmpty. Operand 252 states and 392 transitions. [2024-11-08 19:44:53,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:53,551 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:53,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:53,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:53,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:53,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:53,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 253 states and 392 transitions. [2024-11-08 19:44:53,710 INFO L276 IsEmpty]: Start isEmpty. Operand 253 states and 392 transitions. [2024-11-08 19:44:53,711 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:53,714 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:53,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:53,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:53,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:53,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:53,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 254 states and 392 transitions. [2024-11-08 19:44:53,872 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 392 transitions. [2024-11-08 19:44:53,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:53,873 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:53,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:53,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:54,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:54,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:54,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 255 states and 392 transitions. [2024-11-08 19:44:54,023 INFO L276 IsEmpty]: Start isEmpty. Operand 255 states and 392 transitions. [2024-11-08 19:44:54,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:54,024 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:54,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:54,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:54,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:54,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:54,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 256 states and 392 transitions. [2024-11-08 19:44:54,167 INFO L276 IsEmpty]: Start isEmpty. Operand 256 states and 392 transitions. [2024-11-08 19:44:54,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:54,169 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:54,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:54,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:54,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:54,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:54,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 257 states and 392 transitions. [2024-11-08 19:44:54,310 INFO L276 IsEmpty]: Start isEmpty. Operand 257 states and 392 transitions. [2024-11-08 19:44:54,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:54,311 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:54,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:54,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:54,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:54,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:54,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 258 states and 392 transitions. [2024-11-08 19:44:54,444 INFO L276 IsEmpty]: Start isEmpty. Operand 258 states and 392 transitions. [2024-11-08 19:44:54,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:54,445 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:54,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:54,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:54,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:54,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:54,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 259 states and 392 transitions. [2024-11-08 19:44:54,586 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states and 392 transitions. [2024-11-08 19:44:54,587 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:54,587 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:54,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:54,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:54,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:54,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:54,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 260 states and 392 transitions. [2024-11-08 19:44:54,706 INFO L276 IsEmpty]: Start isEmpty. Operand 260 states and 392 transitions. [2024-11-08 19:44:54,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:54,707 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:54,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:54,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:54,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:55,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:55,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 296 states and 463 transitions. [2024-11-08 19:44:55,160 INFO L276 IsEmpty]: Start isEmpty. Operand 296 states and 463 transitions. [2024-11-08 19:44:55,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:55,161 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:55,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:55,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:55,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:55,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:55,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 297 states and 463 transitions. [2024-11-08 19:44:55,303 INFO L276 IsEmpty]: Start isEmpty. Operand 297 states and 463 transitions. [2024-11-08 19:44:55,304 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:55,304 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:55,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:55,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:55,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:55,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:55,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 298 states and 463 transitions. [2024-11-08 19:44:55,498 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 463 transitions. [2024-11-08 19:44:55,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:55,502 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:55,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:55,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:55,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:55,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:55,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 299 states and 463 transitions. [2024-11-08 19:44:55,658 INFO L276 IsEmpty]: Start isEmpty. Operand 299 states and 463 transitions. [2024-11-08 19:44:55,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:55,659 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:55,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:55,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:55,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:55,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:55,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 300 states and 463 transitions. [2024-11-08 19:44:55,790 INFO L276 IsEmpty]: Start isEmpty. Operand 300 states and 463 transitions. [2024-11-08 19:44:55,792 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:55,792 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:55,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:55,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:55,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:55,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:55,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 301 states and 463 transitions. [2024-11-08 19:44:55,941 INFO L276 IsEmpty]: Start isEmpty. Operand 301 states and 463 transitions. [2024-11-08 19:44:55,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:55,942 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:55,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:55,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:56,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:56,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:56,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 302 states and 463 transitions. [2024-11-08 19:44:56,064 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 463 transitions. [2024-11-08 19:44:56,065 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:56,065 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:56,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:56,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:56,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:56,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:56,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 303 states and 463 transitions. [2024-11-08 19:44:56,187 INFO L276 IsEmpty]: Start isEmpty. Operand 303 states and 463 transitions. [2024-11-08 19:44:56,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:56,188 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:56,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:56,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:56,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:56,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:56,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 304 states and 463 transitions. [2024-11-08 19:44:56,310 INFO L276 IsEmpty]: Start isEmpty. Operand 304 states and 463 transitions. [2024-11-08 19:44:56,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:56,311 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:56,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:56,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:56,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:56,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:56,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 305 states and 463 transitions. [2024-11-08 19:44:56,457 INFO L276 IsEmpty]: Start isEmpty. Operand 305 states and 463 transitions. [2024-11-08 19:44:56,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:56,458 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:56,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:56,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:56,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:56,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:56,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 306 states and 463 transitions. [2024-11-08 19:44:56,599 INFO L276 IsEmpty]: Start isEmpty. Operand 306 states and 463 transitions. [2024-11-08 19:44:56,600 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:56,600 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:56,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:56,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:56,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:56,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:56,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 307 states and 463 transitions. [2024-11-08 19:44:56,729 INFO L276 IsEmpty]: Start isEmpty. Operand 307 states and 463 transitions. [2024-11-08 19:44:56,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:56,730 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:56,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:56,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:56,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:57,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:57,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 339 states and 528 transitions. [2024-11-08 19:44:57,183 INFO L276 IsEmpty]: Start isEmpty. Operand 339 states and 528 transitions. [2024-11-08 19:44:57,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:57,184 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:57,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:57,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:57,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:57,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:57,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 340 states and 528 transitions. [2024-11-08 19:44:57,317 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 528 transitions. [2024-11-08 19:44:57,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:57,318 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:57,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:57,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:57,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:57,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:57,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 341 states and 528 transitions. [2024-11-08 19:44:57,449 INFO L276 IsEmpty]: Start isEmpty. Operand 341 states and 528 transitions. [2024-11-08 19:44:57,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:57,450 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:57,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:57,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:57,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:57,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:57,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 342 states and 528 transitions. [2024-11-08 19:44:57,629 INFO L276 IsEmpty]: Start isEmpty. Operand 342 states and 528 transitions. [2024-11-08 19:44:57,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:57,631 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:57,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:57,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:57,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:57,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:57,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 343 states and 528 transitions. [2024-11-08 19:44:57,803 INFO L276 IsEmpty]: Start isEmpty. Operand 343 states and 528 transitions. [2024-11-08 19:44:57,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:57,804 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:57,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:57,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:57,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:57,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:57,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 344 states and 528 transitions. [2024-11-08 19:44:57,933 INFO L276 IsEmpty]: Start isEmpty. Operand 344 states and 528 transitions. [2024-11-08 19:44:57,934 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:57,934 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:57,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:57,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:58,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:58,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:58,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 345 states and 528 transitions. [2024-11-08 19:44:58,065 INFO L276 IsEmpty]: Start isEmpty. Operand 345 states and 528 transitions. [2024-11-08 19:44:58,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:58,068 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:58,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:58,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:58,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:58,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:58,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 346 states and 528 transitions. [2024-11-08 19:44:58,210 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 528 transitions. [2024-11-08 19:44:58,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:58,211 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:58,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:58,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:58,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:58,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:58,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 347 states and 528 transitions. [2024-11-08 19:44:58,337 INFO L276 IsEmpty]: Start isEmpty. Operand 347 states and 528 transitions. [2024-11-08 19:44:58,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:58,338 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:58,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:58,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:58,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:58,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:58,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 348 states and 528 transitions. [2024-11-08 19:44:58,462 INFO L276 IsEmpty]: Start isEmpty. Operand 348 states and 528 transitions. [2024-11-08 19:44:58,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:58,463 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:58,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:58,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:58,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:58,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:58,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 349 states and 528 transitions. [2024-11-08 19:44:58,588 INFO L276 IsEmpty]: Start isEmpty. Operand 349 states and 528 transitions. [2024-11-08 19:44:58,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:58,590 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:58,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:58,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:58,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:44:59,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:44:59,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 375 states and 581 transitions. [2024-11-08 19:44:59,527 INFO L276 IsEmpty]: Start isEmpty. Operand 375 states and 581 transitions. [2024-11-08 19:44:59,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:44:59,528 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:44:59,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:44:59,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:44:59,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:00,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:00,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 376 states and 581 transitions. [2024-11-08 19:45:00,144 INFO L276 IsEmpty]: Start isEmpty. Operand 376 states and 581 transitions. [2024-11-08 19:45:00,145 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:00,145 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:00,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:00,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:00,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:00,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:00,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 377 states and 581 transitions. [2024-11-08 19:45:00,714 INFO L276 IsEmpty]: Start isEmpty. Operand 377 states and 581 transitions. [2024-11-08 19:45:00,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:00,715 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:00,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:00,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:00,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:01,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:01,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 378 states and 581 transitions. [2024-11-08 19:45:01,315 INFO L276 IsEmpty]: Start isEmpty. Operand 378 states and 581 transitions. [2024-11-08 19:45:01,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:01,316 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:01,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:01,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:01,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:01,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:01,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 379 states and 581 transitions. [2024-11-08 19:45:01,918 INFO L276 IsEmpty]: Start isEmpty. Operand 379 states and 581 transitions. [2024-11-08 19:45:01,920 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:01,920 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:01,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:01,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:02,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:02,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:02,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 380 states and 581 transitions. [2024-11-08 19:45:02,542 INFO L276 IsEmpty]: Start isEmpty. Operand 380 states and 581 transitions. [2024-11-08 19:45:02,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:02,543 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:02,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:02,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:02,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:03,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:03,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 381 states and 581 transitions. [2024-11-08 19:45:03,222 INFO L276 IsEmpty]: Start isEmpty. Operand 381 states and 581 transitions. [2024-11-08 19:45:03,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:03,224 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:03,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:03,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:03,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:03,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:03,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 382 states and 581 transitions. [2024-11-08 19:45:03,847 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 581 transitions. [2024-11-08 19:45:03,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:03,848 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:03,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:03,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:03,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:04,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:04,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 383 states and 581 transitions. [2024-11-08 19:45:04,435 INFO L276 IsEmpty]: Start isEmpty. Operand 383 states and 581 transitions. [2024-11-08 19:45:04,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:04,436 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:04,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:04,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:04,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:04,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:04,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 403 states and 622 transitions. [2024-11-08 19:45:04,940 INFO L276 IsEmpty]: Start isEmpty. Operand 403 states and 622 transitions. [2024-11-08 19:45:04,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:04,943 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:04,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:04,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:05,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:05,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:05,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 404 states and 622 transitions. [2024-11-08 19:45:05,082 INFO L276 IsEmpty]: Start isEmpty. Operand 404 states and 622 transitions. [2024-11-08 19:45:05,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:05,083 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:05,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:05,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:05,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:05,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:05,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 405 states and 622 transitions. [2024-11-08 19:45:05,220 INFO L276 IsEmpty]: Start isEmpty. Operand 405 states and 622 transitions. [2024-11-08 19:45:05,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:05,221 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:05,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:05,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:05,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:05,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:05,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 406 states and 622 transitions. [2024-11-08 19:45:05,360 INFO L276 IsEmpty]: Start isEmpty. Operand 406 states and 622 transitions. [2024-11-08 19:45:05,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:05,361 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:05,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:05,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:05,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:05,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:05,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 407 states and 622 transitions. [2024-11-08 19:45:05,505 INFO L276 IsEmpty]: Start isEmpty. Operand 407 states and 622 transitions. [2024-11-08 19:45:05,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:05,506 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:05,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:05,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:05,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:05,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:05,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 408 states and 622 transitions. [2024-11-08 19:45:05,659 INFO L276 IsEmpty]: Start isEmpty. Operand 408 states and 622 transitions. [2024-11-08 19:45:05,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:05,660 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:05,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:05,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:05,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:05,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:05,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 409 states and 622 transitions. [2024-11-08 19:45:05,791 INFO L276 IsEmpty]: Start isEmpty. Operand 409 states and 622 transitions. [2024-11-08 19:45:05,792 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:05,792 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:05,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:05,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:05,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:06,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:06,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 423 states and 651 transitions. [2024-11-08 19:45:06,808 INFO L276 IsEmpty]: Start isEmpty. Operand 423 states and 651 transitions. [2024-11-08 19:45:06,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:06,809 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:06,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:06,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:06,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:07,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:07,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 424 states and 651 transitions. [2024-11-08 19:45:07,341 INFO L276 IsEmpty]: Start isEmpty. Operand 424 states and 651 transitions. [2024-11-08 19:45:07,342 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:07,342 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:07,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:07,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:07,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:07,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:07,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 425 states and 651 transitions. [2024-11-08 19:45:07,883 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 651 transitions. [2024-11-08 19:45:07,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:07,884 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:07,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:07,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:07,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:08,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:08,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 426 states and 651 transitions. [2024-11-08 19:45:08,433 INFO L276 IsEmpty]: Start isEmpty. Operand 426 states and 651 transitions. [2024-11-08 19:45:08,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:08,435 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:08,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:08,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:08,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:08,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:08,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 427 states and 651 transitions. [2024-11-08 19:45:08,961 INFO L276 IsEmpty]: Start isEmpty. Operand 427 states and 651 transitions. [2024-11-08 19:45:08,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:08,962 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:08,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:08,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:09,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:09,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:09,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 717 states to 435 states and 668 transitions. [2024-11-08 19:45:09,492 INFO L276 IsEmpty]: Start isEmpty. Operand 435 states and 668 transitions. [2024-11-08 19:45:09,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:09,493 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:09,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:09,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:09,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:09,620 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:09,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 717 states to 436 states and 668 transitions. [2024-11-08 19:45:09,622 INFO L276 IsEmpty]: Start isEmpty. Operand 436 states and 668 transitions. [2024-11-08 19:45:09,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:09,623 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:09,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:09,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:09,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:09,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:09,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 717 states to 437 states and 668 transitions. [2024-11-08 19:45:09,753 INFO L276 IsEmpty]: Start isEmpty. Operand 437 states and 668 transitions. [2024-11-08 19:45:09,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:09,754 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:09,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:09,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:09,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:10,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:10,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 735 states to 442 states and 679 transitions. [2024-11-08 19:45:10,296 INFO L276 IsEmpty]: Start isEmpty. Operand 442 states and 679 transitions. [2024-11-08 19:45:10,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:10,297 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:10,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:10,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:10,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:10,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:10,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 735 states to 443 states and 679 transitions. [2024-11-08 19:45:10,417 INFO L276 IsEmpty]: Start isEmpty. Operand 443 states and 679 transitions. [2024-11-08 19:45:10,418 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:10,418 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:10,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:10,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:10,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:13,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:13,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 852 states to 489 states and 770 transitions. [2024-11-08 19:45:13,473 INFO L276 IsEmpty]: Start isEmpty. Operand 489 states and 770 transitions. [2024-11-08 19:45:13,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:13,475 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:13,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:13,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:13,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:14,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:14,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 868 states to 491 states and 775 transitions. [2024-11-08 19:45:14,948 INFO L276 IsEmpty]: Start isEmpty. Operand 491 states and 775 transitions. [2024-11-08 19:45:14,949 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:14,949 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:14,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:14,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:15,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:17,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:17,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 902 states to 502 states and 798 transitions. [2024-11-08 19:45:17,421 INFO L276 IsEmpty]: Start isEmpty. Operand 502 states and 798 transitions. [2024-11-08 19:45:17,422 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:17,422 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:17,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:17,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:17,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:22,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:22,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 948 states to 519 states and 833 transitions. [2024-11-08 19:45:22,797 INFO L276 IsEmpty]: Start isEmpty. Operand 519 states and 833 transitions. [2024-11-08 19:45:22,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:22,799 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:22,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:22,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:23,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:28,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:28,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1006 states to 542 states and 880 transitions. [2024-11-08 19:45:28,439 INFO L276 IsEmpty]: Start isEmpty. Operand 542 states and 880 transitions. [2024-11-08 19:45:28,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:28,441 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:28,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:28,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:28,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:35,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:35,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1076 states to 571 states and 939 transitions. [2024-11-08 19:45:35,914 INFO L276 IsEmpty]: Start isEmpty. Operand 571 states and 939 transitions. [2024-11-08 19:45:35,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-08 19:45:35,915 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:35,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:35,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:36,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:46,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:46,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1164 states to 609 states and 1016 transitions. [2024-11-08 19:45:46,140 INFO L276 IsEmpty]: Start isEmpty. Operand 609 states and 1016 transitions. [2024-11-08 19:45:46,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-08 19:45:46,141 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:46,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:46,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:46,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:46,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:46,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1165 states to 610 states and 1017 transitions. [2024-11-08 19:45:46,449 INFO L276 IsEmpty]: Start isEmpty. Operand 610 states and 1017 transitions. [2024-11-08 19:45:46,451 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-08 19:45:46,451 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:46,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:46,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:46,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:46,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:46,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1166 states to 611 states and 1018 transitions. [2024-11-08 19:45:46,797 INFO L276 IsEmpty]: Start isEmpty. Operand 611 states and 1018 transitions. [2024-11-08 19:45:46,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-08 19:45:46,798 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:46,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:46,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:46,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:47,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:47,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1167 states to 612 states and 1019 transitions. [2024-11-08 19:45:47,488 INFO L276 IsEmpty]: Start isEmpty. Operand 612 states and 1019 transitions. [2024-11-08 19:45:47,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-08 19:45:47,489 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:47,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:47,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:47,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:47,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:47,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1168 states to 613 states and 1020 transitions. [2024-11-08 19:45:47,837 INFO L276 IsEmpty]: Start isEmpty. Operand 613 states and 1020 transitions. [2024-11-08 19:45:47,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-08 19:45:47,838 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:47,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:47,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:47,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:48,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:48,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1169 states to 614 states and 1021 transitions. [2024-11-08 19:45:48,689 INFO L276 IsEmpty]: Start isEmpty. Operand 614 states and 1021 transitions. [2024-11-08 19:45:48,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-08 19:45:48,690 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:48,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:48,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:48,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:49,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:49,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 615 states and 1022 transitions. [2024-11-08 19:45:49,107 INFO L276 IsEmpty]: Start isEmpty. Operand 615 states and 1022 transitions. [2024-11-08 19:45:49,108 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-08 19:45:49,108 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:49,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:49,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:49,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:49,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:49,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1171 states to 616 states and 1023 transitions. [2024-11-08 19:45:49,593 INFO L276 IsEmpty]: Start isEmpty. Operand 616 states and 1023 transitions. [2024-11-08 19:45:49,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-08 19:45:49,594 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:49,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:49,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:49,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:50,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:50,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1172 states to 617 states and 1024 transitions. [2024-11-08 19:45:50,126 INFO L276 IsEmpty]: Start isEmpty. Operand 617 states and 1024 transitions. [2024-11-08 19:45:50,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-08 19:45:50,127 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:50,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:50,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:50,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:50,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:50,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1173 states to 618 states and 1025 transitions. [2024-11-08 19:45:50,602 INFO L276 IsEmpty]: Start isEmpty. Operand 618 states and 1025 transitions. [2024-11-08 19:45:50,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-08 19:45:50,603 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:50,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:50,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:50,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:53,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:53,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1174 states to 619 states and 1026 transitions. [2024-11-08 19:45:53,170 INFO L276 IsEmpty]: Start isEmpty. Operand 619 states and 1026 transitions. [2024-11-08 19:45:53,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-08 19:45:53,171 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:53,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:53,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:53,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:53,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:53,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 620 states and 1027 transitions. [2024-11-08 19:45:53,620 INFO L276 IsEmpty]: Start isEmpty. Operand 620 states and 1027 transitions. [2024-11-08 19:45:53,621 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-08 19:45:53,621 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:53,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:53,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:53,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:54,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:54,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1176 states to 621 states and 1028 transitions. [2024-11-08 19:45:54,066 INFO L276 IsEmpty]: Start isEmpty. Operand 621 states and 1028 transitions. [2024-11-08 19:45:54,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-08 19:45:54,067 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:54,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:54,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 19:45:54,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 19:45:54,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-08 19:45:54,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1106 states to 582 states and 960 transitions. [2024-11-08 19:45:54,209 INFO L276 IsEmpty]: Start isEmpty. Operand 582 states and 960 transitions. [2024-11-08 19:45:54,210 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-08 19:45:54,210 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-08 19:45:54,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 19:45:54,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 19:45:54,248 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 19:45:54,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 19:45:54,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 19:45:54,516 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 19:45:54,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 19:45:54,753 WARN L473 CodeCheckObserver]: This program is UNSAFE, Check terminated with 84 iterations. [2024-11-08 19:45:54,963 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 08.11 07:45:54 ImpRootNode [2024-11-08 19:45:54,965 INFO L131 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2024-11-08 19:45:54,966 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-08 19:45:54,966 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-08 19:45:54,967 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-08 19:45:54,967 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 07:44:51" (3/4) ... [2024-11-08 19:45:54,968 INFO L136 WitnessPrinter]: Generating witness for reachability counterexample [2024-11-08 19:45:55,151 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/witness.graphml [2024-11-08 19:45:55,152 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-08 19:45:55,152 INFO L158 Benchmark]: Toolchain (without parser) took 66598.27ms. Allocated memory was 148.9MB in the beginning and 597.7MB in the end (delta: 448.8MB). Free memory was 116.5MB in the beginning and 349.6MB in the end (delta: -233.0MB). Peak memory consumption was 215.7MB. Max. memory is 16.1GB. [2024-11-08 19:45:55,152 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 115.3MB. Free memory is still 87.4MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-08 19:45:55,153 INFO L158 Benchmark]: CACSL2BoogieTranslator took 635.88ms. Allocated memory is still 148.9MB. Free memory was 116.5MB in the beginning and 109.4MB in the end (delta: 7.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-08 19:45:55,153 INFO L158 Benchmark]: Boogie Procedure Inliner took 71.75ms. Allocated memory is still 148.9MB. Free memory was 109.4MB in the beginning and 105.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-08 19:45:55,153 INFO L158 Benchmark]: Boogie Preprocessor took 51.30ms. Allocated memory is still 148.9MB. Free memory was 105.2MB in the beginning and 101.0MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-08 19:45:55,153 INFO L158 Benchmark]: RCFGBuilder took 1962.05ms. Allocated memory was 148.9MB in the beginning and 180.4MB in the end (delta: 31.5MB). Free memory was 101.0MB in the beginning and 109.2MB in the end (delta: -8.1MB). Peak memory consumption was 76.7MB. Max. memory is 16.1GB. [2024-11-08 19:45:55,154 INFO L158 Benchmark]: CodeCheck took 63686.69ms. Allocated memory was 180.4MB in the beginning and 597.7MB in the end (delta: 417.3MB). Free memory was 109.2MB in the beginning and 377.9MB in the end (delta: -268.7MB). Peak memory consumption was 148.6MB. Max. memory is 16.1GB. [2024-11-08 19:45:55,154 INFO L158 Benchmark]: Witness Printer took 185.60ms. Allocated memory is still 597.7MB. Free memory was 377.9MB in the beginning and 349.6MB in the end (delta: 28.3MB). Peak memory consumption was 27.3MB. Max. memory is 16.1GB. [2024-11-08 19:45:55,156 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 7 procedures, 206 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 63.4s, OverallIterations: 84, TraceHistogramMax: 0, PathProgramHistogramMax: 0, EmptinessCheckTime: 0.0s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 55582 SdHoareTripleChecker+Valid, 65.8s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 45174 mSDsluCounter, 89407 SdHoareTripleChecker+Invalid, 54.8s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 72018 mSDsCounter, 4223 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 31667 IncrementalHoareTripleChecker+Invalid, 35890 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 4223 mSolverCounterUnsat, 17389 mSDtfsCounter, 31667 mSolverCounterSat, 2.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 53486 GetRequests, 52229 SyntacticMatches, 855 SemanticMatches, 402 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 120112 ImplicationChecksByTransitivity, 48.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, InterpolantAutomatonStates: 0, traceCheckStatistics: 0.6s SsaConstructionTime, 0.9s SatisfiabilityAnalysisTime, 9.3s InterpolantComputationTime, 5643 NumberOfCodeBlocks, 5643 NumberOfCodeBlocksAsserted, 84 NumberOfCheckSat, 5491 ConstructedInterpolants, 0 QuantifiedInterpolants, 14565 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 83 InterpolantComputations, 83 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int t8_pc = 0; [L34] int t9_pc = 0; [L35] int t10_pc = 0; [L36] int t11_pc = 0; [L37] int t12_pc = 0; [L38] int t13_pc = 0; [L39] int m_st ; [L40] int t1_st ; [L41] int t2_st ; [L42] int t3_st ; [L43] int t4_st ; [L44] int t5_st ; [L45] int t6_st ; [L46] int t7_st ; [L47] int t8_st ; [L48] int t9_st ; [L49] int t10_st ; [L50] int t11_st ; [L51] int t12_st ; [L52] int t13_st ; [L53] int m_i ; [L54] int t1_i ; [L55] int t2_i ; [L56] int t3_i ; [L57] int t4_i ; [L58] int t5_i ; [L59] int t6_i ; [L60] int t7_i ; [L61] int t8_i ; [L62] int t9_i ; [L63] int t10_i ; [L64] int t11_i ; [L65] int t12_i ; [L66] int t13_i ; [L67] int M_E = 2; [L68] int T1_E = 2; [L69] int T2_E = 2; [L70] int T3_E = 2; [L71] int T4_E = 2; [L72] int T5_E = 2; [L73] int T6_E = 2; [L74] int T7_E = 2; [L75] int T8_E = 2; [L76] int T9_E = 2; [L77] int T10_E = 2; [L78] int T11_E = 2; [L79] int T12_E = 2; [L80] int T13_E = 2; [L81] int E_1 = 2; [L82] int E_2 = 2; [L83] int E_3 = 2; [L84] int E_4 = 2; [L85] int E_5 = 2; [L86] int E_6 = 2; [L87] int E_7 = 2; [L88] int E_8 = 2; [L89] int E_9 = 2; [L90] int E_10 = 2; [L91] int E_11 = 2; [L92] int E_12 = 2; [L93] int E_13 = 2; [L1937] int __retres1 ; [L1941] CALL init_model() [L1840] m_i = 1 [L1841] t1_i = 1 [L1842] t2_i = 1 [L1843] t3_i = 1 [L1844] t4_i = 1 [L1845] t5_i = 1 [L1846] t6_i = 1 [L1847] t7_i = 1 [L1848] t8_i = 1 [L1849] t9_i = 1 [L1850] t10_i = 1 [L1851] t11_i = 1 [L1852] t12_i = 1 [L1853] t13_i = 1 [L1941] RET init_model() [L1942] CALL start_simulation() [L1878] int kernel_st ; [L1879] int tmp ; [L1880] int tmp___0 ; [L1884] kernel_st = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1885] FCALL update_channels() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1886] CALL init_threads() [L881] COND TRUE m_i == 1 [L882] m_st = 0 [L886] COND TRUE t1_i == 1 [L887] t1_st = 0 [L891] COND TRUE t2_i == 1 [L892] t2_st = 0 [L896] COND TRUE t3_i == 1 [L897] t3_st = 0 [L901] COND TRUE t4_i == 1 [L902] t4_st = 0 [L906] COND TRUE t5_i == 1 [L907] t5_st = 0 [L911] COND TRUE t6_i == 1 [L912] t6_st = 0 [L916] COND TRUE t7_i == 1 [L917] t7_st = 0 [L921] COND TRUE t8_i == 1 [L922] t8_st = 0 [L926] COND TRUE t9_i == 1 [L927] t9_st = 0 [L931] COND TRUE t10_i == 1 [L932] t10_st = 0 [L936] COND TRUE t11_i == 1 [L937] t11_st = 0 [L941] COND TRUE t12_i == 1 [L942] t12_st = 0 [L946] COND TRUE t13_i == 1 [L947] t13_st = 0 [L1886] RET init_threads() [L1887] CALL fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1258] COND FALSE !(M_E == 0) [L1263] COND FALSE !(T1_E == 0) [L1268] COND FALSE !(T2_E == 0) [L1273] COND FALSE !(T3_E == 0) [L1278] COND FALSE !(T4_E == 0) [L1283] COND FALSE !(T5_E == 0) [L1288] COND FALSE !(T6_E == 0) [L1293] COND FALSE !(T7_E == 0) [L1298] COND FALSE !(T8_E == 0) [L1303] COND FALSE !(T9_E == 0) [L1308] COND FALSE !(T10_E == 0) [L1313] COND FALSE !(T11_E == 0) [L1318] COND FALSE !(T12_E == 0) [L1323] COND FALSE !(T13_E == 0) [L1328] COND FALSE !(E_1 == 0) [L1333] COND FALSE !(E_2 == 0) [L1338] COND FALSE !(E_3 == 0) [L1343] COND FALSE !(E_4 == 0) [L1348] COND FALSE !(E_5 == 0) [L1353] COND FALSE !(E_6 == 0) [L1358] COND FALSE !(E_7 == 0) [L1363] COND FALSE !(E_8 == 0) [L1368] COND FALSE !(E_9 == 0) [L1373] COND FALSE !(E_10 == 0) [L1378] COND FALSE !(E_11 == 0) [L1383] COND FALSE !(E_12 == 0) [L1388] COND FALSE !(E_13 == 0) [L1887] RET fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1888] CALL activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1541] int tmp ; [L1542] int tmp___0 ; [L1543] int tmp___1 ; [L1544] int tmp___2 ; [L1545] int tmp___3 ; [L1546] int tmp___4 ; [L1547] int tmp___5 ; [L1548] int tmp___6 ; [L1549] int tmp___7 ; [L1550] int tmp___8 ; [L1551] int tmp___9 ; [L1552] int tmp___10 ; [L1553] int tmp___11 ; [L1554] int tmp___12 ; [L1558] CALL, EXPR is_master_triggered() [L604] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L607] COND FALSE !(m_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L617] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L619] return (__retres1); [L1558] RET, EXPR is_master_triggered() [L1558] tmp = is_master_triggered() [L1560] COND FALSE !(\read(tmp)) [L1566] CALL, EXPR is_transmit1_triggered() [L623] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L626] COND FALSE !(t1_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L636] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L638] return (__retres1); [L1566] RET, EXPR is_transmit1_triggered() [L1566] tmp___0 = is_transmit1_triggered() [L1568] COND FALSE !(\read(tmp___0)) [L1574] CALL, EXPR is_transmit2_triggered() [L642] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L645] COND FALSE !(t2_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L655] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L657] return (__retres1); [L1574] RET, EXPR is_transmit2_triggered() [L1574] tmp___1 = is_transmit2_triggered() [L1576] COND FALSE !(\read(tmp___1)) [L1582] CALL, EXPR is_transmit3_triggered() [L661] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L664] COND FALSE !(t3_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L674] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L676] return (__retres1); [L1582] RET, EXPR is_transmit3_triggered() [L1582] tmp___2 = is_transmit3_triggered() [L1584] COND FALSE !(\read(tmp___2)) [L1590] CALL, EXPR is_transmit4_triggered() [L680] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L683] COND FALSE !(t4_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L693] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L695] return (__retres1); [L1590] RET, EXPR is_transmit4_triggered() [L1590] tmp___3 = is_transmit4_triggered() [L1592] COND FALSE !(\read(tmp___3)) [L1598] CALL, EXPR is_transmit5_triggered() [L699] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L702] COND FALSE !(t5_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L712] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L714] return (__retres1); [L1598] RET, EXPR is_transmit5_triggered() [L1598] tmp___4 = is_transmit5_triggered() [L1600] COND FALSE !(\read(tmp___4)) [L1606] CALL, EXPR is_transmit6_triggered() [L718] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L721] COND FALSE !(t6_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L731] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L733] return (__retres1); [L1606] RET, EXPR is_transmit6_triggered() [L1606] tmp___5 = is_transmit6_triggered() [L1608] COND FALSE !(\read(tmp___5)) [L1614] CALL, EXPR is_transmit7_triggered() [L737] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L740] COND FALSE !(t7_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L750] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L752] return (__retres1); [L1614] RET, EXPR is_transmit7_triggered() [L1614] tmp___6 = is_transmit7_triggered() [L1616] COND FALSE !(\read(tmp___6)) [L1622] CALL, EXPR is_transmit8_triggered() [L756] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L759] COND FALSE !(t8_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L769] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L771] return (__retres1); [L1622] RET, EXPR is_transmit8_triggered() [L1622] tmp___7 = is_transmit8_triggered() [L1624] COND FALSE !(\read(tmp___7)) [L1630] CALL, EXPR is_transmit9_triggered() [L775] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L778] COND FALSE !(t9_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L788] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L790] return (__retres1); [L1630] RET, EXPR is_transmit9_triggered() [L1630] tmp___8 = is_transmit9_triggered() [L1632] COND FALSE !(\read(tmp___8)) [L1638] CALL, EXPR is_transmit10_triggered() [L794] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L797] COND FALSE !(t10_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L807] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L809] return (__retres1); [L1638] RET, EXPR is_transmit10_triggered() [L1638] tmp___9 = is_transmit10_triggered() [L1640] COND FALSE !(\read(tmp___9)) [L1646] CALL, EXPR is_transmit11_triggered() [L813] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L816] COND FALSE !(t11_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L826] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L828] return (__retres1); [L1646] RET, EXPR is_transmit11_triggered() [L1646] tmp___10 = is_transmit11_triggered() [L1648] COND FALSE !(\read(tmp___10)) [L1654] CALL, EXPR is_transmit12_triggered() [L832] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L835] COND FALSE !(t12_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L845] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L847] return (__retres1); [L1654] RET, EXPR is_transmit12_triggered() [L1654] tmp___11 = is_transmit12_triggered() [L1656] COND FALSE !(\read(tmp___11)) [L1662] CALL, EXPR is_transmit13_triggered() [L851] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L854] COND FALSE !(t13_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L864] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L866] return (__retres1); [L1662] RET, EXPR is_transmit13_triggered() [L1662] tmp___12 = is_transmit13_triggered() [L1664] COND FALSE !(\read(tmp___12)) [L1888] RET activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1889] CALL reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1401] COND FALSE !(M_E == 1) [L1406] COND FALSE !(T1_E == 1) [L1411] COND FALSE !(T2_E == 1) [L1416] COND FALSE !(T3_E == 1) [L1421] COND FALSE !(T4_E == 1) [L1426] COND FALSE !(T5_E == 1) [L1431] COND FALSE !(T6_E == 1) [L1436] COND FALSE !(T7_E == 1) [L1441] COND FALSE !(T8_E == 1) [L1446] COND FALSE !(T9_E == 1) [L1451] COND FALSE !(T10_E == 1) [L1456] COND FALSE !(T11_E == 1) [L1461] COND FALSE !(T12_E == 1) [L1466] COND FALSE !(T13_E == 1) [L1471] COND FALSE !(E_1 == 1) [L1476] COND FALSE !(E_2 == 1) [L1481] COND FALSE !(E_3 == 1) [L1486] COND FALSE !(E_4 == 1) [L1491] COND FALSE !(E_5 == 1) [L1496] COND FALSE !(E_6 == 1) [L1501] COND FALSE !(E_7 == 1) [L1506] COND FALSE !(E_8 == 1) [L1511] COND FALSE !(E_9 == 1) [L1516] COND FALSE !(E_10 == 1) [L1521] COND FALSE !(E_11 == 1) [L1526] COND FALSE !(E_12 == 1) [L1531] COND FALSE !(E_13 == 1) [L1889] RET reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1892] COND TRUE 1 [L1895] kernel_st = 1 [L1896] CALL eval() [L1037] int tmp ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1041] COND TRUE 1 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1044] CALL, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L956] int __retres1 ; [L959] COND TRUE m_st == 0 [L960] __retres1 = 1 [L1032] return (__retres1); [L1044] RET, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1044] tmp = exists_runnable_thread() [L1046] COND TRUE \read(tmp) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1051] COND TRUE m_st == 0 [L1052] int tmp_ndt_1; [L1053] tmp_ndt_1 = __VERIFIER_nondet_int() [L1054] COND FALSE !(\read(tmp_ndt_1)) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1065] COND TRUE t1_st == 0 [L1066] int tmp_ndt_2; [L1067] tmp_ndt_2 = __VERIFIER_nondet_int() [L1068] COND FALSE !(\read(tmp_ndt_2)) [L1074] CALL error() [L21] reach_error() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 115.3MB. Free memory is still 87.4MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 635.88ms. Allocated memory is still 148.9MB. Free memory was 116.5MB in the beginning and 109.4MB in the end (delta: 7.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 71.75ms. Allocated memory is still 148.9MB. Free memory was 109.4MB in the beginning and 105.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 51.30ms. Allocated memory is still 148.9MB. Free memory was 105.2MB in the beginning and 101.0MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1962.05ms. Allocated memory was 148.9MB in the beginning and 180.4MB in the end (delta: 31.5MB). Free memory was 101.0MB in the beginning and 109.2MB in the end (delta: -8.1MB). Peak memory consumption was 76.7MB. Max. memory is 16.1GB. * CodeCheck took 63686.69ms. Allocated memory was 180.4MB in the beginning and 597.7MB in the end (delta: 417.3MB). Free memory was 109.2MB in the beginning and 377.9MB in the end (delta: -268.7MB). Peak memory consumption was 148.6MB. Max. memory is 16.1GB. * Witness Printer took 185.60ms. Allocated memory is still 597.7MB. Free memory was 377.9MB in the beginning and 349.6MB in the end (delta: 28.3MB). Peak memory consumption was 27.3MB. Max. memory is 16.1GB. RESULT: Ultimate proved your program to be incorrect! [2024-11-08 19:45:55,198 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_85b701ab-c495-4aef-9a70-f107f35b8b4a/bin/ukojak-verify-ImItNfHLgk/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE