./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm/config/KojakReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm/config/svcomp-Reach-32bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 21:25:16,574 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 21:25:16,634 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm/config/svcomp-Reach-32bit-Kojak_Default.epf [2024-11-13 21:25:16,639 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 21:25:16,639 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck.Interpolating solver [2024-11-13 21:25:16,660 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 21:25:16,660 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-13 21:25:16,661 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ALWAYS [2024-11-13 21:25:16,661 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 21:25:16,661 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 21:25:16,665 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 21:25:16,666 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-13 21:25:16,666 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 21:25:16,666 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 21:25:16,666 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 21:25:16,666 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 21:25:16,666 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-13 21:25:16,666 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-13 21:25:16,666 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-13 21:25:16,666 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 21:25:16,667 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 21:25:16,667 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 21:25:16,667 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 21:25:16,667 INFO L151 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2024-11-13 21:25:16,667 INFO L153 SettingsManager]: * Timeout in seconds=1000000 [2024-11-13 21:25:16,667 INFO L153 SettingsManager]: * Theory for external solver=ALL [2024-11-13 21:25:16,667 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 21:25:16,667 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2024-11-13 21:25:16,668 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 21:25:16,668 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-13 21:25:16,668 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-13 21:25:16,668 INFO L153 SettingsManager]: * Trace refinement strategy=PENGUIN [2024-11-13 21:25:16,668 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-13 21:25:16,668 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2024-11-13 21:25:16,941 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 21:25:16,949 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 21:25:16,951 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 21:25:16,952 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 21:25:16,953 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 21:25:16,954 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm/../../sv-benchmarks/c/systemc/transmitter.15.cil.c Unable to find full path for "g++" [2024-11-13 21:25:18,879 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 21:25:19,273 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 21:25:19,274 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/sv-benchmarks/c/systemc/transmitter.15.cil.c [2024-11-13 21:25:19,299 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm/data/048f1b369/a61a9cbef2364c709535baf99a836e2d/FLAGad4d9e72d [2024-11-13 21:25:19,320 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm/data/048f1b369/a61a9cbef2364c709535baf99a836e2d [2024-11-13 21:25:19,324 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 21:25:19,327 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 21:25:19,329 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 21:25:19,330 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 21:25:19,335 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 21:25:19,336 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 09:25:19" (1/1) ... [2024-11-13 21:25:19,337 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@78b6c77b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 09:25:19, skipping insertion in model container [2024-11-13 21:25:19,340 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 09:25:19" (1/1) ... [2024-11-13 21:25:19,392 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 21:25:19,573 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2024-11-13 21:25:19,803 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 21:25:19,817 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 21:25:19,830 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2024-11-13 21:25:19,946 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 21:25:19,979 INFO L204 MainTranslator]: Completed translation [2024-11-13 21:25:19,979 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 09:25:19 WrapperNode [2024-11-13 21:25:19,980 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 21:25:19,981 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 21:25:19,981 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 21:25:19,981 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 21:25:19,988 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 09:25:19" (1/1) ... [2024-11-13 21:25:20,005 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 09:25:19" (1/1) ... [2024-11-13 21:25:20,075 INFO L138 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 38, calls inlined = 38, statements flattened = 901 [2024-11-13 21:25:20,075 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 21:25:20,080 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 21:25:20,080 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 21:25:20,080 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 21:25:20,088 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 09:25:19" (1/1) ... [2024-11-13 21:25:20,088 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 09:25:19" (1/1) ... [2024-11-13 21:25:20,092 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 09:25:19" (1/1) ... [2024-11-13 21:25:20,093 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 09:25:19" (1/1) ... [2024-11-13 21:25:20,106 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 09:25:19" (1/1) ... [2024-11-13 21:25:20,119 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 09:25:19" (1/1) ... [2024-11-13 21:25:20,122 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 09:25:19" (1/1) ... [2024-11-13 21:25:20,125 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 09:25:19" (1/1) ... [2024-11-13 21:25:20,130 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 21:25:20,131 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 21:25:20,131 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 21:25:20,131 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 21:25:20,132 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 09:25:19" (1/1) ... [2024-11-13 21:25:20,138 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2024-11-13 21:25:20,158 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm/z3 [2024-11-13 21:25:20,176 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) [2024-11-13 21:25:20,182 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Waiting until timeout for monitored process [2024-11-13 21:25:20,202 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 21:25:20,202 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2024-11-13 21:25:20,202 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2024-11-13 21:25:20,202 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2024-11-13 21:25:20,202 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2024-11-13 21:25:20,203 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2024-11-13 21:25:20,203 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2024-11-13 21:25:20,203 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2024-11-13 21:25:20,203 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2024-11-13 21:25:20,203 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2024-11-13 21:25:20,203 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2024-11-13 21:25:20,203 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2024-11-13 21:25:20,203 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2024-11-13 21:25:20,203 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2024-11-13 21:25:20,204 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 21:25:20,204 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 21:25:20,356 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 21:25:20,358 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 21:25:21,464 INFO L? ?]: Removed 103 outVars from TransFormulas that were not future-live. [2024-11-13 21:25:21,464 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 21:25:22,232 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 21:25:22,234 INFO L316 CfgBuilder]: Removed 17 assume(true) statements. [2024-11-13 21:25:22,234 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 09:25:22 BoogieIcfgContainer [2024-11-13 21:25:22,234 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 21:25:22,235 INFO L112 PluginConnector]: ------------------------CodeCheck---------------------------- [2024-11-13 21:25:22,235 INFO L270 PluginConnector]: Initializing CodeCheck... [2024-11-13 21:25:22,250 INFO L274 PluginConnector]: CodeCheck initialized [2024-11-13 21:25:22,250 INFO L184 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 09:25:22" (1/1) ... [2024-11-13 21:25:22,260 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 21:25:22,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:22,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312 states to 206 states and 312 transitions. [2024-11-13 21:25:22,335 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 312 transitions. [2024-11-13 21:25:22,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:22,344 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:22,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:22,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:23,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:23,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:23,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 247 states and 392 transitions. [2024-11-13 21:25:23,280 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 392 transitions. [2024-11-13 21:25:23,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:23,283 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:23,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:23,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:23,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:23,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:23,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 248 states and 392 transitions. [2024-11-13 21:25:23,689 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 392 transitions. [2024-11-13 21:25:23,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:23,691 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:23,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:23,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:23,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:23,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:23,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 249 states and 392 transitions. [2024-11-13 21:25:23,929 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 392 transitions. [2024-11-13 21:25:23,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:23,933 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:23,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:23,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:24,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:24,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:24,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 250 states and 392 transitions. [2024-11-13 21:25:24,183 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 392 transitions. [2024-11-13 21:25:24,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:24,185 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:24,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:24,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:24,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:24,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:24,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 251 states and 392 transitions. [2024-11-13 21:25:24,420 INFO L276 IsEmpty]: Start isEmpty. Operand 251 states and 392 transitions. [2024-11-13 21:25:24,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:24,421 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:24,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:24,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:24,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:24,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:24,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 252 states and 392 transitions. [2024-11-13 21:25:24,616 INFO L276 IsEmpty]: Start isEmpty. Operand 252 states and 392 transitions. [2024-11-13 21:25:24,617 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:24,617 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:24,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:24,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:24,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:24,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:24,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 253 states and 392 transitions. [2024-11-13 21:25:24,806 INFO L276 IsEmpty]: Start isEmpty. Operand 253 states and 392 transitions. [2024-11-13 21:25:24,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:24,811 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:24,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:24,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:24,963 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:24,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:24,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 254 states and 392 transitions. [2024-11-13 21:25:24,983 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 392 transitions. [2024-11-13 21:25:24,987 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:24,987 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:24,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:25,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:25,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:25,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:25,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 255 states and 392 transitions. [2024-11-13 21:25:25,131 INFO L276 IsEmpty]: Start isEmpty. Operand 255 states and 392 transitions. [2024-11-13 21:25:25,132 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:25,132 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:25,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:25,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:25,257 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:25,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:25,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 256 states and 392 transitions. [2024-11-13 21:25:25,277 INFO L276 IsEmpty]: Start isEmpty. Operand 256 states and 392 transitions. [2024-11-13 21:25:25,278 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:25,278 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:25,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:25,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:25,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:25,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:25,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 257 states and 392 transitions. [2024-11-13 21:25:25,438 INFO L276 IsEmpty]: Start isEmpty. Operand 257 states and 392 transitions. [2024-11-13 21:25:25,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:25,439 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:25,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:25,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:25,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:25,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:25,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 258 states and 392 transitions. [2024-11-13 21:25:25,578 INFO L276 IsEmpty]: Start isEmpty. Operand 258 states and 392 transitions. [2024-11-13 21:25:25,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:25,579 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:25,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:25,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:25,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:25,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:25,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 259 states and 392 transitions. [2024-11-13 21:25:25,730 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states and 392 transitions. [2024-11-13 21:25:25,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:25,734 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:25,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:25,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:25,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:25,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:25,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 260 states and 392 transitions. [2024-11-13 21:25:25,865 INFO L276 IsEmpty]: Start isEmpty. Operand 260 states and 392 transitions. [2024-11-13 21:25:25,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:25,868 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:25,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:25,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:26,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:26,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:26,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 296 states and 463 transitions. [2024-11-13 21:25:26,295 INFO L276 IsEmpty]: Start isEmpty. Operand 296 states and 463 transitions. [2024-11-13 21:25:26,296 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:26,296 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:26,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:26,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:26,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:26,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:26,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 297 states and 463 transitions. [2024-11-13 21:25:26,443 INFO L276 IsEmpty]: Start isEmpty. Operand 297 states and 463 transitions. [2024-11-13 21:25:26,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:26,445 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:26,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:26,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:26,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:26,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:26,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 298 states and 463 transitions. [2024-11-13 21:25:26,624 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 463 transitions. [2024-11-13 21:25:26,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:26,625 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:26,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:26,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:26,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:26,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:26,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 299 states and 463 transitions. [2024-11-13 21:25:26,798 INFO L276 IsEmpty]: Start isEmpty. Operand 299 states and 463 transitions. [2024-11-13 21:25:26,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:26,799 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:26,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:26,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:26,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:26,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:26,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 300 states and 463 transitions. [2024-11-13 21:25:26,955 INFO L276 IsEmpty]: Start isEmpty. Operand 300 states and 463 transitions. [2024-11-13 21:25:26,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:26,957 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:26,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:26,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:27,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:27,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:27,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 301 states and 463 transitions. [2024-11-13 21:25:27,090 INFO L276 IsEmpty]: Start isEmpty. Operand 301 states and 463 transitions. [2024-11-13 21:25:27,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:27,091 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:27,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:27,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:27,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:27,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:27,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 302 states and 463 transitions. [2024-11-13 21:25:27,230 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 463 transitions. [2024-11-13 21:25:27,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:27,231 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:27,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:27,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:27,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:27,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:27,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 303 states and 463 transitions. [2024-11-13 21:25:27,372 INFO L276 IsEmpty]: Start isEmpty. Operand 303 states and 463 transitions. [2024-11-13 21:25:27,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:27,373 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:27,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:27,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:27,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:27,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:27,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 304 states and 463 transitions. [2024-11-13 21:25:27,532 INFO L276 IsEmpty]: Start isEmpty. Operand 304 states and 463 transitions. [2024-11-13 21:25:27,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:27,532 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:27,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:27,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:27,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:27,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:27,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 305 states and 463 transitions. [2024-11-13 21:25:27,660 INFO L276 IsEmpty]: Start isEmpty. Operand 305 states and 463 transitions. [2024-11-13 21:25:27,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:27,661 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:27,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:27,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:27,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:27,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:27,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 306 states and 463 transitions. [2024-11-13 21:25:27,802 INFO L276 IsEmpty]: Start isEmpty. Operand 306 states and 463 transitions. [2024-11-13 21:25:27,803 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:27,804 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:27,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:27,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:27,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:27,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:27,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 307 states and 463 transitions. [2024-11-13 21:25:27,932 INFO L276 IsEmpty]: Start isEmpty. Operand 307 states and 463 transitions. [2024-11-13 21:25:27,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:27,933 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:27,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:27,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:28,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:28,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:28,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 339 states and 528 transitions. [2024-11-13 21:25:28,427 INFO L276 IsEmpty]: Start isEmpty. Operand 339 states and 528 transitions. [2024-11-13 21:25:28,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:28,428 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:28,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:28,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:28,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:28,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:28,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 340 states and 528 transitions. [2024-11-13 21:25:28,558 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 528 transitions. [2024-11-13 21:25:28,560 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:28,560 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:28,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:28,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:28,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:28,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:28,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 341 states and 528 transitions. [2024-11-13 21:25:28,689 INFO L276 IsEmpty]: Start isEmpty. Operand 341 states and 528 transitions. [2024-11-13 21:25:28,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:28,690 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:28,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:28,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:28,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:28,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:28,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 342 states and 528 transitions. [2024-11-13 21:25:28,816 INFO L276 IsEmpty]: Start isEmpty. Operand 342 states and 528 transitions. [2024-11-13 21:25:28,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:28,817 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:28,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:28,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:28,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:28,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:28,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 343 states and 528 transitions. [2024-11-13 21:25:28,946 INFO L276 IsEmpty]: Start isEmpty. Operand 343 states and 528 transitions. [2024-11-13 21:25:28,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:28,947 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:28,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:28,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:29,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:29,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:29,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 344 states and 528 transitions. [2024-11-13 21:25:29,081 INFO L276 IsEmpty]: Start isEmpty. Operand 344 states and 528 transitions. [2024-11-13 21:25:29,082 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:29,084 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:29,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:29,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:29,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:29,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:29,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 345 states and 528 transitions. [2024-11-13 21:25:29,229 INFO L276 IsEmpty]: Start isEmpty. Operand 345 states and 528 transitions. [2024-11-13 21:25:29,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:29,233 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:29,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:29,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:29,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:29,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:29,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 346 states and 528 transitions. [2024-11-13 21:25:29,361 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 528 transitions. [2024-11-13 21:25:29,362 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:29,362 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:29,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:29,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:29,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:29,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:29,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 347 states and 528 transitions. [2024-11-13 21:25:29,486 INFO L276 IsEmpty]: Start isEmpty. Operand 347 states and 528 transitions. [2024-11-13 21:25:29,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:29,487 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:29,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:29,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:29,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:29,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:29,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 348 states and 528 transitions. [2024-11-13 21:25:29,610 INFO L276 IsEmpty]: Start isEmpty. Operand 348 states and 528 transitions. [2024-11-13 21:25:29,611 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:29,611 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:29,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:29,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:29,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:29,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:29,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 349 states and 528 transitions. [2024-11-13 21:25:29,731 INFO L276 IsEmpty]: Start isEmpty. Operand 349 states and 528 transitions. [2024-11-13 21:25:29,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:29,733 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:29,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:29,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:29,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:30,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:30,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 375 states and 581 transitions. [2024-11-13 21:25:30,861 INFO L276 IsEmpty]: Start isEmpty. Operand 375 states and 581 transitions. [2024-11-13 21:25:30,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:30,862 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:30,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:30,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:30,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:31,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:31,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 376 states and 581 transitions. [2024-11-13 21:25:31,592 INFO L276 IsEmpty]: Start isEmpty. Operand 376 states and 581 transitions. [2024-11-13 21:25:31,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:31,594 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:31,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:31,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:31,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:32,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:32,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 377 states and 581 transitions. [2024-11-13 21:25:32,211 INFO L276 IsEmpty]: Start isEmpty. Operand 377 states and 581 transitions. [2024-11-13 21:25:32,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:32,212 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:32,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:32,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:32,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:32,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:32,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 378 states and 581 transitions. [2024-11-13 21:25:32,829 INFO L276 IsEmpty]: Start isEmpty. Operand 378 states and 581 transitions. [2024-11-13 21:25:32,830 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:32,830 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:32,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:32,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:32,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:33,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:33,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 379 states and 581 transitions. [2024-11-13 21:25:33,461 INFO L276 IsEmpty]: Start isEmpty. Operand 379 states and 581 transitions. [2024-11-13 21:25:33,462 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:33,462 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:33,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:33,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:33,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:34,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:34,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 380 states and 581 transitions. [2024-11-13 21:25:34,065 INFO L276 IsEmpty]: Start isEmpty. Operand 380 states and 581 transitions. [2024-11-13 21:25:34,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:34,066 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:34,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:34,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:34,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:34,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:34,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 381 states and 581 transitions. [2024-11-13 21:25:34,683 INFO L276 IsEmpty]: Start isEmpty. Operand 381 states and 581 transitions. [2024-11-13 21:25:34,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:34,685 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:34,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:34,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:34,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:35,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:35,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 382 states and 581 transitions. [2024-11-13 21:25:35,280 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 581 transitions. [2024-11-13 21:25:35,281 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:35,281 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:35,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:35,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:35,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:35,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:35,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 383 states and 581 transitions. [2024-11-13 21:25:35,869 INFO L276 IsEmpty]: Start isEmpty. Operand 383 states and 581 transitions. [2024-11-13 21:25:35,870 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:35,870 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:35,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:35,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:36,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:36,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:36,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 403 states and 622 transitions. [2024-11-13 21:25:36,387 INFO L276 IsEmpty]: Start isEmpty. Operand 403 states and 622 transitions. [2024-11-13 21:25:36,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:36,388 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:36,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:36,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:36,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:36,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:36,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 404 states and 622 transitions. [2024-11-13 21:25:36,496 INFO L276 IsEmpty]: Start isEmpty. Operand 404 states and 622 transitions. [2024-11-13 21:25:36,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:36,498 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:36,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:36,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:36,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:36,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:36,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 405 states and 622 transitions. [2024-11-13 21:25:36,611 INFO L276 IsEmpty]: Start isEmpty. Operand 405 states and 622 transitions. [2024-11-13 21:25:36,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:36,612 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:36,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:36,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:36,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:36,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:36,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 406 states and 622 transitions. [2024-11-13 21:25:36,734 INFO L276 IsEmpty]: Start isEmpty. Operand 406 states and 622 transitions. [2024-11-13 21:25:36,735 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:36,735 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:36,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:36,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:36,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:36,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:36,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 407 states and 622 transitions. [2024-11-13 21:25:36,851 INFO L276 IsEmpty]: Start isEmpty. Operand 407 states and 622 transitions. [2024-11-13 21:25:36,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:36,852 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:36,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:36,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:36,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:36,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:36,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 408 states and 622 transitions. [2024-11-13 21:25:36,992 INFO L276 IsEmpty]: Start isEmpty. Operand 408 states and 622 transitions. [2024-11-13 21:25:36,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:36,993 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:36,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:37,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:37,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:37,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:37,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 409 states and 622 transitions. [2024-11-13 21:25:37,099 INFO L276 IsEmpty]: Start isEmpty. Operand 409 states and 622 transitions. [2024-11-13 21:25:37,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:37,101 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:37,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:37,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:37,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:38,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:38,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 423 states and 651 transitions. [2024-11-13 21:25:38,071 INFO L276 IsEmpty]: Start isEmpty. Operand 423 states and 651 transitions. [2024-11-13 21:25:38,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:38,072 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:38,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:38,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:38,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:38,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:38,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 424 states and 651 transitions. [2024-11-13 21:25:38,620 INFO L276 IsEmpty]: Start isEmpty. Operand 424 states and 651 transitions. [2024-11-13 21:25:38,621 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:38,621 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:38,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:38,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:38,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:39,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:39,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 425 states and 651 transitions. [2024-11-13 21:25:39,162 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 651 transitions. [2024-11-13 21:25:39,163 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:39,163 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:39,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:39,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:39,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:39,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:39,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 426 states and 651 transitions. [2024-11-13 21:25:39,717 INFO L276 IsEmpty]: Start isEmpty. Operand 426 states and 651 transitions. [2024-11-13 21:25:39,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:39,718 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:39,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:39,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:39,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:40,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:40,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 427 states and 651 transitions. [2024-11-13 21:25:40,247 INFO L276 IsEmpty]: Start isEmpty. Operand 427 states and 651 transitions. [2024-11-13 21:25:40,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:40,249 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:40,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:40,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:40,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:40,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:40,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 717 states to 435 states and 668 transitions. [2024-11-13 21:25:40,760 INFO L276 IsEmpty]: Start isEmpty. Operand 435 states and 668 transitions. [2024-11-13 21:25:40,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:40,761 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:40,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:40,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:40,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:40,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:40,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 717 states to 436 states and 668 transitions. [2024-11-13 21:25:40,868 INFO L276 IsEmpty]: Start isEmpty. Operand 436 states and 668 transitions. [2024-11-13 21:25:40,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:40,869 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:40,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:40,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:40,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:40,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:40,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 717 states to 437 states and 668 transitions. [2024-11-13 21:25:40,973 INFO L276 IsEmpty]: Start isEmpty. Operand 437 states and 668 transitions. [2024-11-13 21:25:40,974 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:40,974 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:40,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:40,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:41,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:41,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:41,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 735 states to 442 states and 679 transitions. [2024-11-13 21:25:41,548 INFO L276 IsEmpty]: Start isEmpty. Operand 442 states and 679 transitions. [2024-11-13 21:25:41,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:41,549 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:41,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:41,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:41,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:41,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:41,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 735 states to 443 states and 679 transitions. [2024-11-13 21:25:41,652 INFO L276 IsEmpty]: Start isEmpty. Operand 443 states and 679 transitions. [2024-11-13 21:25:41,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:41,653 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:41,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:41,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:41,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:44,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:44,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 852 states to 489 states and 770 transitions. [2024-11-13 21:25:44,824 INFO L276 IsEmpty]: Start isEmpty. Operand 489 states and 770 transitions. [2024-11-13 21:25:44,825 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:44,825 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:44,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:44,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:45,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:46,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:46,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 868 states to 491 states and 775 transitions. [2024-11-13 21:25:46,274 INFO L276 IsEmpty]: Start isEmpty. Operand 491 states and 775 transitions. [2024-11-13 21:25:46,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:46,275 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:46,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:46,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:46,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:48,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:48,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 902 states to 502 states and 798 transitions. [2024-11-13 21:25:48,841 INFO L276 IsEmpty]: Start isEmpty. Operand 502 states and 798 transitions. [2024-11-13 21:25:48,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:48,843 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:48,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:48,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:49,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:53,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:53,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 948 states to 519 states and 833 transitions. [2024-11-13 21:25:53,999 INFO L276 IsEmpty]: Start isEmpty. Operand 519 states and 833 transitions. [2024-11-13 21:25:54,000 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:54,000 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:54,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:54,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:54,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:25:59,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:25:59,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1006 states to 542 states and 880 transitions. [2024-11-13 21:25:59,488 INFO L276 IsEmpty]: Start isEmpty. Operand 542 states and 880 transitions. [2024-11-13 21:25:59,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:25:59,490 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:25:59,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:25:59,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:25:59,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:06,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:06,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1076 states to 571 states and 939 transitions. [2024-11-13 21:26:06,206 INFO L276 IsEmpty]: Start isEmpty. Operand 571 states and 939 transitions. [2024-11-13 21:26:06,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 21:26:06,207 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:06,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:06,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:26:06,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:15,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:15,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1164 states to 609 states and 1016 transitions. [2024-11-13 21:26:15,943 INFO L276 IsEmpty]: Start isEmpty. Operand 609 states and 1016 transitions. [2024-11-13 21:26:15,944 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-13 21:26:15,944 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:15,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:15,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:26:16,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:16,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:16,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1165 states to 610 states and 1017 transitions. [2024-11-13 21:26:16,232 INFO L276 IsEmpty]: Start isEmpty. Operand 610 states and 1017 transitions. [2024-11-13 21:26:16,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-13 21:26:16,233 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:16,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:16,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:26:16,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:16,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:16,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1166 states to 611 states and 1018 transitions. [2024-11-13 21:26:16,545 INFO L276 IsEmpty]: Start isEmpty. Operand 611 states and 1018 transitions. [2024-11-13 21:26:16,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-13 21:26:16,545 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:16,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:16,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:26:16,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:17,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:17,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1167 states to 612 states and 1019 transitions. [2024-11-13 21:26:17,325 INFO L276 IsEmpty]: Start isEmpty. Operand 612 states and 1019 transitions. [2024-11-13 21:26:17,326 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-13 21:26:17,326 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:17,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:17,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:26:17,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:17,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:17,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1168 states to 613 states and 1020 transitions. [2024-11-13 21:26:17,724 INFO L276 IsEmpty]: Start isEmpty. Operand 613 states and 1020 transitions. [2024-11-13 21:26:17,725 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-13 21:26:17,725 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:17,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:17,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:26:17,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:18,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:18,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1169 states to 614 states and 1021 transitions. [2024-11-13 21:26:18,424 INFO L276 IsEmpty]: Start isEmpty. Operand 614 states and 1021 transitions. [2024-11-13 21:26:18,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-13 21:26:18,425 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:18,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:18,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:26:18,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:18,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:18,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1170 states to 615 states and 1022 transitions. [2024-11-13 21:26:18,816 INFO L276 IsEmpty]: Start isEmpty. Operand 615 states and 1022 transitions. [2024-11-13 21:26:18,816 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-13 21:26:18,816 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:18,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:18,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:26:18,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:19,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:19,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1171 states to 616 states and 1023 transitions. [2024-11-13 21:26:19,272 INFO L276 IsEmpty]: Start isEmpty. Operand 616 states and 1023 transitions. [2024-11-13 21:26:19,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-13 21:26:19,273 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:19,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:19,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:26:19,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:19,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:19,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1172 states to 617 states and 1024 transitions. [2024-11-13 21:26:19,787 INFO L276 IsEmpty]: Start isEmpty. Operand 617 states and 1024 transitions. [2024-11-13 21:26:19,788 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-13 21:26:19,788 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:19,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:19,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:26:19,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:20,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:20,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1173 states to 618 states and 1025 transitions. [2024-11-13 21:26:20,193 INFO L276 IsEmpty]: Start isEmpty. Operand 618 states and 1025 transitions. [2024-11-13 21:26:20,193 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-13 21:26:20,193 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:20,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:20,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:26:20,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:22,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:22,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1174 states to 619 states and 1026 transitions. [2024-11-13 21:26:22,391 INFO L276 IsEmpty]: Start isEmpty. Operand 619 states and 1026 transitions. [2024-11-13 21:26:22,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-13 21:26:22,392 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:22,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:22,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:26:22,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:22,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:22,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 620 states and 1027 transitions. [2024-11-13 21:26:22,798 INFO L276 IsEmpty]: Start isEmpty. Operand 620 states and 1027 transitions. [2024-11-13 21:26:22,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-13 21:26:22,799 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:22,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:22,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:26:22,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:23,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:23,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1176 states to 621 states and 1028 transitions. [2024-11-13 21:26:23,153 INFO L276 IsEmpty]: Start isEmpty. Operand 621 states and 1028 transitions. [2024-11-13 21:26:23,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-13 21:26:23,153 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:23,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:23,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 21:26:23,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 21:26:23,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-13 21:26:23,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1106 states to 582 states and 960 transitions. [2024-11-13 21:26:23,241 INFO L276 IsEmpty]: Start isEmpty. Operand 582 states and 960 transitions. [2024-11-13 21:26:23,241 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-13 21:26:23,241 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-13 21:26:23,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 21:26:23,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 21:26:23,260 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 21:26:23,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 21:26:23,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 21:26:23,563 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 21:26:23,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 21:26:23,790 WARN L473 CodeCheckObserver]: This program is UNSAFE, Check terminated with 84 iterations. [2024-11-13 21:26:24,003 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 13.11 09:26:24 ImpRootNode [2024-11-13 21:26:24,003 INFO L131 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2024-11-13 21:26:24,004 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 21:26:24,004 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 21:26:24,004 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 21:26:24,005 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 09:25:22" (3/4) ... [2024-11-13 21:26:24,006 INFO L136 WitnessPrinter]: Generating witness for reachability counterexample [2024-11-13 21:26:24,271 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm/witness.graphml [2024-11-13 21:26:24,272 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 21:26:24,274 INFO L158 Benchmark]: Toolchain (without parser) took 64947.26ms. Allocated memory was 117.4MB in the beginning and 629.1MB in the end (delta: 511.7MB). Free memory was 93.9MB in the beginning and 551.2MB in the end (delta: -457.2MB). Peak memory consumption was 397.5MB. Max. memory is 16.1GB. [2024-11-13 21:26:24,274 INFO L158 Benchmark]: CDTParser took 0.35ms. Allocated memory is still 167.8MB. Free memory is still 104.8MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 21:26:24,274 INFO L158 Benchmark]: CACSL2BoogieTranslator took 651.17ms. Allocated memory is still 117.4MB. Free memory was 93.6MB in the beginning and 71.3MB in the end (delta: 22.2MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-13 21:26:24,275 INFO L158 Benchmark]: Boogie Procedure Inliner took 98.58ms. Allocated memory is still 117.4MB. Free memory was 71.3MB in the beginning and 67.6MB in the end (delta: 3.8MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 21:26:24,275 INFO L158 Benchmark]: Boogie Preprocessor took 50.59ms. Allocated memory is still 117.4MB. Free memory was 67.6MB in the beginning and 64.2MB in the end (delta: 3.4MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 21:26:24,276 INFO L158 Benchmark]: RCFGBuilder took 2103.64ms. Allocated memory was 117.4MB in the beginning and 352.3MB in the end (delta: 234.9MB). Free memory was 63.8MB in the beginning and 223.3MB in the end (delta: -159.5MB). Peak memory consumption was 80.4MB. Max. memory is 16.1GB. [2024-11-13 21:26:24,278 INFO L158 Benchmark]: CodeCheck took 61767.94ms. Allocated memory was 352.3MB in the beginning and 629.1MB in the end (delta: 276.8MB). Free memory was 223.3MB in the beginning and 230.7MB in the end (delta: -7.4MB). Peak memory consumption was 272.3MB. Max. memory is 16.1GB. [2024-11-13 21:26:24,278 INFO L158 Benchmark]: Witness Printer took 268.44ms. Allocated memory is still 629.1MB. Free memory was 230.7MB in the beginning and 551.2MB in the end (delta: -320.5MB). Peak memory consumption was 23.4MB. Max. memory is 16.1GB. [2024-11-13 21:26:24,280 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 7 procedures, 206 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 61.5s, OverallIterations: 84, TraceHistogramMax: 0, PathProgramHistogramMax: 0, EmptinessCheckTime: 0.0s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 55582 SdHoareTripleChecker+Valid, 64.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 45174 mSDsluCounter, 89407 SdHoareTripleChecker+Invalid, 54.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 72018 mSDsCounter, 4223 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 31667 IncrementalHoareTripleChecker+Invalid, 35890 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 4223 mSolverCounterUnsat, 17389 mSDtfsCounter, 31667 mSolverCounterSat, 2.6s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 53486 GetRequests, 52229 SyntacticMatches, 855 SemanticMatches, 402 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 120112 ImplicationChecksByTransitivity, 46.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, InterpolantAutomatonStates: 0, traceCheckStatistics: 0.6s SsaConstructionTime, 0.9s SatisfiabilityAnalysisTime, 8.9s InterpolantComputationTime, 5643 NumberOfCodeBlocks, 5643 NumberOfCodeBlocksAsserted, 84 NumberOfCheckSat, 5491 ConstructedInterpolants, 0 QuantifiedInterpolants, 14565 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 83 InterpolantComputations, 83 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int t8_pc = 0; [L34] int t9_pc = 0; [L35] int t10_pc = 0; [L36] int t11_pc = 0; [L37] int t12_pc = 0; [L38] int t13_pc = 0; [L39] int m_st ; [L40] int t1_st ; [L41] int t2_st ; [L42] int t3_st ; [L43] int t4_st ; [L44] int t5_st ; [L45] int t6_st ; [L46] int t7_st ; [L47] int t8_st ; [L48] int t9_st ; [L49] int t10_st ; [L50] int t11_st ; [L51] int t12_st ; [L52] int t13_st ; [L53] int m_i ; [L54] int t1_i ; [L55] int t2_i ; [L56] int t3_i ; [L57] int t4_i ; [L58] int t5_i ; [L59] int t6_i ; [L60] int t7_i ; [L61] int t8_i ; [L62] int t9_i ; [L63] int t10_i ; [L64] int t11_i ; [L65] int t12_i ; [L66] int t13_i ; [L67] int M_E = 2; [L68] int T1_E = 2; [L69] int T2_E = 2; [L70] int T3_E = 2; [L71] int T4_E = 2; [L72] int T5_E = 2; [L73] int T6_E = 2; [L74] int T7_E = 2; [L75] int T8_E = 2; [L76] int T9_E = 2; [L77] int T10_E = 2; [L78] int T11_E = 2; [L79] int T12_E = 2; [L80] int T13_E = 2; [L81] int E_1 = 2; [L82] int E_2 = 2; [L83] int E_3 = 2; [L84] int E_4 = 2; [L85] int E_5 = 2; [L86] int E_6 = 2; [L87] int E_7 = 2; [L88] int E_8 = 2; [L89] int E_9 = 2; [L90] int E_10 = 2; [L91] int E_11 = 2; [L92] int E_12 = 2; [L93] int E_13 = 2; [L1937] int __retres1 ; [L1941] CALL init_model() [L1840] m_i = 1 [L1841] t1_i = 1 [L1842] t2_i = 1 [L1843] t3_i = 1 [L1844] t4_i = 1 [L1845] t5_i = 1 [L1846] t6_i = 1 [L1847] t7_i = 1 [L1848] t8_i = 1 [L1849] t9_i = 1 [L1850] t10_i = 1 [L1851] t11_i = 1 [L1852] t12_i = 1 [L1853] t13_i = 1 [L1941] RET init_model() [L1942] CALL start_simulation() [L1878] int kernel_st ; [L1879] int tmp ; [L1880] int tmp___0 ; [L1884] kernel_st = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1885] FCALL update_channels() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1886] CALL init_threads() [L881] COND TRUE m_i == 1 [L882] m_st = 0 [L886] COND TRUE t1_i == 1 [L887] t1_st = 0 [L891] COND TRUE t2_i == 1 [L892] t2_st = 0 [L896] COND TRUE t3_i == 1 [L897] t3_st = 0 [L901] COND TRUE t4_i == 1 [L902] t4_st = 0 [L906] COND TRUE t5_i == 1 [L907] t5_st = 0 [L911] COND TRUE t6_i == 1 [L912] t6_st = 0 [L916] COND TRUE t7_i == 1 [L917] t7_st = 0 [L921] COND TRUE t8_i == 1 [L922] t8_st = 0 [L926] COND TRUE t9_i == 1 [L927] t9_st = 0 [L931] COND TRUE t10_i == 1 [L932] t10_st = 0 [L936] COND TRUE t11_i == 1 [L937] t11_st = 0 [L941] COND TRUE t12_i == 1 [L942] t12_st = 0 [L946] COND TRUE t13_i == 1 [L947] t13_st = 0 [L1886] RET init_threads() [L1887] CALL fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1258] COND FALSE !(M_E == 0) [L1263] COND FALSE !(T1_E == 0) [L1268] COND FALSE !(T2_E == 0) [L1273] COND FALSE !(T3_E == 0) [L1278] COND FALSE !(T4_E == 0) [L1283] COND FALSE !(T5_E == 0) [L1288] COND FALSE !(T6_E == 0) [L1293] COND FALSE !(T7_E == 0) [L1298] COND FALSE !(T8_E == 0) [L1303] COND FALSE !(T9_E == 0) [L1308] COND FALSE !(T10_E == 0) [L1313] COND FALSE !(T11_E == 0) [L1318] COND FALSE !(T12_E == 0) [L1323] COND FALSE !(T13_E == 0) [L1328] COND FALSE !(E_1 == 0) [L1333] COND FALSE !(E_2 == 0) [L1338] COND FALSE !(E_3 == 0) [L1343] COND FALSE !(E_4 == 0) [L1348] COND FALSE !(E_5 == 0) [L1353] COND FALSE !(E_6 == 0) [L1358] COND FALSE !(E_7 == 0) [L1363] COND FALSE !(E_8 == 0) [L1368] COND FALSE !(E_9 == 0) [L1373] COND FALSE !(E_10 == 0) [L1378] COND FALSE !(E_11 == 0) [L1383] COND FALSE !(E_12 == 0) [L1388] COND FALSE !(E_13 == 0) [L1887] RET fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1888] CALL activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1541] int tmp ; [L1542] int tmp___0 ; [L1543] int tmp___1 ; [L1544] int tmp___2 ; [L1545] int tmp___3 ; [L1546] int tmp___4 ; [L1547] int tmp___5 ; [L1548] int tmp___6 ; [L1549] int tmp___7 ; [L1550] int tmp___8 ; [L1551] int tmp___9 ; [L1552] int tmp___10 ; [L1553] int tmp___11 ; [L1554] int tmp___12 ; [L1558] CALL, EXPR is_master_triggered() [L604] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L607] COND FALSE !(m_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L617] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L619] return (__retres1); [L1558] RET, EXPR is_master_triggered() [L1558] tmp = is_master_triggered() [L1560] COND FALSE !(\read(tmp)) [L1566] CALL, EXPR is_transmit1_triggered() [L623] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L626] COND FALSE !(t1_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L636] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L638] return (__retres1); [L1566] RET, EXPR is_transmit1_triggered() [L1566] tmp___0 = is_transmit1_triggered() [L1568] COND FALSE !(\read(tmp___0)) [L1574] CALL, EXPR is_transmit2_triggered() [L642] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L645] COND FALSE !(t2_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L655] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L657] return (__retres1); [L1574] RET, EXPR is_transmit2_triggered() [L1574] tmp___1 = is_transmit2_triggered() [L1576] COND FALSE !(\read(tmp___1)) [L1582] CALL, EXPR is_transmit3_triggered() [L661] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L664] COND FALSE !(t3_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L674] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L676] return (__retres1); [L1582] RET, EXPR is_transmit3_triggered() [L1582] tmp___2 = is_transmit3_triggered() [L1584] COND FALSE !(\read(tmp___2)) [L1590] CALL, EXPR is_transmit4_triggered() [L680] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L683] COND FALSE !(t4_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L693] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L695] return (__retres1); [L1590] RET, EXPR is_transmit4_triggered() [L1590] tmp___3 = is_transmit4_triggered() [L1592] COND FALSE !(\read(tmp___3)) [L1598] CALL, EXPR is_transmit5_triggered() [L699] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L702] COND FALSE !(t5_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L712] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L714] return (__retres1); [L1598] RET, EXPR is_transmit5_triggered() [L1598] tmp___4 = is_transmit5_triggered() [L1600] COND FALSE !(\read(tmp___4)) [L1606] CALL, EXPR is_transmit6_triggered() [L718] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L721] COND FALSE !(t6_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L731] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L733] return (__retres1); [L1606] RET, EXPR is_transmit6_triggered() [L1606] tmp___5 = is_transmit6_triggered() [L1608] COND FALSE !(\read(tmp___5)) [L1614] CALL, EXPR is_transmit7_triggered() [L737] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L740] COND FALSE !(t7_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L750] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L752] return (__retres1); [L1614] RET, EXPR is_transmit7_triggered() [L1614] tmp___6 = is_transmit7_triggered() [L1616] COND FALSE !(\read(tmp___6)) [L1622] CALL, EXPR is_transmit8_triggered() [L756] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L759] COND FALSE !(t8_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L769] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L771] return (__retres1); [L1622] RET, EXPR is_transmit8_triggered() [L1622] tmp___7 = is_transmit8_triggered() [L1624] COND FALSE !(\read(tmp___7)) [L1630] CALL, EXPR is_transmit9_triggered() [L775] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L778] COND FALSE !(t9_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L788] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L790] return (__retres1); [L1630] RET, EXPR is_transmit9_triggered() [L1630] tmp___8 = is_transmit9_triggered() [L1632] COND FALSE !(\read(tmp___8)) [L1638] CALL, EXPR is_transmit10_triggered() [L794] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L797] COND FALSE !(t10_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L807] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L809] return (__retres1); [L1638] RET, EXPR is_transmit10_triggered() [L1638] tmp___9 = is_transmit10_triggered() [L1640] COND FALSE !(\read(tmp___9)) [L1646] CALL, EXPR is_transmit11_triggered() [L813] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L816] COND FALSE !(t11_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L826] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L828] return (__retres1); [L1646] RET, EXPR is_transmit11_triggered() [L1646] tmp___10 = is_transmit11_triggered() [L1648] COND FALSE !(\read(tmp___10)) [L1654] CALL, EXPR is_transmit12_triggered() [L832] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L835] COND FALSE !(t12_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L845] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L847] return (__retres1); [L1654] RET, EXPR is_transmit12_triggered() [L1654] tmp___11 = is_transmit12_triggered() [L1656] COND FALSE !(\read(tmp___11)) [L1662] CALL, EXPR is_transmit13_triggered() [L851] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L854] COND FALSE !(t13_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L864] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L866] return (__retres1); [L1662] RET, EXPR is_transmit13_triggered() [L1662] tmp___12 = is_transmit13_triggered() [L1664] COND FALSE !(\read(tmp___12)) [L1888] RET activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1889] CALL reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1401] COND FALSE !(M_E == 1) [L1406] COND FALSE !(T1_E == 1) [L1411] COND FALSE !(T2_E == 1) [L1416] COND FALSE !(T3_E == 1) [L1421] COND FALSE !(T4_E == 1) [L1426] COND FALSE !(T5_E == 1) [L1431] COND FALSE !(T6_E == 1) [L1436] COND FALSE !(T7_E == 1) [L1441] COND FALSE !(T8_E == 1) [L1446] COND FALSE !(T9_E == 1) [L1451] COND FALSE !(T10_E == 1) [L1456] COND FALSE !(T11_E == 1) [L1461] COND FALSE !(T12_E == 1) [L1466] COND FALSE !(T13_E == 1) [L1471] COND FALSE !(E_1 == 1) [L1476] COND FALSE !(E_2 == 1) [L1481] COND FALSE !(E_3 == 1) [L1486] COND FALSE !(E_4 == 1) [L1491] COND FALSE !(E_5 == 1) [L1496] COND FALSE !(E_6 == 1) [L1501] COND FALSE !(E_7 == 1) [L1506] COND FALSE !(E_8 == 1) [L1511] COND FALSE !(E_9 == 1) [L1516] COND FALSE !(E_10 == 1) [L1521] COND FALSE !(E_11 == 1) [L1526] COND FALSE !(E_12 == 1) [L1531] COND FALSE !(E_13 == 1) [L1889] RET reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1892] COND TRUE 1 [L1895] kernel_st = 1 [L1896] CALL eval() [L1037] int tmp ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1041] COND TRUE 1 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1044] CALL, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L956] int __retres1 ; [L959] COND TRUE m_st == 0 [L960] __retres1 = 1 [L1032] return (__retres1); [L1044] RET, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1044] tmp = exists_runnable_thread() [L1046] COND TRUE \read(tmp) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1051] COND TRUE m_st == 0 [L1052] int tmp_ndt_1; [L1053] tmp_ndt_1 = __VERIFIER_nondet_int() [L1054] COND FALSE !(\read(tmp_ndt_1)) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1065] COND TRUE t1_st == 0 [L1066] int tmp_ndt_2; [L1067] tmp_ndt_2 = __VERIFIER_nondet_int() [L1068] COND FALSE !(\read(tmp_ndt_2)) [L1074] CALL error() [L21] reach_error() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.35ms. Allocated memory is still 167.8MB. Free memory is still 104.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 651.17ms. Allocated memory is still 117.4MB. Free memory was 93.6MB in the beginning and 71.3MB in the end (delta: 22.2MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 98.58ms. Allocated memory is still 117.4MB. Free memory was 71.3MB in the beginning and 67.6MB in the end (delta: 3.8MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 50.59ms. Allocated memory is still 117.4MB. Free memory was 67.6MB in the beginning and 64.2MB in the end (delta: 3.4MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 2103.64ms. Allocated memory was 117.4MB in the beginning and 352.3MB in the end (delta: 234.9MB). Free memory was 63.8MB in the beginning and 223.3MB in the end (delta: -159.5MB). Peak memory consumption was 80.4MB. Max. memory is 16.1GB. * CodeCheck took 61767.94ms. Allocated memory was 352.3MB in the beginning and 629.1MB in the end (delta: 276.8MB). Free memory was 223.3MB in the beginning and 230.7MB in the end (delta: -7.4MB). Peak memory consumption was 272.3MB. Max. memory is 16.1GB. * Witness Printer took 268.44ms. Allocated memory is still 629.1MB. Free memory was 230.7MB in the beginning and 551.2MB in the end (delta: -320.5MB). Peak memory consumption was 23.4MB. Max. memory is 16.1GB. RESULT: Ultimate proved your program to be incorrect! [2024-11-13 21:26:24,318 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_897cf8aa-a54a-44af-bac0-25b062611f51/bin/ukojak-verify-EEHR8qb7sm/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE