./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/config/KojakReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/config/svcomp-Reach-32bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3 --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-11-25 05:20:31,216 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-25 05:20:31,300 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/config/svcomp-Reach-32bit-Kojak_Default.epf [2024-11-25 05:20:31,316 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-25 05:20:31,316 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck.Interpolating solver [2024-11-25 05:20:31,365 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-25 05:20:31,366 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-25 05:20:31,367 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ALWAYS [2024-11-25 05:20:31,368 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-25 05:20:31,369 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-25 05:20:31,369 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-25 05:20:31,370 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-25 05:20:31,371 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-25 05:20:31,371 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-25 05:20:31,371 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-25 05:20:31,371 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-25 05:20:31,371 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-25 05:20:31,371 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-25 05:20:31,372 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-25 05:20:31,373 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-25 05:20:31,373 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-25 05:20:31,373 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-25 05:20:31,373 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-25 05:20:31,373 INFO L151 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2024-11-25 05:20:31,373 INFO L153 SettingsManager]: * Timeout in seconds=1000000 [2024-11-25 05:20:31,374 INFO L153 SettingsManager]: * Theory for external solver=ALL [2024-11-25 05:20:31,374 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-25 05:20:31,374 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2024-11-25 05:20:31,374 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-25 05:20:31,374 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-25 05:20:31,375 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-25 05:20:31,375 INFO L153 SettingsManager]: * Trace refinement strategy=PENGUIN [2024-11-25 05:20:31,375 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-25 05:20:31,375 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2024-11-25 05:20:31,796 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-25 05:20:31,815 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-25 05:20:31,820 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-25 05:20:31,822 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-25 05:20:31,822 INFO L274 PluginConnector]: CDTParser initialized [2024-11-25 05:20:31,826 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/../../sv-benchmarks/c/systemc/transmitter.15.cil.c [2024-11-25 05:20:35,360 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/data/fec86f698/915e35ec947c42508ec016a7e0a1aedc/FLAGd3bc357f2 [2024-11-25 05:20:35,765 INFO L384 CDTParser]: Found 1 translation units. [2024-11-25 05:20:35,765 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/sv-benchmarks/c/systemc/transmitter.15.cil.c [2024-11-25 05:20:35,793 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/data/fec86f698/915e35ec947c42508ec016a7e0a1aedc/FLAGd3bc357f2 [2024-11-25 05:20:35,823 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/data/fec86f698/915e35ec947c42508ec016a7e0a1aedc [2024-11-25 05:20:35,829 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-25 05:20:35,830 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-25 05:20:35,835 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-25 05:20:35,835 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-25 05:20:35,841 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-25 05:20:35,842 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 05:20:35" (1/1) ... [2024-11-25 05:20:35,844 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2e18f5d4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:20:35, skipping insertion in model container [2024-11-25 05:20:35,845 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 05:20:35" (1/1) ... [2024-11-25 05:20:35,915 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-25 05:20:36,134 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2024-11-25 05:20:36,402 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-25 05:20:36,418 INFO L200 MainTranslator]: Completed pre-run [2024-11-25 05:20:36,435 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2024-11-25 05:20:36,609 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-25 05:20:36,660 INFO L204 MainTranslator]: Completed translation [2024-11-25 05:20:36,661 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:20:36 WrapperNode [2024-11-25 05:20:36,661 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-25 05:20:36,662 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-25 05:20:36,663 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-25 05:20:36,663 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-25 05:20:36,676 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:20:36" (1/1) ... [2024-11-25 05:20:36,700 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:20:36" (1/1) ... [2024-11-25 05:20:36,812 INFO L138 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 38, calls inlined = 38, statements flattened = 901 [2024-11-25 05:20:36,813 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-25 05:20:36,813 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-25 05:20:36,814 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-25 05:20:36,814 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-25 05:20:36,824 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:20:36" (1/1) ... [2024-11-25 05:20:36,825 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:20:36" (1/1) ... [2024-11-25 05:20:36,834 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:20:36" (1/1) ... [2024-11-25 05:20:36,835 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:20:36" (1/1) ... [2024-11-25 05:20:36,864 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:20:36" (1/1) ... [2024-11-25 05:20:36,870 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:20:36" (1/1) ... [2024-11-25 05:20:36,898 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:20:36" (1/1) ... [2024-11-25 05:20:36,901 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:20:36" (1/1) ... [2024-11-25 05:20:36,904 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:20:36" (1/1) ... [2024-11-25 05:20:36,911 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-25 05:20:36,912 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-25 05:20:36,912 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-25 05:20:36,912 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-25 05:20:36,913 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 05:20:36" (1/1) ... [2024-11-25 05:20:36,921 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2024-11-25 05:20:36,940 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/z3 [2024-11-25 05:20:36,964 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) [2024-11-25 05:20:36,969 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Waiting until timeout for monitored process [2024-11-25 05:20:37,009 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-25 05:20:37,009 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2024-11-25 05:20:37,009 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2024-11-25 05:20:37,009 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2024-11-25 05:20:37,009 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2024-11-25 05:20:37,009 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2024-11-25 05:20:37,009 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2024-11-25 05:20:37,009 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2024-11-25 05:20:37,009 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2024-11-25 05:20:37,010 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2024-11-25 05:20:37,010 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2024-11-25 05:20:37,010 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2024-11-25 05:20:37,010 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2024-11-25 05:20:37,010 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2024-11-25 05:20:37,010 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-25 05:20:37,010 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-25 05:20:37,178 INFO L234 CfgBuilder]: Building ICFG [2024-11-25 05:20:37,181 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-25 05:20:38,695 INFO L? ?]: Removed 103 outVars from TransFormulas that were not future-live. [2024-11-25 05:20:38,695 INFO L283 CfgBuilder]: Performing block encoding [2024-11-25 05:20:39,654 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-25 05:20:39,655 INFO L312 CfgBuilder]: Removed 34 assume(true) statements. [2024-11-25 05:20:39,655 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 05:20:39 BoogieIcfgContainer [2024-11-25 05:20:39,655 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-25 05:20:39,657 INFO L112 PluginConnector]: ------------------------CodeCheck---------------------------- [2024-11-25 05:20:39,657 INFO L270 PluginConnector]: Initializing CodeCheck... [2024-11-25 05:20:39,671 INFO L274 PluginConnector]: CodeCheck initialized [2024-11-25 05:20:39,671 INFO L184 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 05:20:39" (1/1) ... [2024-11-25 05:20:39,682 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-25 05:20:39,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:39,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311 states to 205 states and 311 transitions. [2024-11-25 05:20:39,781 INFO L276 IsEmpty]: Start isEmpty. Operand 205 states and 311 transitions. [2024-11-25 05:20:39,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:39,792 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:39,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:40,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:40,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:42,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:42,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 246 states and 391 transitions. [2024-11-25 05:20:42,175 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 391 transitions. [2024-11-25 05:20:42,177 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:42,178 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:42,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:42,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:42,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:43,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:43,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 247 states and 391 transitions. [2024-11-25 05:20:43,284 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 391 transitions. [2024-11-25 05:20:43,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:43,286 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:43,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:43,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:43,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:44,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:44,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 248 states and 391 transitions. [2024-11-25 05:20:44,309 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 391 transitions. [2024-11-25 05:20:44,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:44,311 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:44,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:44,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:44,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:45,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:45,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 249 states and 391 transitions. [2024-11-25 05:20:45,176 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 391 transitions. [2024-11-25 05:20:45,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:45,181 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:45,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:45,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:45,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:46,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:46,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 250 states and 391 transitions. [2024-11-25 05:20:46,030 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 391 transitions. [2024-11-25 05:20:46,031 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:46,031 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:46,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:46,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:46,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:46,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:46,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 251 states and 391 transitions. [2024-11-25 05:20:46,840 INFO L276 IsEmpty]: Start isEmpty. Operand 251 states and 391 transitions. [2024-11-25 05:20:46,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:46,841 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:46,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:46,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:46,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:47,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:47,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 252 states and 391 transitions. [2024-11-25 05:20:47,653 INFO L276 IsEmpty]: Start isEmpty. Operand 252 states and 391 transitions. [2024-11-25 05:20:47,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:47,655 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:47,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:47,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:47,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:48,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:48,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 253 states and 391 transitions. [2024-11-25 05:20:48,527 INFO L276 IsEmpty]: Start isEmpty. Operand 253 states and 391 transitions. [2024-11-25 05:20:48,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:48,528 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:48,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:48,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:48,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:49,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:49,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 254 states and 391 transitions. [2024-11-25 05:20:49,303 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 391 transitions. [2024-11-25 05:20:49,304 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:49,304 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:49,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:49,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:49,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:50,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:50,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 255 states and 391 transitions. [2024-11-25 05:20:50,081 INFO L276 IsEmpty]: Start isEmpty. Operand 255 states and 391 transitions. [2024-11-25 05:20:50,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:50,084 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:50,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:50,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:50,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:50,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:50,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 256 states and 391 transitions. [2024-11-25 05:20:50,853 INFO L276 IsEmpty]: Start isEmpty. Operand 256 states and 391 transitions. [2024-11-25 05:20:50,854 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:50,854 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:50,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:50,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:50,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:51,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:51,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 257 states and 391 transitions. [2024-11-25 05:20:51,658 INFO L276 IsEmpty]: Start isEmpty. Operand 257 states and 391 transitions. [2024-11-25 05:20:51,658 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:51,658 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:51,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:51,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:51,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:52,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:52,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 258 states and 391 transitions. [2024-11-25 05:20:52,467 INFO L276 IsEmpty]: Start isEmpty. Operand 258 states and 391 transitions. [2024-11-25 05:20:52,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:52,469 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:52,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:52,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:52,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:53,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:53,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 259 states and 391 transitions. [2024-11-25 05:20:53,231 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states and 391 transitions. [2024-11-25 05:20:53,232 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:53,232 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:53,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:53,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:53,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:54,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:54,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 298 states and 470 transitions. [2024-11-25 05:20:54,115 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 470 transitions. [2024-11-25 05:20:54,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:54,118 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:54,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:54,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:54,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:54,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:54,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 299 states and 470 transitions. [2024-11-25 05:20:54,413 INFO L276 IsEmpty]: Start isEmpty. Operand 299 states and 470 transitions. [2024-11-25 05:20:54,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:54,417 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:54,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:54,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:54,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:54,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:54,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 300 states and 470 transitions. [2024-11-25 05:20:54,687 INFO L276 IsEmpty]: Start isEmpty. Operand 300 states and 470 transitions. [2024-11-25 05:20:54,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:54,688 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:54,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:54,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:54,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:54,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:54,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 301 states and 470 transitions. [2024-11-25 05:20:54,933 INFO L276 IsEmpty]: Start isEmpty. Operand 301 states and 470 transitions. [2024-11-25 05:20:54,934 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:54,934 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:54,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:54,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:55,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:55,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:55,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 302 states and 470 transitions. [2024-11-25 05:20:55,190 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 470 transitions. [2024-11-25 05:20:55,191 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:55,192 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:55,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:55,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:55,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:55,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:55,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 303 states and 470 transitions. [2024-11-25 05:20:55,413 INFO L276 IsEmpty]: Start isEmpty. Operand 303 states and 470 transitions. [2024-11-25 05:20:55,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:55,414 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:55,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:55,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:55,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:55,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:55,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 304 states and 470 transitions. [2024-11-25 05:20:55,634 INFO L276 IsEmpty]: Start isEmpty. Operand 304 states and 470 transitions. [2024-11-25 05:20:55,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:55,635 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:55,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:55,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:55,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:55,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:55,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 305 states and 470 transitions. [2024-11-25 05:20:55,865 INFO L276 IsEmpty]: Start isEmpty. Operand 305 states and 470 transitions. [2024-11-25 05:20:55,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:55,866 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:55,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:55,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:55,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:56,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:56,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 306 states and 470 transitions. [2024-11-25 05:20:56,063 INFO L276 IsEmpty]: Start isEmpty. Operand 306 states and 470 transitions. [2024-11-25 05:20:56,063 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:56,064 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:56,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:56,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:56,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:56,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:56,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 307 states and 470 transitions. [2024-11-25 05:20:56,246 INFO L276 IsEmpty]: Start isEmpty. Operand 307 states and 470 transitions. [2024-11-25 05:20:56,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:56,247 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:56,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:56,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:56,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:56,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:56,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 308 states and 470 transitions. [2024-11-25 05:20:56,487 INFO L276 IsEmpty]: Start isEmpty. Operand 308 states and 470 transitions. [2024-11-25 05:20:56,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:56,488 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:56,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:56,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:56,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:56,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:56,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 309 states and 470 transitions. [2024-11-25 05:20:56,699 INFO L276 IsEmpty]: Start isEmpty. Operand 309 states and 470 transitions. [2024-11-25 05:20:56,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:56,700 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:56,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:56,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:56,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:57,170 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:57,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 345 states and 545 transitions. [2024-11-25 05:20:57,175 INFO L276 IsEmpty]: Start isEmpty. Operand 345 states and 545 transitions. [2024-11-25 05:20:57,176 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:57,177 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:57,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:57,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:57,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:57,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:57,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 346 states and 545 transitions. [2024-11-25 05:20:57,366 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 545 transitions. [2024-11-25 05:20:57,367 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:57,367 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:57,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:57,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:57,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:57,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:57,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 347 states and 545 transitions. [2024-11-25 05:20:57,516 INFO L276 IsEmpty]: Start isEmpty. Operand 347 states and 545 transitions. [2024-11-25 05:20:57,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:57,518 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:57,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:57,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:57,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:57,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:57,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 348 states and 545 transitions. [2024-11-25 05:20:57,673 INFO L276 IsEmpty]: Start isEmpty. Operand 348 states and 545 transitions. [2024-11-25 05:20:57,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:57,674 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:57,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:57,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:57,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:57,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:57,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 349 states and 545 transitions. [2024-11-25 05:20:57,850 INFO L276 IsEmpty]: Start isEmpty. Operand 349 states and 545 transitions. [2024-11-25 05:20:57,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:57,852 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:57,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:57,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:57,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:58,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:58,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 350 states and 545 transitions. [2024-11-25 05:20:58,036 INFO L276 IsEmpty]: Start isEmpty. Operand 350 states and 545 transitions. [2024-11-25 05:20:58,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:58,037 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:58,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:58,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:58,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:58,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:58,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 351 states and 545 transitions. [2024-11-25 05:20:58,235 INFO L276 IsEmpty]: Start isEmpty. Operand 351 states and 545 transitions. [2024-11-25 05:20:58,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:58,239 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:58,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:58,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:58,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:58,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:58,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 352 states and 545 transitions. [2024-11-25 05:20:58,394 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 545 transitions. [2024-11-25 05:20:58,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:58,412 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:58,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:58,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:58,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:58,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:58,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 353 states and 545 transitions. [2024-11-25 05:20:58,584 INFO L276 IsEmpty]: Start isEmpty. Operand 353 states and 545 transitions. [2024-11-25 05:20:58,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:58,586 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:58,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:58,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:58,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:58,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:58,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 354 states and 545 transitions. [2024-11-25 05:20:58,751 INFO L276 IsEmpty]: Start isEmpty. Operand 354 states and 545 transitions. [2024-11-25 05:20:58,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:58,752 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:58,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:58,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:58,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:58,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:58,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 355 states and 545 transitions. [2024-11-25 05:20:58,903 INFO L276 IsEmpty]: Start isEmpty. Operand 355 states and 545 transitions. [2024-11-25 05:20:58,904 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:58,904 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:58,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:58,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:59,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:59,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:59,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 388 states and 614 transitions. [2024-11-25 05:20:59,490 INFO L276 IsEmpty]: Start isEmpty. Operand 388 states and 614 transitions. [2024-11-25 05:20:59,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:59,493 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:59,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:59,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:59,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:59,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:59,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 389 states and 614 transitions. [2024-11-25 05:20:59,691 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 614 transitions. [2024-11-25 05:20:59,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:59,692 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:59,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:59,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:59,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:20:59,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:20:59,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 390 states and 614 transitions. [2024-11-25 05:20:59,867 INFO L276 IsEmpty]: Start isEmpty. Operand 390 states and 614 transitions. [2024-11-25 05:20:59,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:20:59,869 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:20:59,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:20:59,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:20:59,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:00,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:00,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 391 states and 614 transitions. [2024-11-25 05:21:00,057 INFO L276 IsEmpty]: Start isEmpty. Operand 391 states and 614 transitions. [2024-11-25 05:21:00,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:00,058 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:00,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:00,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:00,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:00,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:00,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 392 states and 614 transitions. [2024-11-25 05:21:00,240 INFO L276 IsEmpty]: Start isEmpty. Operand 392 states and 614 transitions. [2024-11-25 05:21:00,242 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:00,243 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:00,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:00,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:00,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:00,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:00,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 393 states and 614 transitions. [2024-11-25 05:21:00,414 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 614 transitions. [2024-11-25 05:21:00,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:00,415 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:00,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:00,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:00,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:00,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:00,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 394 states and 614 transitions. [2024-11-25 05:21:00,584 INFO L276 IsEmpty]: Start isEmpty. Operand 394 states and 614 transitions. [2024-11-25 05:21:00,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:00,585 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:00,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:00,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:00,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:00,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:00,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 395 states and 614 transitions. [2024-11-25 05:21:00,760 INFO L276 IsEmpty]: Start isEmpty. Operand 395 states and 614 transitions. [2024-11-25 05:21:00,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:00,761 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:00,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:00,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:00,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:00,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:00,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 396 states and 614 transitions. [2024-11-25 05:21:00,925 INFO L276 IsEmpty]: Start isEmpty. Operand 396 states and 614 transitions. [2024-11-25 05:21:00,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:00,927 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:00,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:00,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:01,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:01,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:01,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 685 states to 416 states and 655 transitions. [2024-11-25 05:21:01,991 INFO L276 IsEmpty]: Start isEmpty. Operand 416 states and 655 transitions. [2024-11-25 05:21:01,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:01,992 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:01,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:02,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:02,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:02,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:02,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 685 states to 417 states and 655 transitions. [2024-11-25 05:21:02,783 INFO L276 IsEmpty]: Start isEmpty. Operand 417 states and 655 transitions. [2024-11-25 05:21:02,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:02,785 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:02,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:02,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:02,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:03,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:03,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 685 states to 418 states and 655 transitions. [2024-11-25 05:21:03,546 INFO L276 IsEmpty]: Start isEmpty. Operand 418 states and 655 transitions. [2024-11-25 05:21:03,547 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:03,547 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:03,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:03,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:03,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:04,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:04,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 685 states to 419 states and 655 transitions. [2024-11-25 05:21:04,333 INFO L276 IsEmpty]: Start isEmpty. Operand 419 states and 655 transitions. [2024-11-25 05:21:04,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:04,334 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:04,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:04,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:04,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:05,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:05,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 685 states to 420 states and 655 transitions. [2024-11-25 05:21:05,130 INFO L276 IsEmpty]: Start isEmpty. Operand 420 states and 655 transitions. [2024-11-25 05:21:05,132 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:05,132 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:05,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:05,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:05,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:05,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:05,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 685 states to 421 states and 655 transitions. [2024-11-25 05:21:05,921 INFO L276 IsEmpty]: Start isEmpty. Operand 421 states and 655 transitions. [2024-11-25 05:21:05,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:05,922 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:05,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:05,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:05,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:06,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:06,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 685 states to 422 states and 655 transitions. [2024-11-25 05:21:06,680 INFO L276 IsEmpty]: Start isEmpty. Operand 422 states and 655 transitions. [2024-11-25 05:21:06,681 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:06,681 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:06,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:06,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:06,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:07,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:07,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 748 states to 449 states and 712 transitions. [2024-11-25 05:21:07,334 INFO L276 IsEmpty]: Start isEmpty. Operand 449 states and 712 transitions. [2024-11-25 05:21:07,335 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:07,336 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:07,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:07,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:07,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:07,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:07,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 748 states to 450 states and 712 transitions. [2024-11-25 05:21:07,480 INFO L276 IsEmpty]: Start isEmpty. Operand 450 states and 712 transitions. [2024-11-25 05:21:07,480 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:07,480 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:07,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:07,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:07,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:07,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:07,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 748 states to 451 states and 712 transitions. [2024-11-25 05:21:07,638 INFO L276 IsEmpty]: Start isEmpty. Operand 451 states and 712 transitions. [2024-11-25 05:21:07,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:07,639 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:07,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:07,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:07,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:07,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:07,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 748 states to 452 states and 712 transitions. [2024-11-25 05:21:07,785 INFO L276 IsEmpty]: Start isEmpty. Operand 452 states and 712 transitions. [2024-11-25 05:21:07,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:07,785 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:07,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:07,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:07,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:07,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:07,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 748 states to 453 states and 712 transitions. [2024-11-25 05:21:07,933 INFO L276 IsEmpty]: Start isEmpty. Operand 453 states and 712 transitions. [2024-11-25 05:21:07,934 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:07,934 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:07,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:07,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:08,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:08,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:08,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 771 states to 461 states and 729 transitions. [2024-11-25 05:21:08,850 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 729 transitions. [2024-11-25 05:21:08,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:08,851 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:08,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:08,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:08,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:09,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:09,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 771 states to 462 states and 729 transitions. [2024-11-25 05:21:09,492 INFO L276 IsEmpty]: Start isEmpty. Operand 462 states and 729 transitions. [2024-11-25 05:21:09,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:09,493 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:09,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:09,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:09,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:10,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:10,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 771 states to 463 states and 729 transitions. [2024-11-25 05:21:10,142 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 729 transitions. [2024-11-25 05:21:10,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:10,143 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:10,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:10,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:10,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:11,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:11,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 810 states to 478 states and 762 transitions. [2024-11-25 05:21:11,026 INFO L276 IsEmpty]: Start isEmpty. Operand 478 states and 762 transitions. [2024-11-25 05:21:11,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:11,027 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:11,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:11,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:11,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:11,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:11,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 810 states to 479 states and 762 transitions. [2024-11-25 05:21:11,171 INFO L276 IsEmpty]: Start isEmpty. Operand 479 states and 762 transitions. [2024-11-25 05:21:11,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:11,174 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:11,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:11,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:11,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:15,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:15,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 934 states to 527 states and 870 transitions. [2024-11-25 05:21:15,093 INFO L276 IsEmpty]: Start isEmpty. Operand 527 states and 870 transitions. [2024-11-25 05:21:15,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:15,094 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:15,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:15,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:15,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:17,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:17,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 961 states to 533 states and 888 transitions. [2024-11-25 05:21:17,224 INFO L276 IsEmpty]: Start isEmpty. Operand 533 states and 888 transitions. [2024-11-25 05:21:17,225 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:17,225 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:17,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:17,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:17,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:20,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:20,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 545 states and 925 transitions. [2024-11-25 05:21:20,418 INFO L276 IsEmpty]: Start isEmpty. Operand 545 states and 925 transitions. [2024-11-25 05:21:20,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:20,419 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:20,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:20,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:20,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:21,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:21,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1013 states to 548 states and 931 transitions. [2024-11-25 05:21:21,378 INFO L276 IsEmpty]: Start isEmpty. Operand 548 states and 931 transitions. [2024-11-25 05:21:21,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:21,379 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:21,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:21,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:21,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:22,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:22,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1025 states to 554 states and 943 transitions. [2024-11-25 05:21:22,640 INFO L276 IsEmpty]: Start isEmpty. Operand 554 states and 943 transitions. [2024-11-25 05:21:22,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:22,641 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:22,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:22,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:22,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:23,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:23,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1027 states to 555 states and 945 transitions. [2024-11-25 05:21:23,140 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 945 transitions. [2024-11-25 05:21:23,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:23,141 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:23,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:23,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:23,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:30,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:30,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1085 states to 572 states and 994 transitions. [2024-11-25 05:21:30,561 INFO L276 IsEmpty]: Start isEmpty. Operand 572 states and 994 transitions. [2024-11-25 05:21:30,562 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:30,562 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:30,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:30,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:30,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:33,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:33,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1088 states to 573 states and 997 transitions. [2024-11-25 05:21:33,463 INFO L276 IsEmpty]: Start isEmpty. Operand 573 states and 997 transitions. [2024-11-25 05:21:33,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:33,463 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:33,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:33,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:33,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:36,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:36,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1091 states to 575 states and 1000 transitions. [2024-11-25 05:21:36,506 INFO L276 IsEmpty]: Start isEmpty. Operand 575 states and 1000 transitions. [2024-11-25 05:21:36,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:36,506 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:36,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:36,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:36,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:39,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:39,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 576 states and 1003 transitions. [2024-11-25 05:21:39,414 INFO L276 IsEmpty]: Start isEmpty. Operand 576 states and 1003 transitions. [2024-11-25 05:21:39,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:39,415 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:39,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:39,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:39,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:42,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:42,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1096 states to 577 states and 1005 transitions. [2024-11-25 05:21:42,271 INFO L276 IsEmpty]: Start isEmpty. Operand 577 states and 1005 transitions. [2024-11-25 05:21:42,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:42,271 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:42,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:42,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:42,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:46,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:46,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1109 states to 583 states and 1018 transitions. [2024-11-25 05:21:46,194 INFO L276 IsEmpty]: Start isEmpty. Operand 583 states and 1018 transitions. [2024-11-25 05:21:46,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:46,194 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:46,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:46,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:46,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:49,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:49,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1115 states to 586 states and 1024 transitions. [2024-11-25 05:21:49,030 INFO L276 IsEmpty]: Start isEmpty. Operand 586 states and 1024 transitions. [2024-11-25 05:21:49,030 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:49,030 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:49,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:49,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:49,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:51,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:51,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1117 states to 587 states and 1026 transitions. [2024-11-25 05:21:51,416 INFO L276 IsEmpty]: Start isEmpty. Operand 587 states and 1026 transitions. [2024-11-25 05:21:51,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:51,417 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:51,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:51,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:51,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:21:54,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:21:54,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1123 states to 590 states and 1032 transitions. [2024-11-25 05:21:54,266 INFO L276 IsEmpty]: Start isEmpty. Operand 590 states and 1032 transitions. [2024-11-25 05:21:54,267 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:21:54,267 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:21:54,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:21:54,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:21:54,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:01,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:01,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1199 states to 614 states and 1099 transitions. [2024-11-25 05:22:01,363 INFO L276 IsEmpty]: Start isEmpty. Operand 614 states and 1099 transitions. [2024-11-25 05:22:01,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:01,363 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:01,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:01,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:01,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:02,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:02,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1205 states to 617 states and 1105 transitions. [2024-11-25 05:22:02,659 INFO L276 IsEmpty]: Start isEmpty. Operand 617 states and 1105 transitions. [2024-11-25 05:22:02,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:02,660 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:02,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:02,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:02,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:04,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:04,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1225 states to 626 states and 1125 transitions. [2024-11-25 05:22:04,908 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 1125 transitions. [2024-11-25 05:22:04,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:04,909 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:04,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:04,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:04,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:05,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:05,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1227 states to 627 states and 1127 transitions. [2024-11-25 05:22:05,584 INFO L276 IsEmpty]: Start isEmpty. Operand 627 states and 1127 transitions. [2024-11-25 05:22:05,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:05,585 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:05,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:05,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:05,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:06,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:06,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1229 states to 628 states and 1129 transitions. [2024-11-25 05:22:06,360 INFO L276 IsEmpty]: Start isEmpty. Operand 628 states and 1129 transitions. [2024-11-25 05:22:06,360 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:06,360 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:06,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:06,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:06,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:06,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:06,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1231 states to 629 states and 1131 transitions. [2024-11-25 05:22:06,453 INFO L276 IsEmpty]: Start isEmpty. Operand 629 states and 1131 transitions. [2024-11-25 05:22:06,454 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:06,454 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:06,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:06,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:06,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:08,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:08,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1249 states to 638 states and 1149 transitions. [2024-11-25 05:22:08,066 INFO L276 IsEmpty]: Start isEmpty. Operand 638 states and 1149 transitions. [2024-11-25 05:22:08,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:08,066 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:08,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:08,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:08,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:17,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:17,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1337 states to 668 states and 1228 transitions. [2024-11-25 05:22:17,308 INFO L276 IsEmpty]: Start isEmpty. Operand 668 states and 1228 transitions. [2024-11-25 05:22:17,309 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:17,309 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:17,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:17,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:17,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:18,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:18,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1340 states to 669 states and 1231 transitions. [2024-11-25 05:22:18,186 INFO L276 IsEmpty]: Start isEmpty. Operand 669 states and 1231 transitions. [2024-11-25 05:22:18,187 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:18,187 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:18,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:18,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:18,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:19,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:19,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1348 states to 672 states and 1239 transitions. [2024-11-25 05:22:19,474 INFO L276 IsEmpty]: Start isEmpty. Operand 672 states and 1239 transitions. [2024-11-25 05:22:19,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:19,475 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:19,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:19,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:19,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:22,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:22,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1376 states to 684 states and 1267 transitions. [2024-11-25 05:22:22,855 INFO L276 IsEmpty]: Start isEmpty. Operand 684 states and 1267 transitions. [2024-11-25 05:22:22,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:22,856 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:22,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:22,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:22,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:26,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:26,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1401 states to 695 states and 1292 transitions. [2024-11-25 05:22:26,650 INFO L276 IsEmpty]: Start isEmpty. Operand 695 states and 1292 transitions. [2024-11-25 05:22:26,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:26,651 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:26,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:26,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:26,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:27,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:27,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1403 states to 696 states and 1294 transitions. [2024-11-25 05:22:27,419 INFO L276 IsEmpty]: Start isEmpty. Operand 696 states and 1294 transitions. [2024-11-25 05:22:27,420 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:27,420 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:27,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:27,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:27,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:28,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:28,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1405 states to 697 states and 1296 transitions. [2024-11-25 05:22:28,252 INFO L276 IsEmpty]: Start isEmpty. Operand 697 states and 1296 transitions. [2024-11-25 05:22:28,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:28,252 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:28,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:28,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:28,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:28,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:28,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1407 states to 698 states and 1298 transitions. [2024-11-25 05:22:28,393 INFO L276 IsEmpty]: Start isEmpty. Operand 698 states and 1298 transitions. [2024-11-25 05:22:28,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:28,395 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:28,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:28,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:28,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:29,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:29,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1409 states to 699 states and 1300 transitions. [2024-11-25 05:22:29,223 INFO L276 IsEmpty]: Start isEmpty. Operand 699 states and 1300 transitions. [2024-11-25 05:22:29,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:29,224 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:29,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:29,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:29,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:29,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:29,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1411 states to 700 states and 1302 transitions. [2024-11-25 05:22:29,325 INFO L276 IsEmpty]: Start isEmpty. Operand 700 states and 1302 transitions. [2024-11-25 05:22:29,326 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:29,326 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:29,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:29,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:29,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:33,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:33,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1421 states to 706 states and 1302 transitions. [2024-11-25 05:22:33,862 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 1302 transitions. [2024-11-25 05:22:33,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:33,862 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:33,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:33,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:33,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:35,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:35,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1411 states to 706 states and 1292 transitions. [2024-11-25 05:22:35,974 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 1292 transitions. [2024-11-25 05:22:35,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:35,975 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:35,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:35,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:36,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:36,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:36,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1407 states to 706 states and 1288 transitions. [2024-11-25 05:22:36,492 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 1288 transitions. [2024-11-25 05:22:36,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:36,493 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:36,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:36,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:36,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:36,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:36,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1403 states to 706 states and 1284 transitions. [2024-11-25 05:22:36,946 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 1284 transitions. [2024-11-25 05:22:36,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-11-25 05:22:36,947 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:36,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:36,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:37,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:37,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:37,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1399 states to 706 states and 1280 transitions. [2024-11-25 05:22:37,356 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 1280 transitions. [2024-11-25 05:22:37,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-25 05:22:37,357 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:37,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:37,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:37,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:37,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:37,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1390 states to 701 states and 1271 transitions. [2024-11-25 05:22:37,734 INFO L276 IsEmpty]: Start isEmpty. Operand 701 states and 1271 transitions. [2024-11-25 05:22:37,735 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-25 05:22:37,735 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:37,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:37,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:37,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:38,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:38,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1386 states to 699 states and 1267 transitions. [2024-11-25 05:22:38,085 INFO L276 IsEmpty]: Start isEmpty. Operand 699 states and 1267 transitions. [2024-11-25 05:22:38,085 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-25 05:22:38,085 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:38,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:38,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:38,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:38,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:38,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1382 states to 697 states and 1263 transitions. [2024-11-25 05:22:38,401 INFO L276 IsEmpty]: Start isEmpty. Operand 697 states and 1263 transitions. [2024-11-25 05:22:38,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-25 05:22:38,402 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:38,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:38,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:38,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:38,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:38,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1383 states to 698 states and 1264 transitions. [2024-11-25 05:22:38,770 INFO L276 IsEmpty]: Start isEmpty. Operand 698 states and 1264 transitions. [2024-11-25 05:22:38,771 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-25 05:22:38,771 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:38,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:38,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:38,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:39,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:39,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1384 states to 699 states and 1265 transitions. [2024-11-25 05:22:39,689 INFO L276 IsEmpty]: Start isEmpty. Operand 699 states and 1265 transitions. [2024-11-25 05:22:39,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-25 05:22:39,690 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:39,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:39,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:39,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:40,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:40,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1385 states to 700 states and 1266 transitions. [2024-11-25 05:22:40,097 INFO L276 IsEmpty]: Start isEmpty. Operand 700 states and 1266 transitions. [2024-11-25 05:22:40,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-25 05:22:40,098 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:40,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:40,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:40,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:40,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:40,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1386 states to 701 states and 1267 transitions. [2024-11-25 05:22:40,952 INFO L276 IsEmpty]: Start isEmpty. Operand 701 states and 1267 transitions. [2024-11-25 05:22:40,953 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-25 05:22:40,953 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:40,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:40,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:41,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:41,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:41,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1387 states to 702 states and 1268 transitions. [2024-11-25 05:22:41,377 INFO L276 IsEmpty]: Start isEmpty. Operand 702 states and 1268 transitions. [2024-11-25 05:22:41,378 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-25 05:22:41,378 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:41,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:41,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:41,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:41,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:41,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1388 states to 703 states and 1269 transitions. [2024-11-25 05:22:41,847 INFO L276 IsEmpty]: Start isEmpty. Operand 703 states and 1269 transitions. [2024-11-25 05:22:41,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-25 05:22:41,848 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:41,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:41,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:41,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:42,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:42,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1389 states to 704 states and 1270 transitions. [2024-11-25 05:22:42,377 INFO L276 IsEmpty]: Start isEmpty. Operand 704 states and 1270 transitions. [2024-11-25 05:22:42,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-25 05:22:42,378 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:42,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:42,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:42,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:45,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:45,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1390 states to 705 states and 1271 transitions. [2024-11-25 05:22:45,249 INFO L276 IsEmpty]: Start isEmpty. Operand 705 states and 1271 transitions. [2024-11-25 05:22:45,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-25 05:22:45,250 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:45,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:45,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:45,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:45,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:45,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1391 states to 706 states and 1272 transitions. [2024-11-25 05:22:45,743 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 1272 transitions. [2024-11-25 05:22:45,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-25 05:22:45,744 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:45,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:45,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 05:22:45,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 05:22:45,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 05:22:45,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1337 states to 676 states and 1219 transitions. [2024-11-25 05:22:45,909 INFO L276 IsEmpty]: Start isEmpty. Operand 676 states and 1219 transitions. [2024-11-25 05:22:45,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-11-25 05:22:45,910 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 05:22:45,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 05:22:45,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-25 05:22:45,942 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-25 05:22:45,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-25 05:22:46,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-25 05:22:46,303 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-25 05:22:46,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-25 05:22:46,558 WARN L473 CodeCheckObserver]: This program is UNSAFE, Check terminated with 114 iterations. [2024-11-25 05:22:46,834 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 25.11 05:22:46 ImpRootNode [2024-11-25 05:22:46,838 INFO L131 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2024-11-25 05:22:46,838 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-25 05:22:46,841 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-25 05:22:46,841 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-25 05:22:46,842 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 05:20:39" (3/4) ... [2024-11-25 05:22:46,843 INFO L140 WitnessPrinter]: Generating witness for reachability counterexample [2024-11-25 05:22:47,088 INFO L129 tionWitnessGenerator]: Generated YAML witness of length 146. [2024-11-25 05:22:47,280 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/witness.graphml [2024-11-25 05:22:47,280 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/witness.yml [2024-11-25 05:22:47,281 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-25 05:22:47,282 INFO L158 Benchmark]: Toolchain (without parser) took 131451.47ms. Allocated memory was 117.4MB in the beginning and 880.8MB in the end (delta: 763.4MB). Free memory was 90.8MB in the beginning and 594.0MB in the end (delta: -503.1MB). Peak memory consumption was 260.9MB. Max. memory is 16.1GB. [2024-11-25 05:22:47,284 INFO L158 Benchmark]: CDTParser took 0.57ms. Allocated memory is still 83.9MB. Free memory is still 40.6MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-25 05:22:47,284 INFO L158 Benchmark]: CACSL2BoogieTranslator took 827.63ms. Allocated memory is still 117.4MB. Free memory was 90.8MB in the beginning and 68.4MB in the end (delta: 22.4MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-25 05:22:47,285 INFO L158 Benchmark]: Boogie Procedure Inliner took 150.30ms. Allocated memory is still 117.4MB. Free memory was 68.4MB in the beginning and 64.6MB in the end (delta: 3.8MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-25 05:22:47,285 INFO L158 Benchmark]: Boogie Preprocessor took 97.55ms. Allocated memory is still 117.4MB. Free memory was 64.6MB in the beginning and 61.1MB in the end (delta: 3.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-25 05:22:47,285 INFO L158 Benchmark]: RCFGBuilder took 2743.64ms. Allocated memory is still 117.4MB. Free memory was 60.8MB in the beginning and 53.2MB in the end (delta: 7.6MB). Peak memory consumption was 38.5MB. Max. memory is 16.1GB. [2024-11-25 05:22:47,287 INFO L158 Benchmark]: CodeCheck took 127181.25ms. Allocated memory was 117.4MB in the beginning and 880.8MB in the end (delta: 763.4MB). Free memory was 53.2MB in the beginning and 627.5MB in the end (delta: -574.3MB). Peak memory consumption was 191.0MB. Max. memory is 16.1GB. [2024-11-25 05:22:47,288 INFO L158 Benchmark]: Witness Printer took 442.37ms. Allocated memory is still 880.8MB. Free memory was 627.5MB in the beginning and 594.0MB in the end (delta: 33.6MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2024-11-25 05:22:47,290 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 7 procedures, 205 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 126.9s, OverallIterations: 114, TraceHistogramMax: 0, PathProgramHistogramMax: 0, EmptinessCheckTime: 0.0s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 100859 SdHoareTripleChecker+Valid, 119.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 86649 mSDsluCounter, 176567 SdHoareTripleChecker+Invalid, 108.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 148853 mSDsCounter, 8690 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 60532 IncrementalHoareTripleChecker+Invalid, 69222 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 8690 mSolverCounterUnsat, 27714 mSDtfsCounter, 60532 mSolverCounterSat, 4.9s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 75228 GetRequests, 68085 SyntacticMatches, 6563 SemanticMatches, 580 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 382507 ImplicationChecksByTransitivity, 109.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, InterpolantAutomatonStates: 0, traceCheckStatistics: 0.7s SsaConstructionTime, 1.0s SatisfiabilityAnalysisTime, 10.4s InterpolantComputationTime, 7539 NumberOfCodeBlocks, 7539 NumberOfCodeBlocksAsserted, 114 NumberOfCheckSat, 7358 ConstructedInterpolants, 0 QuantifiedInterpolants, 19009 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 113 InterpolantComputations, 113 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int t8_pc = 0; [L34] int t9_pc = 0; [L35] int t10_pc = 0; [L36] int t11_pc = 0; [L37] int t12_pc = 0; [L38] int t13_pc = 0; [L39] int m_st ; [L40] int t1_st ; [L41] int t2_st ; [L42] int t3_st ; [L43] int t4_st ; [L44] int t5_st ; [L45] int t6_st ; [L46] int t7_st ; [L47] int t8_st ; [L48] int t9_st ; [L49] int t10_st ; [L50] int t11_st ; [L51] int t12_st ; [L52] int t13_st ; [L53] int m_i ; [L54] int t1_i ; [L55] int t2_i ; [L56] int t3_i ; [L57] int t4_i ; [L58] int t5_i ; [L59] int t6_i ; [L60] int t7_i ; [L61] int t8_i ; [L62] int t9_i ; [L63] int t10_i ; [L64] int t11_i ; [L65] int t12_i ; [L66] int t13_i ; [L67] int M_E = 2; [L68] int T1_E = 2; [L69] int T2_E = 2; [L70] int T3_E = 2; [L71] int T4_E = 2; [L72] int T5_E = 2; [L73] int T6_E = 2; [L74] int T7_E = 2; [L75] int T8_E = 2; [L76] int T9_E = 2; [L77] int T10_E = 2; [L78] int T11_E = 2; [L79] int T12_E = 2; [L80] int T13_E = 2; [L81] int E_1 = 2; [L82] int E_2 = 2; [L83] int E_3 = 2; [L84] int E_4 = 2; [L85] int E_5 = 2; [L86] int E_6 = 2; [L87] int E_7 = 2; [L88] int E_8 = 2; [L89] int E_9 = 2; [L90] int E_10 = 2; [L91] int E_11 = 2; [L92] int E_12 = 2; [L93] int E_13 = 2; [L1937] int __retres1 ; [L1941] CALL init_model() [L1840] m_i = 1 [L1841] t1_i = 1 [L1842] t2_i = 1 [L1843] t3_i = 1 [L1844] t4_i = 1 [L1845] t5_i = 1 [L1846] t6_i = 1 [L1847] t7_i = 1 [L1848] t8_i = 1 [L1849] t9_i = 1 [L1850] t10_i = 1 [L1851] t11_i = 1 [L1852] t12_i = 1 [L1853] t13_i = 1 [L1941] RET init_model() [L1942] CALL start_simulation() [L1878] int kernel_st ; [L1879] int tmp ; [L1880] int tmp___0 ; [L1884] kernel_st = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1885] FCALL update_channels() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1886] CALL init_threads() [L881] COND TRUE m_i == 1 [L882] m_st = 0 [L886] COND TRUE t1_i == 1 [L887] t1_st = 0 [L891] COND TRUE t2_i == 1 [L892] t2_st = 0 [L896] COND TRUE t3_i == 1 [L897] t3_st = 0 [L901] COND TRUE t4_i == 1 [L902] t4_st = 0 [L906] COND TRUE t5_i == 1 [L907] t5_st = 0 [L911] COND TRUE t6_i == 1 [L912] t6_st = 0 [L916] COND TRUE t7_i == 1 [L917] t7_st = 0 [L921] COND TRUE t8_i == 1 [L922] t8_st = 0 [L926] COND TRUE t9_i == 1 [L927] t9_st = 0 [L931] COND TRUE t10_i == 1 [L932] t10_st = 0 [L936] COND TRUE t11_i == 1 [L937] t11_st = 0 [L941] COND TRUE t12_i == 1 [L942] t12_st = 0 [L946] COND TRUE t13_i == 1 [L947] t13_st = 0 [L1886] RET init_threads() [L1887] CALL fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1258] COND FALSE !(M_E == 0) [L1263] COND FALSE !(T1_E == 0) [L1268] COND FALSE !(T2_E == 0) [L1273] COND FALSE !(T3_E == 0) [L1278] COND FALSE !(T4_E == 0) [L1283] COND FALSE !(T5_E == 0) [L1288] COND FALSE !(T6_E == 0) [L1293] COND FALSE !(T7_E == 0) [L1298] COND FALSE !(T8_E == 0) [L1303] COND FALSE !(T9_E == 0) [L1308] COND FALSE !(T10_E == 0) [L1313] COND FALSE !(T11_E == 0) [L1318] COND FALSE !(T12_E == 0) [L1323] COND FALSE !(T13_E == 0) [L1328] COND FALSE !(E_1 == 0) [L1333] COND FALSE !(E_2 == 0) [L1338] COND FALSE !(E_3 == 0) [L1343] COND FALSE !(E_4 == 0) [L1348] COND FALSE !(E_5 == 0) [L1353] COND FALSE !(E_6 == 0) [L1358] COND FALSE !(E_7 == 0) [L1363] COND FALSE !(E_8 == 0) [L1368] COND FALSE !(E_9 == 0) [L1373] COND FALSE !(E_10 == 0) [L1378] COND FALSE !(E_11 == 0) [L1383] COND FALSE !(E_12 == 0) [L1388] COND FALSE !(E_13 == 0) [L1887] RET fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1888] CALL activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1541] int tmp ; [L1542] int tmp___0 ; [L1543] int tmp___1 ; [L1544] int tmp___2 ; [L1545] int tmp___3 ; [L1546] int tmp___4 ; [L1547] int tmp___5 ; [L1548] int tmp___6 ; [L1549] int tmp___7 ; [L1550] int tmp___8 ; [L1551] int tmp___9 ; [L1552] int tmp___10 ; [L1553] int tmp___11 ; [L1554] int tmp___12 ; [L1558] CALL, EXPR is_master_triggered() [L604] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L607] COND FALSE !(m_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L617] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L619] return (__retres1); [L1558] RET, EXPR is_master_triggered() [L1558] tmp = is_master_triggered() [L1560] COND FALSE !(\read(tmp)) [L1566] CALL, EXPR is_transmit1_triggered() [L623] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L626] COND FALSE !(t1_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L636] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L638] return (__retres1); [L1566] RET, EXPR is_transmit1_triggered() [L1566] tmp___0 = is_transmit1_triggered() [L1568] COND FALSE !(\read(tmp___0)) [L1574] CALL, EXPR is_transmit2_triggered() [L642] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L645] COND FALSE !(t2_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L655] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L657] return (__retres1); [L1574] RET, EXPR is_transmit2_triggered() [L1574] tmp___1 = is_transmit2_triggered() [L1576] COND FALSE !(\read(tmp___1)) [L1582] CALL, EXPR is_transmit3_triggered() [L661] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L664] COND FALSE !(t3_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L674] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L676] return (__retres1); [L1582] RET, EXPR is_transmit3_triggered() [L1582] tmp___2 = is_transmit3_triggered() [L1584] COND FALSE !(\read(tmp___2)) [L1590] CALL, EXPR is_transmit4_triggered() [L680] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L683] COND FALSE !(t4_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L693] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L695] return (__retres1); [L1590] RET, EXPR is_transmit4_triggered() [L1590] tmp___3 = is_transmit4_triggered() [L1592] COND FALSE !(\read(tmp___3)) [L1598] CALL, EXPR is_transmit5_triggered() [L699] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L702] COND FALSE !(t5_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L712] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L714] return (__retres1); [L1598] RET, EXPR is_transmit5_triggered() [L1598] tmp___4 = is_transmit5_triggered() [L1600] COND FALSE !(\read(tmp___4)) [L1606] CALL, EXPR is_transmit6_triggered() [L718] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L721] COND FALSE !(t6_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L731] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L733] return (__retres1); [L1606] RET, EXPR is_transmit6_triggered() [L1606] tmp___5 = is_transmit6_triggered() [L1608] COND FALSE !(\read(tmp___5)) [L1614] CALL, EXPR is_transmit7_triggered() [L737] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L740] COND FALSE !(t7_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L750] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L752] return (__retres1); [L1614] RET, EXPR is_transmit7_triggered() [L1614] tmp___6 = is_transmit7_triggered() [L1616] COND FALSE !(\read(tmp___6)) [L1622] CALL, EXPR is_transmit8_triggered() [L756] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L759] COND FALSE !(t8_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L769] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L771] return (__retres1); [L1622] RET, EXPR is_transmit8_triggered() [L1622] tmp___7 = is_transmit8_triggered() [L1624] COND FALSE !(\read(tmp___7)) [L1630] CALL, EXPR is_transmit9_triggered() [L775] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L778] COND FALSE !(t9_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L788] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L790] return (__retres1); [L1630] RET, EXPR is_transmit9_triggered() [L1630] tmp___8 = is_transmit9_triggered() [L1632] COND FALSE !(\read(tmp___8)) [L1638] CALL, EXPR is_transmit10_triggered() [L794] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L797] COND FALSE !(t10_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L807] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L809] return (__retres1); [L1638] RET, EXPR is_transmit10_triggered() [L1638] tmp___9 = is_transmit10_triggered() [L1640] COND FALSE !(\read(tmp___9)) [L1646] CALL, EXPR is_transmit11_triggered() [L813] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L816] COND FALSE !(t11_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L826] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L828] return (__retres1); [L1646] RET, EXPR is_transmit11_triggered() [L1646] tmp___10 = is_transmit11_triggered() [L1648] COND FALSE !(\read(tmp___10)) [L1654] CALL, EXPR is_transmit12_triggered() [L832] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L835] COND FALSE !(t12_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L845] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L847] return (__retres1); [L1654] RET, EXPR is_transmit12_triggered() [L1654] tmp___11 = is_transmit12_triggered() [L1656] COND FALSE !(\read(tmp___11)) [L1662] CALL, EXPR is_transmit13_triggered() [L851] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L854] COND FALSE !(t13_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L864] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L866] return (__retres1); [L1662] RET, EXPR is_transmit13_triggered() [L1662] tmp___12 = is_transmit13_triggered() [L1664] COND FALSE !(\read(tmp___12)) [L1888] RET activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1889] CALL reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1401] COND FALSE !(M_E == 1) [L1406] COND FALSE !(T1_E == 1) [L1411] COND FALSE !(T2_E == 1) [L1416] COND FALSE !(T3_E == 1) [L1421] COND FALSE !(T4_E == 1) [L1426] COND FALSE !(T5_E == 1) [L1431] COND FALSE !(T6_E == 1) [L1436] COND FALSE !(T7_E == 1) [L1441] COND FALSE !(T8_E == 1) [L1446] COND FALSE !(T9_E == 1) [L1451] COND FALSE !(T10_E == 1) [L1456] COND FALSE !(T11_E == 1) [L1461] COND FALSE !(T12_E == 1) [L1466] COND FALSE !(T13_E == 1) [L1471] COND FALSE !(E_1 == 1) [L1476] COND FALSE !(E_2 == 1) [L1481] COND FALSE !(E_3 == 1) [L1486] COND FALSE !(E_4 == 1) [L1491] COND FALSE !(E_5 == 1) [L1496] COND FALSE !(E_6 == 1) [L1501] COND FALSE !(E_7 == 1) [L1506] COND FALSE !(E_8 == 1) [L1511] COND FALSE !(E_9 == 1) [L1516] COND FALSE !(E_10 == 1) [L1521] COND FALSE !(E_11 == 1) [L1526] COND FALSE !(E_12 == 1) [L1531] COND FALSE !(E_13 == 1) [L1889] RET reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1895] kernel_st = 1 [L1896] CALL eval() [L1037] int tmp ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1044] CALL, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L956] int __retres1 ; [L959] COND TRUE m_st == 0 [L960] __retres1 = 1 [L1032] return (__retres1); [L1044] RET, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1044] tmp = exists_runnable_thread() [L1046] COND TRUE \read(tmp) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1051] COND TRUE m_st == 0 [L1052] int tmp_ndt_1; [L1053] tmp_ndt_1 = __VERIFIER_nondet_int() [L1054] COND FALSE !(\read(tmp_ndt_1)) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1065] COND TRUE t1_st == 0 [L1066] int tmp_ndt_2; [L1067] tmp_ndt_2 = __VERIFIER_nondet_int() [L1068] COND FALSE !(\read(tmp_ndt_2)) [L1074] CALL error() [L21] reach_error() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.57ms. Allocated memory is still 83.9MB. Free memory is still 40.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 827.63ms. Allocated memory is still 117.4MB. Free memory was 90.8MB in the beginning and 68.4MB in the end (delta: 22.4MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 150.30ms. Allocated memory is still 117.4MB. Free memory was 68.4MB in the beginning and 64.6MB in the end (delta: 3.8MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 97.55ms. Allocated memory is still 117.4MB. Free memory was 64.6MB in the beginning and 61.1MB in the end (delta: 3.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 2743.64ms. Allocated memory is still 117.4MB. Free memory was 60.8MB in the beginning and 53.2MB in the end (delta: 7.6MB). Peak memory consumption was 38.5MB. Max. memory is 16.1GB. * CodeCheck took 127181.25ms. Allocated memory was 117.4MB in the beginning and 880.8MB in the end (delta: 763.4MB). Free memory was 53.2MB in the beginning and 627.5MB in the end (delta: -574.3MB). Peak memory consumption was 191.0MB. Max. memory is 16.1GB. * Witness Printer took 442.37ms. Allocated memory is still 880.8MB. Free memory was 627.5MB in the beginning and 594.0MB in the end (delta: 33.6MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. RESULT: Ultimate proved your program to be incorrect! [2024-11-25 05:22:47,328 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_61adda64-15bd-4c05-b503-b60a08911e9d/bin/ukojak-verify-ENZ3QT5qd3/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE