./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/config/KojakReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.16.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/config/svcomp-Reach-32bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3 --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-11-25 04:35:02,956 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-25 04:35:03,022 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/config/svcomp-Reach-32bit-Kojak_Default.epf [2024-11-25 04:35:03,028 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-25 04:35:03,028 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck.Interpolating solver [2024-11-25 04:35:03,072 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-25 04:35:03,076 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-25 04:35:03,076 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ALWAYS [2024-11-25 04:35:03,076 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-25 04:35:03,076 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-25 04:35:03,077 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-25 04:35:03,077 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-25 04:35:03,077 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-25 04:35:03,077 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-25 04:35:03,077 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-25 04:35:03,077 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-25 04:35:03,077 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-25 04:35:03,077 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-25 04:35:03,078 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-25 04:35:03,078 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-25 04:35:03,078 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-25 04:35:03,078 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-25 04:35:03,078 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-25 04:35:03,078 INFO L151 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2024-11-25 04:35:03,078 INFO L153 SettingsManager]: * Timeout in seconds=1000000 [2024-11-25 04:35:03,079 INFO L153 SettingsManager]: * Theory for external solver=ALL [2024-11-25 04:35:03,079 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-25 04:35:03,079 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2024-11-25 04:35:03,079 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-25 04:35:03,079 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-25 04:35:03,079 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-25 04:35:03,082 INFO L153 SettingsManager]: * Trace refinement strategy=PENGUIN [2024-11-25 04:35:03,082 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-25 04:35:03,082 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 [2024-11-25 04:35:03,418 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-25 04:35:03,431 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-25 04:35:03,438 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-25 04:35:03,440 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-25 04:35:03,440 INFO L274 PluginConnector]: CDTParser initialized [2024-11-25 04:35:03,442 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/../../sv-benchmarks/c/systemc/transmitter.16.cil.c [2024-11-25 04:35:06,571 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/data/9fdcabada/14a05814fcf140849fc2e49aa2aca4d0/FLAGb84b3ac94 [2024-11-25 04:35:06,899 INFO L384 CDTParser]: Found 1 translation units. [2024-11-25 04:35:06,899 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/sv-benchmarks/c/systemc/transmitter.16.cil.c [2024-11-25 04:35:06,917 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/data/9fdcabada/14a05814fcf140849fc2e49aa2aca4d0/FLAGb84b3ac94 [2024-11-25 04:35:06,935 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/data/9fdcabada/14a05814fcf140849fc2e49aa2aca4d0 [2024-11-25 04:35:06,937 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-25 04:35:06,940 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-25 04:35:06,941 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-25 04:35:06,941 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-25 04:35:06,947 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-25 04:35:06,947 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 04:35:06" (1/1) ... [2024-11-25 04:35:06,948 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@cb3008f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 04:35:06, skipping insertion in model container [2024-11-25 04:35:06,949 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.11 04:35:06" (1/1) ... [2024-11-25 04:35:07,013 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-25 04:35:07,184 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2024-11-25 04:35:07,407 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-25 04:35:07,432 INFO L200 MainTranslator]: Completed pre-run [2024-11-25 04:35:07,444 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2024-11-25 04:35:07,528 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-25 04:35:07,552 INFO L204 MainTranslator]: Completed translation [2024-11-25 04:35:07,553 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 04:35:07 WrapperNode [2024-11-25 04:35:07,553 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-25 04:35:07,554 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-25 04:35:07,554 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-25 04:35:07,555 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-25 04:35:07,563 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 04:35:07" (1/1) ... [2024-11-25 04:35:07,576 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 04:35:07" (1/1) ... [2024-11-25 04:35:07,644 INFO L138 Inliner]: procedures = 56, calls = 71, calls flagged for inlining = 40, calls inlined = 40, statements flattened = 956 [2024-11-25 04:35:07,645 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-25 04:35:07,646 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-25 04:35:07,649 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-25 04:35:07,650 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-25 04:35:07,664 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 04:35:07" (1/1) ... [2024-11-25 04:35:07,664 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 04:35:07" (1/1) ... [2024-11-25 04:35:07,676 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 04:35:07" (1/1) ... [2024-11-25 04:35:07,676 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 04:35:07" (1/1) ... [2024-11-25 04:35:07,695 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 04:35:07" (1/1) ... [2024-11-25 04:35:07,701 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 04:35:07" (1/1) ... [2024-11-25 04:35:07,731 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 04:35:07" (1/1) ... [2024-11-25 04:35:07,734 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 04:35:07" (1/1) ... [2024-11-25 04:35:07,739 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 04:35:07" (1/1) ... [2024-11-25 04:35:07,755 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-25 04:35:07,756 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-25 04:35:07,756 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-25 04:35:07,756 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-25 04:35:07,757 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.11 04:35:07" (1/1) ... [2024-11-25 04:35:07,773 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2024-11-25 04:35:07,792 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/z3 [2024-11-25 04:35:07,810 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) [2024-11-25 04:35:07,816 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Waiting until timeout for monitored process [2024-11-25 04:35:07,853 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-25 04:35:07,853 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2024-11-25 04:35:07,853 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2024-11-25 04:35:07,853 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2024-11-25 04:35:07,853 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2024-11-25 04:35:07,853 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2024-11-25 04:35:07,854 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2024-11-25 04:35:07,854 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2024-11-25 04:35:07,854 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2024-11-25 04:35:07,854 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2024-11-25 04:35:07,854 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2024-11-25 04:35:07,854 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2024-11-25 04:35:07,854 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2024-11-25 04:35:07,854 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2024-11-25 04:35:07,854 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-25 04:35:07,854 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-25 04:35:08,010 INFO L234 CfgBuilder]: Building ICFG [2024-11-25 04:35:08,014 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-25 04:35:09,428 INFO L? ?]: Removed 109 outVars from TransFormulas that were not future-live. [2024-11-25 04:35:09,428 INFO L283 CfgBuilder]: Performing block encoding [2024-11-25 04:35:10,339 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-25 04:35:10,339 INFO L312 CfgBuilder]: Removed 36 assume(true) statements. [2024-11-25 04:35:10,339 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 04:35:10 BoogieIcfgContainer [2024-11-25 04:35:10,339 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-25 04:35:10,364 INFO L112 PluginConnector]: ------------------------CodeCheck---------------------------- [2024-11-25 04:35:10,364 INFO L270 PluginConnector]: Initializing CodeCheck... [2024-11-25 04:35:10,376 INFO L274 PluginConnector]: CodeCheck initialized [2024-11-25 04:35:10,376 INFO L184 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 04:35:10" (1/1) ... [2024-11-25 04:35:10,388 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-25 04:35:10,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:10,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 209 states and 317 transitions. [2024-11-25 04:35:10,477 INFO L276 IsEmpty]: Start isEmpty. Operand 209 states and 317 transitions. [2024-11-25 04:35:10,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:10,488 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:10,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:10,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:11,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:12,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:12,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 253 states and 403 transitions. [2024-11-25 04:35:12,505 INFO L276 IsEmpty]: Start isEmpty. Operand 253 states and 403 transitions. [2024-11-25 04:35:12,507 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:12,507 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:12,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:12,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:12,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:13,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:13,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 254 states and 403 transitions. [2024-11-25 04:35:13,626 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 403 transitions. [2024-11-25 04:35:13,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:13,633 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:13,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:13,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:13,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:14,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:14,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 255 states and 403 transitions. [2024-11-25 04:35:14,595 INFO L276 IsEmpty]: Start isEmpty. Operand 255 states and 403 transitions. [2024-11-25 04:35:14,600 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:14,600 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:14,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:14,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:14,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:15,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:15,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 256 states and 403 transitions. [2024-11-25 04:35:15,593 INFO L276 IsEmpty]: Start isEmpty. Operand 256 states and 403 transitions. [2024-11-25 04:35:15,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:15,598 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:15,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:15,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:15,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:16,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:16,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 257 states and 403 transitions. [2024-11-25 04:35:16,557 INFO L276 IsEmpty]: Start isEmpty. Operand 257 states and 403 transitions. [2024-11-25 04:35:16,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:16,558 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:16,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:16,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:16,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:17,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:17,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 258 states and 403 transitions. [2024-11-25 04:35:17,445 INFO L276 IsEmpty]: Start isEmpty. Operand 258 states and 403 transitions. [2024-11-25 04:35:17,446 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:17,446 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:17,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:17,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:17,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:18,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:18,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 259 states and 403 transitions. [2024-11-25 04:35:18,270 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states and 403 transitions. [2024-11-25 04:35:18,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:18,271 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:18,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:18,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:18,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:19,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:19,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 260 states and 403 transitions. [2024-11-25 04:35:19,133 INFO L276 IsEmpty]: Start isEmpty. Operand 260 states and 403 transitions. [2024-11-25 04:35:19,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:19,134 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:19,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:19,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:19,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:19,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:19,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 261 states and 403 transitions. [2024-11-25 04:35:19,984 INFO L276 IsEmpty]: Start isEmpty. Operand 261 states and 403 transitions. [2024-11-25 04:35:19,985 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:19,985 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:19,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:20,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:20,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:20,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:20,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 262 states and 403 transitions. [2024-11-25 04:35:20,815 INFO L276 IsEmpty]: Start isEmpty. Operand 262 states and 403 transitions. [2024-11-25 04:35:20,815 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:20,815 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:20,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:20,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:20,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:21,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:21,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 263 states and 403 transitions. [2024-11-25 04:35:21,667 INFO L276 IsEmpty]: Start isEmpty. Operand 263 states and 403 transitions. [2024-11-25 04:35:21,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:21,667 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:21,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:21,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:21,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:22,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:22,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 264 states and 403 transitions. [2024-11-25 04:35:22,470 INFO L276 IsEmpty]: Start isEmpty. Operand 264 states and 403 transitions. [2024-11-25 04:35:22,471 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:22,472 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:22,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:22,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:22,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:23,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:23,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 265 states and 403 transitions. [2024-11-25 04:35:23,311 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 403 transitions. [2024-11-25 04:35:23,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:23,311 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:23,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:23,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:23,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:24,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:24,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 266 states and 403 transitions. [2024-11-25 04:35:24,170 INFO L276 IsEmpty]: Start isEmpty. Operand 266 states and 403 transitions. [2024-11-25 04:35:24,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:24,174 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:24,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:24,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:24,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:24,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:24,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 267 states and 403 transitions. [2024-11-25 04:35:24,896 INFO L276 IsEmpty]: Start isEmpty. Operand 267 states and 403 transitions. [2024-11-25 04:35:24,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:24,900 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:24,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:24,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:25,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:25,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:25,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 309 states and 488 transitions. [2024-11-25 04:35:25,831 INFO L276 IsEmpty]: Start isEmpty. Operand 309 states and 488 transitions. [2024-11-25 04:35:25,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:25,832 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:25,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:25,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:25,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:26,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:26,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 310 states and 488 transitions. [2024-11-25 04:35:26,140 INFO L276 IsEmpty]: Start isEmpty. Operand 310 states and 488 transitions. [2024-11-25 04:35:26,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:26,141 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:26,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:26,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:26,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:26,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:26,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 311 states and 488 transitions. [2024-11-25 04:35:26,419 INFO L276 IsEmpty]: Start isEmpty. Operand 311 states and 488 transitions. [2024-11-25 04:35:26,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:26,420 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:26,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:26,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:26,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:26,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:26,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 312 states and 488 transitions. [2024-11-25 04:35:26,683 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 488 transitions. [2024-11-25 04:35:26,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:26,684 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:26,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:26,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:26,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:26,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:26,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 313 states and 488 transitions. [2024-11-25 04:35:26,952 INFO L276 IsEmpty]: Start isEmpty. Operand 313 states and 488 transitions. [2024-11-25 04:35:26,953 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:26,954 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:26,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:26,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:27,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:27,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:27,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 314 states and 488 transitions. [2024-11-25 04:35:27,209 INFO L276 IsEmpty]: Start isEmpty. Operand 314 states and 488 transitions. [2024-11-25 04:35:27,210 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:27,211 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:27,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:27,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:27,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:27,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:27,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 315 states and 488 transitions. [2024-11-25 04:35:27,474 INFO L276 IsEmpty]: Start isEmpty. Operand 315 states and 488 transitions. [2024-11-25 04:35:27,475 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:27,475 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:27,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:27,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:27,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:27,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:27,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 316 states and 488 transitions. [2024-11-25 04:35:27,717 INFO L276 IsEmpty]: Start isEmpty. Operand 316 states and 488 transitions. [2024-11-25 04:35:27,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:27,718 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:27,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:27,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:27,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:27,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:27,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 317 states and 488 transitions. [2024-11-25 04:35:27,977 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 488 transitions. [2024-11-25 04:35:27,978 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:27,978 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:27,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:27,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:28,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:28,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:28,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 318 states and 488 transitions. [2024-11-25 04:35:28,248 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 488 transitions. [2024-11-25 04:35:28,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:28,250 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:28,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:28,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:28,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:28,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:28,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 319 states and 488 transitions. [2024-11-25 04:35:28,480 INFO L276 IsEmpty]: Start isEmpty. Operand 319 states and 488 transitions. [2024-11-25 04:35:28,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:28,481 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:28,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:28,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:28,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:28,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:28,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 320 states and 488 transitions. [2024-11-25 04:35:28,691 INFO L276 IsEmpty]: Start isEmpty. Operand 320 states and 488 transitions. [2024-11-25 04:35:28,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:28,691 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:28,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:28,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:28,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:28,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:28,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 321 states and 488 transitions. [2024-11-25 04:35:28,882 INFO L276 IsEmpty]: Start isEmpty. Operand 321 states and 488 transitions. [2024-11-25 04:35:28,883 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:28,883 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:28,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:28,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:29,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:29,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:29,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 360 states and 569 transitions. [2024-11-25 04:35:29,365 INFO L276 IsEmpty]: Start isEmpty. Operand 360 states and 569 transitions. [2024-11-25 04:35:29,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:29,366 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:29,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:29,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:29,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:29,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:29,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 361 states and 569 transitions. [2024-11-25 04:35:29,550 INFO L276 IsEmpty]: Start isEmpty. Operand 361 states and 569 transitions. [2024-11-25 04:35:29,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:29,551 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:29,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:29,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:29,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:29,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:29,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 362 states and 569 transitions. [2024-11-25 04:35:29,734 INFO L276 IsEmpty]: Start isEmpty. Operand 362 states and 569 transitions. [2024-11-25 04:35:29,735 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:29,735 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:29,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:29,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:29,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:29,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:29,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 363 states and 569 transitions. [2024-11-25 04:35:29,929 INFO L276 IsEmpty]: Start isEmpty. Operand 363 states and 569 transitions. [2024-11-25 04:35:29,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:29,931 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:29,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:29,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:30,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:30,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:30,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 364 states and 569 transitions. [2024-11-25 04:35:30,196 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 569 transitions. [2024-11-25 04:35:30,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:30,197 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:30,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:30,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:30,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:30,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:30,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 365 states and 569 transitions. [2024-11-25 04:35:30,352 INFO L276 IsEmpty]: Start isEmpty. Operand 365 states and 569 transitions. [2024-11-25 04:35:30,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:30,352 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:30,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:30,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:30,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:30,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:30,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 366 states and 569 transitions. [2024-11-25 04:35:30,507 INFO L276 IsEmpty]: Start isEmpty. Operand 366 states and 569 transitions. [2024-11-25 04:35:30,508 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:30,508 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:30,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:30,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:30,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:30,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:30,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 367 states and 569 transitions. [2024-11-25 04:35:30,683 INFO L276 IsEmpty]: Start isEmpty. Operand 367 states and 569 transitions. [2024-11-25 04:35:30,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:30,684 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:30,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:30,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:30,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:30,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:30,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 368 states and 569 transitions. [2024-11-25 04:35:30,895 INFO L276 IsEmpty]: Start isEmpty. Operand 368 states and 569 transitions. [2024-11-25 04:35:30,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:30,896 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:30,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:30,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:31,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:31,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:31,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 369 states and 569 transitions. [2024-11-25 04:35:31,069 INFO L276 IsEmpty]: Start isEmpty. Operand 369 states and 569 transitions. [2024-11-25 04:35:31,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:31,071 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:31,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:31,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:31,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:31,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:31,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 370 states and 569 transitions. [2024-11-25 04:35:31,232 INFO L276 IsEmpty]: Start isEmpty. Operand 370 states and 569 transitions. [2024-11-25 04:35:31,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:31,234 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:31,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:31,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:31,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:31,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:31,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 371 states and 569 transitions. [2024-11-25 04:35:31,401 INFO L276 IsEmpty]: Start isEmpty. Operand 371 states and 569 transitions. [2024-11-25 04:35:31,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:31,402 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:31,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:31,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:31,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:31,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:31,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 407 states and 644 transitions. [2024-11-25 04:35:31,963 INFO L276 IsEmpty]: Start isEmpty. Operand 407 states and 644 transitions. [2024-11-25 04:35:31,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:31,964 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:31,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:31,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:32,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:32,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:32,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 408 states and 644 transitions. [2024-11-25 04:35:32,126 INFO L276 IsEmpty]: Start isEmpty. Operand 408 states and 644 transitions. [2024-11-25 04:35:32,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:32,127 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:32,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:32,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:32,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:32,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:32,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 409 states and 644 transitions. [2024-11-25 04:35:32,298 INFO L276 IsEmpty]: Start isEmpty. Operand 409 states and 644 transitions. [2024-11-25 04:35:32,300 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:32,300 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:32,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:32,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:32,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:32,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:32,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 410 states and 644 transitions. [2024-11-25 04:35:32,469 INFO L276 IsEmpty]: Start isEmpty. Operand 410 states and 644 transitions. [2024-11-25 04:35:32,470 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:32,471 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:32,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:32,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:32,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:32,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:32,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 411 states and 644 transitions. [2024-11-25 04:35:32,634 INFO L276 IsEmpty]: Start isEmpty. Operand 411 states and 644 transitions. [2024-11-25 04:35:32,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:32,636 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:32,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:32,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:32,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:32,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:32,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 412 states and 644 transitions. [2024-11-25 04:35:32,788 INFO L276 IsEmpty]: Start isEmpty. Operand 412 states and 644 transitions. [2024-11-25 04:35:32,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:32,789 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:32,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:32,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:32,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:32,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:32,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 413 states and 644 transitions. [2024-11-25 04:35:32,946 INFO L276 IsEmpty]: Start isEmpty. Operand 413 states and 644 transitions. [2024-11-25 04:35:32,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:32,947 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:32,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:32,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:33,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:33,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:33,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 414 states and 644 transitions. [2024-11-25 04:35:33,089 INFO L276 IsEmpty]: Start isEmpty. Operand 414 states and 644 transitions. [2024-11-25 04:35:33,090 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:33,090 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:33,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:33,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:33,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:33,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:33,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 415 states and 644 transitions. [2024-11-25 04:35:33,232 INFO L276 IsEmpty]: Start isEmpty. Operand 415 states and 644 transitions. [2024-11-25 04:35:33,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:33,233 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:33,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:33,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:33,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:33,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:33,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 416 states and 644 transitions. [2024-11-25 04:35:33,388 INFO L276 IsEmpty]: Start isEmpty. Operand 416 states and 644 transitions. [2024-11-25 04:35:33,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:33,389 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:33,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:33,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:33,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:34,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:34,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 439 states and 691 transitions. [2024-11-25 04:35:34,613 INFO L276 IsEmpty]: Start isEmpty. Operand 439 states and 691 transitions. [2024-11-25 04:35:34,614 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:34,615 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:34,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:34,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:34,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:35,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:35,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 440 states and 691 transitions. [2024-11-25 04:35:35,399 INFO L276 IsEmpty]: Start isEmpty. Operand 440 states and 691 transitions. [2024-11-25 04:35:35,400 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:35,400 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:35,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:35,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:35,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:36,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:36,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 441 states and 691 transitions. [2024-11-25 04:35:36,207 INFO L276 IsEmpty]: Start isEmpty. Operand 441 states and 691 transitions. [2024-11-25 04:35:36,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:36,208 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:36,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:36,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:36,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:37,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:37,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 442 states and 691 transitions. [2024-11-25 04:35:37,088 INFO L276 IsEmpty]: Start isEmpty. Operand 442 states and 691 transitions. [2024-11-25 04:35:37,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:37,089 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:37,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:37,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:37,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:37,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:37,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 443 states and 691 transitions. [2024-11-25 04:35:37,897 INFO L276 IsEmpty]: Start isEmpty. Operand 443 states and 691 transitions. [2024-11-25 04:35:37,897 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:37,897 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:37,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:37,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:37,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:38,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:38,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 444 states and 691 transitions. [2024-11-25 04:35:38,654 INFO L276 IsEmpty]: Start isEmpty. Operand 444 states and 691 transitions. [2024-11-25 04:35:38,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:38,655 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:38,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:38,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:38,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:39,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:39,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 445 states and 691 transitions. [2024-11-25 04:35:39,394 INFO L276 IsEmpty]: Start isEmpty. Operand 445 states and 691 transitions. [2024-11-25 04:35:39,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:39,395 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:39,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:39,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:39,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:40,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:40,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 446 states and 691 transitions. [2024-11-25 04:35:40,079 INFO L276 IsEmpty]: Start isEmpty. Operand 446 states and 691 transitions. [2024-11-25 04:35:40,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:40,080 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:40,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:40,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:40,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:40,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:40,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 476 states and 754 transitions. [2024-11-25 04:35:40,863 INFO L276 IsEmpty]: Start isEmpty. Operand 476 states and 754 transitions. [2024-11-25 04:35:40,863 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:40,863 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:40,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:40,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:40,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:41,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:41,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 477 states and 754 transitions. [2024-11-25 04:35:41,006 INFO L276 IsEmpty]: Start isEmpty. Operand 477 states and 754 transitions. [2024-11-25 04:35:41,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:41,007 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:41,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:41,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:41,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:41,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:41,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 478 states and 754 transitions. [2024-11-25 04:35:41,151 INFO L276 IsEmpty]: Start isEmpty. Operand 478 states and 754 transitions. [2024-11-25 04:35:41,152 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:41,152 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:41,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:41,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:41,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:41,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:41,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 479 states and 754 transitions. [2024-11-25 04:35:41,307 INFO L276 IsEmpty]: Start isEmpty. Operand 479 states and 754 transitions. [2024-11-25 04:35:41,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:41,308 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:41,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:41,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:41,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:41,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:41,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 480 states and 754 transitions. [2024-11-25 04:35:41,442 INFO L276 IsEmpty]: Start isEmpty. Operand 480 states and 754 transitions. [2024-11-25 04:35:41,443 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:41,443 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:41,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:41,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:41,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:41,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:41,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 481 states and 754 transitions. [2024-11-25 04:35:41,575 INFO L276 IsEmpty]: Start isEmpty. Operand 481 states and 754 transitions. [2024-11-25 04:35:41,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:41,575 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:41,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:41,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:41,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:42,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:42,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 819 states to 492 states and 777 transitions. [2024-11-25 04:35:42,500 INFO L276 IsEmpty]: Start isEmpty. Operand 492 states and 777 transitions. [2024-11-25 04:35:42,500 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:42,501 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:42,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:42,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:42,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:43,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:43,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 819 states to 493 states and 777 transitions. [2024-11-25 04:35:43,178 INFO L276 IsEmpty]: Start isEmpty. Operand 493 states and 777 transitions. [2024-11-25 04:35:43,179 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:43,179 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:43,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:43,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:43,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:43,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:43,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 819 states to 494 states and 777 transitions. [2024-11-25 04:35:43,851 INFO L276 IsEmpty]: Start isEmpty. Operand 494 states and 777 transitions. [2024-11-25 04:35:43,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:43,852 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:43,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:43,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:43,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:44,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:44,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 819 states to 495 states and 777 transitions. [2024-11-25 04:35:44,458 INFO L276 IsEmpty]: Start isEmpty. Operand 495 states and 777 transitions. [2024-11-25 04:35:44,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:44,458 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:44,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:44,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:44,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:45,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:45,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 864 states to 513 states and 816 transitions. [2024-11-25 04:35:45,235 INFO L276 IsEmpty]: Start isEmpty. Operand 513 states and 816 transitions. [2024-11-25 04:35:45,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:45,236 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:45,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:45,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:45,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:45,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:45,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 864 states to 514 states and 816 transitions. [2024-11-25 04:35:45,386 INFO L276 IsEmpty]: Start isEmpty. Operand 514 states and 816 transitions. [2024-11-25 04:35:45,387 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:45,387 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:45,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:45,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:45,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:45,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:45,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 864 states to 515 states and 816 transitions. [2024-11-25 04:35:45,544 INFO L276 IsEmpty]: Start isEmpty. Operand 515 states and 816 transitions. [2024-11-25 04:35:45,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:45,545 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:45,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:45,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:45,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:46,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:46,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 891 states to 524 states and 837 transitions. [2024-11-25 04:35:46,320 INFO L276 IsEmpty]: Start isEmpty. Operand 524 states and 837 transitions. [2024-11-25 04:35:46,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:46,320 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:46,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:46,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:46,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:50,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:50,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1024 states to 575 states and 953 transitions. [2024-11-25 04:35:50,849 INFO L276 IsEmpty]: Start isEmpty. Operand 575 states and 953 transitions. [2024-11-25 04:35:50,850 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:50,850 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:50,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:50,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:51,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:53,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:53,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1053 states to 581 states and 973 transitions. [2024-11-25 04:35:53,310 INFO L276 IsEmpty]: Start isEmpty. Operand 581 states and 973 transitions. [2024-11-25 04:35:53,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:53,311 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:53,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:53,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:53,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:54,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:54,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1059 states to 584 states and 979 transitions. [2024-11-25 04:35:54,191 INFO L276 IsEmpty]: Start isEmpty. Operand 584 states and 979 transitions. [2024-11-25 04:35:54,191 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:54,191 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:54,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:54,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:54,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:58,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:58,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1112 states to 599 states and 1023 transitions. [2024-11-25 04:35:58,651 INFO L276 IsEmpty]: Start isEmpty. Operand 599 states and 1023 transitions. [2024-11-25 04:35:58,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:58,651 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:58,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:58,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:58,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:35:59,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:35:59,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1115 states to 600 states and 1026 transitions. [2024-11-25 04:35:59,356 INFO L276 IsEmpty]: Start isEmpty. Operand 600 states and 1026 transitions. [2024-11-25 04:35:59,356 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:35:59,356 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:35:59,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:35:59,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:35:59,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:00,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:00,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1122 states to 603 states and 1033 transitions. [2024-11-25 04:36:00,326 INFO L276 IsEmpty]: Start isEmpty. Operand 603 states and 1033 transitions. [2024-11-25 04:36:00,327 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:00,327 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:00,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:00,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:00,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:01,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:01,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1140 states to 612 states and 1051 transitions. [2024-11-25 04:36:01,627 INFO L276 IsEmpty]: Start isEmpty. Operand 612 states and 1051 transitions. [2024-11-25 04:36:01,628 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:01,628 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:01,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:01,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:01,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:01,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:01,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1142 states to 613 states and 1053 transitions. [2024-11-25 04:36:01,734 INFO L276 IsEmpty]: Start isEmpty. Operand 613 states and 1053 transitions. [2024-11-25 04:36:01,735 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:01,735 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:01,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:01,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:02,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:10,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:10,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1203 states to 633 states and 1105 transitions. [2024-11-25 04:36:10,161 INFO L276 IsEmpty]: Start isEmpty. Operand 633 states and 1105 transitions. [2024-11-25 04:36:10,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:10,162 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:10,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:10,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:10,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:15,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:15,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1233 states to 645 states and 1135 transitions. [2024-11-25 04:36:15,905 INFO L276 IsEmpty]: Start isEmpty. Operand 645 states and 1135 transitions. [2024-11-25 04:36:15,906 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:15,906 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:15,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:15,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:15,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:20,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:20,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1247 states to 651 states and 1149 transitions. [2024-11-25 04:36:20,384 INFO L276 IsEmpty]: Start isEmpty. Operand 651 states and 1149 transitions. [2024-11-25 04:36:20,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:20,385 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:20,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:20,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:20,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:23,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:23,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1249 states to 652 states and 1151 transitions. [2024-11-25 04:36:23,880 INFO L276 IsEmpty]: Start isEmpty. Operand 652 states and 1151 transitions. [2024-11-25 04:36:23,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:23,881 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:23,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:23,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:23,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:26,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:26,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1251 states to 653 states and 1153 transitions. [2024-11-25 04:36:26,896 INFO L276 IsEmpty]: Start isEmpty. Operand 653 states and 1153 transitions. [2024-11-25 04:36:26,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:26,896 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:26,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:26,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:26,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:30,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:30,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1253 states to 654 states and 1155 transitions. [2024-11-25 04:36:30,283 INFO L276 IsEmpty]: Start isEmpty. Operand 654 states and 1155 transitions. [2024-11-25 04:36:30,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:30,283 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:30,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:30,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:30,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:33,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:33,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1255 states to 655 states and 1157 transitions. [2024-11-25 04:36:33,208 INFO L276 IsEmpty]: Start isEmpty. Operand 655 states and 1157 transitions. [2024-11-25 04:36:33,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:33,209 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:33,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:33,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:33,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:42,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:42,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1338 states to 682 states and 1231 transitions. [2024-11-25 04:36:42,267 INFO L276 IsEmpty]: Start isEmpty. Operand 682 states and 1231 transitions. [2024-11-25 04:36:42,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:42,268 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:42,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:42,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:42,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:44,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:44,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1352 states to 688 states and 1245 transitions. [2024-11-25 04:36:44,269 INFO L276 IsEmpty]: Start isEmpty. Operand 688 states and 1245 transitions. [2024-11-25 04:36:44,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:44,270 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:44,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:44,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:44,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:45,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:45,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1354 states to 689 states and 1247 transitions. [2024-11-25 04:36:45,149 INFO L276 IsEmpty]: Start isEmpty. Operand 689 states and 1247 transitions. [2024-11-25 04:36:45,150 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:45,150 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:45,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:45,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:45,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:48,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:48,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1392 states to 707 states and 1285 transitions. [2024-11-25 04:36:48,661 INFO L276 IsEmpty]: Start isEmpty. Operand 707 states and 1285 transitions. [2024-11-25 04:36:48,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:48,662 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:48,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:48,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:48,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:48,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:48,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1394 states to 708 states and 1287 transitions. [2024-11-25 04:36:48,845 INFO L276 IsEmpty]: Start isEmpty. Operand 708 states and 1287 transitions. [2024-11-25 04:36:48,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:48,846 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:48,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:48,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:48,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:49,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:49,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1396 states to 709 states and 1289 transitions. [2024-11-25 04:36:49,688 INFO L276 IsEmpty]: Start isEmpty. Operand 709 states and 1289 transitions. [2024-11-25 04:36:49,689 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:49,689 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:49,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:49,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:49,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:36:49,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:36:49,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1398 states to 710 states and 1291 transitions. [2024-11-25 04:36:49,842 INFO L276 IsEmpty]: Start isEmpty. Operand 710 states and 1291 transitions. [2024-11-25 04:36:49,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:36:49,843 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:36:49,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:36:49,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:36:50,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:01,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:01,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1495 states to 743 states and 1379 transitions. [2024-11-25 04:37:01,059 INFO L276 IsEmpty]: Start isEmpty. Operand 743 states and 1379 transitions. [2024-11-25 04:37:01,060 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:01,060 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:01,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:01,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:01,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:04,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:04,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1523 states to 755 states and 1407 transitions. [2024-11-25 04:37:04,507 INFO L276 IsEmpty]: Start isEmpty. Operand 755 states and 1407 transitions. [2024-11-25 04:37:04,507 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:04,507 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:04,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:04,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:04,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:05,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:05,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1529 states to 758 states and 1413 transitions. [2024-11-25 04:37:05,216 INFO L276 IsEmpty]: Start isEmpty. Operand 758 states and 1413 transitions. [2024-11-25 04:37:05,217 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:05,217 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:05,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:05,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:05,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:08,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:08,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1551 states to 767 states and 1435 transitions. [2024-11-25 04:37:08,296 INFO L276 IsEmpty]: Start isEmpty. Operand 767 states and 1435 transitions. [2024-11-25 04:37:08,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:08,297 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:08,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:08,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:08,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:10,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:10,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1565 states to 773 states and 1449 transitions. [2024-11-25 04:37:10,807 INFO L276 IsEmpty]: Start isEmpty. Operand 773 states and 1449 transitions. [2024-11-25 04:37:10,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:10,808 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:10,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:10,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:10,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:11,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:11,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1567 states to 774 states and 1451 transitions. [2024-11-25 04:37:11,861 INFO L276 IsEmpty]: Start isEmpty. Operand 774 states and 1451 transitions. [2024-11-25 04:37:11,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:11,862 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:11,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:11,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:11,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:11,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:11,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1569 states to 775 states and 1453 transitions. [2024-11-25 04:37:11,994 INFO L276 IsEmpty]: Start isEmpty. Operand 775 states and 1453 transitions. [2024-11-25 04:37:11,995 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:11,995 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:11,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:12,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:12,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:12,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:12,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 776 states and 1455 transitions. [2024-11-25 04:37:12,876 INFO L276 IsEmpty]: Start isEmpty. Operand 776 states and 1455 transitions. [2024-11-25 04:37:12,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:12,876 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:12,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:12,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:12,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:13,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:13,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1573 states to 777 states and 1457 transitions. [2024-11-25 04:37:13,024 INFO L276 IsEmpty]: Start isEmpty. Operand 777 states and 1457 transitions. [2024-11-25 04:37:13,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:13,025 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:13,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:13,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:13,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:13,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:13,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1575 states to 778 states and 1459 transitions. [2024-11-25 04:37:13,926 INFO L276 IsEmpty]: Start isEmpty. Operand 778 states and 1459 transitions. [2024-11-25 04:37:13,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:13,926 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:13,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:13,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:13,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:14,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:14,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1577 states to 779 states and 1461 transitions. [2024-11-25 04:37:14,033 INFO L276 IsEmpty]: Start isEmpty. Operand 779 states and 1461 transitions. [2024-11-25 04:37:14,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:14,033 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:14,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:14,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:14,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:17,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:17,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1584 states to 782 states and 1458 transitions. [2024-11-25 04:37:17,873 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1458 transitions. [2024-11-25 04:37:17,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:17,874 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:17,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:17,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:17,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:18,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:18,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1576 states to 782 states and 1450 transitions. [2024-11-25 04:37:18,697 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1450 transitions. [2024-11-25 04:37:18,697 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:18,697 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:18,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:18,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:18,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:19,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:19,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1572 states to 782 states and 1446 transitions. [2024-11-25 04:37:19,258 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1446 transitions. [2024-11-25 04:37:19,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:19,258 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:19,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:19,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:19,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:20,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:20,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1570 states to 782 states and 1444 transitions. [2024-11-25 04:37:20,261 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1444 transitions. [2024-11-25 04:37:20,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:20,261 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:20,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:20,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:20,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:20,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:20,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 782 states and 1440 transitions. [2024-11-25 04:37:20,740 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1440 transitions. [2024-11-25 04:37:20,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:20,741 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:20,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:20,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:20,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:21,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:21,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1562 states to 782 states and 1436 transitions. [2024-11-25 04:37:21,311 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1436 transitions. [2024-11-25 04:37:21,312 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:21,312 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:21,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:21,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:21,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:21,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:21,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1558 states to 782 states and 1432 transitions. [2024-11-25 04:37:21,856 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1432 transitions. [2024-11-25 04:37:21,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-25 04:37:21,856 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:21,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:21,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:21,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:22,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:22,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1554 states to 782 states and 1428 transitions. [2024-11-25 04:37:22,308 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1428 transitions. [2024-11-25 04:37:22,312 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-25 04:37:22,312 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:22,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:22,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:22,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:22,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:22,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1545 states to 777 states and 1419 transitions. [2024-11-25 04:37:22,856 INFO L276 IsEmpty]: Start isEmpty. Operand 777 states and 1419 transitions. [2024-11-25 04:37:22,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-25 04:37:22,857 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:22,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:22,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:22,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:23,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:23,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1541 states to 775 states and 1415 transitions. [2024-11-25 04:37:23,194 INFO L276 IsEmpty]: Start isEmpty. Operand 775 states and 1415 transitions. [2024-11-25 04:37:23,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-25 04:37:23,195 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:23,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:23,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:23,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:23,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:23,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1537 states to 773 states and 1411 transitions. [2024-11-25 04:37:23,544 INFO L276 IsEmpty]: Start isEmpty. Operand 773 states and 1411 transitions. [2024-11-25 04:37:23,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-25 04:37:23,545 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:23,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:23,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:23,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:23,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:23,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1538 states to 774 states and 1412 transitions. [2024-11-25 04:37:23,864 INFO L276 IsEmpty]: Start isEmpty. Operand 774 states and 1412 transitions. [2024-11-25 04:37:23,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-25 04:37:23,864 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:23,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:23,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:23,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:24,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:24,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1539 states to 775 states and 1413 transitions. [2024-11-25 04:37:24,898 INFO L276 IsEmpty]: Start isEmpty. Operand 775 states and 1413 transitions. [2024-11-25 04:37:24,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-25 04:37:24,899 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:24,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:24,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:24,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:25,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:25,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1540 states to 776 states and 1414 transitions. [2024-11-25 04:37:25,323 INFO L276 IsEmpty]: Start isEmpty. Operand 776 states and 1414 transitions. [2024-11-25 04:37:25,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-25 04:37:25,323 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:25,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:25,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:25,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:26,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:26,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1541 states to 777 states and 1415 transitions. [2024-11-25 04:37:26,543 INFO L276 IsEmpty]: Start isEmpty. Operand 777 states and 1415 transitions. [2024-11-25 04:37:26,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-25 04:37:26,544 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:26,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:26,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:26,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:27,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:27,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1542 states to 778 states and 1416 transitions. [2024-11-25 04:37:27,020 INFO L276 IsEmpty]: Start isEmpty. Operand 778 states and 1416 transitions. [2024-11-25 04:37:27,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-25 04:37:27,021 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:27,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:27,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:27,070 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:27,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:27,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1543 states to 779 states and 1417 transitions. [2024-11-25 04:37:27,508 INFO L276 IsEmpty]: Start isEmpty. Operand 779 states and 1417 transitions. [2024-11-25 04:37:27,508 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-25 04:37:27,508 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:27,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:27,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:27,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:27,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:27,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1544 states to 780 states and 1418 transitions. [2024-11-25 04:37:27,995 INFO L276 IsEmpty]: Start isEmpty. Operand 780 states and 1418 transitions. [2024-11-25 04:37:27,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-25 04:37:27,996 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:27,996 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:28,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:28,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:28,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:28,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1545 states to 781 states and 1419 transitions. [2024-11-25 04:37:28,502 INFO L276 IsEmpty]: Start isEmpty. Operand 781 states and 1419 transitions. [2024-11-25 04:37:28,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-25 04:37:28,502 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:28,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:28,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:28,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:32,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:32,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1546 states to 782 states and 1420 transitions. [2024-11-25 04:37:32,153 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1420 transitions. [2024-11-25 04:37:32,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-25 04:37:32,153 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:32,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:32,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:32,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:32,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:32,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1547 states to 783 states and 1421 transitions. [2024-11-25 04:37:32,663 INFO L276 IsEmpty]: Start isEmpty. Operand 783 states and 1421 transitions. [2024-11-25 04:37:32,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-25 04:37:32,664 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:32,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:32,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-25 04:37:32,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-25 04:37:32,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-11-25 04:37:32,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 750 states and 1363 transitions. [2024-11-25 04:37:32,908 INFO L276 IsEmpty]: Start isEmpty. Operand 750 states and 1363 transitions. [2024-11-25 04:37:32,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2024-11-25 04:37:32,909 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-11-25 04:37:32,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-25 04:37:32,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-25 04:37:32,945 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-25 04:37:32,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-25 04:37:33,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-25 04:37:33,298 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-25 04:37:33,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-25 04:37:33,651 WARN L473 CodeCheckObserver]: This program is UNSAFE, Check terminated with 128 iterations. [2024-11-25 04:37:33,922 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 25.11 04:37:33 ImpRootNode [2024-11-25 04:37:33,922 INFO L131 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2024-11-25 04:37:33,923 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-25 04:37:33,923 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-25 04:37:33,924 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-25 04:37:33,924 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.11 04:35:10" (3/4) ... [2024-11-25 04:37:33,926 INFO L140 WitnessPrinter]: Generating witness for reachability counterexample [2024-11-25 04:37:34,223 INFO L129 tionWitnessGenerator]: Generated YAML witness of length 155. [2024-11-25 04:37:34,396 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/witness.graphml [2024-11-25 04:37:34,397 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/witness.yml [2024-11-25 04:37:34,397 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-25 04:37:34,398 INFO L158 Benchmark]: Toolchain (without parser) took 147458.58ms. Allocated memory was 117.4MB in the beginning and 1.0GB in the end (delta: 889.2MB). Free memory was 91.9MB in the beginning and 739.1MB in the end (delta: -647.2MB). Peak memory consumption was 242.4MB. Max. memory is 16.1GB. [2024-11-25 04:37:34,399 INFO L158 Benchmark]: CDTParser took 0.41ms. Allocated memory is still 117.4MB. Free memory was 74.3MB in the beginning and 74.1MB in the end (delta: 195.8kB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-25 04:37:34,399 INFO L158 Benchmark]: CACSL2BoogieTranslator took 612.43ms. Allocated memory is still 117.4MB. Free memory was 91.6MB in the beginning and 68.6MB in the end (delta: 23.0MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-25 04:37:34,400 INFO L158 Benchmark]: Boogie Procedure Inliner took 90.81ms. Allocated memory is still 117.4MB. Free memory was 68.6MB in the beginning and 64.6MB in the end (delta: 4.1MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-25 04:37:34,400 INFO L158 Benchmark]: Boogie Preprocessor took 109.43ms. Allocated memory is still 117.4MB. Free memory was 64.6MB in the beginning and 60.6MB in the end (delta: 4.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-25 04:37:34,400 INFO L158 Benchmark]: RCFGBuilder took 2583.69ms. Allocated memory is still 117.4MB. Free memory was 60.6MB in the beginning and 26.2MB in the end (delta: 34.3MB). Peak memory consumption was 39.0MB. Max. memory is 16.1GB. [2024-11-25 04:37:34,401 INFO L158 Benchmark]: CodeCheck took 143558.73ms. Allocated memory was 117.4MB in the beginning and 1.0GB in the end (delta: 889.2MB). Free memory was 82.1MB in the beginning and 776.8MB in the end (delta: -694.7MB). Peak memory consumption was 187.2MB. Max. memory is 16.1GB. [2024-11-25 04:37:34,401 INFO L158 Benchmark]: Witness Printer took 474.30ms. Allocated memory is still 1.0GB. Free memory was 776.8MB in the beginning and 739.1MB in the end (delta: 37.8MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2024-11-25 04:37:34,404 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 7 procedures, 209 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 143.2s, OverallIterations: 128, TraceHistogramMax: 0, PathProgramHistogramMax: 0, EmptinessCheckTime: 0.0s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 128087 SdHoareTripleChecker+Valid, 137.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 111734 mSDsluCounter, 226030 SdHoareTripleChecker+Invalid, 124.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 193016 mSDsCounter, 10363 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 75327 IncrementalHoareTripleChecker+Invalid, 85690 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 10363 mSolverCounterUnsat, 33014 mSDtfsCounter, 75327 mSolverCounterSat, 5.7s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 88577 GetRequests, 80484 SyntacticMatches, 7459 SemanticMatches, 634 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 461423 ImplicationChecksByTransitivity, 122.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, InterpolantAutomatonStates: 0, traceCheckStatistics: 0.8s SsaConstructionTime, 1.1s SatisfiabilityAnalysisTime, 12.0s InterpolantComputationTime, 8848 NumberOfCodeBlocks, 8848 NumberOfCodeBlocksAsserted, 128 NumberOfCheckSat, 8650 ConstructedInterpolants, 0 QuantifiedInterpolants, 22894 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 127 InterpolantComputations, 127 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int t8_pc = 0; [L34] int t9_pc = 0; [L35] int t10_pc = 0; [L36] int t11_pc = 0; [L37] int t12_pc = 0; [L38] int t13_pc = 0; [L39] int t14_pc = 0; [L40] int m_st ; [L41] int t1_st ; [L42] int t2_st ; [L43] int t3_st ; [L44] int t4_st ; [L45] int t5_st ; [L46] int t6_st ; [L47] int t7_st ; [L48] int t8_st ; [L49] int t9_st ; [L50] int t10_st ; [L51] int t11_st ; [L52] int t12_st ; [L53] int t13_st ; [L54] int t14_st ; [L55] int m_i ; [L56] int t1_i ; [L57] int t2_i ; [L58] int t3_i ; [L59] int t4_i ; [L60] int t5_i ; [L61] int t6_i ; [L62] int t7_i ; [L63] int t8_i ; [L64] int t9_i ; [L65] int t10_i ; [L66] int t11_i ; [L67] int t12_i ; [L68] int t13_i ; [L69] int t14_i ; [L70] int M_E = 2; [L71] int T1_E = 2; [L72] int T2_E = 2; [L73] int T3_E = 2; [L74] int T4_E = 2; [L75] int T5_E = 2; [L76] int T6_E = 2; [L77] int T7_E = 2; [L78] int T8_E = 2; [L79] int T9_E = 2; [L80] int T10_E = 2; [L81] int T11_E = 2; [L82] int T12_E = 2; [L83] int T13_E = 2; [L84] int T14_E = 2; [L85] int E_1 = 2; [L86] int E_2 = 2; [L87] int E_3 = 2; [L88] int E_4 = 2; [L89] int E_5 = 2; [L90] int E_6 = 2; [L91] int E_7 = 2; [L92] int E_8 = 2; [L93] int E_9 = 2; [L94] int E_10 = 2; [L95] int E_11 = 2; [L96] int E_12 = 2; [L97] int E_13 = 2; [L98] int E_14 = 2; [L2062] int __retres1 ; [L2066] CALL init_model() [L1964] m_i = 1 [L1965] t1_i = 1 [L1966] t2_i = 1 [L1967] t3_i = 1 [L1968] t4_i = 1 [L1969] t5_i = 1 [L1970] t6_i = 1 [L1971] t7_i = 1 [L1972] t8_i = 1 [L1973] t9_i = 1 [L1974] t10_i = 1 [L1975] t11_i = 1 [L1976] t12_i = 1 [L1977] t13_i = 1 [L1978] t14_i = 1 [L2066] RET init_model() [L2067] CALL start_simulation() [L2003] int kernel_st ; [L2004] int tmp ; [L2005] int tmp___0 ; [L2009] kernel_st = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2010] FCALL update_channels() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2011] CALL init_threads() [L939] COND TRUE m_i == 1 [L940] m_st = 0 [L944] COND TRUE t1_i == 1 [L945] t1_st = 0 [L949] COND TRUE t2_i == 1 [L950] t2_st = 0 [L954] COND TRUE t3_i == 1 [L955] t3_st = 0 [L959] COND TRUE t4_i == 1 [L960] t4_st = 0 [L964] COND TRUE t5_i == 1 [L965] t5_st = 0 [L969] COND TRUE t6_i == 1 [L970] t6_st = 0 [L974] COND TRUE t7_i == 1 [L975] t7_st = 0 [L979] COND TRUE t8_i == 1 [L980] t8_st = 0 [L984] COND TRUE t9_i == 1 [L985] t9_st = 0 [L989] COND TRUE t10_i == 1 [L990] t10_st = 0 [L994] COND TRUE t11_i == 1 [L995] t11_st = 0 [L999] COND TRUE t12_i == 1 [L1000] t12_st = 0 [L1004] COND TRUE t13_i == 1 [L1005] t13_st = 0 [L1009] COND TRUE t14_i == 1 [L1010] t14_st = 0 [L2011] RET init_threads() [L2012] CALL fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_14)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T14_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1342] COND FALSE !(M_E == 0) [L1347] COND FALSE !(T1_E == 0) [L1352] COND FALSE !(T2_E == 0) [L1357] COND FALSE !(T3_E == 0) [L1362] COND FALSE !(T4_E == 0) [L1367] COND FALSE !(T5_E == 0) [L1372] COND FALSE !(T6_E == 0) [L1377] COND FALSE !(T7_E == 0) [L1382] COND FALSE !(T8_E == 0) [L1387] COND FALSE !(T9_E == 0) [L1392] COND FALSE !(T10_E == 0) [L1397] COND FALSE !(T11_E == 0) [L1402] COND FALSE !(T12_E == 0) [L1407] COND FALSE !(T13_E == 0) [L1412] COND FALSE !(T14_E == 0) [L1417] COND FALSE !(E_1 == 0) [L1422] COND FALSE !(E_2 == 0) [L1427] COND FALSE !(E_3 == 0) [L1432] COND FALSE !(E_4 == 0) [L1437] COND FALSE !(E_5 == 0) [L1442] COND FALSE !(E_6 == 0) [L1447] COND FALSE !(E_7 == 0) [L1452] COND FALSE !(E_8 == 0) [L1457] COND FALSE !(E_9 == 0) [L1462] COND FALSE !(E_10 == 0) [L1467] COND FALSE !(E_11 == 0) [L1472] COND FALSE !(E_12 == 0) [L1477] COND FALSE !(E_13 == 0) [L1482] COND FALSE !(E_14 == 0) [L2012] RET fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2013] CALL activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1645] int tmp ; [L1646] int tmp___0 ; [L1647] int tmp___1 ; [L1648] int tmp___2 ; [L1649] int tmp___3 ; [L1650] int tmp___4 ; [L1651] int tmp___5 ; [L1652] int tmp___6 ; [L1653] int tmp___7 ; [L1654] int tmp___8 ; [L1655] int tmp___9 ; [L1656] int tmp___10 ; [L1657] int tmp___11 ; [L1658] int tmp___12 ; [L1659] int tmp___13 ; [L1664] CALL, EXPR is_master_triggered() [L643] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L646] COND FALSE !(m_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L656] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L658] return (__retres1); [L1664] RET, EXPR is_master_triggered() [L1664] tmp = is_master_triggered() [L1666] COND FALSE !(\read(tmp)) [L1672] CALL, EXPR is_transmit1_triggered() [L662] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L665] COND FALSE !(t1_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L675] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L677] return (__retres1); [L1672] RET, EXPR is_transmit1_triggered() [L1672] tmp___0 = is_transmit1_triggered() [L1674] COND FALSE !(\read(tmp___0)) [L1680] CALL, EXPR is_transmit2_triggered() [L681] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L684] COND FALSE !(t2_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L694] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L696] return (__retres1); [L1680] RET, EXPR is_transmit2_triggered() [L1680] tmp___1 = is_transmit2_triggered() [L1682] COND FALSE !(\read(tmp___1)) [L1688] CALL, EXPR is_transmit3_triggered() [L700] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L703] COND FALSE !(t3_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L713] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L715] return (__retres1); [L1688] RET, EXPR is_transmit3_triggered() [L1688] tmp___2 = is_transmit3_triggered() [L1690] COND FALSE !(\read(tmp___2)) [L1696] CALL, EXPR is_transmit4_triggered() [L719] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L722] COND FALSE !(t4_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L732] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L734] return (__retres1); [L1696] RET, EXPR is_transmit4_triggered() [L1696] tmp___3 = is_transmit4_triggered() [L1698] COND FALSE !(\read(tmp___3)) [L1704] CALL, EXPR is_transmit5_triggered() [L738] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L741] COND FALSE !(t5_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L751] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L753] return (__retres1); [L1704] RET, EXPR is_transmit5_triggered() [L1704] tmp___4 = is_transmit5_triggered() [L1706] COND FALSE !(\read(tmp___4)) [L1712] CALL, EXPR is_transmit6_triggered() [L757] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L760] COND FALSE !(t6_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L770] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L772] return (__retres1); [L1712] RET, EXPR is_transmit6_triggered() [L1712] tmp___5 = is_transmit6_triggered() [L1714] COND FALSE !(\read(tmp___5)) [L1720] CALL, EXPR is_transmit7_triggered() [L776] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L779] COND FALSE !(t7_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L789] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L791] return (__retres1); [L1720] RET, EXPR is_transmit7_triggered() [L1720] tmp___6 = is_transmit7_triggered() [L1722] COND FALSE !(\read(tmp___6)) [L1728] CALL, EXPR is_transmit8_triggered() [L795] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L798] COND FALSE !(t8_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L808] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L810] return (__retres1); [L1728] RET, EXPR is_transmit8_triggered() [L1728] tmp___7 = is_transmit8_triggered() [L1730] COND FALSE !(\read(tmp___7)) [L1736] CALL, EXPR is_transmit9_triggered() [L814] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L817] COND FALSE !(t9_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L827] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L829] return (__retres1); [L1736] RET, EXPR is_transmit9_triggered() [L1736] tmp___8 = is_transmit9_triggered() [L1738] COND FALSE !(\read(tmp___8)) [L1744] CALL, EXPR is_transmit10_triggered() [L833] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L836] COND FALSE !(t10_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L846] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L848] return (__retres1); [L1744] RET, EXPR is_transmit10_triggered() [L1744] tmp___9 = is_transmit10_triggered() [L1746] COND FALSE !(\read(tmp___9)) [L1752] CALL, EXPR is_transmit11_triggered() [L852] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L855] COND FALSE !(t11_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L865] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L867] return (__retres1); [L1752] RET, EXPR is_transmit11_triggered() [L1752] tmp___10 = is_transmit11_triggered() [L1754] COND FALSE !(\read(tmp___10)) [L1760] CALL, EXPR is_transmit12_triggered() [L871] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L874] COND FALSE !(t12_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L884] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L886] return (__retres1); [L1760] RET, EXPR is_transmit12_triggered() [L1760] tmp___11 = is_transmit12_triggered() [L1762] COND FALSE !(\read(tmp___11)) [L1768] CALL, EXPR is_transmit13_triggered() [L890] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L893] COND FALSE !(t13_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L903] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L905] return (__retres1); [L1768] RET, EXPR is_transmit13_triggered() [L1768] tmp___12 = is_transmit13_triggered() [L1770] COND FALSE !(\read(tmp___12)) [L1776] CALL, EXPR is_transmit14_triggered() [L909] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L912] COND FALSE !(t14_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L922] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L924] return (__retres1); [L1776] RET, EXPR is_transmit14_triggered() [L1776] tmp___13 = is_transmit14_triggered() [L1778] COND FALSE !(\read(tmp___13)) [L2013] RET activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2014] CALL reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_14)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T14_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1495] COND FALSE !(M_E == 1) [L1500] COND FALSE !(T1_E == 1) [L1505] COND FALSE !(T2_E == 1) [L1510] COND FALSE !(T3_E == 1) [L1515] COND FALSE !(T4_E == 1) [L1520] COND FALSE !(T5_E == 1) [L1525] COND FALSE !(T6_E == 1) [L1530] COND FALSE !(T7_E == 1) [L1535] COND FALSE !(T8_E == 1) [L1540] COND FALSE !(T9_E == 1) [L1545] COND FALSE !(T10_E == 1) [L1550] COND FALSE !(T11_E == 1) [L1555] COND FALSE !(T12_E == 1) [L1560] COND FALSE !(T13_E == 1) [L1565] COND FALSE !(T14_E == 1) [L1570] COND FALSE !(E_1 == 1) [L1575] COND FALSE !(E_2 == 1) [L1580] COND FALSE !(E_3 == 1) [L1585] COND FALSE !(E_4 == 1) [L1590] COND FALSE !(E_5 == 1) [L1595] COND FALSE !(E_6 == 1) [L1600] COND FALSE !(E_7 == 1) [L1605] COND FALSE !(E_8 == 1) [L1610] COND FALSE !(E_9 == 1) [L1615] COND FALSE !(E_10 == 1) [L1620] COND FALSE !(E_11 == 1) [L1625] COND FALSE !(E_12 == 1) [L1630] COND FALSE !(E_13 == 1) [L1635] COND FALSE !(E_14 == 1) [L2014] RET reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2020] kernel_st = 1 [L2021] CALL eval() [L1106] int tmp ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1113] CALL, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1019] int __retres1 ; [L1022] COND TRUE m_st == 0 [L1023] __retres1 = 1 [L1101] return (__retres1); [L1113] RET, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1113] tmp = exists_runnable_thread() [L1115] COND TRUE \read(tmp) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1120] COND TRUE m_st == 0 [L1121] int tmp_ndt_1; [L1122] tmp_ndt_1 = __VERIFIER_nondet_int() [L1123] COND FALSE !(\read(tmp_ndt_1)) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1134] COND TRUE t1_st == 0 [L1135] int tmp_ndt_2; [L1136] tmp_ndt_2 = __VERIFIER_nondet_int() [L1137] COND FALSE !(\read(tmp_ndt_2)) [L1143] CALL error() [L21] reach_error() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.41ms. Allocated memory is still 117.4MB. Free memory was 74.3MB in the beginning and 74.1MB in the end (delta: 195.8kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 612.43ms. Allocated memory is still 117.4MB. Free memory was 91.6MB in the beginning and 68.6MB in the end (delta: 23.0MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 90.81ms. Allocated memory is still 117.4MB. Free memory was 68.6MB in the beginning and 64.6MB in the end (delta: 4.1MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 109.43ms. Allocated memory is still 117.4MB. Free memory was 64.6MB in the beginning and 60.6MB in the end (delta: 4.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 2583.69ms. Allocated memory is still 117.4MB. Free memory was 60.6MB in the beginning and 26.2MB in the end (delta: 34.3MB). Peak memory consumption was 39.0MB. Max. memory is 16.1GB. * CodeCheck took 143558.73ms. Allocated memory was 117.4MB in the beginning and 1.0GB in the end (delta: 889.2MB). Free memory was 82.1MB in the beginning and 776.8MB in the end (delta: -694.7MB). Peak memory consumption was 187.2MB. Max. memory is 16.1GB. * Witness Printer took 474.30ms. Allocated memory is still 1.0GB. Free memory was 776.8MB in the beginning and 739.1MB in the end (delta: 37.8MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. RESULT: Ultimate proved your program to be incorrect! [2024-11-25 04:37:34,439 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a208fd40-7d6b-4105-b062-4822b03ae343/bin/ukojak-verify-ENZ3QT5qd3/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE