./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/config/KojakReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/config/svcomp-Reach-32bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-12-06 02:44:39,567 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-12-06 02:44:39,625 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/config/svcomp-Reach-32bit-Kojak_Default.epf [2024-12-06 02:44:39,630 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-12-06 02:44:39,630 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck.Interpolating solver [2024-12-06 02:44:39,652 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-12-06 02:44:39,653 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-12-06 02:44:39,653 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ALWAYS [2024-12-06 02:44:39,653 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-12-06 02:44:39,654 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-12-06 02:44:39,654 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-12-06 02:44:39,654 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-12-06 02:44:39,654 INFO L153 SettingsManager]: * sizeof long=4 [2024-12-06 02:44:39,654 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-12-06 02:44:39,654 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-12-06 02:44:39,654 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-12-06 02:44:39,654 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-12-06 02:44:39,654 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-12-06 02:44:39,654 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-12-06 02:44:39,655 INFO L153 SettingsManager]: * sizeof long double=12 [2024-12-06 02:44:39,655 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-12-06 02:44:39,655 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-12-06 02:44:39,655 INFO L153 SettingsManager]: * Use constant arrays=true [2024-12-06 02:44:39,655 INFO L151 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2024-12-06 02:44:39,655 INFO L153 SettingsManager]: * Timeout in seconds=1000000 [2024-12-06 02:44:39,655 INFO L153 SettingsManager]: * Theory for external solver=ALL [2024-12-06 02:44:39,655 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-12-06 02:44:39,655 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2024-12-06 02:44:39,655 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-12-06 02:44:39,656 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-12-06 02:44:39,656 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-12-06 02:44:39,656 INFO L153 SettingsManager]: * Trace refinement strategy=PENGUIN [2024-12-06 02:44:39,656 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-12-06 02:44:39,656 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2024-12-06 02:44:39,907 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-12-06 02:44:39,915 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-12-06 02:44:39,917 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-12-06 02:44:39,919 INFO L270 PluginConnector]: Initializing CDTParser... [2024-12-06 02:44:39,919 INFO L274 PluginConnector]: CDTParser initialized [2024-12-06 02:44:39,920 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/../../sv-benchmarks/c/systemc/transmitter.15.cil.c [2024-12-06 02:44:42,567 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/data/d7e88d229/f604e6e0cbe742018b757091afdc4301/FLAG92c58caf2 [2024-12-06 02:44:42,799 INFO L384 CDTParser]: Found 1 translation units. [2024-12-06 02:44:42,800 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/sv-benchmarks/c/systemc/transmitter.15.cil.c [2024-12-06 02:44:42,812 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/data/d7e88d229/f604e6e0cbe742018b757091afdc4301/FLAG92c58caf2 [2024-12-06 02:44:43,127 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/data/d7e88d229/f604e6e0cbe742018b757091afdc4301 [2024-12-06 02:44:43,129 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-12-06 02:44:43,130 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-12-06 02:44:43,131 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-12-06 02:44:43,131 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-12-06 02:44:43,134 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-12-06 02:44:43,134 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 02:44:43" (1/1) ... [2024-12-06 02:44:43,135 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4f0e3c10 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 02:44:43, skipping insertion in model container [2024-12-06 02:44:43,135 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 02:44:43" (1/1) ... [2024-12-06 02:44:43,164 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-12-06 02:44:43,271 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2024-12-06 02:44:43,397 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-06 02:44:43,409 INFO L200 MainTranslator]: Completed pre-run [2024-12-06 02:44:43,418 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2024-12-06 02:44:43,470 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-06 02:44:43,490 INFO L204 MainTranslator]: Completed translation [2024-12-06 02:44:43,491 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 02:44:43 WrapperNode [2024-12-06 02:44:43,491 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-12-06 02:44:43,492 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-12-06 02:44:43,492 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-12-06 02:44:43,492 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-12-06 02:44:43,498 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 02:44:43" (1/1) ... [2024-12-06 02:44:43,507 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 02:44:43" (1/1) ... [2024-12-06 02:44:43,537 INFO L138 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 38, calls inlined = 38, statements flattened = 901 [2024-12-06 02:44:43,537 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-12-06 02:44:43,537 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-12-06 02:44:43,538 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-12-06 02:44:43,538 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-12-06 02:44:43,543 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 02:44:43" (1/1) ... [2024-12-06 02:44:43,543 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 02:44:43" (1/1) ... [2024-12-06 02:44:43,545 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 02:44:43" (1/1) ... [2024-12-06 02:44:43,546 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 02:44:43" (1/1) ... [2024-12-06 02:44:43,553 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 02:44:43" (1/1) ... [2024-12-06 02:44:43,555 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 02:44:43" (1/1) ... [2024-12-06 02:44:43,567 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 02:44:43" (1/1) ... [2024-12-06 02:44:43,569 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 02:44:43" (1/1) ... [2024-12-06 02:44:43,572 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 02:44:43" (1/1) ... [2024-12-06 02:44:43,577 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-12-06 02:44:43,578 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-12-06 02:44:43,578 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-12-06 02:44:43,578 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-12-06 02:44:43,579 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 02:44:43" (1/1) ... [2024-12-06 02:44:43,584 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2024-12-06 02:44:43,596 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/z3 [2024-12-06 02:44:43,608 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) [2024-12-06 02:44:43,611 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Waiting until timeout for monitored process [2024-12-06 02:44:43,637 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-12-06 02:44:43,637 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2024-12-06 02:44:43,637 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2024-12-06 02:44:43,637 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2024-12-06 02:44:43,637 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2024-12-06 02:44:43,638 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2024-12-06 02:44:43,638 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2024-12-06 02:44:43,638 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2024-12-06 02:44:43,638 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2024-12-06 02:44:43,638 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2024-12-06 02:44:43,638 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2024-12-06 02:44:43,638 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2024-12-06 02:44:43,638 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2024-12-06 02:44:43,638 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2024-12-06 02:44:43,638 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-12-06 02:44:43,638 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-12-06 02:44:43,749 INFO L234 CfgBuilder]: Building ICFG [2024-12-06 02:44:43,751 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-12-06 02:44:44,616 INFO L? ?]: Removed 103 outVars from TransFormulas that were not future-live. [2024-12-06 02:44:44,616 INFO L283 CfgBuilder]: Performing block encoding [2024-12-06 02:44:45,030 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-12-06 02:44:45,031 INFO L312 CfgBuilder]: Removed 34 assume(true) statements. [2024-12-06 02:44:45,031 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 02:44:45 BoogieIcfgContainer [2024-12-06 02:44:45,031 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-12-06 02:44:45,032 INFO L112 PluginConnector]: ------------------------CodeCheck---------------------------- [2024-12-06 02:44:45,032 INFO L270 PluginConnector]: Initializing CodeCheck... [2024-12-06 02:44:45,039 INFO L274 PluginConnector]: CodeCheck initialized [2024-12-06 02:44:45,039 INFO L184 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 02:44:45" (1/1) ... [2024-12-06 02:44:45,045 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-06 02:44:45,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:45,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311 states to 205 states and 311 transitions. [2024-12-06 02:44:45,089 INFO L276 IsEmpty]: Start isEmpty. Operand 205 states and 311 transitions. [2024-12-06 02:44:45,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:45,094 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:45,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:45,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:45,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:46,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:46,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 246 states and 391 transitions. [2024-12-06 02:44:46,389 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 391 transitions. [2024-12-06 02:44:46,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:46,391 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:46,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:46,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:46,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:47,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:47,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 247 states and 391 transitions. [2024-12-06 02:44:47,033 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 391 transitions. [2024-12-06 02:44:47,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:47,035 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:47,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:47,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:47,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:47,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:47,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 248 states and 391 transitions. [2024-12-06 02:44:47,627 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 391 transitions. [2024-12-06 02:44:47,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:47,629 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:47,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:47,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:47,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:48,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:48,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 249 states and 391 transitions. [2024-12-06 02:44:48,129 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 391 transitions. [2024-12-06 02:44:48,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:48,131 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:48,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:48,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:48,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:48,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:48,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 250 states and 391 transitions. [2024-12-06 02:44:48,618 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 391 transitions. [2024-12-06 02:44:48,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:48,619 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:48,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:48,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:48,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:49,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:49,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 251 states and 391 transitions. [2024-12-06 02:44:49,092 INFO L276 IsEmpty]: Start isEmpty. Operand 251 states and 391 transitions. [2024-12-06 02:44:49,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:49,093 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:49,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:49,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:49,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:49,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:49,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 252 states and 391 transitions. [2024-12-06 02:44:49,611 INFO L276 IsEmpty]: Start isEmpty. Operand 252 states and 391 transitions. [2024-12-06 02:44:49,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:49,612 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:49,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:49,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:49,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:50,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:50,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 253 states and 391 transitions. [2024-12-06 02:44:50,128 INFO L276 IsEmpty]: Start isEmpty. Operand 253 states and 391 transitions. [2024-12-06 02:44:50,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:50,128 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:50,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:50,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:50,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:50,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:50,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 254 states and 391 transitions. [2024-12-06 02:44:50,599 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 391 transitions. [2024-12-06 02:44:50,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:50,599 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:50,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:50,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:50,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:51,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:51,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 255 states and 391 transitions. [2024-12-06 02:44:51,110 INFO L276 IsEmpty]: Start isEmpty. Operand 255 states and 391 transitions. [2024-12-06 02:44:51,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:51,111 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:51,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:51,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:51,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:51,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:51,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 256 states and 391 transitions. [2024-12-06 02:44:51,659 INFO L276 IsEmpty]: Start isEmpty. Operand 256 states and 391 transitions. [2024-12-06 02:44:51,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:51,659 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:51,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:51,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:51,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:52,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:52,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 257 states and 391 transitions. [2024-12-06 02:44:52,250 INFO L276 IsEmpty]: Start isEmpty. Operand 257 states and 391 transitions. [2024-12-06 02:44:52,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:52,251 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:52,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:52,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:52,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:52,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:52,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 258 states and 391 transitions. [2024-12-06 02:44:52,730 INFO L276 IsEmpty]: Start isEmpty. Operand 258 states and 391 transitions. [2024-12-06 02:44:52,731 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:52,731 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:52,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:52,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:52,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:53,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:53,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 259 states and 391 transitions. [2024-12-06 02:44:53,235 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states and 391 transitions. [2024-12-06 02:44:53,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:53,236 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:53,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:53,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:53,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:53,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:53,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 298 states and 470 transitions. [2024-12-06 02:44:53,796 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 470 transitions. [2024-12-06 02:44:53,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:53,797 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:53,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:53,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:53,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:54,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:54,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 299 states and 470 transitions. [2024-12-06 02:44:54,009 INFO L276 IsEmpty]: Start isEmpty. Operand 299 states and 470 transitions. [2024-12-06 02:44:54,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:54,010 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:54,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:54,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:54,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:54,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:54,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 300 states and 470 transitions. [2024-12-06 02:44:54,208 INFO L276 IsEmpty]: Start isEmpty. Operand 300 states and 470 transitions. [2024-12-06 02:44:54,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:54,208 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:54,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:54,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:54,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:54,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:54,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 301 states and 470 transitions. [2024-12-06 02:44:54,381 INFO L276 IsEmpty]: Start isEmpty. Operand 301 states and 470 transitions. [2024-12-06 02:44:54,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:54,381 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:54,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:54,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:54,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:54,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:54,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 302 states and 470 transitions. [2024-12-06 02:44:54,574 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 470 transitions. [2024-12-06 02:44:54,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:54,575 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:54,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:54,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:54,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:54,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:54,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 303 states and 470 transitions. [2024-12-06 02:44:54,722 INFO L276 IsEmpty]: Start isEmpty. Operand 303 states and 470 transitions. [2024-12-06 02:44:54,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:54,723 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:54,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:54,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:54,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:54,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:54,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 304 states and 470 transitions. [2024-12-06 02:44:54,869 INFO L276 IsEmpty]: Start isEmpty. Operand 304 states and 470 transitions. [2024-12-06 02:44:54,870 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:54,870 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:54,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:54,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:54,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:55,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:55,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 305 states and 470 transitions. [2024-12-06 02:44:55,005 INFO L276 IsEmpty]: Start isEmpty. Operand 305 states and 470 transitions. [2024-12-06 02:44:55,005 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:55,005 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:55,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:55,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:55,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:55,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:55,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 306 states and 470 transitions. [2024-12-06 02:44:55,151 INFO L276 IsEmpty]: Start isEmpty. Operand 306 states and 470 transitions. [2024-12-06 02:44:55,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:55,151 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:55,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:55,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:55,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:55,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:55,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 307 states and 470 transitions. [2024-12-06 02:44:55,276 INFO L276 IsEmpty]: Start isEmpty. Operand 307 states and 470 transitions. [2024-12-06 02:44:55,277 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:55,277 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:55,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:55,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:55,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:55,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:55,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 308 states and 470 transitions. [2024-12-06 02:44:55,395 INFO L276 IsEmpty]: Start isEmpty. Operand 308 states and 470 transitions. [2024-12-06 02:44:55,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:55,395 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:55,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:55,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:55,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:55,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:55,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 309 states and 470 transitions. [2024-12-06 02:44:55,509 INFO L276 IsEmpty]: Start isEmpty. Operand 309 states and 470 transitions. [2024-12-06 02:44:55,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:55,510 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:55,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:55,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:55,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:55,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:55,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 345 states and 545 transitions. [2024-12-06 02:44:55,795 INFO L276 IsEmpty]: Start isEmpty. Operand 345 states and 545 transitions. [2024-12-06 02:44:55,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:55,796 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:55,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:55,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:55,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:55,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:55,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 346 states and 545 transitions. [2024-12-06 02:44:55,901 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 545 transitions. [2024-12-06 02:44:55,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:55,902 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:55,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:55,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:55,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:55,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:55,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 347 states and 545 transitions. [2024-12-06 02:44:55,989 INFO L276 IsEmpty]: Start isEmpty. Operand 347 states and 545 transitions. [2024-12-06 02:44:55,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:55,990 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:55,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:56,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:56,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:56,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:56,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 348 states and 545 transitions. [2024-12-06 02:44:56,106 INFO L276 IsEmpty]: Start isEmpty. Operand 348 states and 545 transitions. [2024-12-06 02:44:56,107 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:56,107 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:56,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:56,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:56,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:56,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:56,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 349 states and 545 transitions. [2024-12-06 02:44:56,248 INFO L276 IsEmpty]: Start isEmpty. Operand 349 states and 545 transitions. [2024-12-06 02:44:56,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:56,249 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:56,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:56,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:56,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:56,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:56,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 350 states and 545 transitions. [2024-12-06 02:44:56,400 INFO L276 IsEmpty]: Start isEmpty. Operand 350 states and 545 transitions. [2024-12-06 02:44:56,401 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:56,401 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:56,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:56,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:56,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:56,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:56,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 351 states and 545 transitions. [2024-12-06 02:44:56,504 INFO L276 IsEmpty]: Start isEmpty. Operand 351 states and 545 transitions. [2024-12-06 02:44:56,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:56,505 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:56,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:56,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:56,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:56,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:56,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 352 states and 545 transitions. [2024-12-06 02:44:56,597 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 545 transitions. [2024-12-06 02:44:56,597 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:56,597 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:56,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:56,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:56,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:56,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:56,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 353 states and 545 transitions. [2024-12-06 02:44:56,689 INFO L276 IsEmpty]: Start isEmpty. Operand 353 states and 545 transitions. [2024-12-06 02:44:56,689 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:56,689 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:56,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:56,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:56,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:56,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:56,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 354 states and 545 transitions. [2024-12-06 02:44:56,807 INFO L276 IsEmpty]: Start isEmpty. Operand 354 states and 545 transitions. [2024-12-06 02:44:56,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:56,808 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:56,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:56,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:56,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:56,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:56,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 355 states and 545 transitions. [2024-12-06 02:44:56,895 INFO L276 IsEmpty]: Start isEmpty. Operand 355 states and 545 transitions. [2024-12-06 02:44:56,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:56,896 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:56,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:56,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:56,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:57,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:57,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 388 states and 614 transitions. [2024-12-06 02:44:57,241 INFO L276 IsEmpty]: Start isEmpty. Operand 388 states and 614 transitions. [2024-12-06 02:44:57,241 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:57,241 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:57,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:57,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:57,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:57,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:57,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 389 states and 614 transitions. [2024-12-06 02:44:57,326 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 614 transitions. [2024-12-06 02:44:57,326 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:57,326 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:57,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:57,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:57,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:57,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:57,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 390 states and 614 transitions. [2024-12-06 02:44:57,449 INFO L276 IsEmpty]: Start isEmpty. Operand 390 states and 614 transitions. [2024-12-06 02:44:57,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:57,450 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:57,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:57,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:57,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:57,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:57,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 391 states and 614 transitions. [2024-12-06 02:44:57,567 INFO L276 IsEmpty]: Start isEmpty. Operand 391 states and 614 transitions. [2024-12-06 02:44:57,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:57,567 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:57,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:57,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:57,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:57,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:57,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 392 states and 614 transitions. [2024-12-06 02:44:57,676 INFO L276 IsEmpty]: Start isEmpty. Operand 392 states and 614 transitions. [2024-12-06 02:44:57,676 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:57,676 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:57,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:57,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:57,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:57,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:57,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 393 states and 614 transitions. [2024-12-06 02:44:57,767 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 614 transitions. [2024-12-06 02:44:57,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:57,767 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:57,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:57,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:57,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:57,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:57,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 394 states and 614 transitions. [2024-12-06 02:44:57,851 INFO L276 IsEmpty]: Start isEmpty. Operand 394 states and 614 transitions. [2024-12-06 02:44:57,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:57,851 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:57,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:57,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:57,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:57,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:57,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 395 states and 614 transitions. [2024-12-06 02:44:57,960 INFO L276 IsEmpty]: Start isEmpty. Operand 395 states and 614 transitions. [2024-12-06 02:44:57,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:57,961 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:57,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:57,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:58,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:58,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:58,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 638 states to 396 states and 614 transitions. [2024-12-06 02:44:58,040 INFO L276 IsEmpty]: Start isEmpty. Operand 396 states and 614 transitions. [2024-12-06 02:44:58,040 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:58,040 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:58,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:58,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:58,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:58,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:58,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 685 states to 416 states and 655 transitions. [2024-12-06 02:44:58,709 INFO L276 IsEmpty]: Start isEmpty. Operand 416 states and 655 transitions. [2024-12-06 02:44:58,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:58,710 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:58,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:58,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:58,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:59,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:59,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 685 states to 417 states and 655 transitions. [2024-12-06 02:44:59,196 INFO L276 IsEmpty]: Start isEmpty. Operand 417 states and 655 transitions. [2024-12-06 02:44:59,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:59,196 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:59,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:59,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:59,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:44:59,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:44:59,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 685 states to 418 states and 655 transitions. [2024-12-06 02:44:59,693 INFO L276 IsEmpty]: Start isEmpty. Operand 418 states and 655 transitions. [2024-12-06 02:44:59,693 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:44:59,693 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:44:59,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:44:59,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:44:59,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:00,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:00,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 685 states to 419 states and 655 transitions. [2024-12-06 02:45:00,099 INFO L276 IsEmpty]: Start isEmpty. Operand 419 states and 655 transitions. [2024-12-06 02:45:00,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:00,100 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:00,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:00,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:00,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:00,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:00,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 685 states to 420 states and 655 transitions. [2024-12-06 02:45:00,549 INFO L276 IsEmpty]: Start isEmpty. Operand 420 states and 655 transitions. [2024-12-06 02:45:00,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:00,549 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:00,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:00,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:00,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:01,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:01,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 685 states to 421 states and 655 transitions. [2024-12-06 02:45:01,035 INFO L276 IsEmpty]: Start isEmpty. Operand 421 states and 655 transitions. [2024-12-06 02:45:01,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:01,035 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:01,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:01,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:01,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:01,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:01,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 685 states to 422 states and 655 transitions. [2024-12-06 02:45:01,530 INFO L276 IsEmpty]: Start isEmpty. Operand 422 states and 655 transitions. [2024-12-06 02:45:01,530 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:01,530 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:01,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:01,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:01,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:01,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:01,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 748 states to 449 states and 712 transitions. [2024-12-06 02:45:01,991 INFO L276 IsEmpty]: Start isEmpty. Operand 449 states and 712 transitions. [2024-12-06 02:45:01,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:01,992 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:01,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:02,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:02,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:02,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:02,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 748 states to 450 states and 712 transitions. [2024-12-06 02:45:02,073 INFO L276 IsEmpty]: Start isEmpty. Operand 450 states and 712 transitions. [2024-12-06 02:45:02,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:02,073 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:02,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:02,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:02,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:02,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:02,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 748 states to 451 states and 712 transitions. [2024-12-06 02:45:02,174 INFO L276 IsEmpty]: Start isEmpty. Operand 451 states and 712 transitions. [2024-12-06 02:45:02,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:02,174 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:02,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:02,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:02,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:02,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:02,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 748 states to 452 states and 712 transitions. [2024-12-06 02:45:02,269 INFO L276 IsEmpty]: Start isEmpty. Operand 452 states and 712 transitions. [2024-12-06 02:45:02,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:02,269 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:02,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:02,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:02,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:02,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:02,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 748 states to 453 states and 712 transitions. [2024-12-06 02:45:02,377 INFO L276 IsEmpty]: Start isEmpty. Operand 453 states and 712 transitions. [2024-12-06 02:45:02,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:02,377 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:02,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:02,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:02,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:02,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:02,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 771 states to 461 states and 729 transitions. [2024-12-06 02:45:02,975 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 729 transitions. [2024-12-06 02:45:02,976 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:02,976 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:02,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:02,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:03,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:03,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:03,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 771 states to 462 states and 729 transitions. [2024-12-06 02:45:03,378 INFO L276 IsEmpty]: Start isEmpty. Operand 462 states and 729 transitions. [2024-12-06 02:45:03,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:03,379 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:03,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:03,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:03,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:03,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:03,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 771 states to 463 states and 729 transitions. [2024-12-06 02:45:03,784 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 729 transitions. [2024-12-06 02:45:03,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:03,784 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:03,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:03,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:03,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:04,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:04,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 810 states to 478 states and 762 transitions. [2024-12-06 02:45:04,399 INFO L276 IsEmpty]: Start isEmpty. Operand 478 states and 762 transitions. [2024-12-06 02:45:04,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:04,399 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:04,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:04,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:04,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:04,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:04,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 810 states to 479 states and 762 transitions. [2024-12-06 02:45:04,486 INFO L276 IsEmpty]: Start isEmpty. Operand 479 states and 762 transitions. [2024-12-06 02:45:04,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:04,487 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:04,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:04,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:04,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:07,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:07,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 934 states to 527 states and 870 transitions. [2024-12-06 02:45:07,330 INFO L276 IsEmpty]: Start isEmpty. Operand 527 states and 870 transitions. [2024-12-06 02:45:07,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:07,331 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:07,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:07,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:07,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:08,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:08,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 961 states to 533 states and 888 transitions. [2024-12-06 02:45:08,998 INFO L276 IsEmpty]: Start isEmpty. Operand 533 states and 888 transitions. [2024-12-06 02:45:08,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:08,999 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:08,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:09,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:09,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:11,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:11,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 545 states and 925 transitions. [2024-12-06 02:45:11,411 INFO L276 IsEmpty]: Start isEmpty. Operand 545 states and 925 transitions. [2024-12-06 02:45:11,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:11,411 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:11,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:11,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:11,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:11,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:11,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1010 states to 546 states and 928 transitions. [2024-12-06 02:45:11,799 INFO L276 IsEmpty]: Start isEmpty. Operand 546 states and 928 transitions. [2024-12-06 02:45:11,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:11,799 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:11,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:11,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:11,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:12,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:12,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1013 states to 548 states and 931 transitions. [2024-12-06 02:45:12,111 INFO L276 IsEmpty]: Start isEmpty. Operand 548 states and 931 transitions. [2024-12-06 02:45:12,112 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:12,112 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:12,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:12,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:12,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:13,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:13,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1025 states to 554 states and 943 transitions. [2024-12-06 02:45:13,049 INFO L276 IsEmpty]: Start isEmpty. Operand 554 states and 943 transitions. [2024-12-06 02:45:13,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:13,049 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:13,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:13,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:13,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:13,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:13,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1027 states to 555 states and 945 transitions. [2024-12-06 02:45:13,398 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 945 transitions. [2024-12-06 02:45:13,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:13,398 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:13,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:13,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:13,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:19,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:19,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1085 states to 572 states and 994 transitions. [2024-12-06 02:45:19,128 INFO L276 IsEmpty]: Start isEmpty. Operand 572 states and 994 transitions. [2024-12-06 02:45:19,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:19,128 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:19,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:19,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:19,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:22,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:22,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1108 states to 582 states and 1017 transitions. [2024-12-06 02:45:22,661 INFO L276 IsEmpty]: Start isEmpty. Operand 582 states and 1017 transitions. [2024-12-06 02:45:22,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:22,662 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:22,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:22,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:22,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:24,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:24,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1111 states to 584 states and 1020 transitions. [2024-12-06 02:45:24,838 INFO L276 IsEmpty]: Start isEmpty. Operand 584 states and 1020 transitions. [2024-12-06 02:45:24,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:24,838 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:24,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:24,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:24,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:26,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:26,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1113 states to 585 states and 1022 transitions. [2024-12-06 02:45:26,951 INFO L276 IsEmpty]: Start isEmpty. Operand 585 states and 1022 transitions. [2024-12-06 02:45:26,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:26,952 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:26,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:26,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:27,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:29,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:29,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1115 states to 586 states and 1024 transitions. [2024-12-06 02:45:29,196 INFO L276 IsEmpty]: Start isEmpty. Operand 586 states and 1024 transitions. [2024-12-06 02:45:29,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:29,197 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:29,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:29,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:29,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:30,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:30,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1117 states to 587 states and 1026 transitions. [2024-12-06 02:45:30,999 INFO L276 IsEmpty]: Start isEmpty. Operand 587 states and 1026 transitions. [2024-12-06 02:45:30,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:30,999 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:31,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:31,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:31,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:33,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:33,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1123 states to 590 states and 1032 transitions. [2024-12-06 02:45:33,191 INFO L276 IsEmpty]: Start isEmpty. Operand 590 states and 1032 transitions. [2024-12-06 02:45:33,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:33,192 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:33,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:33,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:33,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:38,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:38,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1195 states to 614 states and 1095 transitions. [2024-12-06 02:45:38,270 INFO L276 IsEmpty]: Start isEmpty. Operand 614 states and 1095 transitions. [2024-12-06 02:45:38,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:38,271 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:38,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:38,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:38,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:39,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:39,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1215 states to 623 states and 1115 transitions. [2024-12-06 02:45:39,883 INFO L276 IsEmpty]: Start isEmpty. Operand 623 states and 1115 transitions. [2024-12-06 02:45:39,883 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:39,883 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:39,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:39,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:39,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:40,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:40,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1218 states to 624 states and 1118 transitions. [2024-12-06 02:45:40,434 INFO L276 IsEmpty]: Start isEmpty. Operand 624 states and 1118 transitions. [2024-12-06 02:45:40,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:40,434 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:40,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:40,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:40,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:42,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:42,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1243 states to 635 states and 1143 transitions. [2024-12-06 02:45:42,749 INFO L276 IsEmpty]: Start isEmpty. Operand 635 states and 1143 transitions. [2024-12-06 02:45:42,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:42,750 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:42,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:42,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:42,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:43,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:43,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1245 states to 636 states and 1145 transitions. [2024-12-06 02:45:43,295 INFO L276 IsEmpty]: Start isEmpty. Operand 636 states and 1145 transitions. [2024-12-06 02:45:43,296 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:43,296 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:43,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:43,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:43,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:43,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:43,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1247 states to 637 states and 1147 transitions. [2024-12-06 02:45:43,811 INFO L276 IsEmpty]: Start isEmpty. Operand 637 states and 1147 transitions. [2024-12-06 02:45:43,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:43,811 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:43,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:43,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:43,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:43,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:43,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1249 states to 638 states and 1149 transitions. [2024-12-06 02:45:43,890 INFO L276 IsEmpty]: Start isEmpty. Operand 638 states and 1149 transitions. [2024-12-06 02:45:43,890 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:43,890 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:43,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:43,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:44,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:51,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:51,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1337 states to 668 states and 1228 transitions. [2024-12-06 02:45:51,089 INFO L276 IsEmpty]: Start isEmpty. Operand 668 states and 1228 transitions. [2024-12-06 02:45:51,090 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:51,090 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:51,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:51,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:51,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:52,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:52,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1348 states to 672 states and 1239 transitions. [2024-12-06 02:45:52,807 INFO L276 IsEmpty]: Start isEmpty. Operand 672 states and 1239 transitions. [2024-12-06 02:45:52,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:52,807 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:52,807 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:52,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:52,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:57,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:57,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1398 states to 693 states and 1289 transitions. [2024-12-06 02:45:57,416 INFO L276 IsEmpty]: Start isEmpty. Operand 693 states and 1289 transitions. [2024-12-06 02:45:57,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:57,416 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:57,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:57,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:57,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:58,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:58,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1401 states to 695 states and 1292 transitions. [2024-12-06 02:45:58,150 INFO L276 IsEmpty]: Start isEmpty. Operand 695 states and 1292 transitions. [2024-12-06 02:45:58,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:58,151 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:58,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:58,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:58,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:58,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:58,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1403 states to 696 states and 1294 transitions. [2024-12-06 02:45:58,746 INFO L276 IsEmpty]: Start isEmpty. Operand 696 states and 1294 transitions. [2024-12-06 02:45:58,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:58,746 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:58,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:58,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:58,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:59,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:59,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1405 states to 697 states and 1296 transitions. [2024-12-06 02:45:59,443 INFO L276 IsEmpty]: Start isEmpty. Operand 697 states and 1296 transitions. [2024-12-06 02:45:59,443 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:59,443 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:59,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:59,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:59,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:45:59,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:45:59,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1407 states to 698 states and 1298 transitions. [2024-12-06 02:45:59,525 INFO L276 IsEmpty]: Start isEmpty. Operand 698 states and 1298 transitions. [2024-12-06 02:45:59,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:45:59,525 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:45:59,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:45:59,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:45:59,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:00,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:00,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1409 states to 699 states and 1300 transitions. [2024-12-06 02:46:00,130 INFO L276 IsEmpty]: Start isEmpty. Operand 699 states and 1300 transitions. [2024-12-06 02:46:00,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:46:00,131 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:00,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:00,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:00,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:00,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:00,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1411 states to 700 states and 1302 transitions. [2024-12-06 02:46:00,214 INFO L276 IsEmpty]: Start isEmpty. Operand 700 states and 1302 transitions. [2024-12-06 02:46:00,214 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:46:00,214 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:00,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:00,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:00,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:03,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:03,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1417 states to 706 states and 1298 transitions. [2024-12-06 02:46:03,946 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 1298 transitions. [2024-12-06 02:46:03,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:46:03,947 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:03,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:03,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:03,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:05,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:05,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1411 states to 706 states and 1292 transitions. [2024-12-06 02:46:05,235 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 1292 transitions. [2024-12-06 02:46:05,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:46:05,236 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:05,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:05,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:05,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:05,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:05,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1407 states to 706 states and 1288 transitions. [2024-12-06 02:46:05,600 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 1288 transitions. [2024-12-06 02:46:05,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:46:05,601 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:05,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:05,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:05,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:05,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:05,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1403 states to 706 states and 1284 transitions. [2024-12-06 02:46:05,970 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 1284 transitions. [2024-12-06 02:46:05,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2024-12-06 02:46:05,970 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:05,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:05,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:06,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:06,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:06,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1399 states to 706 states and 1280 transitions. [2024-12-06 02:46:06,308 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 1280 transitions. [2024-12-06 02:46:06,309 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-12-06 02:46:06,309 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:06,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:06,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:06,361 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:06,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:06,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1390 states to 701 states and 1271 transitions. [2024-12-06 02:46:06,637 INFO L276 IsEmpty]: Start isEmpty. Operand 701 states and 1271 transitions. [2024-12-06 02:46:06,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-12-06 02:46:06,638 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:06,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:06,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:06,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:06,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:06,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1386 states to 699 states and 1267 transitions. [2024-12-06 02:46:06,872 INFO L276 IsEmpty]: Start isEmpty. Operand 699 states and 1267 transitions. [2024-12-06 02:46:06,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-12-06 02:46:06,872 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:06,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:06,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:06,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:07,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:07,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1382 states to 697 states and 1263 transitions. [2024-12-06 02:46:07,119 INFO L276 IsEmpty]: Start isEmpty. Operand 697 states and 1263 transitions. [2024-12-06 02:46:07,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-12-06 02:46:07,120 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:07,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:07,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:07,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:07,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:07,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1383 states to 698 states and 1264 transitions. [2024-12-06 02:46:07,374 INFO L276 IsEmpty]: Start isEmpty. Operand 698 states and 1264 transitions. [2024-12-06 02:46:07,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-12-06 02:46:07,374 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:07,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:07,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:07,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:08,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:08,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1384 states to 699 states and 1265 transitions. [2024-12-06 02:46:08,102 INFO L276 IsEmpty]: Start isEmpty. Operand 699 states and 1265 transitions. [2024-12-06 02:46:08,102 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-12-06 02:46:08,102 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:08,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:08,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:08,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:08,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:08,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1385 states to 700 states and 1266 transitions. [2024-12-06 02:46:08,418 INFO L276 IsEmpty]: Start isEmpty. Operand 700 states and 1266 transitions. [2024-12-06 02:46:08,418 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-12-06 02:46:08,418 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:08,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:08,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:08,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:09,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:09,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1386 states to 701 states and 1267 transitions. [2024-12-06 02:46:09,146 INFO L276 IsEmpty]: Start isEmpty. Operand 701 states and 1267 transitions. [2024-12-06 02:46:09,146 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-12-06 02:46:09,146 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:09,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:09,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:09,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:09,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:09,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1387 states to 702 states and 1268 transitions. [2024-12-06 02:46:09,539 INFO L276 IsEmpty]: Start isEmpty. Operand 702 states and 1268 transitions. [2024-12-06 02:46:09,539 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-12-06 02:46:09,539 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:09,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:09,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:09,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:09,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:09,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1388 states to 703 states and 1269 transitions. [2024-12-06 02:46:09,897 INFO L276 IsEmpty]: Start isEmpty. Operand 703 states and 1269 transitions. [2024-12-06 02:46:09,897 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-12-06 02:46:09,897 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:09,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:09,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:09,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:10,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:10,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1389 states to 704 states and 1270 transitions. [2024-12-06 02:46:10,209 INFO L276 IsEmpty]: Start isEmpty. Operand 704 states and 1270 transitions. [2024-12-06 02:46:10,210 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-12-06 02:46:10,210 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:10,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:10,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:10,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:12,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:12,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1390 states to 705 states and 1271 transitions. [2024-12-06 02:46:12,388 INFO L276 IsEmpty]: Start isEmpty. Operand 705 states and 1271 transitions. [2024-12-06 02:46:12,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-12-06 02:46:12,389 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:12,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:12,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:12,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:12,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:12,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1391 states to 706 states and 1272 transitions. [2024-12-06 02:46:12,720 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 1272 transitions. [2024-12-06 02:46:12,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-12-06 02:46:12,720 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:12,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:12,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 02:46:12,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 02:46:12,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 02:46:12,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1337 states to 676 states and 1219 transitions. [2024-12-06 02:46:12,810 INFO L276 IsEmpty]: Start isEmpty. Operand 676 states and 1219 transitions. [2024-12-06 02:46:12,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2024-12-06 02:46:12,811 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 02:46:12,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 02:46:12,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-06 02:46:12,852 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-06 02:46:12,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-06 02:46:13,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-06 02:46:13,066 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-06 02:46:13,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-06 02:46:13,237 WARN L473 CodeCheckObserver]: This program is UNSAFE, Check terminated with 112 iterations. [2024-12-06 02:46:13,375 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 06.12 02:46:13 ImpRootNode [2024-12-06 02:46:13,375 INFO L131 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2024-12-06 02:46:13,375 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-12-06 02:46:13,375 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-12-06 02:46:13,376 INFO L274 PluginConnector]: Witness Printer initialized [2024-12-06 02:46:13,376 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 02:44:45" (3/4) ... [2024-12-06 02:46:13,377 INFO L140 WitnessPrinter]: Generating witness for reachability counterexample [2024-12-06 02:46:13,549 INFO L129 tionWitnessGenerator]: Generated YAML witness of length 146. [2024-12-06 02:46:13,646 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/witness.graphml [2024-12-06 02:46:13,647 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/witness.yml [2024-12-06 02:46:13,647 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-12-06 02:46:13,648 INFO L158 Benchmark]: Toolchain (without parser) took 90517.75ms. Allocated memory was 142.6MB in the beginning and 755.0MB in the end (delta: 612.4MB). Free memory was 117.6MB in the beginning and 568.6MB in the end (delta: -451.0MB). Peak memory consumption was 161.2MB. Max. memory is 16.1GB. [2024-12-06 02:46:13,648 INFO L158 Benchmark]: CDTParser took 0.28ms. Allocated memory is still 142.6MB. Free memory is still 82.8MB. There was no memory consumed. Max. memory is 16.1GB. [2024-12-06 02:46:13,648 INFO L158 Benchmark]: CACSL2BoogieTranslator took 360.69ms. Allocated memory is still 142.6MB. Free memory was 117.4MB in the beginning and 95.1MB in the end (delta: 22.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-12-06 02:46:13,649 INFO L158 Benchmark]: Boogie Procedure Inliner took 45.19ms. Allocated memory is still 142.6MB. Free memory was 95.1MB in the beginning and 91.5MB in the end (delta: 3.6MB). There was no memory consumed. Max. memory is 16.1GB. [2024-12-06 02:46:13,649 INFO L158 Benchmark]: Boogie Preprocessor took 39.24ms. Allocated memory is still 142.6MB. Free memory was 91.3MB in the beginning and 87.7MB in the end (delta: 3.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-12-06 02:46:13,649 INFO L158 Benchmark]: RCFGBuilder took 1453.44ms. Allocated memory is still 142.6MB. Free memory was 87.7MB in the beginning and 56.2MB in the end (delta: 31.5MB). Peak memory consumption was 53.0MB. Max. memory is 16.1GB. [2024-12-06 02:46:13,649 INFO L158 Benchmark]: CodeCheck took 88343.14ms. Allocated memory was 142.6MB in the beginning and 755.0MB in the end (delta: 612.4MB). Free memory was 56.2MB in the beginning and 606.4MB in the end (delta: -550.1MB). Peak memory consumption was 57.9MB. Max. memory is 16.1GB. [2024-12-06 02:46:13,650 INFO L158 Benchmark]: Witness Printer took 271.74ms. Allocated memory is still 755.0MB. Free memory was 606.4MB in the beginning and 568.6MB in the end (delta: 37.7MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2024-12-06 02:46:13,652 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 7 procedures, 205 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 88.2s, OverallIterations: 112, TraceHistogramMax: 0, PathProgramHistogramMax: 0, EmptinessCheckTime: 0.0s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 98418 SdHoareTripleChecker+Valid, 76.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 84466 mSDsluCounter, 171979 SdHoareTripleChecker+Invalid, 68.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 144915 mSDsCounter, 8410 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 58801 IncrementalHoareTripleChecker+Invalid, 67211 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 8410 mSolverCounterUnsat, 27064 mSDtfsCounter, 58801 mSolverCounterSat, 3.4s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 73734 GetRequests, 66699 SyntacticMatches, 6455 SemanticMatches, 580 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 364229 ImplicationChecksByTransitivity, 76.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, InterpolantAutomatonStates: 0, traceCheckStatistics: 0.4s SsaConstructionTime, 0.6s SatisfiabilityAnalysisTime, 6.5s InterpolantComputationTime, 7407 NumberOfCodeBlocks, 7407 NumberOfCodeBlocksAsserted, 112 NumberOfCheckSat, 7228 ConstructedInterpolants, 0 QuantifiedInterpolants, 18791 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 111 InterpolantComputations, 111 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int t8_pc = 0; [L34] int t9_pc = 0; [L35] int t10_pc = 0; [L36] int t11_pc = 0; [L37] int t12_pc = 0; [L38] int t13_pc = 0; [L39] int m_st ; [L40] int t1_st ; [L41] int t2_st ; [L42] int t3_st ; [L43] int t4_st ; [L44] int t5_st ; [L45] int t6_st ; [L46] int t7_st ; [L47] int t8_st ; [L48] int t9_st ; [L49] int t10_st ; [L50] int t11_st ; [L51] int t12_st ; [L52] int t13_st ; [L53] int m_i ; [L54] int t1_i ; [L55] int t2_i ; [L56] int t3_i ; [L57] int t4_i ; [L58] int t5_i ; [L59] int t6_i ; [L60] int t7_i ; [L61] int t8_i ; [L62] int t9_i ; [L63] int t10_i ; [L64] int t11_i ; [L65] int t12_i ; [L66] int t13_i ; [L67] int M_E = 2; [L68] int T1_E = 2; [L69] int T2_E = 2; [L70] int T3_E = 2; [L71] int T4_E = 2; [L72] int T5_E = 2; [L73] int T6_E = 2; [L74] int T7_E = 2; [L75] int T8_E = 2; [L76] int T9_E = 2; [L77] int T10_E = 2; [L78] int T11_E = 2; [L79] int T12_E = 2; [L80] int T13_E = 2; [L81] int E_1 = 2; [L82] int E_2 = 2; [L83] int E_3 = 2; [L84] int E_4 = 2; [L85] int E_5 = 2; [L86] int E_6 = 2; [L87] int E_7 = 2; [L88] int E_8 = 2; [L89] int E_9 = 2; [L90] int E_10 = 2; [L91] int E_11 = 2; [L92] int E_12 = 2; [L93] int E_13 = 2; [L1937] int __retres1 ; [L1941] CALL init_model() [L1840] m_i = 1 [L1841] t1_i = 1 [L1842] t2_i = 1 [L1843] t3_i = 1 [L1844] t4_i = 1 [L1845] t5_i = 1 [L1846] t6_i = 1 [L1847] t7_i = 1 [L1848] t8_i = 1 [L1849] t9_i = 1 [L1850] t10_i = 1 [L1851] t11_i = 1 [L1852] t12_i = 1 [L1853] t13_i = 1 [L1941] RET init_model() [L1942] CALL start_simulation() [L1878] int kernel_st ; [L1879] int tmp ; [L1880] int tmp___0 ; [L1884] kernel_st = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1885] FCALL update_channels() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1886] CALL init_threads() [L881] COND TRUE m_i == 1 [L882] m_st = 0 [L886] COND TRUE t1_i == 1 [L887] t1_st = 0 [L891] COND TRUE t2_i == 1 [L892] t2_st = 0 [L896] COND TRUE t3_i == 1 [L897] t3_st = 0 [L901] COND TRUE t4_i == 1 [L902] t4_st = 0 [L906] COND TRUE t5_i == 1 [L907] t5_st = 0 [L911] COND TRUE t6_i == 1 [L912] t6_st = 0 [L916] COND TRUE t7_i == 1 [L917] t7_st = 0 [L921] COND TRUE t8_i == 1 [L922] t8_st = 0 [L926] COND TRUE t9_i == 1 [L927] t9_st = 0 [L931] COND TRUE t10_i == 1 [L932] t10_st = 0 [L936] COND TRUE t11_i == 1 [L937] t11_st = 0 [L941] COND TRUE t12_i == 1 [L942] t12_st = 0 [L946] COND TRUE t13_i == 1 [L947] t13_st = 0 [L1886] RET init_threads() [L1887] CALL fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1258] COND FALSE !(M_E == 0) [L1263] COND FALSE !(T1_E == 0) [L1268] COND FALSE !(T2_E == 0) [L1273] COND FALSE !(T3_E == 0) [L1278] COND FALSE !(T4_E == 0) [L1283] COND FALSE !(T5_E == 0) [L1288] COND FALSE !(T6_E == 0) [L1293] COND FALSE !(T7_E == 0) [L1298] COND FALSE !(T8_E == 0) [L1303] COND FALSE !(T9_E == 0) [L1308] COND FALSE !(T10_E == 0) [L1313] COND FALSE !(T11_E == 0) [L1318] COND FALSE !(T12_E == 0) [L1323] COND FALSE !(T13_E == 0) [L1328] COND FALSE !(E_1 == 0) [L1333] COND FALSE !(E_2 == 0) [L1338] COND FALSE !(E_3 == 0) [L1343] COND FALSE !(E_4 == 0) [L1348] COND FALSE !(E_5 == 0) [L1353] COND FALSE !(E_6 == 0) [L1358] COND FALSE !(E_7 == 0) [L1363] COND FALSE !(E_8 == 0) [L1368] COND FALSE !(E_9 == 0) [L1373] COND FALSE !(E_10 == 0) [L1378] COND FALSE !(E_11 == 0) [L1383] COND FALSE !(E_12 == 0) [L1388] COND FALSE !(E_13 == 0) [L1887] RET fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1888] CALL activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1541] int tmp ; [L1542] int tmp___0 ; [L1543] int tmp___1 ; [L1544] int tmp___2 ; [L1545] int tmp___3 ; [L1546] int tmp___4 ; [L1547] int tmp___5 ; [L1548] int tmp___6 ; [L1549] int tmp___7 ; [L1550] int tmp___8 ; [L1551] int tmp___9 ; [L1552] int tmp___10 ; [L1553] int tmp___11 ; [L1554] int tmp___12 ; [L1558] CALL, EXPR is_master_triggered() [L604] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L607] COND FALSE !(m_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L617] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L619] return (__retres1); [L1558] RET, EXPR is_master_triggered() [L1558] tmp = is_master_triggered() [L1560] COND FALSE !(\read(tmp)) [L1566] CALL, EXPR is_transmit1_triggered() [L623] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L626] COND FALSE !(t1_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L636] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L638] return (__retres1); [L1566] RET, EXPR is_transmit1_triggered() [L1566] tmp___0 = is_transmit1_triggered() [L1568] COND FALSE !(\read(tmp___0)) [L1574] CALL, EXPR is_transmit2_triggered() [L642] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L645] COND FALSE !(t2_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L655] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L657] return (__retres1); [L1574] RET, EXPR is_transmit2_triggered() [L1574] tmp___1 = is_transmit2_triggered() [L1576] COND FALSE !(\read(tmp___1)) [L1582] CALL, EXPR is_transmit3_triggered() [L661] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L664] COND FALSE !(t3_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L674] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L676] return (__retres1); [L1582] RET, EXPR is_transmit3_triggered() [L1582] tmp___2 = is_transmit3_triggered() [L1584] COND FALSE !(\read(tmp___2)) [L1590] CALL, EXPR is_transmit4_triggered() [L680] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L683] COND FALSE !(t4_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L693] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L695] return (__retres1); [L1590] RET, EXPR is_transmit4_triggered() [L1590] tmp___3 = is_transmit4_triggered() [L1592] COND FALSE !(\read(tmp___3)) [L1598] CALL, EXPR is_transmit5_triggered() [L699] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L702] COND FALSE !(t5_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L712] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L714] return (__retres1); [L1598] RET, EXPR is_transmit5_triggered() [L1598] tmp___4 = is_transmit5_triggered() [L1600] COND FALSE !(\read(tmp___4)) [L1606] CALL, EXPR is_transmit6_triggered() [L718] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L721] COND FALSE !(t6_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L731] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L733] return (__retres1); [L1606] RET, EXPR is_transmit6_triggered() [L1606] tmp___5 = is_transmit6_triggered() [L1608] COND FALSE !(\read(tmp___5)) [L1614] CALL, EXPR is_transmit7_triggered() [L737] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L740] COND FALSE !(t7_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L750] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L752] return (__retres1); [L1614] RET, EXPR is_transmit7_triggered() [L1614] tmp___6 = is_transmit7_triggered() [L1616] COND FALSE !(\read(tmp___6)) [L1622] CALL, EXPR is_transmit8_triggered() [L756] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L759] COND FALSE !(t8_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L769] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L771] return (__retres1); [L1622] RET, EXPR is_transmit8_triggered() [L1622] tmp___7 = is_transmit8_triggered() [L1624] COND FALSE !(\read(tmp___7)) [L1630] CALL, EXPR is_transmit9_triggered() [L775] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L778] COND FALSE !(t9_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L788] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L790] return (__retres1); [L1630] RET, EXPR is_transmit9_triggered() [L1630] tmp___8 = is_transmit9_triggered() [L1632] COND FALSE !(\read(tmp___8)) [L1638] CALL, EXPR is_transmit10_triggered() [L794] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L797] COND FALSE !(t10_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L807] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L809] return (__retres1); [L1638] RET, EXPR is_transmit10_triggered() [L1638] tmp___9 = is_transmit10_triggered() [L1640] COND FALSE !(\read(tmp___9)) [L1646] CALL, EXPR is_transmit11_triggered() [L813] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L816] COND FALSE !(t11_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L826] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L828] return (__retres1); [L1646] RET, EXPR is_transmit11_triggered() [L1646] tmp___10 = is_transmit11_triggered() [L1648] COND FALSE !(\read(tmp___10)) [L1654] CALL, EXPR is_transmit12_triggered() [L832] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L835] COND FALSE !(t12_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L845] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L847] return (__retres1); [L1654] RET, EXPR is_transmit12_triggered() [L1654] tmp___11 = is_transmit12_triggered() [L1656] COND FALSE !(\read(tmp___11)) [L1662] CALL, EXPR is_transmit13_triggered() [L851] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L854] COND FALSE !(t13_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L864] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L866] return (__retres1); [L1662] RET, EXPR is_transmit13_triggered() [L1662] tmp___12 = is_transmit13_triggered() [L1664] COND FALSE !(\read(tmp___12)) [L1888] RET activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1889] CALL reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1401] COND FALSE !(M_E == 1) [L1406] COND FALSE !(T1_E == 1) [L1411] COND FALSE !(T2_E == 1) [L1416] COND FALSE !(T3_E == 1) [L1421] COND FALSE !(T4_E == 1) [L1426] COND FALSE !(T5_E == 1) [L1431] COND FALSE !(T6_E == 1) [L1436] COND FALSE !(T7_E == 1) [L1441] COND FALSE !(T8_E == 1) [L1446] COND FALSE !(T9_E == 1) [L1451] COND FALSE !(T10_E == 1) [L1456] COND FALSE !(T11_E == 1) [L1461] COND FALSE !(T12_E == 1) [L1466] COND FALSE !(T13_E == 1) [L1471] COND FALSE !(E_1 == 1) [L1476] COND FALSE !(E_2 == 1) [L1481] COND FALSE !(E_3 == 1) [L1486] COND FALSE !(E_4 == 1) [L1491] COND FALSE !(E_5 == 1) [L1496] COND FALSE !(E_6 == 1) [L1501] COND FALSE !(E_7 == 1) [L1506] COND FALSE !(E_8 == 1) [L1511] COND FALSE !(E_9 == 1) [L1516] COND FALSE !(E_10 == 1) [L1521] COND FALSE !(E_11 == 1) [L1526] COND FALSE !(E_12 == 1) [L1531] COND FALSE !(E_13 == 1) [L1889] RET reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1895] kernel_st = 1 [L1896] CALL eval() [L1037] int tmp ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1044] CALL, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L956] int __retres1 ; [L959] COND TRUE m_st == 0 [L960] __retres1 = 1 [L1032] return (__retres1); [L1044] RET, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1044] tmp = exists_runnable_thread() [L1046] COND TRUE \read(tmp) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1051] COND TRUE m_st == 0 [L1052] int tmp_ndt_1; [L1053] tmp_ndt_1 = __VERIFIER_nondet_int() [L1054] COND FALSE !(\read(tmp_ndt_1)) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1065] COND TRUE t1_st == 0 [L1066] int tmp_ndt_2; [L1067] tmp_ndt_2 = __VERIFIER_nondet_int() [L1068] COND FALSE !(\read(tmp_ndt_2)) [L1074] CALL error() [L21] reach_error() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.28ms. Allocated memory is still 142.6MB. Free memory is still 82.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 360.69ms. Allocated memory is still 142.6MB. Free memory was 117.4MB in the beginning and 95.1MB in the end (delta: 22.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 45.19ms. Allocated memory is still 142.6MB. Free memory was 95.1MB in the beginning and 91.5MB in the end (delta: 3.6MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 39.24ms. Allocated memory is still 142.6MB. Free memory was 91.3MB in the beginning and 87.7MB in the end (delta: 3.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 1453.44ms. Allocated memory is still 142.6MB. Free memory was 87.7MB in the beginning and 56.2MB in the end (delta: 31.5MB). Peak memory consumption was 53.0MB. Max. memory is 16.1GB. * CodeCheck took 88343.14ms. Allocated memory was 142.6MB in the beginning and 755.0MB in the end (delta: 612.4MB). Free memory was 56.2MB in the beginning and 606.4MB in the end (delta: -550.1MB). Peak memory consumption was 57.9MB. Max. memory is 16.1GB. * Witness Printer took 271.74ms. Allocated memory is still 755.0MB. Free memory was 606.4MB in the beginning and 568.6MB in the end (delta: 37.7MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. RESULT: Ultimate proved your program to be incorrect! [2024-12-06 02:46:13,673 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4f78f78-18a2-42c8-bcf9-ec76cd811593/bin/ukojak-verify-CZk0znPC7b/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE