./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/config/KojakReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.16.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/config/svcomp-Reach-32bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-12-06 05:33:47,683 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-12-06 05:33:47,735 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/config/svcomp-Reach-32bit-Kojak_Default.epf [2024-12-06 05:33:47,739 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-12-06 05:33:47,739 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck.Interpolating solver [2024-12-06 05:33:47,756 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-12-06 05:33:47,757 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-12-06 05:33:47,757 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ALWAYS [2024-12-06 05:33:47,757 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-12-06 05:33:47,757 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-12-06 05:33:47,758 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-12-06 05:33:47,758 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-12-06 05:33:47,758 INFO L153 SettingsManager]: * sizeof long=4 [2024-12-06 05:33:47,758 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-12-06 05:33:47,758 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-12-06 05:33:47,758 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-12-06 05:33:47,758 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-12-06 05:33:47,758 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-12-06 05:33:47,758 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-12-06 05:33:47,758 INFO L153 SettingsManager]: * sizeof long double=12 [2024-12-06 05:33:47,758 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-12-06 05:33:47,758 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-12-06 05:33:47,758 INFO L153 SettingsManager]: * Use constant arrays=true [2024-12-06 05:33:47,759 INFO L151 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2024-12-06 05:33:47,759 INFO L153 SettingsManager]: * Timeout in seconds=1000000 [2024-12-06 05:33:47,759 INFO L153 SettingsManager]: * Theory for external solver=ALL [2024-12-06 05:33:47,759 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-12-06 05:33:47,759 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2024-12-06 05:33:47,759 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-12-06 05:33:47,759 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-12-06 05:33:47,759 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-12-06 05:33:47,759 INFO L153 SettingsManager]: * Trace refinement strategy=PENGUIN [2024-12-06 05:33:47,759 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-12-06 05:33:47,759 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 [2024-12-06 05:33:47,980 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-12-06 05:33:47,988 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-12-06 05:33:47,990 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-12-06 05:33:47,991 INFO L270 PluginConnector]: Initializing CDTParser... [2024-12-06 05:33:47,992 INFO L274 PluginConnector]: CDTParser initialized [2024-12-06 05:33:47,993 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/../../sv-benchmarks/c/systemc/transmitter.16.cil.c [2024-12-06 05:33:50,668 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/data/3a6591ff2/757e6e1313ee46909ebe7d83603c3044/FLAG97d390ff6 [2024-12-06 05:33:50,889 INFO L384 CDTParser]: Found 1 translation units. [2024-12-06 05:33:50,889 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/sv-benchmarks/c/systemc/transmitter.16.cil.c [2024-12-06 05:33:50,902 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/data/3a6591ff2/757e6e1313ee46909ebe7d83603c3044/FLAG97d390ff6 [2024-12-06 05:33:50,916 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/data/3a6591ff2/757e6e1313ee46909ebe7d83603c3044 [2024-12-06 05:33:50,918 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-12-06 05:33:50,919 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-12-06 05:33:50,920 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-12-06 05:33:50,921 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-12-06 05:33:50,925 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-12-06 05:33:50,926 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 05:33:50" (1/1) ... [2024-12-06 05:33:50,926 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1b7f9f7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:33:50, skipping insertion in model container [2024-12-06 05:33:50,927 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.12 05:33:50" (1/1) ... [2024-12-06 05:33:50,957 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-12-06 05:33:51,086 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2024-12-06 05:33:51,219 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-06 05:33:51,231 INFO L200 MainTranslator]: Completed pre-run [2024-12-06 05:33:51,240 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2024-12-06 05:33:51,292 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-06 05:33:51,312 INFO L204 MainTranslator]: Completed translation [2024-12-06 05:33:51,313 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:33:51 WrapperNode [2024-12-06 05:33:51,313 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-12-06 05:33:51,314 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-12-06 05:33:51,314 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-12-06 05:33:51,314 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-12-06 05:33:51,320 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:33:51" (1/1) ... [2024-12-06 05:33:51,331 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:33:51" (1/1) ... [2024-12-06 05:33:51,367 INFO L138 Inliner]: procedures = 56, calls = 71, calls flagged for inlining = 40, calls inlined = 40, statements flattened = 956 [2024-12-06 05:33:51,367 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-12-06 05:33:51,368 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-12-06 05:33:51,368 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-12-06 05:33:51,368 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-12-06 05:33:51,376 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:33:51" (1/1) ... [2024-12-06 05:33:51,376 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:33:51" (1/1) ... [2024-12-06 05:33:51,380 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:33:51" (1/1) ... [2024-12-06 05:33:51,380 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:33:51" (1/1) ... [2024-12-06 05:33:51,392 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:33:51" (1/1) ... [2024-12-06 05:33:51,394 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:33:51" (1/1) ... [2024-12-06 05:33:51,407 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:33:51" (1/1) ... [2024-12-06 05:33:51,410 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:33:51" (1/1) ... [2024-12-06 05:33:51,413 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:33:51" (1/1) ... [2024-12-06 05:33:51,417 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-12-06 05:33:51,418 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-12-06 05:33:51,418 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-12-06 05:33:51,418 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-12-06 05:33:51,419 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.12 05:33:51" (1/1) ... [2024-12-06 05:33:51,425 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2024-12-06 05:33:51,437 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/z3 [2024-12-06 05:33:51,449 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) [2024-12-06 05:33:51,451 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Waiting until timeout for monitored process [2024-12-06 05:33:51,476 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-12-06 05:33:51,476 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2024-12-06 05:33:51,476 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2024-12-06 05:33:51,476 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2024-12-06 05:33:51,477 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2024-12-06 05:33:51,477 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2024-12-06 05:33:51,477 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2024-12-06 05:33:51,477 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2024-12-06 05:33:51,477 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2024-12-06 05:33:51,477 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2024-12-06 05:33:51,477 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2024-12-06 05:33:51,477 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2024-12-06 05:33:51,477 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2024-12-06 05:33:51,477 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2024-12-06 05:33:51,477 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-12-06 05:33:51,477 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-12-06 05:33:51,585 INFO L234 CfgBuilder]: Building ICFG [2024-12-06 05:33:51,587 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-12-06 05:33:52,442 INFO L? ?]: Removed 109 outVars from TransFormulas that were not future-live. [2024-12-06 05:33:52,442 INFO L283 CfgBuilder]: Performing block encoding [2024-12-06 05:33:52,941 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-12-06 05:33:52,942 INFO L312 CfgBuilder]: Removed 36 assume(true) statements. [2024-12-06 05:33:52,942 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 05:33:52 BoogieIcfgContainer [2024-12-06 05:33:52,942 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-12-06 05:33:52,943 INFO L112 PluginConnector]: ------------------------CodeCheck---------------------------- [2024-12-06 05:33:52,943 INFO L270 PluginConnector]: Initializing CodeCheck... [2024-12-06 05:33:52,950 INFO L274 PluginConnector]: CodeCheck initialized [2024-12-06 05:33:52,950 INFO L184 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 05:33:52" (1/1) ... [2024-12-06 05:33:52,957 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-06 05:33:52,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:33:53,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 209 states and 317 transitions. [2024-12-06 05:33:53,004 INFO L276 IsEmpty]: Start isEmpty. Operand 209 states and 317 transitions. [2024-12-06 05:33:53,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:33:53,008 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:33:53,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:33:53,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:33:53,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:33:54,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:33:54,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 253 states and 403 transitions. [2024-12-06 05:33:54,269 INFO L276 IsEmpty]: Start isEmpty. Operand 253 states and 403 transitions. [2024-12-06 05:33:54,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:33:54,271 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:33:54,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:33:54,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:33:54,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:33:54,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:33:54,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 254 states and 403 transitions. [2024-12-06 05:33:54,936 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 403 transitions. [2024-12-06 05:33:54,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:33:54,938 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:33:54,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:33:54,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:33:55,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:33:55,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:33:55,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 255 states and 403 transitions. [2024-12-06 05:33:55,535 INFO L276 IsEmpty]: Start isEmpty. Operand 255 states and 403 transitions. [2024-12-06 05:33:55,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:33:55,537 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:33:55,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:33:55,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:33:55,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:33:56,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:33:56,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 256 states and 403 transitions. [2024-12-06 05:33:56,115 INFO L276 IsEmpty]: Start isEmpty. Operand 256 states and 403 transitions. [2024-12-06 05:33:56,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:33:56,117 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:33:56,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:33:56,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:33:56,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:33:56,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:33:56,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 257 states and 403 transitions. [2024-12-06 05:33:56,667 INFO L276 IsEmpty]: Start isEmpty. Operand 257 states and 403 transitions. [2024-12-06 05:33:56,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:33:56,668 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:33:56,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:33:56,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:33:56,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:33:57,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:33:57,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 258 states and 403 transitions. [2024-12-06 05:33:57,208 INFO L276 IsEmpty]: Start isEmpty. Operand 258 states and 403 transitions. [2024-12-06 05:33:57,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:33:57,209 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:33:57,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:33:57,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:33:57,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:33:57,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:33:57,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 259 states and 403 transitions. [2024-12-06 05:33:57,737 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states and 403 transitions. [2024-12-06 05:33:57,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:33:57,738 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:33:57,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:33:57,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:33:57,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:33:58,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:33:58,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 260 states and 403 transitions. [2024-12-06 05:33:58,300 INFO L276 IsEmpty]: Start isEmpty. Operand 260 states and 403 transitions. [2024-12-06 05:33:58,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:33:58,301 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:33:58,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:33:58,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:33:58,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:33:58,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:33:58,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 261 states and 403 transitions. [2024-12-06 05:33:58,807 INFO L276 IsEmpty]: Start isEmpty. Operand 261 states and 403 transitions. [2024-12-06 05:33:58,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:33:58,808 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:33:58,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:33:58,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:33:58,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:33:59,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:33:59,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 262 states and 403 transitions. [2024-12-06 05:33:59,333 INFO L276 IsEmpty]: Start isEmpty. Operand 262 states and 403 transitions. [2024-12-06 05:33:59,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:33:59,334 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:33:59,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:33:59,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:33:59,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:33:59,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:33:59,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 263 states and 403 transitions. [2024-12-06 05:33:59,898 INFO L276 IsEmpty]: Start isEmpty. Operand 263 states and 403 transitions. [2024-12-06 05:33:59,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:33:59,899 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:33:59,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:33:59,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:33:59,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:00,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:00,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 264 states and 403 transitions. [2024-12-06 05:34:00,481 INFO L276 IsEmpty]: Start isEmpty. Operand 264 states and 403 transitions. [2024-12-06 05:34:00,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:00,482 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:00,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:00,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:00,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:01,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:01,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 265 states and 403 transitions. [2024-12-06 05:34:01,007 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 403 transitions. [2024-12-06 05:34:01,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:01,008 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:01,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:01,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:01,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:01,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:01,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 266 states and 403 transitions. [2024-12-06 05:34:01,544 INFO L276 IsEmpty]: Start isEmpty. Operand 266 states and 403 transitions. [2024-12-06 05:34:01,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:01,545 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:01,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:01,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:01,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:02,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:02,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 267 states and 403 transitions. [2024-12-06 05:34:02,118 INFO L276 IsEmpty]: Start isEmpty. Operand 267 states and 403 transitions. [2024-12-06 05:34:02,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:02,119 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:02,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:02,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:02,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:02,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:02,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 309 states and 488 transitions. [2024-12-06 05:34:02,765 INFO L276 IsEmpty]: Start isEmpty. Operand 309 states and 488 transitions. [2024-12-06 05:34:02,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:02,766 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:02,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:02,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:02,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:02,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:02,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 310 states and 488 transitions. [2024-12-06 05:34:02,989 INFO L276 IsEmpty]: Start isEmpty. Operand 310 states and 488 transitions. [2024-12-06 05:34:02,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:02,990 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:02,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:03,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:03,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:03,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:03,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 311 states and 488 transitions. [2024-12-06 05:34:03,163 INFO L276 IsEmpty]: Start isEmpty. Operand 311 states and 488 transitions. [2024-12-06 05:34:03,164 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:03,164 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:03,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:03,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:03,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:03,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:03,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 312 states and 488 transitions. [2024-12-06 05:34:03,351 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 488 transitions. [2024-12-06 05:34:03,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:03,352 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:03,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:03,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:03,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:03,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:03,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 313 states and 488 transitions. [2024-12-06 05:34:03,527 INFO L276 IsEmpty]: Start isEmpty. Operand 313 states and 488 transitions. [2024-12-06 05:34:03,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:03,528 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:03,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:03,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:03,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:03,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:03,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 314 states and 488 transitions. [2024-12-06 05:34:03,705 INFO L276 IsEmpty]: Start isEmpty. Operand 314 states and 488 transitions. [2024-12-06 05:34:03,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:03,705 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:03,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:03,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:03,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:03,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:03,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 315 states and 488 transitions. [2024-12-06 05:34:03,878 INFO L276 IsEmpty]: Start isEmpty. Operand 315 states and 488 transitions. [2024-12-06 05:34:03,878 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:03,878 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:03,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:03,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:03,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:04,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:04,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 316 states and 488 transitions. [2024-12-06 05:34:04,043 INFO L276 IsEmpty]: Start isEmpty. Operand 316 states and 488 transitions. [2024-12-06 05:34:04,043 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:04,043 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:04,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:04,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:04,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:04,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:04,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 317 states and 488 transitions. [2024-12-06 05:34:04,166 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 488 transitions. [2024-12-06 05:34:04,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:04,166 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:04,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:04,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:04,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:04,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:04,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 318 states and 488 transitions. [2024-12-06 05:34:04,313 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 488 transitions. [2024-12-06 05:34:04,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:04,314 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:04,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:04,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:04,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:04,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:04,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 319 states and 488 transitions. [2024-12-06 05:34:04,504 INFO L276 IsEmpty]: Start isEmpty. Operand 319 states and 488 transitions. [2024-12-06 05:34:04,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:04,505 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:04,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:04,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:04,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:04,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:04,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 320 states and 488 transitions. [2024-12-06 05:34:04,639 INFO L276 IsEmpty]: Start isEmpty. Operand 320 states and 488 transitions. [2024-12-06 05:34:04,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:04,639 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:04,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:04,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:04,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:04,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:04,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 500 states to 321 states and 488 transitions. [2024-12-06 05:34:04,748 INFO L276 IsEmpty]: Start isEmpty. Operand 321 states and 488 transitions. [2024-12-06 05:34:04,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:04,749 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:04,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:04,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:04,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:05,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:05,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 360 states and 569 transitions. [2024-12-06 05:34:05,047 INFO L276 IsEmpty]: Start isEmpty. Operand 360 states and 569 transitions. [2024-12-06 05:34:05,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:05,048 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:05,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:05,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:05,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:05,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:05,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 361 states and 569 transitions. [2024-12-06 05:34:05,149 INFO L276 IsEmpty]: Start isEmpty. Operand 361 states and 569 transitions. [2024-12-06 05:34:05,150 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:05,150 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:05,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:05,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:05,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:05,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:05,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 362 states and 569 transitions. [2024-12-06 05:34:05,248 INFO L276 IsEmpty]: Start isEmpty. Operand 362 states and 569 transitions. [2024-12-06 05:34:05,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:05,249 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:05,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:05,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:05,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:05,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:05,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 363 states and 569 transitions. [2024-12-06 05:34:05,355 INFO L276 IsEmpty]: Start isEmpty. Operand 363 states and 569 transitions. [2024-12-06 05:34:05,356 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:05,356 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:05,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:05,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:05,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:05,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:05,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 364 states and 569 transitions. [2024-12-06 05:34:05,451 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 569 transitions. [2024-12-06 05:34:05,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:05,452 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:05,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:05,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:05,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:05,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:05,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 365 states and 569 transitions. [2024-12-06 05:34:05,540 INFO L276 IsEmpty]: Start isEmpty. Operand 365 states and 569 transitions. [2024-12-06 05:34:05,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:05,540 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:05,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:05,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:05,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:05,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:05,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 366 states and 569 transitions. [2024-12-06 05:34:05,639 INFO L276 IsEmpty]: Start isEmpty. Operand 366 states and 569 transitions. [2024-12-06 05:34:05,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:05,640 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:05,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:05,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:05,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:05,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:05,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 367 states and 569 transitions. [2024-12-06 05:34:05,763 INFO L276 IsEmpty]: Start isEmpty. Operand 367 states and 569 transitions. [2024-12-06 05:34:05,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:05,764 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:05,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:05,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:05,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:05,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:05,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 368 states and 569 transitions. [2024-12-06 05:34:05,877 INFO L276 IsEmpty]: Start isEmpty. Operand 368 states and 569 transitions. [2024-12-06 05:34:05,878 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:05,878 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:05,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:05,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:05,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:05,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:05,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 369 states and 569 transitions. [2024-12-06 05:34:05,971 INFO L276 IsEmpty]: Start isEmpty. Operand 369 states and 569 transitions. [2024-12-06 05:34:05,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:05,971 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:05,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:05,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:06,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:06,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:06,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 370 states and 569 transitions. [2024-12-06 05:34:06,091 INFO L276 IsEmpty]: Start isEmpty. Operand 370 states and 569 transitions. [2024-12-06 05:34:06,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:06,091 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:06,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:06,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:06,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:06,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:06,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 371 states and 569 transitions. [2024-12-06 05:34:06,237 INFO L276 IsEmpty]: Start isEmpty. Operand 371 states and 569 transitions. [2024-12-06 05:34:06,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:06,238 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:06,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:06,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:06,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:06,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:06,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 407 states and 644 transitions. [2024-12-06 05:34:06,569 INFO L276 IsEmpty]: Start isEmpty. Operand 407 states and 644 transitions. [2024-12-06 05:34:06,569 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:06,569 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:06,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:06,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:06,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:06,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:06,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 408 states and 644 transitions. [2024-12-06 05:34:06,658 INFO L276 IsEmpty]: Start isEmpty. Operand 408 states and 644 transitions. [2024-12-06 05:34:06,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:06,659 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:06,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:06,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:06,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:06,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:06,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 409 states and 644 transitions. [2024-12-06 05:34:06,754 INFO L276 IsEmpty]: Start isEmpty. Operand 409 states and 644 transitions. [2024-12-06 05:34:06,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:06,755 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:06,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:06,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:06,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:06,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:06,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 410 states and 644 transitions. [2024-12-06 05:34:06,837 INFO L276 IsEmpty]: Start isEmpty. Operand 410 states and 644 transitions. [2024-12-06 05:34:06,837 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:06,837 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:06,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:06,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:06,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:06,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:06,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 411 states and 644 transitions. [2024-12-06 05:34:06,915 INFO L276 IsEmpty]: Start isEmpty. Operand 411 states and 644 transitions. [2024-12-06 05:34:06,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:06,916 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:06,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:06,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:06,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:07,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:07,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 412 states and 644 transitions. [2024-12-06 05:34:07,001 INFO L276 IsEmpty]: Start isEmpty. Operand 412 states and 644 transitions. [2024-12-06 05:34:07,001 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:07,001 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:07,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:07,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:07,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:07,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:07,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 413 states and 644 transitions. [2024-12-06 05:34:07,078 INFO L276 IsEmpty]: Start isEmpty. Operand 413 states and 644 transitions. [2024-12-06 05:34:07,078 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:07,078 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:07,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:07,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:07,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:07,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:07,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 414 states and 644 transitions. [2024-12-06 05:34:07,164 INFO L276 IsEmpty]: Start isEmpty. Operand 414 states and 644 transitions. [2024-12-06 05:34:07,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:07,165 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:07,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:07,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:07,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:07,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:07,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 415 states and 644 transitions. [2024-12-06 05:34:07,257 INFO L276 IsEmpty]: Start isEmpty. Operand 415 states and 644 transitions. [2024-12-06 05:34:07,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:07,258 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:07,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:07,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:07,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:07,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:07,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 416 states and 644 transitions. [2024-12-06 05:34:07,339 INFO L276 IsEmpty]: Start isEmpty. Operand 416 states and 644 transitions. [2024-12-06 05:34:07,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:07,339 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:07,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:07,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:07,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:08,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:08,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 439 states and 691 transitions. [2024-12-06 05:34:08,027 INFO L276 IsEmpty]: Start isEmpty. Operand 439 states and 691 transitions. [2024-12-06 05:34:08,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:08,027 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:08,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:08,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:08,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:08,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:08,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 440 states and 691 transitions. [2024-12-06 05:34:08,559 INFO L276 IsEmpty]: Start isEmpty. Operand 440 states and 691 transitions. [2024-12-06 05:34:08,560 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:08,560 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:08,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:08,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:08,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:09,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:09,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 441 states and 691 transitions. [2024-12-06 05:34:09,098 INFO L276 IsEmpty]: Start isEmpty. Operand 441 states and 691 transitions. [2024-12-06 05:34:09,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:09,099 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:09,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:09,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:09,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:09,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:09,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 442 states and 691 transitions. [2024-12-06 05:34:09,603 INFO L276 IsEmpty]: Start isEmpty. Operand 442 states and 691 transitions. [2024-12-06 05:34:09,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:09,603 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:09,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:09,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:09,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:10,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:10,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 443 states and 691 transitions. [2024-12-06 05:34:10,108 INFO L276 IsEmpty]: Start isEmpty. Operand 443 states and 691 transitions. [2024-12-06 05:34:10,108 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:10,108 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:10,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:10,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:10,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:10,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:10,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 444 states and 691 transitions. [2024-12-06 05:34:10,634 INFO L276 IsEmpty]: Start isEmpty. Operand 444 states and 691 transitions. [2024-12-06 05:34:10,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:10,635 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:10,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:10,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:10,678 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:11,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:11,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 445 states and 691 transitions. [2024-12-06 05:34:11,150 INFO L276 IsEmpty]: Start isEmpty. Operand 445 states and 691 transitions. [2024-12-06 05:34:11,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:11,151 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:11,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:11,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:11,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:11,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:11,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 721 states to 446 states and 691 transitions. [2024-12-06 05:34:11,664 INFO L276 IsEmpty]: Start isEmpty. Operand 446 states and 691 transitions. [2024-12-06 05:34:11,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:11,664 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:11,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:11,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:11,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:12,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:12,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 476 states and 754 transitions. [2024-12-06 05:34:12,173 INFO L276 IsEmpty]: Start isEmpty. Operand 476 states and 754 transitions. [2024-12-06 05:34:12,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:12,174 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:12,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:12,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:12,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:12,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:12,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 477 states and 754 transitions. [2024-12-06 05:34:12,252 INFO L276 IsEmpty]: Start isEmpty. Operand 477 states and 754 transitions. [2024-12-06 05:34:12,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:12,252 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:12,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:12,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:12,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:12,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:12,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 478 states and 754 transitions. [2024-12-06 05:34:12,328 INFO L276 IsEmpty]: Start isEmpty. Operand 478 states and 754 transitions. [2024-12-06 05:34:12,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:12,329 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:12,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:12,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:12,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:12,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:12,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 479 states and 754 transitions. [2024-12-06 05:34:12,439 INFO L276 IsEmpty]: Start isEmpty. Operand 479 states and 754 transitions. [2024-12-06 05:34:12,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:12,440 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:12,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:12,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:12,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:12,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:12,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 480 states and 754 transitions. [2024-12-06 05:34:12,538 INFO L276 IsEmpty]: Start isEmpty. Operand 480 states and 754 transitions. [2024-12-06 05:34:12,538 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:12,538 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:12,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:12,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:12,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:12,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:12,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 481 states and 754 transitions. [2024-12-06 05:34:12,630 INFO L276 IsEmpty]: Start isEmpty. Operand 481 states and 754 transitions. [2024-12-06 05:34:12,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:12,631 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:12,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:12,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:12,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:13,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:13,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 819 states to 492 states and 777 transitions. [2024-12-06 05:34:13,268 INFO L276 IsEmpty]: Start isEmpty. Operand 492 states and 777 transitions. [2024-12-06 05:34:13,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:13,268 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:13,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:13,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:13,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:13,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:13,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 819 states to 493 states and 777 transitions. [2024-12-06 05:34:13,733 INFO L276 IsEmpty]: Start isEmpty. Operand 493 states and 777 transitions. [2024-12-06 05:34:13,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:13,734 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:13,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:13,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:13,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:14,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:14,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 819 states to 494 states and 777 transitions. [2024-12-06 05:34:14,219 INFO L276 IsEmpty]: Start isEmpty. Operand 494 states and 777 transitions. [2024-12-06 05:34:14,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:14,220 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:14,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:14,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:14,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:14,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:14,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 819 states to 495 states and 777 transitions. [2024-12-06 05:34:14,695 INFO L276 IsEmpty]: Start isEmpty. Operand 495 states and 777 transitions. [2024-12-06 05:34:14,695 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:14,695 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:14,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:14,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:14,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:15,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:15,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 864 states to 513 states and 816 transitions. [2024-12-06 05:34:15,249 INFO L276 IsEmpty]: Start isEmpty. Operand 513 states and 816 transitions. [2024-12-06 05:34:15,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:15,249 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:15,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:15,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:15,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:15,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:15,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 864 states to 514 states and 816 transitions. [2024-12-06 05:34:15,332 INFO L276 IsEmpty]: Start isEmpty. Operand 514 states and 816 transitions. [2024-12-06 05:34:15,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:15,333 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:15,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:15,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:15,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:15,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:15,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 864 states to 515 states and 816 transitions. [2024-12-06 05:34:15,416 INFO L276 IsEmpty]: Start isEmpty. Operand 515 states and 816 transitions. [2024-12-06 05:34:15,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:15,416 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:15,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:15,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:15,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:15,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:15,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 891 states to 524 states and 837 transitions. [2024-12-06 05:34:15,899 INFO L276 IsEmpty]: Start isEmpty. Operand 524 states and 837 transitions. [2024-12-06 05:34:15,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:15,899 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:15,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:15,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:16,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:19,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:19,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1024 states to 575 states and 953 transitions. [2024-12-06 05:34:19,351 INFO L276 IsEmpty]: Start isEmpty. Operand 575 states and 953 transitions. [2024-12-06 05:34:19,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:19,352 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:19,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:19,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:19,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:21,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:21,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1053 states to 581 states and 973 transitions. [2024-12-06 05:34:21,215 INFO L276 IsEmpty]: Start isEmpty. Operand 581 states and 973 transitions. [2024-12-06 05:34:21,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:21,215 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:21,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:21,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:21,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:21,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:21,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1059 states to 584 states and 979 transitions. [2024-12-06 05:34:21,857 INFO L276 IsEmpty]: Start isEmpty. Operand 584 states and 979 transitions. [2024-12-06 05:34:21,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:21,858 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:21,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:21,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:22,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:25,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:25,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1112 states to 599 states and 1023 transitions. [2024-12-06 05:34:25,144 INFO L276 IsEmpty]: Start isEmpty. Operand 599 states and 1023 transitions. [2024-12-06 05:34:25,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:25,144 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:25,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:25,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:25,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:26,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:26,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1126 states to 605 states and 1037 transitions. [2024-12-06 05:34:26,191 INFO L276 IsEmpty]: Start isEmpty. Operand 605 states and 1037 transitions. [2024-12-06 05:34:26,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:26,192 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:26,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:26,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:26,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:26,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:26,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1128 states to 606 states and 1039 transitions. [2024-12-06 05:34:26,666 INFO L276 IsEmpty]: Start isEmpty. Operand 606 states and 1039 transitions. [2024-12-06 05:34:26,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:26,667 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:26,667 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:26,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:26,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:27,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:27,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1140 states to 612 states and 1051 transitions. [2024-12-06 05:34:27,416 INFO L276 IsEmpty]: Start isEmpty. Operand 612 states and 1051 transitions. [2024-12-06 05:34:27,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:27,417 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:27,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:27,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:27,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:27,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:27,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1142 states to 613 states and 1053 transitions. [2024-12-06 05:34:27,501 INFO L276 IsEmpty]: Start isEmpty. Operand 613 states and 1053 transitions. [2024-12-06 05:34:27,501 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:27,501 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:27,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:27,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:27,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:34,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:34,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1205 states to 633 states and 1107 transitions. [2024-12-06 05:34:34,382 INFO L276 IsEmpty]: Start isEmpty. Operand 633 states and 1107 transitions. [2024-12-06 05:34:34,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:34,383 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:34,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:34,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:34,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:38,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:38,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1227 states to 642 states and 1129 transitions. [2024-12-06 05:34:38,164 INFO L276 IsEmpty]: Start isEmpty. Operand 642 states and 1129 transitions. [2024-12-06 05:34:38,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:38,165 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:38,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:38,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:38,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:41,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:41,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1241 states to 648 states and 1143 transitions. [2024-12-06 05:34:41,759 INFO L276 IsEmpty]: Start isEmpty. Operand 648 states and 1143 transitions. [2024-12-06 05:34:41,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:41,760 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:41,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:41,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:41,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:44,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:44,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1247 states to 651 states and 1149 transitions. [2024-12-06 05:34:44,372 INFO L276 IsEmpty]: Start isEmpty. Operand 651 states and 1149 transitions. [2024-12-06 05:34:44,372 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:44,373 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:44,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:44,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:44,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:46,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:46,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1249 states to 652 states and 1151 transitions. [2024-12-06 05:34:46,932 INFO L276 IsEmpty]: Start isEmpty. Operand 652 states and 1151 transitions. [2024-12-06 05:34:46,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:46,932 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:46,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:46,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:46,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:49,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:49,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1251 states to 653 states and 1153 transitions. [2024-12-06 05:34:49,243 INFO L276 IsEmpty]: Start isEmpty. Operand 653 states and 1153 transitions. [2024-12-06 05:34:49,243 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:49,243 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:49,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:49,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:49,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:51,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:51,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1253 states to 654 states and 1155 transitions. [2024-12-06 05:34:51,862 INFO L276 IsEmpty]: Start isEmpty. Operand 654 states and 1155 transitions. [2024-12-06 05:34:51,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:51,862 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:51,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:51,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:51,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:34:54,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:34:54,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1255 states to 655 states and 1157 transitions. [2024-12-06 05:34:54,195 INFO L276 IsEmpty]: Start isEmpty. Operand 655 states and 1157 transitions. [2024-12-06 05:34:54,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:34:54,195 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:34:54,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:34:54,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:34:54,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:00,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:00,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1334 states to 682 states and 1227 transitions. [2024-12-06 05:35:00,206 INFO L276 IsEmpty]: Start isEmpty. Operand 682 states and 1227 transitions. [2024-12-06 05:35:00,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:00,206 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:00,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:00,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:00,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:03,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:03,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1376 states to 700 states and 1269 transitions. [2024-12-06 05:35:03,858 INFO L276 IsEmpty]: Start isEmpty. Operand 700 states and 1269 transitions. [2024-12-06 05:35:03,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:03,858 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:03,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:03,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:03,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:05,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:05,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1390 states to 706 states and 1283 transitions. [2024-12-06 05:35:05,542 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 1283 transitions. [2024-12-06 05:35:05,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:05,542 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:05,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:05,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:05,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:06,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:06,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1392 states to 707 states and 1285 transitions. [2024-12-06 05:35:06,191 INFO L276 IsEmpty]: Start isEmpty. Operand 707 states and 1285 transitions. [2024-12-06 05:35:06,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:06,192 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:06,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:06,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:06,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:06,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:06,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1394 states to 708 states and 1287 transitions. [2024-12-06 05:35:06,285 INFO L276 IsEmpty]: Start isEmpty. Operand 708 states and 1287 transitions. [2024-12-06 05:35:06,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:06,286 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:06,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:06,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:06,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:06,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:06,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1396 states to 709 states and 1289 transitions. [2024-12-06 05:35:06,889 INFO L276 IsEmpty]: Start isEmpty. Operand 709 states and 1289 transitions. [2024-12-06 05:35:06,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:06,889 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:06,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:06,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:06,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:06,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:06,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1398 states to 710 states and 1291 transitions. [2024-12-06 05:35:06,987 INFO L276 IsEmpty]: Start isEmpty. Operand 710 states and 1291 transitions. [2024-12-06 05:35:06,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:06,988 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:06,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:06,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:07,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:15,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:15,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1493 states to 743 states and 1377 transitions. [2024-12-06 05:35:15,579 INFO L276 IsEmpty]: Start isEmpty. Operand 743 states and 1377 transitions. [2024-12-06 05:35:15,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:15,580 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:15,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:15,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:15,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:16,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:16,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1501 states to 746 states and 1385 transitions. [2024-12-06 05:35:16,732 INFO L276 IsEmpty]: Start isEmpty. Operand 746 states and 1385 transitions. [2024-12-06 05:35:16,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:16,733 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:16,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:16,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:16,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:23,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:23,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1565 states to 773 states and 1449 transitions. [2024-12-06 05:35:23,572 INFO L276 IsEmpty]: Start isEmpty. Operand 773 states and 1449 transitions. [2024-12-06 05:35:23,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:23,572 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:23,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:23,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:23,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:24,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:24,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1567 states to 774 states and 1451 transitions. [2024-12-06 05:35:24,331 INFO L276 IsEmpty]: Start isEmpty. Operand 774 states and 1451 transitions. [2024-12-06 05:35:24,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:24,332 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:24,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:24,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:24,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:24,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:24,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1569 states to 775 states and 1453 transitions. [2024-12-06 05:35:24,412 INFO L276 IsEmpty]: Start isEmpty. Operand 775 states and 1453 transitions. [2024-12-06 05:35:24,413 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:24,413 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:24,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:24,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:24,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:25,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:25,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 776 states and 1455 transitions. [2024-12-06 05:35:25,115 INFO L276 IsEmpty]: Start isEmpty. Operand 776 states and 1455 transitions. [2024-12-06 05:35:25,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:25,116 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:25,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:25,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:25,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:25,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:25,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1573 states to 777 states and 1457 transitions. [2024-12-06 05:35:25,253 INFO L276 IsEmpty]: Start isEmpty. Operand 777 states and 1457 transitions. [2024-12-06 05:35:25,254 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:25,254 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:25,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:25,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:25,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:25,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:25,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1575 states to 778 states and 1459 transitions. [2024-12-06 05:35:25,970 INFO L276 IsEmpty]: Start isEmpty. Operand 778 states and 1459 transitions. [2024-12-06 05:35:25,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:25,971 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:25,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:25,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:26,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:26,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:26,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1577 states to 779 states and 1461 transitions. [2024-12-06 05:35:26,064 INFO L276 IsEmpty]: Start isEmpty. Operand 779 states and 1461 transitions. [2024-12-06 05:35:26,064 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:26,064 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:26,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:26,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:26,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:28,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:28,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1588 states to 782 states and 1462 transitions. [2024-12-06 05:35:28,950 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1462 transitions. [2024-12-06 05:35:28,950 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:28,950 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:28,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:28,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:28,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:29,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:29,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1580 states to 782 states and 1454 transitions. [2024-12-06 05:35:29,344 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1454 transitions. [2024-12-06 05:35:29,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:29,345 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:29,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:29,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:29,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:29,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:29,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1576 states to 782 states and 1450 transitions. [2024-12-06 05:35:29,746 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1450 transitions. [2024-12-06 05:35:29,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:29,746 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:29,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:29,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:29,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:30,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:30,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1572 states to 782 states and 1446 transitions. [2024-12-06 05:35:30,170 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1446 transitions. [2024-12-06 05:35:30,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:30,171 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:30,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:30,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:30,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:30,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:30,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1570 states to 782 states and 1444 transitions. [2024-12-06 05:35:30,961 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1444 transitions. [2024-12-06 05:35:30,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:30,962 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:30,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:30,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:31,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:31,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:31,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 782 states and 1440 transitions. [2024-12-06 05:35:31,406 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1440 transitions. [2024-12-06 05:35:31,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:31,406 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:31,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:31,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:31,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:31,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:31,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1562 states to 782 states and 1436 transitions. [2024-12-06 05:35:31,787 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1436 transitions. [2024-12-06 05:35:31,787 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:31,787 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:31,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:31,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:31,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:32,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:32,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1558 states to 782 states and 1432 transitions. [2024-12-06 05:35:32,178 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1432 transitions. [2024-12-06 05:35:32,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-12-06 05:35:32,178 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:32,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:32,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:32,215 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:32,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:32,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1554 states to 782 states and 1428 transitions. [2024-12-06 05:35:32,561 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1428 transitions. [2024-12-06 05:35:32,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-12-06 05:35:32,561 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:32,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:32,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:32,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:32,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:32,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1545 states to 777 states and 1419 transitions. [2024-12-06 05:35:32,958 INFO L276 IsEmpty]: Start isEmpty. Operand 777 states and 1419 transitions. [2024-12-06 05:35:32,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-12-06 05:35:32,959 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:32,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:32,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:33,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:33,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:33,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1541 states to 775 states and 1415 transitions. [2024-12-06 05:35:33,218 INFO L276 IsEmpty]: Start isEmpty. Operand 775 states and 1415 transitions. [2024-12-06 05:35:33,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-12-06 05:35:33,218 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:33,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:33,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:33,259 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:33,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:33,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1537 states to 773 states and 1411 transitions. [2024-12-06 05:35:33,470 INFO L276 IsEmpty]: Start isEmpty. Operand 773 states and 1411 transitions. [2024-12-06 05:35:33,470 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-12-06 05:35:33,470 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:33,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:33,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:33,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:33,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:33,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1538 states to 774 states and 1412 transitions. [2024-12-06 05:35:33,777 INFO L276 IsEmpty]: Start isEmpty. Operand 774 states and 1412 transitions. [2024-12-06 05:35:33,777 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-12-06 05:35:33,777 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:33,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:33,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:33,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:34,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:34,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1539 states to 775 states and 1413 transitions. [2024-12-06 05:35:34,586 INFO L276 IsEmpty]: Start isEmpty. Operand 775 states and 1413 transitions. [2024-12-06 05:35:34,587 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-12-06 05:35:34,587 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:34,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:34,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:34,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:34,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:34,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1540 states to 776 states and 1414 transitions. [2024-12-06 05:35:34,921 INFO L276 IsEmpty]: Start isEmpty. Operand 776 states and 1414 transitions. [2024-12-06 05:35:34,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-12-06 05:35:34,921 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:34,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:34,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:34,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:35,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:35,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1541 states to 777 states and 1415 transitions. [2024-12-06 05:35:35,694 INFO L276 IsEmpty]: Start isEmpty. Operand 777 states and 1415 transitions. [2024-12-06 05:35:35,694 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-12-06 05:35:35,694 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:35,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:35,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:35,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:36,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:36,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1542 states to 778 states and 1416 transitions. [2024-12-06 05:35:36,066 INFO L276 IsEmpty]: Start isEmpty. Operand 778 states and 1416 transitions. [2024-12-06 05:35:36,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-12-06 05:35:36,066 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:36,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:36,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:36,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:36,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:36,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1543 states to 779 states and 1417 transitions. [2024-12-06 05:35:36,504 INFO L276 IsEmpty]: Start isEmpty. Operand 779 states and 1417 transitions. [2024-12-06 05:35:36,504 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-12-06 05:35:36,504 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:36,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:36,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:36,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:36,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:36,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1544 states to 780 states and 1418 transitions. [2024-12-06 05:35:36,881 INFO L276 IsEmpty]: Start isEmpty. Operand 780 states and 1418 transitions. [2024-12-06 05:35:36,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-12-06 05:35:36,882 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:36,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:36,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:36,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:37,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:37,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1545 states to 781 states and 1419 transitions. [2024-12-06 05:35:37,273 INFO L276 IsEmpty]: Start isEmpty. Operand 781 states and 1419 transitions. [2024-12-06 05:35:37,274 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-12-06 05:35:37,274 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:37,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:37,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:37,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:40,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:40,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1546 states to 782 states and 1420 transitions. [2024-12-06 05:35:40,072 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1420 transitions. [2024-12-06 05:35:40,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-12-06 05:35:40,073 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:40,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:40,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:40,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:40,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:40,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1547 states to 783 states and 1421 transitions. [2024-12-06 05:35:40,509 INFO L276 IsEmpty]: Start isEmpty. Operand 783 states and 1421 transitions. [2024-12-06 05:35:40,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-12-06 05:35:40,510 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:40,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:40,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-06 05:35:40,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-06 05:35:40,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2024-12-06 05:35:40,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1488 states to 750 states and 1363 transitions. [2024-12-06 05:35:40,627 INFO L276 IsEmpty]: Start isEmpty. Operand 750 states and 1363 transitions. [2024-12-06 05:35:40,627 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2024-12-06 05:35:40,627 INFO L420 CodeCheckObserver]: Error Path is FOUND. [2024-12-06 05:35:40,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-06 05:35:40,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-06 05:35:40,645 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-06 05:35:40,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-06 05:35:40,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-06 05:35:40,858 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-06 05:35:40,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-06 05:35:41,035 WARN L473 CodeCheckObserver]: This program is UNSAFE, Check terminated with 128 iterations. [2024-12-06 05:35:41,160 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 06.12 05:35:41 ImpRootNode [2024-12-06 05:35:41,160 INFO L131 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2024-12-06 05:35:41,161 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-12-06 05:35:41,161 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-12-06 05:35:41,161 INFO L274 PluginConnector]: Witness Printer initialized [2024-12-06 05:35:41,162 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.12 05:33:52" (3/4) ... [2024-12-06 05:35:41,162 INFO L140 WitnessPrinter]: Generating witness for reachability counterexample [2024-12-06 05:35:41,318 INFO L129 tionWitnessGenerator]: Generated YAML witness of length 155. [2024-12-06 05:35:41,418 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/witness.graphml [2024-12-06 05:35:41,418 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/witness.yml [2024-12-06 05:35:41,419 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-12-06 05:35:41,419 INFO L158 Benchmark]: Toolchain (without parser) took 110500.11ms. Allocated memory was 117.4MB in the beginning and 838.9MB in the end (delta: 721.4MB). Free memory was 91.7MB in the beginning and 436.6MB in the end (delta: -344.9MB). Peak memory consumption was 373.4MB. Max. memory is 16.1GB. [2024-12-06 05:35:41,420 INFO L158 Benchmark]: CDTParser took 0.31ms. Allocated memory is still 117.4MB. Free memory was 72.8MB in the beginning and 72.7MB in the end (delta: 83.9kB). There was no memory consumed. Max. memory is 16.1GB. [2024-12-06 05:35:41,420 INFO L158 Benchmark]: CACSL2BoogieTranslator took 392.70ms. Allocated memory is still 117.4MB. Free memory was 91.7MB in the beginning and 68.5MB in the end (delta: 23.2MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-12-06 05:35:41,420 INFO L158 Benchmark]: Boogie Procedure Inliner took 53.65ms. Allocated memory is still 117.4MB. Free memory was 68.5MB in the beginning and 64.6MB in the end (delta: 3.9MB). There was no memory consumed. Max. memory is 16.1GB. [2024-12-06 05:35:41,420 INFO L158 Benchmark]: Boogie Preprocessor took 49.59ms. Allocated memory is still 117.4MB. Free memory was 64.6MB in the beginning and 60.7MB in the end (delta: 3.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-12-06 05:35:41,421 INFO L158 Benchmark]: RCFGBuilder took 1524.01ms. Allocated memory was 117.4MB in the beginning and 218.1MB in the end (delta: 100.7MB). Free memory was 60.7MB in the beginning and 78.9MB in the end (delta: -18.2MB). Peak memory consumption was 80.6MB. Max. memory is 16.1GB. [2024-12-06 05:35:41,421 INFO L158 Benchmark]: CodeCheck took 108217.79ms. Allocated memory was 218.1MB in the beginning and 838.9MB in the end (delta: 620.8MB). Free memory was 78.9MB in the beginning and 474.3MB in the end (delta: -395.5MB). Peak memory consumption was 229.5MB. Max. memory is 16.1GB. [2024-12-06 05:35:41,421 INFO L158 Benchmark]: Witness Printer took 257.59ms. Allocated memory is still 838.9MB. Free memory was 474.3MB in the beginning and 436.6MB in the end (delta: 37.7MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2024-12-06 05:35:41,423 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 7 procedures, 209 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 108.1s, OverallIterations: 128, TraceHistogramMax: 0, PathProgramHistogramMax: 0, EmptinessCheckTime: 0.0s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 127941 SdHoareTripleChecker+Valid, 95.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 111588 mSDsluCounter, 225626 SdHoareTripleChecker+Invalid, 85.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 192622 mSDsCounter, 10351 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 75147 IncrementalHoareTripleChecker+Invalid, 85498 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 10351 mSolverCounterUnsat, 33004 mSDtfsCounter, 75147 mSolverCounterSat, 4.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 88498 GetRequests, 80357 SyntacticMatches, 7507 SemanticMatches, 634 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 464875 ImplicationChecksByTransitivity, 94.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, InterpolantAutomatonStates: 0, traceCheckStatistics: 0.5s SsaConstructionTime, 0.7s SatisfiabilityAnalysisTime, 7.4s InterpolantComputationTime, 8848 NumberOfCodeBlocks, 8848 NumberOfCodeBlocksAsserted, 128 NumberOfCheckSat, 8650 ConstructedInterpolants, 0 QuantifiedInterpolants, 22768 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 127 InterpolantComputations, 127 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int t8_pc = 0; [L34] int t9_pc = 0; [L35] int t10_pc = 0; [L36] int t11_pc = 0; [L37] int t12_pc = 0; [L38] int t13_pc = 0; [L39] int t14_pc = 0; [L40] int m_st ; [L41] int t1_st ; [L42] int t2_st ; [L43] int t3_st ; [L44] int t4_st ; [L45] int t5_st ; [L46] int t6_st ; [L47] int t7_st ; [L48] int t8_st ; [L49] int t9_st ; [L50] int t10_st ; [L51] int t11_st ; [L52] int t12_st ; [L53] int t13_st ; [L54] int t14_st ; [L55] int m_i ; [L56] int t1_i ; [L57] int t2_i ; [L58] int t3_i ; [L59] int t4_i ; [L60] int t5_i ; [L61] int t6_i ; [L62] int t7_i ; [L63] int t8_i ; [L64] int t9_i ; [L65] int t10_i ; [L66] int t11_i ; [L67] int t12_i ; [L68] int t13_i ; [L69] int t14_i ; [L70] int M_E = 2; [L71] int T1_E = 2; [L72] int T2_E = 2; [L73] int T3_E = 2; [L74] int T4_E = 2; [L75] int T5_E = 2; [L76] int T6_E = 2; [L77] int T7_E = 2; [L78] int T8_E = 2; [L79] int T9_E = 2; [L80] int T10_E = 2; [L81] int T11_E = 2; [L82] int T12_E = 2; [L83] int T13_E = 2; [L84] int T14_E = 2; [L85] int E_1 = 2; [L86] int E_2 = 2; [L87] int E_3 = 2; [L88] int E_4 = 2; [L89] int E_5 = 2; [L90] int E_6 = 2; [L91] int E_7 = 2; [L92] int E_8 = 2; [L93] int E_9 = 2; [L94] int E_10 = 2; [L95] int E_11 = 2; [L96] int E_12 = 2; [L97] int E_13 = 2; [L98] int E_14 = 2; [L2062] int __retres1 ; [L2066] CALL init_model() [L1964] m_i = 1 [L1965] t1_i = 1 [L1966] t2_i = 1 [L1967] t3_i = 1 [L1968] t4_i = 1 [L1969] t5_i = 1 [L1970] t6_i = 1 [L1971] t7_i = 1 [L1972] t8_i = 1 [L1973] t9_i = 1 [L1974] t10_i = 1 [L1975] t11_i = 1 [L1976] t12_i = 1 [L1977] t13_i = 1 [L1978] t14_i = 1 [L2066] RET init_model() [L2067] CALL start_simulation() [L2003] int kernel_st ; [L2004] int tmp ; [L2005] int tmp___0 ; [L2009] kernel_st = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2010] FCALL update_channels() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2011] CALL init_threads() [L939] COND TRUE m_i == 1 [L940] m_st = 0 [L944] COND TRUE t1_i == 1 [L945] t1_st = 0 [L949] COND TRUE t2_i == 1 [L950] t2_st = 0 [L954] COND TRUE t3_i == 1 [L955] t3_st = 0 [L959] COND TRUE t4_i == 1 [L960] t4_st = 0 [L964] COND TRUE t5_i == 1 [L965] t5_st = 0 [L969] COND TRUE t6_i == 1 [L970] t6_st = 0 [L974] COND TRUE t7_i == 1 [L975] t7_st = 0 [L979] COND TRUE t8_i == 1 [L980] t8_st = 0 [L984] COND TRUE t9_i == 1 [L985] t9_st = 0 [L989] COND TRUE t10_i == 1 [L990] t10_st = 0 [L994] COND TRUE t11_i == 1 [L995] t11_st = 0 [L999] COND TRUE t12_i == 1 [L1000] t12_st = 0 [L1004] COND TRUE t13_i == 1 [L1005] t13_st = 0 [L1009] COND TRUE t14_i == 1 [L1010] t14_st = 0 [L2011] RET init_threads() [L2012] CALL fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_14)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T14_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1342] COND FALSE !(M_E == 0) [L1347] COND FALSE !(T1_E == 0) [L1352] COND FALSE !(T2_E == 0) [L1357] COND FALSE !(T3_E == 0) [L1362] COND FALSE !(T4_E == 0) [L1367] COND FALSE !(T5_E == 0) [L1372] COND FALSE !(T6_E == 0) [L1377] COND FALSE !(T7_E == 0) [L1382] COND FALSE !(T8_E == 0) [L1387] COND FALSE !(T9_E == 0) [L1392] COND FALSE !(T10_E == 0) [L1397] COND FALSE !(T11_E == 0) [L1402] COND FALSE !(T12_E == 0) [L1407] COND FALSE !(T13_E == 0) [L1412] COND FALSE !(T14_E == 0) [L1417] COND FALSE !(E_1 == 0) [L1422] COND FALSE !(E_2 == 0) [L1427] COND FALSE !(E_3 == 0) [L1432] COND FALSE !(E_4 == 0) [L1437] COND FALSE !(E_5 == 0) [L1442] COND FALSE !(E_6 == 0) [L1447] COND FALSE !(E_7 == 0) [L1452] COND FALSE !(E_8 == 0) [L1457] COND FALSE !(E_9 == 0) [L1462] COND FALSE !(E_10 == 0) [L1467] COND FALSE !(E_11 == 0) [L1472] COND FALSE !(E_12 == 0) [L1477] COND FALSE !(E_13 == 0) [L1482] COND FALSE !(E_14 == 0) [L2012] RET fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2013] CALL activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1645] int tmp ; [L1646] int tmp___0 ; [L1647] int tmp___1 ; [L1648] int tmp___2 ; [L1649] int tmp___3 ; [L1650] int tmp___4 ; [L1651] int tmp___5 ; [L1652] int tmp___6 ; [L1653] int tmp___7 ; [L1654] int tmp___8 ; [L1655] int tmp___9 ; [L1656] int tmp___10 ; [L1657] int tmp___11 ; [L1658] int tmp___12 ; [L1659] int tmp___13 ; [L1664] CALL, EXPR is_master_triggered() [L643] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L646] COND FALSE !(m_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L656] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L658] return (__retres1); [L1664] RET, EXPR is_master_triggered() [L1664] tmp = is_master_triggered() [L1666] COND FALSE !(\read(tmp)) [L1672] CALL, EXPR is_transmit1_triggered() [L662] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L665] COND FALSE !(t1_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L675] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L677] return (__retres1); [L1672] RET, EXPR is_transmit1_triggered() [L1672] tmp___0 = is_transmit1_triggered() [L1674] COND FALSE !(\read(tmp___0)) [L1680] CALL, EXPR is_transmit2_triggered() [L681] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L684] COND FALSE !(t2_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L694] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L696] return (__retres1); [L1680] RET, EXPR is_transmit2_triggered() [L1680] tmp___1 = is_transmit2_triggered() [L1682] COND FALSE !(\read(tmp___1)) [L1688] CALL, EXPR is_transmit3_triggered() [L700] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L703] COND FALSE !(t3_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L713] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L715] return (__retres1); [L1688] RET, EXPR is_transmit3_triggered() [L1688] tmp___2 = is_transmit3_triggered() [L1690] COND FALSE !(\read(tmp___2)) [L1696] CALL, EXPR is_transmit4_triggered() [L719] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L722] COND FALSE !(t4_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L732] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L734] return (__retres1); [L1696] RET, EXPR is_transmit4_triggered() [L1696] tmp___3 = is_transmit4_triggered() [L1698] COND FALSE !(\read(tmp___3)) [L1704] CALL, EXPR is_transmit5_triggered() [L738] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L741] COND FALSE !(t5_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L751] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L753] return (__retres1); [L1704] RET, EXPR is_transmit5_triggered() [L1704] tmp___4 = is_transmit5_triggered() [L1706] COND FALSE !(\read(tmp___4)) [L1712] CALL, EXPR is_transmit6_triggered() [L757] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L760] COND FALSE !(t6_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L770] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L772] return (__retres1); [L1712] RET, EXPR is_transmit6_triggered() [L1712] tmp___5 = is_transmit6_triggered() [L1714] COND FALSE !(\read(tmp___5)) [L1720] CALL, EXPR is_transmit7_triggered() [L776] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L779] COND FALSE !(t7_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L789] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L791] return (__retres1); [L1720] RET, EXPR is_transmit7_triggered() [L1720] tmp___6 = is_transmit7_triggered() [L1722] COND FALSE !(\read(tmp___6)) [L1728] CALL, EXPR is_transmit8_triggered() [L795] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L798] COND FALSE !(t8_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L808] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L810] return (__retres1); [L1728] RET, EXPR is_transmit8_triggered() [L1728] tmp___7 = is_transmit8_triggered() [L1730] COND FALSE !(\read(tmp___7)) [L1736] CALL, EXPR is_transmit9_triggered() [L814] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L817] COND FALSE !(t9_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L827] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L829] return (__retres1); [L1736] RET, EXPR is_transmit9_triggered() [L1736] tmp___8 = is_transmit9_triggered() [L1738] COND FALSE !(\read(tmp___8)) [L1744] CALL, EXPR is_transmit10_triggered() [L833] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L836] COND FALSE !(t10_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L846] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L848] return (__retres1); [L1744] RET, EXPR is_transmit10_triggered() [L1744] tmp___9 = is_transmit10_triggered() [L1746] COND FALSE !(\read(tmp___9)) [L1752] CALL, EXPR is_transmit11_triggered() [L852] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L855] COND FALSE !(t11_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L865] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L867] return (__retres1); [L1752] RET, EXPR is_transmit11_triggered() [L1752] tmp___10 = is_transmit11_triggered() [L1754] COND FALSE !(\read(tmp___10)) [L1760] CALL, EXPR is_transmit12_triggered() [L871] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L874] COND FALSE !(t12_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L884] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L886] return (__retres1); [L1760] RET, EXPR is_transmit12_triggered() [L1760] tmp___11 = is_transmit12_triggered() [L1762] COND FALSE !(\read(tmp___11)) [L1768] CALL, EXPR is_transmit13_triggered() [L890] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L893] COND FALSE !(t13_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L903] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L905] return (__retres1); [L1768] RET, EXPR is_transmit13_triggered() [L1768] tmp___12 = is_transmit13_triggered() [L1770] COND FALSE !(\read(tmp___12)) [L1776] CALL, EXPR is_transmit14_triggered() [L909] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L912] COND FALSE !(t14_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L922] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L924] return (__retres1); [L1776] RET, EXPR is_transmit14_triggered() [L1776] tmp___13 = is_transmit14_triggered() [L1778] COND FALSE !(\read(tmp___13)) [L2013] RET activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2014] CALL reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_14)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T14_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1495] COND FALSE !(M_E == 1) [L1500] COND FALSE !(T1_E == 1) [L1505] COND FALSE !(T2_E == 1) [L1510] COND FALSE !(T3_E == 1) [L1515] COND FALSE !(T4_E == 1) [L1520] COND FALSE !(T5_E == 1) [L1525] COND FALSE !(T6_E == 1) [L1530] COND FALSE !(T7_E == 1) [L1535] COND FALSE !(T8_E == 1) [L1540] COND FALSE !(T9_E == 1) [L1545] COND FALSE !(T10_E == 1) [L1550] COND FALSE !(T11_E == 1) [L1555] COND FALSE !(T12_E == 1) [L1560] COND FALSE !(T13_E == 1) [L1565] COND FALSE !(T14_E == 1) [L1570] COND FALSE !(E_1 == 1) [L1575] COND FALSE !(E_2 == 1) [L1580] COND FALSE !(E_3 == 1) [L1585] COND FALSE !(E_4 == 1) [L1590] COND FALSE !(E_5 == 1) [L1595] COND FALSE !(E_6 == 1) [L1600] COND FALSE !(E_7 == 1) [L1605] COND FALSE !(E_8 == 1) [L1610] COND FALSE !(E_9 == 1) [L1615] COND FALSE !(E_10 == 1) [L1620] COND FALSE !(E_11 == 1) [L1625] COND FALSE !(E_12 == 1) [L1630] COND FALSE !(E_13 == 1) [L1635] COND FALSE !(E_14 == 1) [L2014] RET reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2020] kernel_st = 1 [L2021] CALL eval() [L1106] int tmp ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1113] CALL, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1019] int __retres1 ; [L1022] COND TRUE m_st == 0 [L1023] __retres1 = 1 [L1101] return (__retres1); [L1113] RET, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1113] tmp = exists_runnable_thread() [L1115] COND TRUE \read(tmp) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1120] COND TRUE m_st == 0 [L1121] int tmp_ndt_1; [L1122] tmp_ndt_1 = __VERIFIER_nondet_int() [L1123] COND FALSE !(\read(tmp_ndt_1)) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1134] COND TRUE t1_st == 0 [L1135] int tmp_ndt_2; [L1136] tmp_ndt_2 = __VERIFIER_nondet_int() [L1137] COND FALSE !(\read(tmp_ndt_2)) [L1143] CALL error() [L21] reach_error() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.31ms. Allocated memory is still 117.4MB. Free memory was 72.8MB in the beginning and 72.7MB in the end (delta: 83.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 392.70ms. Allocated memory is still 117.4MB. Free memory was 91.7MB in the beginning and 68.5MB in the end (delta: 23.2MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 53.65ms. Allocated memory is still 117.4MB. Free memory was 68.5MB in the beginning and 64.6MB in the end (delta: 3.9MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 49.59ms. Allocated memory is still 117.4MB. Free memory was 64.6MB in the beginning and 60.7MB in the end (delta: 3.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 1524.01ms. Allocated memory was 117.4MB in the beginning and 218.1MB in the end (delta: 100.7MB). Free memory was 60.7MB in the beginning and 78.9MB in the end (delta: -18.2MB). Peak memory consumption was 80.6MB. Max. memory is 16.1GB. * CodeCheck took 108217.79ms. Allocated memory was 218.1MB in the beginning and 838.9MB in the end (delta: 620.8MB). Free memory was 78.9MB in the beginning and 474.3MB in the end (delta: -395.5MB). Peak memory consumption was 229.5MB. Max. memory is 16.1GB. * Witness Printer took 257.59ms. Allocated memory is still 838.9MB. Free memory was 474.3MB in the beginning and 436.6MB in the end (delta: 37.7MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. RESULT: Ultimate proved your program to be incorrect! [2024-12-06 05:35:41,441 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_09b90d98-7578-41c4-b595-31a48c42df7f/bin/ukojak-verify-CZk0znPC7b/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE