./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/pipeline.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/pipeline.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 79bbe68806c3ba3852cd8c209d4ce80dca551636a131cc65daaf97524d927c63 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-14 03:56:00,544 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-14 03:56:00,647 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/config/svcomp-Reach-32bit-Taipan_Default.epf [2024-11-14 03:56:00,655 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-14 03:56:00,655 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-14 03:56:00,687 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-14 03:56:00,688 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-14 03:56:00,688 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-14 03:56:00,688 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-14 03:56:00,689 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-14 03:56:00,689 INFO L153 SettingsManager]: * User list type=DISABLED [2024-11-14 03:56:00,689 INFO L151 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2024-11-14 03:56:00,689 INFO L153 SettingsManager]: * Explicit value domain=true [2024-11-14 03:56:00,690 INFO L153 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2024-11-14 03:56:00,690 INFO L153 SettingsManager]: * Octagon Domain=false [2024-11-14 03:56:00,691 INFO L153 SettingsManager]: * Abstract domain=CompoundDomain [2024-11-14 03:56:00,691 INFO L153 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2024-11-14 03:56:00,691 INFO L153 SettingsManager]: * Use the RCFG-of-the-future interface=true [2024-11-14 03:56:00,692 INFO L153 SettingsManager]: * Interval Domain=false [2024-11-14 03:56:00,692 INFO L151 SettingsManager]: Preferences of Sifa differ from their defaults: [2024-11-14 03:56:00,692 INFO L153 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2024-11-14 03:56:00,692 INFO L153 SettingsManager]: * Simplification Technique=POLY_PAC [2024-11-14 03:56:00,692 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-14 03:56:00,692 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-14 03:56:00,692 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-14 03:56:00,692 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-14 03:56:00,692 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-14 03:56:00,693 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-14 03:56:00,693 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-14 03:56:00,693 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-14 03:56:00,693 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-14 03:56:00,693 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-14 03:56:00,693 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-14 03:56:00,693 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-14 03:56:00,693 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-14 03:56:00,693 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-14 03:56:00,693 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-14 03:56:00,693 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-14 03:56:00,693 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-11-14 03:56:00,694 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-14 03:56:00,694 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-14 03:56:00,694 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-14 03:56:00,695 INFO L153 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2024-11-14 03:56:00,695 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-14 03:56:00,696 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-14 03:56:00,696 INFO L153 SettingsManager]: * Trace refinement exception blacklist=NONE [2024-11-14 03:56:00,696 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-14 03:56:00,696 INFO L153 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 79bbe68806c3ba3852cd8c209d4ce80dca551636a131cc65daaf97524d927c63 [2024-11-14 03:56:01,124 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-14 03:56:01,133 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-14 03:56:01,136 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-14 03:56:01,137 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-14 03:56:01,137 INFO L274 PluginConnector]: CDTParser initialized [2024-11-14 03:56:01,139 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/../../sv-benchmarks/c/systemc/pipeline.cil-1.c Unable to find full path for "g++" [2024-11-14 03:56:03,174 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-14 03:56:03,490 INFO L384 CDTParser]: Found 1 translation units. [2024-11-14 03:56:03,491 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/sv-benchmarks/c/systemc/pipeline.cil-1.c [2024-11-14 03:56:03,519 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/data/f30c646b8/e8f275a265e1487aabc1b45cf9ed56ea/FLAGaeb3c6a5a [2024-11-14 03:56:03,544 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/data/f30c646b8/e8f275a265e1487aabc1b45cf9ed56ea [2024-11-14 03:56:03,547 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-14 03:56:03,549 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-14 03:56:03,552 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-14 03:56:03,552 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-14 03:56:03,557 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-14 03:56:03,558 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.11 03:56:03" (1/1) ... [2024-11-14 03:56:03,560 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5f643582 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 03:56:03, skipping insertion in model container [2024-11-14 03:56:03,561 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.11 03:56:03" (1/1) ... [2024-11-14 03:56:03,602 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-14 03:56:03,780 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/sv-benchmarks/c/systemc/pipeline.cil-1.c[640,653] [2024-11-14 03:56:03,898 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-14 03:56:03,919 INFO L200 MainTranslator]: Completed pre-run [2024-11-14 03:56:03,932 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/sv-benchmarks/c/systemc/pipeline.cil-1.c[640,653] [2024-11-14 03:56:04,011 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-14 03:56:04,028 INFO L204 MainTranslator]: Completed translation [2024-11-14 03:56:04,029 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 03:56:04 WrapperNode [2024-11-14 03:56:04,029 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-14 03:56:04,030 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-14 03:56:04,030 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-14 03:56:04,030 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-14 03:56:04,037 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 03:56:04" (1/1) ... [2024-11-14 03:56:04,046 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 03:56:04" (1/1) ... [2024-11-14 03:56:04,079 INFO L138 Inliner]: procedures = 20, calls = 17, calls flagged for inlining = 9, calls inlined = 9, statements flattened = 423 [2024-11-14 03:56:04,079 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-14 03:56:04,079 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-14 03:56:04,080 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-14 03:56:04,080 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-14 03:56:04,092 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 03:56:04" (1/1) ... [2024-11-14 03:56:04,092 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 03:56:04" (1/1) ... [2024-11-14 03:56:04,098 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 03:56:04" (1/1) ... [2024-11-14 03:56:04,099 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 03:56:04" (1/1) ... [2024-11-14 03:56:04,107 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 03:56:04" (1/1) ... [2024-11-14 03:56:04,122 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 03:56:04" (1/1) ... [2024-11-14 03:56:04,123 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 03:56:04" (1/1) ... [2024-11-14 03:56:04,125 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 03:56:04" (1/1) ... [2024-11-14 03:56:04,134 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-14 03:56:04,135 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-14 03:56:04,135 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-14 03:56:04,135 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-14 03:56:04,136 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 03:56:04" (1/1) ... [2024-11-14 03:56:04,146 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-11-14 03:56:04,172 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 [2024-11-14 03:56:04,185 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2024-11-14 03:56:04,192 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2024-11-14 03:56:04,215 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-14 03:56:04,215 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2024-11-14 03:56:04,216 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2024-11-14 03:56:04,216 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2024-11-14 03:56:04,216 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-14 03:56:04,216 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-14 03:56:04,358 INFO L238 CfgBuilder]: Building ICFG [2024-11-14 03:56:04,360 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-14 03:56:05,158 INFO L? ?]: Removed 28 outVars from TransFormulas that were not future-live. [2024-11-14 03:56:05,158 INFO L287 CfgBuilder]: Performing block encoding [2024-11-14 03:56:05,956 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-14 03:56:05,956 INFO L316 CfgBuilder]: Removed 3 assume(true) statements. [2024-11-14 03:56:05,957 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.11 03:56:05 BoogieIcfgContainer [2024-11-14 03:56:05,957 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-14 03:56:05,960 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-14 03:56:05,960 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-14 03:56:05,966 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-14 03:56:05,966 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 14.11 03:56:03" (1/3) ... [2024-11-14 03:56:05,967 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6448c1ab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.11 03:56:05, skipping insertion in model container [2024-11-14 03:56:05,967 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 03:56:04" (2/3) ... [2024-11-14 03:56:05,967 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6448c1ab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.11 03:56:05, skipping insertion in model container [2024-11-14 03:56:05,968 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.11 03:56:05" (3/3) ... [2024-11-14 03:56:05,969 INFO L112 eAbstractionObserver]: Analyzing ICFG pipeline.cil-1.c [2024-11-14 03:56:05,985 INFO L217 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-14 03:56:05,987 INFO L154 ceAbstractionStarter]: Applying trace abstraction to ICFG pipeline.cil-1.c that has 2 procedures, 30 locations, 1 initial locations, 3 loop locations, and 1 error locations. [2024-11-14 03:56:06,051 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-14 03:56:06,064 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@2c945b4, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-14 03:56:06,064 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-14 03:56:06,072 INFO L276 IsEmpty]: Start isEmpty. Operand has 30 states, 24 states have (on average 1.6666666666666667) internal successors, (40), 26 states have internal predecessors, (40), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-14 03:56:06,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2024-11-14 03:56:06,081 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 03:56:06,081 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 03:56:06,082 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 03:56:06,088 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 03:56:06,088 INFO L85 PathProgramCache]: Analyzing trace with hash 133093364, now seen corresponding path program 1 times [2024-11-14 03:56:06,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 03:56:06,097 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [569842469] [2024-11-14 03:56:06,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 03:56:06,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 03:56:06,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 03:56:06,457 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-11-14 03:56:06,457 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-14 03:56:06,458 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [569842469] [2024-11-14 03:56:06,458 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [569842469] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-14 03:56:06,458 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [580591199] [2024-11-14 03:56:06,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 03:56:06,459 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-14 03:56:06,459 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 [2024-11-14 03:56:06,465 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-14 03:56:06,469 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-14 03:56:06,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 03:56:06,760 INFO L255 TraceCheckSpWp]: Trace formula consists of 520 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-14 03:56:06,766 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-14 03:56:06,778 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-11-14 03:56:06,778 INFO L307 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-14 03:56:06,778 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [580591199] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-14 03:56:06,779 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-14 03:56:06,779 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 2 [2024-11-14 03:56:06,781 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918600098] [2024-11-14 03:56:06,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-14 03:56:06,786 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-11-14 03:56:06,786 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-14 03:56:06,808 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-14 03:56:06,808 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-14 03:56:06,810 INFO L87 Difference]: Start difference. First operand has 30 states, 24 states have (on average 1.6666666666666667) internal successors, (40), 26 states have internal predecessors, (40), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 5.5) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-14 03:56:06,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-14 03:56:06,871 INFO L93 Difference]: Finished difference Result 57 states and 92 transitions. [2024-11-14 03:56:06,875 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-14 03:56:06,877 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 5.5) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) Word has length 16 [2024-11-14 03:56:06,877 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-14 03:56:06,885 INFO L225 Difference]: With dead ends: 57 [2024-11-14 03:56:06,885 INFO L226 Difference]: Without dead ends: 29 [2024-11-14 03:56:06,889 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-14 03:56:06,893 INFO L432 NwaCegarLoop]: 36 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 36 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-14 03:56:06,894 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 36 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-14 03:56:06,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2024-11-14 03:56:06,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2024-11-14 03:56:06,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 24 states have (on average 1.5) internal successors, (36), 25 states have internal predecessors, (36), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-14 03:56:06,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 42 transitions. [2024-11-14 03:56:06,936 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 42 transitions. Word has length 16 [2024-11-14 03:56:06,936 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-14 03:56:06,936 INFO L471 AbstractCegarLoop]: Abstraction has 29 states and 42 transitions. [2024-11-14 03:56:06,937 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 5.5) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-14 03:56:06,937 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 42 transitions. [2024-11-14 03:56:06,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2024-11-14 03:56:06,939 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 03:56:06,939 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 03:56:06,961 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-11-14 03:56:07,140 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0,2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-14 03:56:07,140 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 03:56:07,141 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 03:56:07,141 INFO L85 PathProgramCache]: Analyzing trace with hash -1625867790, now seen corresponding path program 1 times [2024-11-14 03:56:07,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 03:56:07,141 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687203831] [2024-11-14 03:56:07,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 03:56:07,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 03:56:07,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 03:56:09,533 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-11-14 03:56:09,533 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-14 03:56:09,534 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687203831] [2024-11-14 03:56:09,534 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1687203831] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-14 03:56:09,534 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [894894764] [2024-11-14 03:56:09,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 03:56:09,534 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-14 03:56:09,534 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 [2024-11-14 03:56:09,537 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-14 03:56:09,539 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-14 03:56:09,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 03:56:09,899 INFO L255 TraceCheckSpWp]: Trace formula consists of 608 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-14 03:56:09,903 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-14 03:56:10,005 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-11-14 03:56:10,006 INFO L307 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-14 03:56:10,006 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [894894764] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-14 03:56:10,006 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-14 03:56:10,007 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [10] total 13 [2024-11-14 03:56:10,007 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [13475549] [2024-11-14 03:56:10,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-14 03:56:10,008 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-14 03:56:10,009 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-14 03:56:10,010 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-14 03:56:10,010 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2024-11-14 03:56:10,011 INFO L87 Difference]: Start difference. First operand 29 states and 42 transitions. Second operand has 4 states, 4 states have (on average 5.25) internal successors, (21), 4 states have internal predecessors, (21), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-14 03:56:10,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-14 03:56:10,119 INFO L93 Difference]: Finished difference Result 67 states and 97 transitions. [2024-11-14 03:56:10,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-14 03:56:10,119 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 5.25) internal successors, (21), 4 states have internal predecessors, (21), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 40 [2024-11-14 03:56:10,120 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-14 03:56:10,121 INFO L225 Difference]: With dead ends: 67 [2024-11-14 03:56:10,121 INFO L226 Difference]: Without dead ends: 40 [2024-11-14 03:56:10,122 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2024-11-14 03:56:10,123 INFO L432 NwaCegarLoop]: 37 mSDtfsCounter, 4 mSDsluCounter, 62 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 99 SdHoareTripleChecker+Invalid, 27 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-14 03:56:10,125 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 99 Invalid, 27 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 26 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-14 03:56:10,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2024-11-14 03:56:10,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 35. [2024-11-14 03:56:10,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 28 states have (on average 1.4285714285714286) internal successors, (40), 29 states have internal predecessors, (40), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 4 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-14 03:56:10,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 50 transitions. [2024-11-14 03:56:10,139 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 50 transitions. Word has length 40 [2024-11-14 03:56:10,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-14 03:56:10,140 INFO L471 AbstractCegarLoop]: Abstraction has 35 states and 50 transitions. [2024-11-14 03:56:10,140 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 5.25) internal successors, (21), 4 states have internal predecessors, (21), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-14 03:56:10,141 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 50 transitions. [2024-11-14 03:56:10,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2024-11-14 03:56:10,143 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 03:56:10,143 INFO L215 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 03:56:10,171 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-11-14 03:56:10,344 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-14 03:56:10,344 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 03:56:10,344 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 03:56:10,345 INFO L85 PathProgramCache]: Analyzing trace with hash -487284050, now seen corresponding path program 1 times [2024-11-14 03:56:10,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 03:56:10,345 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223174194] [2024-11-14 03:56:10,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 03:56:10,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 03:56:10,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 03:56:12,724 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 79 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2024-11-14 03:56:12,727 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-14 03:56:12,727 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [223174194] [2024-11-14 03:56:12,727 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [223174194] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-14 03:56:12,728 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1067918168] [2024-11-14 03:56:12,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 03:56:12,728 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-14 03:56:12,728 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 [2024-11-14 03:56:12,730 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-14 03:56:12,733 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-14 03:56:13,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 03:56:13,175 INFO L255 TraceCheckSpWp]: Trace formula consists of 1103 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-14 03:56:13,180 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-14 03:56:13,279 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-11-14 03:56:13,279 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-14 03:56:13,398 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-11-14 03:56:13,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1067918168] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-14 03:56:13,398 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [422249599] [2024-11-14 03:56:13,418 INFO L159 IcfgInterpreter]: Started Sifa with 27 locations of interest [2024-11-14 03:56:13,418 INFO L166 IcfgInterpreter]: Building call graph [2024-11-14 03:56:13,421 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2024-11-14 03:56:13,426 INFO L176 IcfgInterpreter]: Starting interpretation [2024-11-14 03:56:13,427 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2024-11-14 03:56:20,526 INFO L197 IcfgInterpreter]: Interpreting procedure start_simulation with input of size 1 for LOIs [2024-11-14 03:56:20,838 INFO L180 IcfgInterpreter]: Interpretation finished [2024-11-14 03:56:22,451 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '933#(and (<= 1 |#StackHeapBarrier|) (= ~S3_zero_i~0 0) (= ~S2_presdbl_i~0 0) (= ~D_print_i~0 0) (= ~main_clk_val_t~0 1) (= ~N_generate_i~0 0) (= ~D_z~0 0) (= ~S1_addsub_i~0 0))' at error location [2024-11-14 03:56:22,452 WARN L311 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2024-11-14 03:56:22,453 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-14 03:56:22,453 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 5, 5] total 16 [2024-11-14 03:56:22,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [241263800] [2024-11-14 03:56:22,453 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-14 03:56:22,455 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2024-11-14 03:56:22,455 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-14 03:56:22,457 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2024-11-14 03:56:22,460 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=759, Unknown=0, NotChecked=0, Total=870 [2024-11-14 03:56:22,460 INFO L87 Difference]: Start difference. First operand 35 states and 50 transitions. Second operand has 16 states, 14 states have (on average 5.0) internal successors, (70), 14 states have internal predecessors, (70), 7 states have call successors, (12), 2 states have call predecessors, (12), 3 states have return successors, (12), 6 states have call predecessors, (12), 7 states have call successors, (12) [2024-11-14 03:56:23,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-14 03:56:23,320 INFO L93 Difference]: Finished difference Result 131 states and 204 transitions. [2024-11-14 03:56:23,321 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2024-11-14 03:56:23,322 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 14 states have (on average 5.0) internal successors, (70), 14 states have internal predecessors, (70), 7 states have call successors, (12), 2 states have call predecessors, (12), 3 states have return successors, (12), 6 states have call predecessors, (12), 7 states have call successors, (12) Word has length 78 [2024-11-14 03:56:23,322 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-14 03:56:23,327 INFO L225 Difference]: With dead ends: 131 [2024-11-14 03:56:23,327 INFO L226 Difference]: Without dead ends: 98 [2024-11-14 03:56:23,329 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 259 GetRequests, 218 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 418 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=237, Invalid=1485, Unknown=0, NotChecked=0, Total=1722 [2024-11-14 03:56:23,333 INFO L432 NwaCegarLoop]: 36 mSDtfsCounter, 178 mSDsluCounter, 257 mSDsCounter, 0 mSdLazyCounter, 168 mSolverCounterSat, 59 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 182 SdHoareTripleChecker+Valid, 293 SdHoareTripleChecker+Invalid, 227 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 59 IncrementalHoareTripleChecker+Valid, 168 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-14 03:56:23,334 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [182 Valid, 293 Invalid, 227 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [59 Valid, 168 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-14 03:56:23,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2024-11-14 03:56:23,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 91. [2024-11-14 03:56:23,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 75 states have (on average 1.44) internal successors, (108), 77 states have internal predecessors, (108), 12 states have call successors, (12), 2 states have call predecessors, (12), 3 states have return successors, (22), 11 states have call predecessors, (22), 12 states have call successors, (22) [2024-11-14 03:56:23,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 142 transitions. [2024-11-14 03:56:23,368 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 142 transitions. Word has length 78 [2024-11-14 03:56:23,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-14 03:56:23,369 INFO L471 AbstractCegarLoop]: Abstraction has 91 states and 142 transitions. [2024-11-14 03:56:23,369 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 14 states have (on average 5.0) internal successors, (70), 14 states have internal predecessors, (70), 7 states have call successors, (12), 2 states have call predecessors, (12), 3 states have return successors, (12), 6 states have call predecessors, (12), 7 states have call successors, (12) [2024-11-14 03:56:23,370 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 142 transitions. [2024-11-14 03:56:23,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2024-11-14 03:56:23,376 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 03:56:23,377 INFO L215 NwaCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 03:56:23,405 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2024-11-14 03:56:23,581 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-14 03:56:23,581 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 03:56:23,582 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 03:56:23,582 INFO L85 PathProgramCache]: Analyzing trace with hash -66496781, now seen corresponding path program 1 times [2024-11-14 03:56:23,582 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 03:56:23,582 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158999308] [2024-11-14 03:56:23,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 03:56:23,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 03:56:23,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 03:56:30,824 INFO L134 CoverageAnalysis]: Checked inductivity of 792 backedges. 27 proven. 475 refuted. 0 times theorem prover too weak. 290 trivial. 0 not checked. [2024-11-14 03:56:30,827 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-14 03:56:30,827 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [158999308] [2024-11-14 03:56:30,827 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [158999308] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-14 03:56:30,827 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1846328636] [2024-11-14 03:56:30,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 03:56:30,828 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-14 03:56:30,828 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 [2024-11-14 03:56:30,832 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-14 03:56:30,834 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-14 03:56:31,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 03:56:31,847 INFO L255 TraceCheckSpWp]: Trace formula consists of 2596 conjuncts, 28 conjuncts are in the unsatisfiable core [2024-11-14 03:56:31,870 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-14 03:56:33,048 INFO L134 CoverageAnalysis]: Checked inductivity of 792 backedges. 279 proven. 16 refuted. 0 times theorem prover too weak. 497 trivial. 0 not checked. [2024-11-14 03:56:33,049 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-14 03:56:44,354 WARN L286 SmtUtils]: Spent 7.94s on a formula simplification. DAG size of input: 306 DAG size of output: 53 (called from [L 276] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaUtils.sequentialComposition) [2024-11-14 03:56:44,828 INFO L134 CoverageAnalysis]: Checked inductivity of 792 backedges. 279 proven. 16 refuted. 0 times theorem prover too weak. 497 trivial. 0 not checked. [2024-11-14 03:56:44,828 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1846328636] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-14 03:56:44,829 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [76098258] [2024-11-14 03:56:44,832 INFO L159 IcfgInterpreter]: Started Sifa with 28 locations of interest [2024-11-14 03:56:44,832 INFO L166 IcfgInterpreter]: Building call graph [2024-11-14 03:56:44,832 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2024-11-14 03:56:44,833 INFO L176 IcfgInterpreter]: Starting interpretation [2024-11-14 03:56:44,833 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2024-11-14 03:56:49,302 INFO L197 IcfgInterpreter]: Interpreting procedure start_simulation with input of size 1 for LOIs [2024-11-14 03:56:49,618 INFO L180 IcfgInterpreter]: Interpretation finished [2024-11-14 03:56:50,976 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '2465#(and (<= 1 |#StackHeapBarrier|) (= ~S3_zero_i~0 0) (= ~S2_presdbl_i~0 0) (= ~D_print_i~0 0) (= ~main_clk_val_t~0 1) (= ~N_generate_i~0 0) (= ~D_z~0 0) (= ~S1_addsub_i~0 0))' at error location [2024-11-14 03:56:50,976 WARN L311 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2024-11-14 03:56:50,977 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-14 03:56:50,977 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 10, 11] total 29 [2024-11-14 03:56:50,977 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [604268025] [2024-11-14 03:56:50,977 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-14 03:56:50,979 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 29 states [2024-11-14 03:56:50,979 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-14 03:56:50,981 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2024-11-14 03:56:50,983 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=236, Invalid=1656, Unknown=0, NotChecked=0, Total=1892 [2024-11-14 03:56:50,983 INFO L87 Difference]: Start difference. First operand 91 states and 142 transitions. Second operand has 29 states, 22 states have (on average 5.954545454545454) internal successors, (131), 22 states have internal predecessors, (131), 9 states have call successors, (13), 6 states have call predecessors, (13), 7 states have return successors, (12), 5 states have call predecessors, (12), 9 states have call successors, (12) [2024-11-14 03:56:52,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-14 03:56:52,172 INFO L93 Difference]: Finished difference Result 228 states and 358 transitions. [2024-11-14 03:56:52,173 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2024-11-14 03:56:52,174 INFO L78 Accepts]: Start accepts. Automaton has has 29 states, 22 states have (on average 5.954545454545454) internal successors, (131), 22 states have internal predecessors, (131), 9 states have call successors, (13), 6 states have call predecessors, (13), 7 states have return successors, (12), 5 states have call predecessors, (12), 9 states have call successors, (12) Word has length 195 [2024-11-14 03:56:52,175 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-14 03:56:52,176 INFO L225 Difference]: With dead ends: 228 [2024-11-14 03:56:52,177 INFO L226 Difference]: Without dead ends: 126 [2024-11-14 03:56:52,186 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 631 GetRequests, 572 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1095 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=487, Invalid=3173, Unknown=0, NotChecked=0, Total=3660 [2024-11-14 03:56:52,190 INFO L432 NwaCegarLoop]: 79 mSDtfsCounter, 661 mSDsluCounter, 870 mSDsCounter, 0 mSdLazyCounter, 332 mSolverCounterSat, 67 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 661 SdHoareTripleChecker+Valid, 949 SdHoareTripleChecker+Invalid, 399 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 67 IncrementalHoareTripleChecker+Valid, 332 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-14 03:56:52,191 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [661 Valid, 949 Invalid, 399 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [67 Valid, 332 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-14 03:56:52,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2024-11-14 03:56:52,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 90. [2024-11-14 03:56:52,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90 states, 75 states have (on average 1.4266666666666667) internal successors, (107), 76 states have internal predecessors, (107), 11 states have call successors, (11), 3 states have call predecessors, (11), 3 states have return successors, (11), 10 states have call predecessors, (11), 11 states have call successors, (11) [2024-11-14 03:56:52,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 129 transitions. [2024-11-14 03:56:52,219 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 129 transitions. Word has length 195 [2024-11-14 03:56:52,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-14 03:56:52,220 INFO L471 AbstractCegarLoop]: Abstraction has 90 states and 129 transitions. [2024-11-14 03:56:52,220 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 29 states, 22 states have (on average 5.954545454545454) internal successors, (131), 22 states have internal predecessors, (131), 9 states have call successors, (13), 6 states have call predecessors, (13), 7 states have return successors, (12), 5 states have call predecessors, (12), 9 states have call successors, (12) [2024-11-14 03:56:52,220 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 129 transitions. [2024-11-14 03:56:52,223 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 208 [2024-11-14 03:56:52,223 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 03:56:52,224 INFO L215 NwaCegarLoop]: trace histogram [15, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1] [2024-11-14 03:56:52,252 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2024-11-14 03:56:52,428 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-14 03:56:52,429 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 03:56:52,429 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 03:56:52,429 INFO L85 PathProgramCache]: Analyzing trace with hash -792956989, now seen corresponding path program 2 times [2024-11-14 03:56:52,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 03:56:52,429 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847417510] [2024-11-14 03:56:52,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 03:56:52,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 03:56:52,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-14 03:56:52,866 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-14 03:56:53,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-14 03:56:53,422 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2024-11-14 03:56:53,422 INFO L325 BasicCegarLoop]: Counterexample is feasible [2024-11-14 03:56:53,424 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-11-14 03:56:53,426 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2024-11-14 03:56:53,430 INFO L407 BasicCegarLoop]: Path program histogram: [2, 1, 1, 1] [2024-11-14 03:56:54,076 INFO L173 ceAbstractionStarter]: Computing trace abstraction results [2024-11-14 03:56:54,080 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 14.11 03:56:54 BoogieIcfgContainer [2024-11-14 03:56:54,080 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-11-14 03:56:54,081 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-14 03:56:54,081 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-14 03:56:54,081 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-14 03:56:54,082 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.11 03:56:05" (3/4) ... [2024-11-14 03:56:54,083 INFO L136 WitnessPrinter]: Generating witness for reachability counterexample [2024-11-14 03:56:54,686 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/witness.graphml [2024-11-14 03:56:54,686 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-14 03:56:54,687 INFO L158 Benchmark]: Toolchain (without parser) took 51138.38ms. Allocated memory was 117.4MB in the beginning and 1.9GB in the end (delta: 1.8GB). Free memory was 93.8MB in the beginning and 967.5MB in the end (delta: -873.7MB). Peak memory consumption was 893.7MB. Max. memory is 16.1GB. [2024-11-14 03:56:54,689 INFO L158 Benchmark]: CDTParser took 0.41ms. Allocated memory is still 167.8MB. Free memory is still 104.5MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-14 03:56:54,689 INFO L158 Benchmark]: CACSL2BoogieTranslator took 477.91ms. Allocated memory is still 117.4MB. Free memory was 93.5MB in the beginning and 77.7MB in the end (delta: 15.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-14 03:56:54,690 INFO L158 Benchmark]: Boogie Procedure Inliner took 48.88ms. Allocated memory is still 117.4MB. Free memory was 77.7MB in the beginning and 75.4MB in the end (delta: 2.3MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-14 03:56:54,691 INFO L158 Benchmark]: Boogie Preprocessor took 54.92ms. Allocated memory is still 117.4MB. Free memory was 75.4MB in the beginning and 73.6MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-14 03:56:54,691 INFO L158 Benchmark]: RCFGBuilder took 1821.88ms. Allocated memory was 117.4MB in the beginning and 352.3MB in the end (delta: 234.9MB). Free memory was 73.2MB in the beginning and 267.0MB in the end (delta: -193.7MB). Peak memory consumption was 54.2MB. Max. memory is 16.1GB. [2024-11-14 03:56:54,692 INFO L158 Benchmark]: TraceAbstraction took 48120.27ms. Allocated memory was 352.3MB in the beginning and 1.9GB in the end (delta: 1.5GB). Free memory was 266.3MB in the beginning and 1.1GB in the end (delta: -790.2MB). Peak memory consumption was 744.6MB. Max. memory is 16.1GB. [2024-11-14 03:56:54,693 INFO L158 Benchmark]: Witness Printer took 604.91ms. Allocated memory is still 1.9GB. Free memory was 1.1GB in the beginning and 967.5MB in the end (delta: 89.0MB). Peak memory consumption was 92.3MB. Max. memory is 16.1GB. [2024-11-14 03:56:54,694 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.41ms. Allocated memory is still 167.8MB. Free memory is still 104.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 477.91ms. Allocated memory is still 117.4MB. Free memory was 93.5MB in the beginning and 77.7MB in the end (delta: 15.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 48.88ms. Allocated memory is still 117.4MB. Free memory was 77.7MB in the beginning and 75.4MB in the end (delta: 2.3MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 54.92ms. Allocated memory is still 117.4MB. Free memory was 75.4MB in the beginning and 73.6MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 1821.88ms. Allocated memory was 117.4MB in the beginning and 352.3MB in the end (delta: 234.9MB). Free memory was 73.2MB in the beginning and 267.0MB in the end (delta: -193.7MB). Peak memory consumption was 54.2MB. Max. memory is 16.1GB. * TraceAbstraction took 48120.27ms. Allocated memory was 352.3MB in the beginning and 1.9GB in the end (delta: 1.5GB). Free memory was 266.3MB in the beginning and 1.1GB in the end (delta: -790.2MB). Peak memory consumption was 744.6MB. Max. memory is 16.1GB. * Witness Printer took 604.91ms. Allocated memory is still 1.9GB. Free memory was 1.1GB in the beginning and 967.5MB in the end (delta: 89.0MB). Peak memory consumption was 92.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 19]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L23] int main_in1_val ; [L24] int main_in1_val_t ; [L25] int main_in1_ev ; [L26] int main_in1_req_up ; [L27] int main_in2_val ; [L28] int main_in2_val_t ; [L29] int main_in2_ev ; [L30] int main_in2_req_up ; [L31] int main_diff_val ; [L32] int main_diff_val_t ; [L33] int main_diff_ev ; [L34] int main_diff_req_up ; [L35] int main_sum_val ; [L36] int main_sum_val_t ; [L37] int main_sum_ev ; [L38] int main_sum_req_up ; [L39] int main_pres_val ; [L40] int main_pres_val_t ; [L41] int main_pres_ev ; [L42] int main_pres_req_up ; [L43] int main_dbl_val ; [L44] int main_dbl_val_t ; [L45] int main_dbl_ev ; [L46] int main_dbl_req_up ; [L47] int main_zero_val ; [L48] int main_zero_val_t ; [L49] int main_zero_ev ; [L50] int main_zero_req_up ; [L51] int main_clk_val ; [L52] int main_clk_val_t ; [L53] int main_clk_ev ; [L54] int main_clk_req_up ; [L55] int main_clk_pos_edge ; [L56] int main_clk_neg_edge ; [L57] int N_generate_st ; [L58] int N_generate_i ; [L59] int S1_addsub_st ; [L60] int S1_addsub_i ; [L61] int S2_presdbl_st ; [L62] int S2_presdbl_i ; [L63] int S3_zero_st ; [L64] int S3_zero_i ; [L65] int D_z ; [L66] int D_print_st ; [L67] int D_print_i ; [L759] int count ; [L760] int __retres2 ; [L765] main_in1_ev = 2 [L766] main_in1_req_up = 0 [L767] main_in2_ev = 2 [L768] main_in2_req_up = 0 [L769] main_diff_ev = 2 [L770] main_diff_req_up = 0 [L771] main_sum_ev = 2 [L772] main_sum_req_up = 0 [L773] main_pres_ev = 2 [L774] main_pres_req_up = 0 [L775] main_dbl_ev = 2 [L776] main_dbl_req_up = 0 [L777] main_zero_ev = 2 [L778] main_zero_req_up = 0 [L779] main_clk_val = 0 [L780] main_clk_ev = 2 [L781] main_clk_req_up = 0 [L782] main_clk_pos_edge = 2 [L783] main_clk_neg_edge = 2 [L786] count = 0 [L787] N_generate_i = 0 [L788] S1_addsub_i = 0 [L789] S2_presdbl_i = 0 [L790] S3_zero_i = 0 [L791] D_print_i = 0 VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, count=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L792] CALL start_simulation() VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND FALSE !((int )main_clk_req_up == 1) [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND FALSE !((int )main_clk_ev == 0) [L416] COND FALSE !((int )main_clk_pos_edge == 0) [L421] COND FALSE !((int )main_clk_neg_edge == 0) [L426] COND FALSE !((int )main_clk_pos_edge == 1) [L431] COND FALSE !((int )main_clk_pos_edge == 1) [L436] COND FALSE !((int )main_clk_pos_edge == 1) [L441] COND FALSE !((int )main_clk_pos_edge == 1) [L446] COND FALSE !((int )main_clk_pos_edge == 1) [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND FALSE !((int )main_clk_ev == 1) [L491] COND FALSE !((int )main_clk_pos_edge == 1) [L496] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L148] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L160] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L506] RET eval() [L508] kernel_st = 2 [L509] COND FALSE !((int )main_in1_req_up == 1) [L520] COND FALSE !((int )main_in2_req_up == 1) [L531] COND FALSE !((int )main_sum_req_up == 1) [L542] COND FALSE !((int )main_diff_req_up == 1) [L553] COND FALSE !((int )main_pres_req_up == 1) [L564] COND FALSE !((int )main_dbl_req_up == 1) [L575] COND FALSE !((int )main_zero_req_up == 1) [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L730] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L742] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=0, \old(D_z)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L792] RET start_simulation() VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, count=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L795] COND TRUE 1 [L798] main_clk_val_t = 1 [L799] main_clk_req_up = 1 VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, count=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L800] CALL start_simulation() VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND TRUE (int )main_clk_val == 1 [L338] main_clk_pos_edge = 0 [L339] main_clk_neg_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND TRUE (int )main_clk_pos_edge == 0 [L417] main_clk_pos_edge = 1 [L421] COND FALSE !((int )main_clk_neg_edge == 0) [L426] COND TRUE (int )main_clk_pos_edge == 1 [L427] N_generate_st = 0 [L431] COND TRUE (int )main_clk_pos_edge == 1 [L432] S1_addsub_st = 0 [L436] COND TRUE (int )main_clk_pos_edge == 1 [L437] S2_presdbl_st = 0 [L441] COND TRUE (int )main_clk_pos_edge == 1 [L442] S3_zero_st = 0 [L446] COND TRUE (int )main_clk_pos_edge == 1 [L447] D_print_st = 0 [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND TRUE (int )main_clk_pos_edge == 1 [L492] main_clk_pos_edge = 2 [L496] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L148] COND TRUE (int )N_generate_st == 0 VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L169] COND TRUE (int )N_generate_st == 0 [L171] tmp = __VERIFIER_nondet_int() [L173] COND TRUE \read(tmp) [L175] N_generate_st = 1 [L176] CALL N_generate() [L69] int a ; [L70] int b ; [L73] main_in1_val_t = a [L74] main_in1_req_up = 1 [L75] main_in2_val_t = b [L76] main_in2_req_up = 1 [L176] RET N_generate() [L184] COND TRUE (int )S1_addsub_st == 0 [L186] tmp___0 = __VERIFIER_nondet_int() [L188] COND TRUE \read(tmp___0) [L190] S1_addsub_st = 1 [L191] CALL S1_addsub() [L82] int a ; [L83] int b ; [L86] a = main_in1_val [L87] b = main_in2_val [L88] main_sum_val_t = a + b [L89] main_sum_req_up = 1 [L90] main_diff_val_t = a - b [L91] main_diff_req_up = 1 [L191] RET S1_addsub() [L199] COND TRUE (int )S2_presdbl_st == 0 [L201] tmp___1 = __VERIFIER_nondet_int() [L203] COND TRUE \read(tmp___1) [L205] S2_presdbl_st = 1 [L206] CALL S2_presdbl() [L97] int a ; [L98] int b ; [L99] int c ; [L100] int d ; [L103] a = main_sum_val [L104] b = main_diff_val [L105] main_pres_val_t = a [L106] main_pres_req_up = 1 [L107] c = a + b [L108] d = a - b [L109] main_dbl_val_t = c + d [L110] main_dbl_req_up = 1 [L206] RET S2_presdbl() [L214] COND TRUE (int )S3_zero_st == 0 [L216] tmp___2 = __VERIFIER_nondet_int() [L218] COND TRUE \read(tmp___2) [L220] S3_zero_st = 1 [L221] CALL S3_zero() [L116] int a ; [L117] int b ; [L120] a = main_pres_val [L121] b = main_dbl_val [L122] main_zero_val_t = b - (a + a) [L123] main_zero_req_up = 1 [L221] RET S3_zero() [L229] COND TRUE (int )D_print_st == 0 [L231] tmp___3 = __VERIFIER_nondet_int() [L233] COND TRUE \read(tmp___3) [L235] D_print_st = 1 [L236] CALL D_print() [L132] D_z = main_zero_val [L236] RET D_print() [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=75, tmp___0=81, tmp___1=64, tmp___2=144, tmp___3=51] [L148] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=75, tmp___0=81, tmp___1=64, tmp___2=144, tmp___3=51] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=75, tmp___0=81, tmp___1=64, tmp___2=144, tmp___3=51] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=75, tmp___0=81, tmp___1=64, tmp___2=144, tmp___3=51] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=75, tmp___0=81, tmp___1=64, tmp___2=144, tmp___3=51] [L160] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=75, tmp___0=81, tmp___1=64, tmp___2=144, tmp___3=51] [L506] RET eval() [L508] kernel_st = 2 [L509] COND TRUE (int )main_in1_req_up == 1 [L510] COND FALSE !(main_in1_val != main_in1_val_t) [L516] main_in1_req_up = 0 [L520] COND TRUE (int )main_in2_req_up == 1 [L521] COND FALSE !(main_in2_val != main_in2_val_t) [L527] main_in2_req_up = 0 [L531] COND TRUE (int )main_sum_req_up == 1 [L532] COND FALSE !(main_sum_val != main_sum_val_t) [L538] main_sum_req_up = 0 [L542] COND TRUE (int )main_diff_req_up == 1 [L543] COND FALSE !(main_diff_val != main_diff_val_t) [L549] main_diff_req_up = 0 [L553] COND TRUE (int )main_pres_req_up == 1 [L554] COND FALSE !(main_pres_val != main_pres_val_t) [L560] main_pres_req_up = 0 [L564] COND TRUE (int )main_dbl_req_up == 1 [L565] COND FALSE !(main_dbl_val != main_dbl_val_t) [L571] main_dbl_req_up = 0 [L575] COND TRUE (int )main_zero_req_up == 1 [L576] COND FALSE !(main_zero_val != main_zero_val_t) [L582] main_zero_req_up = 0 [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L730] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L742] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L800] RET start_simulation() VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L801] count += 1 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=1, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L803] COND FALSE !(count == 5) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=1, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L816] main_clk_val_t = 0 [L817] main_clk_req_up = 1 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=1, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L818] CALL start_simulation() VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND FALSE !((int )main_clk_val == 1) [L341] main_clk_neg_edge = 0 [L342] main_clk_pos_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND FALSE !((int )main_clk_pos_edge == 0) [L421] COND TRUE (int )main_clk_neg_edge == 0 [L422] main_clk_neg_edge = 1 [L426] COND FALSE !((int )main_clk_pos_edge == 1) [L431] COND FALSE !((int )main_clk_pos_edge == 1) [L436] COND FALSE !((int )main_clk_pos_edge == 1) [L441] COND FALSE !((int )main_clk_pos_edge == 1) [L446] COND FALSE !((int )main_clk_pos_edge == 1) [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND FALSE !((int )main_clk_pos_edge == 1) [L496] COND TRUE (int )main_clk_neg_edge == 1 [L497] main_clk_neg_edge = 2 VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L148] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L160] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L506] RET eval() [L508] kernel_st = 2 [L509] COND FALSE !((int )main_in1_req_up == 1) [L520] COND FALSE !((int )main_in2_req_up == 1) [L531] COND FALSE !((int )main_sum_req_up == 1) [L542] COND FALSE !((int )main_diff_req_up == 1) [L553] COND FALSE !((int )main_pres_req_up == 1) [L564] COND FALSE !((int )main_dbl_req_up == 1) [L575] COND FALSE !((int )main_zero_req_up == 1) [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L730] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L742] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L818] RET start_simulation() VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, count=1, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L795] COND TRUE 1 [L798] main_clk_val_t = 1 [L799] main_clk_req_up = 1 VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, count=1, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L800] CALL start_simulation() VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND TRUE (int )main_clk_val == 1 [L338] main_clk_pos_edge = 0 [L339] main_clk_neg_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND TRUE (int )main_clk_pos_edge == 0 [L417] main_clk_pos_edge = 1 [L421] COND FALSE !((int )main_clk_neg_edge == 0) [L426] COND TRUE (int )main_clk_pos_edge == 1 [L427] N_generate_st = 0 [L431] COND TRUE (int )main_clk_pos_edge == 1 [L432] S1_addsub_st = 0 [L436] COND TRUE (int )main_clk_pos_edge == 1 [L437] S2_presdbl_st = 0 [L441] COND TRUE (int )main_clk_pos_edge == 1 [L442] S3_zero_st = 0 [L446] COND TRUE (int )main_clk_pos_edge == 1 [L447] D_print_st = 0 [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND TRUE (int )main_clk_pos_edge == 1 [L492] main_clk_pos_edge = 2 [L496] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L148] COND TRUE (int )N_generate_st == 0 VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L169] COND TRUE (int )N_generate_st == 0 [L171] tmp = __VERIFIER_nondet_int() [L173] COND TRUE \read(tmp) [L175] N_generate_st = 1 [L176] CALL N_generate() [L69] int a ; [L70] int b ; [L73] main_in1_val_t = a [L74] main_in1_req_up = 1 [L75] main_in2_val_t = b [L76] main_in2_req_up = 1 [L176] RET N_generate() [L184] COND TRUE (int )S1_addsub_st == 0 [L186] tmp___0 = __VERIFIER_nondet_int() [L188] COND TRUE \read(tmp___0) [L190] S1_addsub_st = 1 [L191] CALL S1_addsub() [L82] int a ; [L83] int b ; [L86] a = main_in1_val [L87] b = main_in2_val [L88] main_sum_val_t = a + b [L89] main_sum_req_up = 1 [L90] main_diff_val_t = a - b [L91] main_diff_req_up = 1 [L191] RET S1_addsub() [L199] COND TRUE (int )S2_presdbl_st == 0 [L201] tmp___1 = __VERIFIER_nondet_int() [L203] COND TRUE \read(tmp___1) [L205] S2_presdbl_st = 1 [L206] CALL S2_presdbl() [L97] int a ; [L98] int b ; [L99] int c ; [L100] int d ; [L103] a = main_sum_val [L104] b = main_diff_val [L105] main_pres_val_t = a [L106] main_pres_req_up = 1 [L107] c = a + b [L108] d = a - b [L109] main_dbl_val_t = c + d [L110] main_dbl_req_up = 1 [L206] RET S2_presdbl() [L214] COND TRUE (int )S3_zero_st == 0 [L216] tmp___2 = __VERIFIER_nondet_int() [L218] COND TRUE \read(tmp___2) [L220] S3_zero_st = 1 [L221] CALL S3_zero() [L116] int a ; [L117] int b ; [L120] a = main_pres_val [L121] b = main_dbl_val [L122] main_zero_val_t = b - (a + a) [L123] main_zero_req_up = 1 [L221] RET S3_zero() [L229] COND TRUE (int )D_print_st == 0 [L231] tmp___3 = __VERIFIER_nondet_int() [L233] COND TRUE \read(tmp___3) [L235] D_print_st = 1 [L236] CALL D_print() [L132] D_z = main_zero_val [L236] RET D_print() [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=76, tmp___0=141, tmp___1=94, tmp___2=118, tmp___3=99] [L148] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=76, tmp___0=141, tmp___1=94, tmp___2=118, tmp___3=99] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=76, tmp___0=141, tmp___1=94, tmp___2=118, tmp___3=99] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=76, tmp___0=141, tmp___1=94, tmp___2=118, tmp___3=99] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=76, tmp___0=141, tmp___1=94, tmp___2=118, tmp___3=99] [L160] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=76, tmp___0=141, tmp___1=94, tmp___2=118, tmp___3=99] [L506] RET eval() [L508] kernel_st = 2 [L509] COND TRUE (int )main_in1_req_up == 1 [L510] COND FALSE !(main_in1_val != main_in1_val_t) [L516] main_in1_req_up = 0 [L520] COND TRUE (int )main_in2_req_up == 1 [L521] COND FALSE !(main_in2_val != main_in2_val_t) [L527] main_in2_req_up = 0 [L531] COND TRUE (int )main_sum_req_up == 1 [L532] COND FALSE !(main_sum_val != main_sum_val_t) [L538] main_sum_req_up = 0 [L542] COND TRUE (int )main_diff_req_up == 1 [L543] COND FALSE !(main_diff_val != main_diff_val_t) [L549] main_diff_req_up = 0 [L553] COND TRUE (int )main_pres_req_up == 1 [L554] COND FALSE !(main_pres_val != main_pres_val_t) [L560] main_pres_req_up = 0 [L564] COND TRUE (int )main_dbl_req_up == 1 [L565] COND FALSE !(main_dbl_val != main_dbl_val_t) [L571] main_dbl_req_up = 0 [L575] COND TRUE (int )main_zero_req_up == 1 [L576] COND FALSE !(main_zero_val != main_zero_val_t) [L582] main_zero_req_up = 0 [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L730] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L742] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L800] RET start_simulation() VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=1, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L801] count += 1 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=2, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L803] COND FALSE !(count == 5) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=2, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L816] main_clk_val_t = 0 [L817] main_clk_req_up = 1 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=2, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L818] CALL start_simulation() VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND FALSE !((int )main_clk_val == 1) [L341] main_clk_neg_edge = 0 [L342] main_clk_pos_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND FALSE !((int )main_clk_pos_edge == 0) [L421] COND TRUE (int )main_clk_neg_edge == 0 [L422] main_clk_neg_edge = 1 [L426] COND FALSE !((int )main_clk_pos_edge == 1) [L431] COND FALSE !((int )main_clk_pos_edge == 1) [L436] COND FALSE !((int )main_clk_pos_edge == 1) [L441] COND FALSE !((int )main_clk_pos_edge == 1) [L446] COND FALSE !((int )main_clk_pos_edge == 1) [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND FALSE !((int )main_clk_pos_edge == 1) [L496] COND TRUE (int )main_clk_neg_edge == 1 [L497] main_clk_neg_edge = 2 VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L148] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L160] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L506] RET eval() [L508] kernel_st = 2 [L509] COND FALSE !((int )main_in1_req_up == 1) [L520] COND FALSE !((int )main_in2_req_up == 1) [L531] COND FALSE !((int )main_sum_req_up == 1) [L542] COND FALSE !((int )main_diff_req_up == 1) [L553] COND FALSE !((int )main_pres_req_up == 1) [L564] COND FALSE !((int )main_dbl_req_up == 1) [L575] COND FALSE !((int )main_zero_req_up == 1) [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L730] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L742] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L818] RET start_simulation() VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, count=2, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L795] COND TRUE 1 [L798] main_clk_val_t = 1 [L799] main_clk_req_up = 1 VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, count=2, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L800] CALL start_simulation() VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND TRUE (int )main_clk_val == 1 [L338] main_clk_pos_edge = 0 [L339] main_clk_neg_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND TRUE (int )main_clk_pos_edge == 0 [L417] main_clk_pos_edge = 1 [L421] COND FALSE !((int )main_clk_neg_edge == 0) [L426] COND TRUE (int )main_clk_pos_edge == 1 [L427] N_generate_st = 0 [L431] COND TRUE (int )main_clk_pos_edge == 1 [L432] S1_addsub_st = 0 [L436] COND TRUE (int )main_clk_pos_edge == 1 [L437] S2_presdbl_st = 0 [L441] COND TRUE (int )main_clk_pos_edge == 1 [L442] S3_zero_st = 0 [L446] COND TRUE (int )main_clk_pos_edge == 1 [L447] D_print_st = 0 [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND TRUE (int )main_clk_pos_edge == 1 [L492] main_clk_pos_edge = 2 [L496] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L148] COND TRUE (int )N_generate_st == 0 VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L169] COND TRUE (int )N_generate_st == 0 [L171] tmp = __VERIFIER_nondet_int() [L173] COND TRUE \read(tmp) [L175] N_generate_st = 1 [L176] CALL N_generate() [L69] int a ; [L70] int b ; [L73] main_in1_val_t = a [L74] main_in1_req_up = 1 [L75] main_in2_val_t = b [L76] main_in2_req_up = 1 [L176] RET N_generate() [L184] COND TRUE (int )S1_addsub_st == 0 [L186] tmp___0 = __VERIFIER_nondet_int() [L188] COND TRUE \read(tmp___0) [L190] S1_addsub_st = 1 [L191] CALL S1_addsub() [L82] int a ; [L83] int b ; [L86] a = main_in1_val [L87] b = main_in2_val [L88] main_sum_val_t = a + b [L89] main_sum_req_up = 1 [L90] main_diff_val_t = a - b [L91] main_diff_req_up = 1 [L191] RET S1_addsub() [L199] COND TRUE (int )S2_presdbl_st == 0 [L201] tmp___1 = __VERIFIER_nondet_int() [L203] COND TRUE \read(tmp___1) [L205] S2_presdbl_st = 1 [L206] CALL S2_presdbl() [L97] int a ; [L98] int b ; [L99] int c ; [L100] int d ; [L103] a = main_sum_val [L104] b = main_diff_val [L105] main_pres_val_t = a [L106] main_pres_req_up = 1 [L107] c = a + b [L108] d = a - b [L109] main_dbl_val_t = c + d [L110] main_dbl_req_up = 1 [L206] RET S2_presdbl() [L214] COND TRUE (int )S3_zero_st == 0 [L216] tmp___2 = __VERIFIER_nondet_int() [L218] COND TRUE \read(tmp___2) [L220] S3_zero_st = 1 [L221] CALL S3_zero() [L116] int a ; [L117] int b ; [L120] a = main_pres_val [L121] b = main_dbl_val [L122] main_zero_val_t = b - (a + a) [L123] main_zero_req_up = 1 [L221] RET S3_zero() [L229] COND TRUE (int )D_print_st == 0 [L231] tmp___3 = __VERIFIER_nondet_int() [L233] COND TRUE \read(tmp___3) [L235] D_print_st = 1 [L236] CALL D_print() [L132] D_z = main_zero_val [L236] RET D_print() [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=129, tmp___0=90, tmp___1=101, tmp___2=115, tmp___3=67] [L148] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=129, tmp___0=90, tmp___1=101, tmp___2=115, tmp___3=67] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=129, tmp___0=90, tmp___1=101, tmp___2=115, tmp___3=67] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=129, tmp___0=90, tmp___1=101, tmp___2=115, tmp___3=67] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=129, tmp___0=90, tmp___1=101, tmp___2=115, tmp___3=67] [L160] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=129, tmp___0=90, tmp___1=101, tmp___2=115, tmp___3=67] [L506] RET eval() [L508] kernel_st = 2 [L509] COND TRUE (int )main_in1_req_up == 1 [L510] COND FALSE !(main_in1_val != main_in1_val_t) [L516] main_in1_req_up = 0 [L520] COND TRUE (int )main_in2_req_up == 1 [L521] COND FALSE !(main_in2_val != main_in2_val_t) [L527] main_in2_req_up = 0 [L531] COND TRUE (int )main_sum_req_up == 1 [L532] COND FALSE !(main_sum_val != main_sum_val_t) [L538] main_sum_req_up = 0 [L542] COND TRUE (int )main_diff_req_up == 1 [L543] COND FALSE !(main_diff_val != main_diff_val_t) [L549] main_diff_req_up = 0 [L553] COND TRUE (int )main_pres_req_up == 1 [L554] COND FALSE !(main_pres_val != main_pres_val_t) [L560] main_pres_req_up = 0 [L564] COND TRUE (int )main_dbl_req_up == 1 [L565] COND FALSE !(main_dbl_val != main_dbl_val_t) [L571] main_dbl_req_up = 0 [L575] COND TRUE (int )main_zero_req_up == 1 [L576] COND FALSE !(main_zero_val != main_zero_val_t) [L582] main_zero_req_up = 0 [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L730] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L742] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L800] RET start_simulation() VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=2, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L801] count += 1 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L803] COND FALSE !(count == 5) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L816] main_clk_val_t = 0 [L817] main_clk_req_up = 1 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L818] CALL start_simulation() VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND FALSE !((int )main_clk_val == 1) [L341] main_clk_neg_edge = 0 [L342] main_clk_pos_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND FALSE !((int )main_clk_pos_edge == 0) [L421] COND TRUE (int )main_clk_neg_edge == 0 [L422] main_clk_neg_edge = 1 [L426] COND FALSE !((int )main_clk_pos_edge == 1) [L431] COND FALSE !((int )main_clk_pos_edge == 1) [L436] COND FALSE !((int )main_clk_pos_edge == 1) [L441] COND FALSE !((int )main_clk_pos_edge == 1) [L446] COND FALSE !((int )main_clk_pos_edge == 1) [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND FALSE !((int )main_clk_pos_edge == 1) [L496] COND TRUE (int )main_clk_neg_edge == 1 [L497] main_clk_neg_edge = 2 VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L148] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L160] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L506] RET eval() [L508] kernel_st = 2 [L509] COND FALSE !((int )main_in1_req_up == 1) [L520] COND FALSE !((int )main_in2_req_up == 1) [L531] COND FALSE !((int )main_sum_req_up == 1) [L542] COND FALSE !((int )main_diff_req_up == 1) [L553] COND FALSE !((int )main_pres_req_up == 1) [L564] COND FALSE !((int )main_dbl_req_up == 1) [L575] COND FALSE !((int )main_zero_req_up == 1) [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L730] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L742] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L818] RET start_simulation() VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, count=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L795] COND TRUE 1 [L798] main_clk_val_t = 1 [L799] main_clk_req_up = 1 VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, count=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L800] CALL start_simulation() VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND TRUE (int )main_clk_val == 1 [L338] main_clk_pos_edge = 0 [L339] main_clk_neg_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND TRUE (int )main_clk_pos_edge == 0 [L417] main_clk_pos_edge = 1 [L421] COND FALSE !((int )main_clk_neg_edge == 0) [L426] COND TRUE (int )main_clk_pos_edge == 1 [L427] N_generate_st = 0 [L431] COND TRUE (int )main_clk_pos_edge == 1 [L432] S1_addsub_st = 0 [L436] COND TRUE (int )main_clk_pos_edge == 1 [L437] S2_presdbl_st = 0 [L441] COND TRUE (int )main_clk_pos_edge == 1 [L442] S3_zero_st = 0 [L446] COND TRUE (int )main_clk_pos_edge == 1 [L447] D_print_st = 0 [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND TRUE (int )main_clk_pos_edge == 1 [L492] main_clk_pos_edge = 2 [L496] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L148] COND TRUE (int )N_generate_st == 0 VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L169] COND TRUE (int )N_generate_st == 0 [L171] tmp = __VERIFIER_nondet_int() [L173] COND TRUE \read(tmp) [L175] N_generate_st = 1 [L176] CALL N_generate() [L69] int a ; [L70] int b ; [L73] main_in1_val_t = a [L74] main_in1_req_up = 1 [L75] main_in2_val_t = b [L76] main_in2_req_up = 1 [L176] RET N_generate() [L184] COND TRUE (int )S1_addsub_st == 0 [L186] tmp___0 = __VERIFIER_nondet_int() [L188] COND TRUE \read(tmp___0) [L190] S1_addsub_st = 1 [L191] CALL S1_addsub() [L82] int a ; [L83] int b ; [L86] a = main_in1_val [L87] b = main_in2_val [L88] main_sum_val_t = a + b [L89] main_sum_req_up = 1 [L90] main_diff_val_t = a - b [L91] main_diff_req_up = 1 [L191] RET S1_addsub() [L199] COND TRUE (int )S2_presdbl_st == 0 [L201] tmp___1 = __VERIFIER_nondet_int() [L203] COND TRUE \read(tmp___1) [L205] S2_presdbl_st = 1 [L206] CALL S2_presdbl() [L97] int a ; [L98] int b ; [L99] int c ; [L100] int d ; [L103] a = main_sum_val [L104] b = main_diff_val [L105] main_pres_val_t = a [L106] main_pres_req_up = 1 [L107] c = a + b [L108] d = a - b [L109] main_dbl_val_t = c + d [L110] main_dbl_req_up = 1 [L206] RET S2_presdbl() [L214] COND TRUE (int )S3_zero_st == 0 [L216] tmp___2 = __VERIFIER_nondet_int() [L218] COND TRUE \read(tmp___2) [L220] S3_zero_st = 1 [L221] CALL S3_zero() [L116] int a ; [L117] int b ; [L120] a = main_pres_val [L121] b = main_dbl_val [L122] main_zero_val_t = b - (a + a) [L123] main_zero_req_up = 1 [L221] RET S3_zero() [L229] COND TRUE (int )D_print_st == 0 [L231] tmp___3 = __VERIFIER_nondet_int() [L233] COND TRUE \read(tmp___3) [L235] D_print_st = 1 [L236] CALL D_print() [L132] D_z = main_zero_val [L236] RET D_print() [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=53, tmp___0=138, tmp___1=140, tmp___2=74, tmp___3=84] [L148] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=53, tmp___0=138, tmp___1=140, tmp___2=74, tmp___3=84] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=53, tmp___0=138, tmp___1=140, tmp___2=74, tmp___3=84] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=53, tmp___0=138, tmp___1=140, tmp___2=74, tmp___3=84] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=53, tmp___0=138, tmp___1=140, tmp___2=74, tmp___3=84] [L160] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=53, tmp___0=138, tmp___1=140, tmp___2=74, tmp___3=84] [L506] RET eval() [L508] kernel_st = 2 [L509] COND TRUE (int )main_in1_req_up == 1 [L510] COND FALSE !(main_in1_val != main_in1_val_t) [L516] main_in1_req_up = 0 [L520] COND TRUE (int )main_in2_req_up == 1 [L521] COND FALSE !(main_in2_val != main_in2_val_t) [L527] main_in2_req_up = 0 [L531] COND TRUE (int )main_sum_req_up == 1 [L532] COND FALSE !(main_sum_val != main_sum_val_t) [L538] main_sum_req_up = 0 [L542] COND TRUE (int )main_diff_req_up == 1 [L543] COND FALSE !(main_diff_val != main_diff_val_t) [L549] main_diff_req_up = 0 [L553] COND TRUE (int )main_pres_req_up == 1 [L554] COND FALSE !(main_pres_val != main_pres_val_t) [L560] main_pres_req_up = 0 [L564] COND TRUE (int )main_dbl_req_up == 1 [L565] COND FALSE !(main_dbl_val != main_dbl_val_t) [L571] main_dbl_req_up = 0 [L575] COND TRUE (int )main_zero_req_up == 1 [L576] COND FALSE !(main_zero_val != main_zero_val_t) [L582] main_zero_req_up = 0 [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L730] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L742] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L800] RET start_simulation() VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L801] count += 1 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=4, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L803] COND FALSE !(count == 5) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=4, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L816] main_clk_val_t = 0 [L817] main_clk_req_up = 1 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=4, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L818] CALL start_simulation() VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND FALSE !((int )main_clk_val == 1) [L341] main_clk_neg_edge = 0 [L342] main_clk_pos_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND FALSE !((int )main_clk_pos_edge == 0) [L421] COND TRUE (int )main_clk_neg_edge == 0 [L422] main_clk_neg_edge = 1 [L426] COND FALSE !((int )main_clk_pos_edge == 1) [L431] COND FALSE !((int )main_clk_pos_edge == 1) [L436] COND FALSE !((int )main_clk_pos_edge == 1) [L441] COND FALSE !((int )main_clk_pos_edge == 1) [L446] COND FALSE !((int )main_clk_pos_edge == 1) [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND FALSE !((int )main_clk_pos_edge == 1) [L496] COND TRUE (int )main_clk_neg_edge == 1 [L497] main_clk_neg_edge = 2 VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L148] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L160] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L506] RET eval() [L508] kernel_st = 2 [L509] COND FALSE !((int )main_in1_req_up == 1) [L520] COND FALSE !((int )main_in2_req_up == 1) [L531] COND FALSE !((int )main_sum_req_up == 1) [L542] COND FALSE !((int )main_diff_req_up == 1) [L553] COND FALSE !((int )main_pres_req_up == 1) [L564] COND FALSE !((int )main_dbl_req_up == 1) [L575] COND FALSE !((int )main_zero_req_up == 1) [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L730] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L742] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=1, \old(D_z)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L818] RET start_simulation() VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, count=4, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L795] COND TRUE 1 [L798] main_clk_val_t = 1 [L799] main_clk_req_up = 1 VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, count=4, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L800] CALL start_simulation() VAL [D_print_i=0, D_print_st=2, D_z=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND TRUE (int )main_clk_val == 1 [L338] main_clk_pos_edge = 0 [L339] main_clk_neg_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND TRUE (int )main_clk_pos_edge == 0 [L417] main_clk_pos_edge = 1 [L421] COND FALSE !((int )main_clk_neg_edge == 0) [L426] COND TRUE (int )main_clk_pos_edge == 1 [L427] N_generate_st = 0 [L431] COND TRUE (int )main_clk_pos_edge == 1 [L432] S1_addsub_st = 0 [L436] COND TRUE (int )main_clk_pos_edge == 1 [L437] S2_presdbl_st = 0 [L441] COND TRUE (int )main_clk_pos_edge == 1 [L442] S3_zero_st = 0 [L446] COND TRUE (int )main_clk_pos_edge == 1 [L447] D_print_st = 0 [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND TRUE (int )main_clk_pos_edge == 1 [L492] main_clk_pos_edge = 2 [L496] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L148] COND TRUE (int )N_generate_st == 0 VAL [D_print_i=0, D_print_st=0, D_z=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L169] COND TRUE (int )N_generate_st == 0 [L171] tmp = __VERIFIER_nondet_int() [L173] COND TRUE \read(tmp) [L175] N_generate_st = 1 [L176] CALL N_generate() [L69] int a ; [L70] int b ; [L73] main_in1_val_t = a [L74] main_in1_req_up = 1 [L75] main_in2_val_t = b [L76] main_in2_req_up = 1 [L176] RET N_generate() [L184] COND TRUE (int )S1_addsub_st == 0 [L186] tmp___0 = __VERIFIER_nondet_int() [L188] COND TRUE \read(tmp___0) [L190] S1_addsub_st = 1 [L191] CALL S1_addsub() [L82] int a ; [L83] int b ; [L86] a = main_in1_val [L87] b = main_in2_val [L88] main_sum_val_t = a + b [L89] main_sum_req_up = 1 [L90] main_diff_val_t = a - b [L91] main_diff_req_up = 1 [L191] RET S1_addsub() [L199] COND TRUE (int )S2_presdbl_st == 0 [L201] tmp___1 = __VERIFIER_nondet_int() [L203] COND TRUE \read(tmp___1) [L205] S2_presdbl_st = 1 [L206] CALL S2_presdbl() [L97] int a ; [L98] int b ; [L99] int c ; [L100] int d ; [L103] a = main_sum_val [L104] b = main_diff_val [L105] main_pres_val_t = a [L106] main_pres_req_up = 1 [L107] c = a + b [L108] d = a - b [L109] main_dbl_val_t = c + d [L110] main_dbl_req_up = 1 [L206] RET S2_presdbl() [L214] COND TRUE (int )S3_zero_st == 0 [L216] tmp___2 = __VERIFIER_nondet_int() [L218] COND TRUE \read(tmp___2) [L220] S3_zero_st = 1 [L221] CALL S3_zero() [L116] int a ; [L117] int b ; [L120] a = main_pres_val [L121] b = main_dbl_val [L122] main_zero_val_t = b - (a + a) [L123] main_zero_req_up = 1 [L221] RET S3_zero() [L229] COND TRUE (int )D_print_st == 0 [L231] tmp___3 = __VERIFIER_nondet_int() [L233] COND TRUE \read(tmp___3) [L235] D_print_st = 1 [L236] CALL D_print() [L132] D_z = main_zero_val [L236] RET D_print() [L146] COND TRUE 1 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=109, tmp___0=88, tmp___1=126, tmp___2=131, tmp___3=127] [L148] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=109, tmp___0=88, tmp___1=126, tmp___2=131, tmp___3=127] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=109, tmp___0=88, tmp___1=126, tmp___2=131, tmp___3=127] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=109, tmp___0=88, tmp___1=126, tmp___2=131, tmp___3=127] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=109, tmp___0=88, tmp___1=126, tmp___2=131, tmp___3=127] [L160] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, tmp=109, tmp___0=88, tmp___1=126, tmp___2=131, tmp___3=127] [L506] RET eval() [L508] kernel_st = 2 [L509] COND TRUE (int )main_in1_req_up == 1 [L510] COND FALSE !(main_in1_val != main_in1_val_t) [L516] main_in1_req_up = 0 [L520] COND TRUE (int )main_in2_req_up == 1 [L521] COND FALSE !(main_in2_val != main_in2_val_t) [L527] main_in2_req_up = 0 [L531] COND TRUE (int )main_sum_req_up == 1 [L532] COND FALSE !(main_sum_val != main_sum_val_t) [L538] main_sum_req_up = 0 [L542] COND TRUE (int )main_diff_req_up == 1 [L543] COND FALSE !(main_diff_val != main_diff_val_t) [L549] main_diff_req_up = 0 [L553] COND TRUE (int )main_pres_req_up == 1 [L554] COND FALSE !(main_pres_val != main_pres_val_t) [L560] main_pres_req_up = 0 [L564] COND TRUE (int )main_dbl_req_up == 1 [L565] COND FALSE !(main_dbl_val != main_dbl_val_t) [L571] main_dbl_req_up = 0 [L575] COND TRUE (int )main_zero_req_up == 1 [L576] COND FALSE !(main_zero_val != main_zero_val_t) [L582] main_zero_req_up = 0 [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L730] COND FALSE !((int )N_generate_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L742] COND FALSE !((int )D_print_st == 0) VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, \old(D_print_st)=2, \old(D_z)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L800] RET start_simulation() VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=4, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L801] count += 1 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, count=5, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L803] COND TRUE count == 5 VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] [L804] COND TRUE (D_z == 0) [L806] CALL error() [L19] reach_error() VAL [D_print_i=0, D_print_st=1, D_z=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 30 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 47.4s, OverallIterations: 5, TraceHistogramMax: 15, PathProgramHistogramMax: 2, EmptinessCheckTime: 0.0s, AutomataDifference: 2.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 850 SdHoareTripleChecker+Valid, 1.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 843 mSDsluCounter, 1377 SdHoareTripleChecker+Invalid, 0.9s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1189 mSDsCounter, 128 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 532 IncrementalHoareTripleChecker+Invalid, 660 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 128 mSolverCounterUnsat, 188 mSDtfsCounter, 532 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 957 GetRequests, 846 SyntacticMatches, 1 SemanticMatches, 110 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1532 ImplicationChecksByTransitivity, 5.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=91occurred in iteration=3, InterpolantAutomatonStates: 47, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 4 MinimizatonAttempts, 48 StatesRemovedByMinimization, 3 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.6s SsaConstructionTime, 1.7s SatisfiabilityAnalysisTime, 25.0s InterpolantComputationTime, 865 NumberOfCodeBlocks, 865 NumberOfCodeBlocksAsserted, 9 NumberOfCheckSat, 921 ConstructedInterpolants, 0 QuantifiedInterpolants, 3632 SizeOfPredicates, 10 NumberOfNonLiveVariables, 4827 ConjunctsInSsa, 36 ConjunctsInUnsatCore, 10 InterpolantComputations, 2 PerfectInterpolantSequences, 2105/2716 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2024-11-14 03:56:54,774 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_96d8b435-0906-47ad-8397-562f714bb05f/bin/utaipan-verify-sOmjnqqW8E/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE