./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 23:49:27,930 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 23:49:28,055 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E/config/svcomp-Reach-32bit-Taipan_Default.epf [2024-11-13 23:49:28,062 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 23:49:28,062 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 23:49:28,111 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 23:49:28,112 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 23:49:28,112 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 23:49:28,113 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-13 23:49:28,113 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-13 23:49:28,113 INFO L153 SettingsManager]: * User list type=DISABLED [2024-11-13 23:49:28,113 INFO L151 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2024-11-13 23:49:28,113 INFO L153 SettingsManager]: * Explicit value domain=true [2024-11-13 23:49:28,113 INFO L153 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2024-11-13 23:49:28,114 INFO L153 SettingsManager]: * Octagon Domain=false [2024-11-13 23:49:28,114 INFO L153 SettingsManager]: * Abstract domain=CompoundDomain [2024-11-13 23:49:28,114 INFO L153 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2024-11-13 23:49:28,114 INFO L153 SettingsManager]: * Use the RCFG-of-the-future interface=true [2024-11-13 23:49:28,114 INFO L153 SettingsManager]: * Interval Domain=false [2024-11-13 23:49:28,114 INFO L151 SettingsManager]: Preferences of Sifa differ from their defaults: [2024-11-13 23:49:28,114 INFO L153 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2024-11-13 23:49:28,115 INFO L153 SettingsManager]: * Simplification Technique=POLY_PAC [2024-11-13 23:49:28,117 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 23:49:28,118 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-13 23:49:28,118 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 23:49:28,118 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 23:49:28,118 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 23:49:28,118 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 23:49:28,118 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-13 23:49:28,118 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-13 23:49:28,118 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-13 23:49:28,119 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 23:49:28,119 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 23:49:28,119 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 23:49:28,119 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 23:49:28,119 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 23:49:28,119 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-13 23:49:28,119 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-13 23:49:28,119 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-11-13 23:49:28,120 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 23:49:28,120 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-13 23:49:28,120 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-13 23:49:28,120 INFO L153 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2024-11-13 23:49:28,120 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-13 23:49:28,120 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-13 23:49:28,121 INFO L153 SettingsManager]: * Trace refinement exception blacklist=NONE [2024-11-13 23:49:28,121 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-13 23:49:28,121 INFO L153 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2024-11-13 23:49:28,463 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 23:49:28,474 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 23:49:28,476 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 23:49:28,478 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 23:49:28,479 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 23:49:28,480 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E/../../sv-benchmarks/c/systemc/transmitter.15.cil.c Unable to find full path for "g++" [2024-11-13 23:49:30,886 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 23:49:31,340 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 23:49:31,344 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/sv-benchmarks/c/systemc/transmitter.15.cil.c [2024-11-13 23:49:31,371 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E/data/c5ade3ed2/2ca24c7704f74a1ab00f3f9d7cfb5d18/FLAGbd922be9f [2024-11-13 23:49:31,389 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E/data/c5ade3ed2/2ca24c7704f74a1ab00f3f9d7cfb5d18 [2024-11-13 23:49:31,392 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 23:49:31,394 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 23:49:31,395 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 23:49:31,396 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 23:49:31,401 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 23:49:31,402 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 11:49:31" (1/1) ... [2024-11-13 23:49:31,403 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5314d2e2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 11:49:31, skipping insertion in model container [2024-11-13 23:49:31,404 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 11:49:31" (1/1) ... [2024-11-13 23:49:31,469 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 23:49:31,708 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2024-11-13 23:49:31,948 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 23:49:31,966 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 23:49:31,978 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2024-11-13 23:49:32,068 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 23:49:32,094 INFO L204 MainTranslator]: Completed translation [2024-11-13 23:49:32,094 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 11:49:32 WrapperNode [2024-11-13 23:49:32,095 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 23:49:32,096 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 23:49:32,096 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 23:49:32,096 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 23:49:32,107 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 11:49:32" (1/1) ... [2024-11-13 23:49:32,118 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 11:49:32" (1/1) ... [2024-11-13 23:49:32,169 INFO L138 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 38, calls inlined = 38, statements flattened = 901 [2024-11-13 23:49:32,169 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 23:49:32,170 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 23:49:32,170 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 23:49:32,170 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 23:49:32,179 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 11:49:32" (1/1) ... [2024-11-13 23:49:32,180 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 11:49:32" (1/1) ... [2024-11-13 23:49:32,184 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 11:49:32" (1/1) ... [2024-11-13 23:49:32,185 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 11:49:32" (1/1) ... [2024-11-13 23:49:32,213 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 11:49:32" (1/1) ... [2024-11-13 23:49:32,241 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 11:49:32" (1/1) ... [2024-11-13 23:49:32,252 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 11:49:32" (1/1) ... [2024-11-13 23:49:32,255 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 11:49:32" (1/1) ... [2024-11-13 23:49:32,267 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 23:49:32,272 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 23:49:32,273 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 23:49:32,273 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 23:49:32,274 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 11:49:32" (1/1) ... [2024-11-13 23:49:32,285 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-11-13 23:49:32,308 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E/z3 [2024-11-13 23:49:32,322 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2024-11-13 23:49:32,327 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2024-11-13 23:49:32,364 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 23:49:32,364 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2024-11-13 23:49:32,364 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2024-11-13 23:49:32,364 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2024-11-13 23:49:32,364 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2024-11-13 23:49:32,365 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2024-11-13 23:49:32,365 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2024-11-13 23:49:32,365 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2024-11-13 23:49:32,365 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2024-11-13 23:49:32,366 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2024-11-13 23:49:32,366 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2024-11-13 23:49:32,366 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2024-11-13 23:49:32,366 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2024-11-13 23:49:32,366 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2024-11-13 23:49:32,366 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 23:49:32,366 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 23:49:32,594 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 23:49:32,597 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 23:49:33,985 INFO L? ?]: Removed 103 outVars from TransFormulas that were not future-live. [2024-11-13 23:49:33,986 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 23:49:34,930 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 23:49:34,932 INFO L316 CfgBuilder]: Removed 17 assume(true) statements. [2024-11-13 23:49:34,933 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 11:49:34 BoogieIcfgContainer [2024-11-13 23:49:34,933 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 23:49:34,939 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-13 23:49:34,939 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-13 23:49:34,945 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-13 23:49:34,946 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 13.11 11:49:31" (1/3) ... [2024-11-13 23:49:34,947 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1a43c9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 13.11 11:49:34, skipping insertion in model container [2024-11-13 23:49:34,948 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 11:49:32" (2/3) ... [2024-11-13 23:49:34,948 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1a43c9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 13.11 11:49:34, skipping insertion in model container [2024-11-13 23:49:34,949 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 11:49:34" (3/3) ... [2024-11-13 23:49:34,950 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.15.cil.c [2024-11-13 23:49:34,973 INFO L217 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-13 23:49:34,975 INFO L154 ceAbstractionStarter]: Applying trace abstraction to ICFG transmitter.15.cil.c that has 7 procedures, 206 locations, 1 initial locations, 17 loop locations, and 1 error locations. [2024-11-13 23:49:35,074 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-13 23:49:35,097 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@155302af, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-13 23:49:35,098 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-13 23:49:35,104 INFO L276 IsEmpty]: Start isEmpty. Operand has 206 states, 172 states have (on average 1.5116279069767442) internal successors, (260), 174 states have internal predecessors, (260), 26 states have call successors, (26), 6 states have call predecessors, (26), 6 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-11-13 23:49:35,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 23:49:35,121 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 23:49:35,122 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 23:49:35,123 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 23:49:35,129 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 23:49:35,129 INFO L85 PathProgramCache]: Analyzing trace with hash 898767360, now seen corresponding path program 1 times [2024-11-13 23:49:35,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-13 23:49:35,143 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061155511] [2024-11-13 23:49:35,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 23:49:35,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 23:49:35,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 23:49:36,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 23:49:36,090 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-13 23:49:36,091 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2061155511] [2024-11-13 23:49:36,092 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2061155511] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 23:49:36,093 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 23:49:36,093 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 23:49:36,097 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1911709247] [2024-11-13 23:49:36,098 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 23:49:36,103 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-13 23:49:36,104 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-13 23:49:36,133 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 23:49:36,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 23:49:36,139 INFO L87 Difference]: Start difference. First operand has 206 states, 172 states have (on average 1.5116279069767442) internal successors, (260), 174 states have internal predecessors, (260), 26 states have call successors, (26), 6 states have call predecessors, (26), 6 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) Second operand has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:37,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 23:49:37,034 INFO L93 Difference]: Finished difference Result 601 states and 940 transitions. [2024-11-13 23:49:37,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 23:49:37,038 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2024-11-13 23:49:37,038 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 23:49:37,059 INFO L225 Difference]: With dead ends: 601 [2024-11-13 23:49:37,059 INFO L226 Difference]: Without dead ends: 396 [2024-11-13 23:49:37,072 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 23:49:37,080 INFO L432 NwaCegarLoop]: 486 mSDtfsCounter, 542 mSDsluCounter, 392 mSDsCounter, 0 mSdLazyCounter, 302 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 542 SdHoareTripleChecker+Valid, 878 SdHoareTripleChecker+Invalid, 316 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 302 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-13 23:49:37,082 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [542 Valid, 878 Invalid, 316 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 302 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-13 23:49:37,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 396 states. [2024-11-13 23:49:37,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 396 to 393. [2024-11-13 23:49:37,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 393 states, 333 states have (on average 1.4714714714714714) internal successors, (490), 334 states have internal predecessors, (490), 47 states have call successors, (47), 12 states have call predecessors, (47), 12 states have return successors, (47), 47 states have call predecessors, (47), 47 states have call successors, (47) [2024-11-13 23:49:37,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 393 states to 393 states and 584 transitions. [2024-11-13 23:49:37,225 INFO L78 Accepts]: Start accepts. Automaton has 393 states and 584 transitions. Word has length 67 [2024-11-13 23:49:37,226 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 23:49:37,226 INFO L471 AbstractCegarLoop]: Abstraction has 393 states and 584 transitions. [2024-11-13 23:49:37,226 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:37,226 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 584 transitions. [2024-11-13 23:49:37,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 23:49:37,231 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 23:49:37,231 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 23:49:37,231 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2024-11-13 23:49:37,231 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 23:49:37,232 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 23:49:37,232 INFO L85 PathProgramCache]: Analyzing trace with hash 1139034689, now seen corresponding path program 1 times [2024-11-13 23:49:37,232 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-13 23:49:37,232 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738550677] [2024-11-13 23:49:37,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 23:49:37,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 23:49:37,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 23:49:37,721 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 23:49:37,723 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-13 23:49:37,724 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1738550677] [2024-11-13 23:49:37,724 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1738550677] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 23:49:37,724 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 23:49:37,724 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 23:49:37,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [709245126] [2024-11-13 23:49:37,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 23:49:37,727 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-13 23:49:37,727 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-13 23:49:37,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 23:49:37,729 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 23:49:37,729 INFO L87 Difference]: Start difference. First operand 393 states and 584 transitions. Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:39,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 23:49:39,143 INFO L93 Difference]: Finished difference Result 1350 states and 2030 transitions. [2024-11-13 23:49:39,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 23:49:39,144 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2024-11-13 23:49:39,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 23:49:39,152 INFO L225 Difference]: With dead ends: 1350 [2024-11-13 23:49:39,152 INFO L226 Difference]: Without dead ends: 935 [2024-11-13 23:49:39,154 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-13 23:49:39,155 INFO L432 NwaCegarLoop]: 478 mSDtfsCounter, 1161 mSDsluCounter, 857 mSDsCounter, 0 mSdLazyCounter, 479 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1175 SdHoareTripleChecker+Valid, 1335 SdHoareTripleChecker+Invalid, 689 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 479 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.2s IncrementalHoareTripleChecker+Time [2024-11-13 23:49:39,156 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [1175 Valid, 1335 Invalid, 689 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 479 Invalid, 0 Unknown, 0 Unchecked, 1.2s Time] [2024-11-13 23:49:39,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 935 states. [2024-11-13 23:49:39,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 935 to 923. [2024-11-13 23:49:39,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 923 states, 802 states have (on average 1.4600997506234414) internal successors, (1171), 791 states have internal predecessors, (1171), 92 states have call successors, (92), 26 states have call predecessors, (92), 28 states have return successors, (106), 106 states have call predecessors, (106), 92 states have call successors, (106) [2024-11-13 23:49:39,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 923 states to 923 states and 1369 transitions. [2024-11-13 23:49:39,247 INFO L78 Accepts]: Start accepts. Automaton has 923 states and 1369 transitions. Word has length 67 [2024-11-13 23:49:39,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 23:49:39,248 INFO L471 AbstractCegarLoop]: Abstraction has 923 states and 1369 transitions. [2024-11-13 23:49:39,248 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:39,248 INFO L276 IsEmpty]: Start isEmpty. Operand 923 states and 1369 transitions. [2024-11-13 23:49:39,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 23:49:39,250 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 23:49:39,250 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 23:49:39,250 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-11-13 23:49:39,251 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 23:49:39,251 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 23:49:39,251 INFO L85 PathProgramCache]: Analyzing trace with hash -961806526, now seen corresponding path program 1 times [2024-11-13 23:49:39,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-13 23:49:39,252 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083951516] [2024-11-13 23:49:39,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 23:49:39,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 23:49:39,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 23:49:39,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 23:49:39,561 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-13 23:49:39,561 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083951516] [2024-11-13 23:49:39,563 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083951516] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 23:49:39,563 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 23:49:39,563 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 23:49:39,563 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1232140304] [2024-11-13 23:49:39,563 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 23:49:39,564 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-13 23:49:39,564 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-13 23:49:39,564 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 23:49:39,564 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 23:49:39,566 INFO L87 Difference]: Start difference. First operand 923 states and 1369 transitions. Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:40,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 23:49:40,822 INFO L93 Difference]: Finished difference Result 3251 states and 4886 transitions. [2024-11-13 23:49:40,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 23:49:40,823 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2024-11-13 23:49:40,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 23:49:40,850 INFO L225 Difference]: With dead ends: 3251 [2024-11-13 23:49:40,850 INFO L226 Difference]: Without dead ends: 2282 [2024-11-13 23:49:40,859 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-13 23:49:40,860 INFO L432 NwaCegarLoop]: 472 mSDtfsCounter, 1161 mSDsluCounter, 580 mSDsCounter, 0 mSdLazyCounter, 424 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1175 SdHoareTripleChecker+Valid, 1052 SdHoareTripleChecker+Invalid, 634 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 424 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-11-13 23:49:40,861 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [1175 Valid, 1052 Invalid, 634 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 424 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-11-13 23:49:40,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2282 states. [2024-11-13 23:49:41,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2282 to 1762. [2024-11-13 23:49:41,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1762 states, 1533 states have (on average 1.4644487932159165) internal successors, (2245), 1523 states have internal predecessors, (2245), 172 states have call successors, (172), 50 states have call predecessors, (172), 56 states have return successors, (213), 189 states have call predecessors, (213), 172 states have call successors, (213) [2024-11-13 23:49:41,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1762 states to 1762 states and 2630 transitions. [2024-11-13 23:49:41,064 INFO L78 Accepts]: Start accepts. Automaton has 1762 states and 2630 transitions. Word has length 67 [2024-11-13 23:49:41,064 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 23:49:41,064 INFO L471 AbstractCegarLoop]: Abstraction has 1762 states and 2630 transitions. [2024-11-13 23:49:41,064 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:41,065 INFO L276 IsEmpty]: Start isEmpty. Operand 1762 states and 2630 transitions. [2024-11-13 23:49:41,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 23:49:41,067 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 23:49:41,067 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 23:49:41,067 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2024-11-13 23:49:41,068 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 23:49:41,068 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 23:49:41,068 INFO L85 PathProgramCache]: Analyzing trace with hash 471028193, now seen corresponding path program 1 times [2024-11-13 23:49:41,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-13 23:49:41,068 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770031147] [2024-11-13 23:49:41,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 23:49:41,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 23:49:41,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 23:49:41,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 23:49:41,376 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-13 23:49:41,376 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770031147] [2024-11-13 23:49:41,376 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1770031147] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 23:49:41,377 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 23:49:41,377 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 23:49:41,377 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953148301] [2024-11-13 23:49:41,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 23:49:41,377 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-13 23:49:41,378 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-13 23:49:41,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 23:49:41,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 23:49:41,379 INFO L87 Difference]: Start difference. First operand 1762 states and 2630 transitions. Second operand has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:42,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 23:49:42,239 INFO L93 Difference]: Finished difference Result 5247 states and 7969 transitions. [2024-11-13 23:49:42,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 23:49:42,240 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2024-11-13 23:49:42,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 23:49:42,277 INFO L225 Difference]: With dead ends: 5247 [2024-11-13 23:49:42,277 INFO L226 Difference]: Without dead ends: 3490 [2024-11-13 23:49:42,286 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 23:49:42,289 INFO L432 NwaCegarLoop]: 485 mSDtfsCounter, 557 mSDsluCounter, 391 mSDsCounter, 0 mSdLazyCounter, 304 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 557 SdHoareTripleChecker+Valid, 876 SdHoareTripleChecker+Invalid, 309 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 304 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-13 23:49:42,290 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [557 Valid, 876 Invalid, 309 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 304 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-13 23:49:42,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3490 states. [2024-11-13 23:49:42,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3490 to 3478. [2024-11-13 23:49:42,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3478 states, 3033 states have (on average 1.4566435872073855) internal successors, (4418), 3013 states have internal predecessors, (4418), 332 states have call successors, (332), 100 states have call predecessors, (332), 112 states have return successors, (411), 365 states have call predecessors, (411), 332 states have call successors, (411) [2024-11-13 23:49:42,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3478 states to 3478 states and 5161 transitions. [2024-11-13 23:49:42,626 INFO L78 Accepts]: Start accepts. Automaton has 3478 states and 5161 transitions. Word has length 67 [2024-11-13 23:49:42,626 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 23:49:42,627 INFO L471 AbstractCegarLoop]: Abstraction has 3478 states and 5161 transitions. [2024-11-13 23:49:42,627 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:42,627 INFO L276 IsEmpty]: Start isEmpty. Operand 3478 states and 5161 transitions. [2024-11-13 23:49:42,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 23:49:42,629 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 23:49:42,629 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 23:49:42,629 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2024-11-13 23:49:42,630 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 23:49:42,630 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 23:49:42,630 INFO L85 PathProgramCache]: Analyzing trace with hash -1684486208, now seen corresponding path program 1 times [2024-11-13 23:49:42,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-13 23:49:42,630 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624118033] [2024-11-13 23:49:42,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 23:49:42,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 23:49:42,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 23:49:42,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 23:49:42,897 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-13 23:49:42,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624118033] [2024-11-13 23:49:42,897 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [624118033] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 23:49:42,897 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 23:49:42,897 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 23:49:42,897 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2023872157] [2024-11-13 23:49:42,897 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 23:49:42,898 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-13 23:49:42,898 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-13 23:49:42,898 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 23:49:42,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 23:49:42,899 INFO L87 Difference]: Start difference. First operand 3478 states and 5161 transitions. Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:44,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 23:49:44,333 INFO L93 Difference]: Finished difference Result 12010 states and 18122 transitions. [2024-11-13 23:49:44,334 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 23:49:44,334 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2024-11-13 23:49:44,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 23:49:44,399 INFO L225 Difference]: With dead ends: 12010 [2024-11-13 23:49:44,399 INFO L226 Difference]: Without dead ends: 8345 [2024-11-13 23:49:44,419 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-13 23:49:44,420 INFO L432 NwaCegarLoop]: 472 mSDtfsCounter, 1161 mSDsluCounter, 580 mSDsCounter, 0 mSdLazyCounter, 424 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1175 SdHoareTripleChecker+Valid, 1052 SdHoareTripleChecker+Invalid, 634 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 424 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-11-13 23:49:44,420 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [1175 Valid, 1052 Invalid, 634 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 424 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-11-13 23:49:44,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8345 states. [2024-11-13 23:49:45,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8345 to 6731. [2024-11-13 23:49:45,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6731 states, 5870 states have (on average 1.4570698466780239) internal successors, (8553), 5858 states have internal predecessors, (8553), 636 states have call successors, (636), 196 states have call predecessors, (636), 224 states have return successors, (815), 677 states have call predecessors, (815), 636 states have call successors, (815) [2024-11-13 23:49:45,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6731 states to 6731 states and 10004 transitions. [2024-11-13 23:49:45,208 INFO L78 Accepts]: Start accepts. Automaton has 6731 states and 10004 transitions. Word has length 67 [2024-11-13 23:49:45,209 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 23:49:45,209 INFO L471 AbstractCegarLoop]: Abstraction has 6731 states and 10004 transitions. [2024-11-13 23:49:45,209 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:45,209 INFO L276 IsEmpty]: Start isEmpty. Operand 6731 states and 10004 transitions. [2024-11-13 23:49:45,210 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 23:49:45,210 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 23:49:45,211 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 23:49:45,211 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2024-11-13 23:49:45,211 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 23:49:45,212 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 23:49:45,212 INFO L85 PathProgramCache]: Analyzing trace with hash 845664479, now seen corresponding path program 1 times [2024-11-13 23:49:45,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-13 23:49:45,212 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317902519] [2024-11-13 23:49:45,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 23:49:45,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 23:49:45,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 23:49:45,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 23:49:45,382 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-13 23:49:45,382 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317902519] [2024-11-13 23:49:45,382 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317902519] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 23:49:45,382 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 23:49:45,382 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 23:49:45,382 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609326434] [2024-11-13 23:49:45,382 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 23:49:45,383 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-13 23:49:45,383 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-13 23:49:45,383 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 23:49:45,383 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 23:49:45,384 INFO L87 Difference]: Start difference. First operand 6731 states and 10004 transitions. Second operand has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:46,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 23:49:46,582 INFO L93 Difference]: Finished difference Result 20070 states and 30356 transitions. [2024-11-13 23:49:46,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 23:49:46,583 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2024-11-13 23:49:46,584 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 23:49:46,709 INFO L225 Difference]: With dead ends: 20070 [2024-11-13 23:49:46,710 INFO L226 Difference]: Without dead ends: 13344 [2024-11-13 23:49:46,740 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 23:49:46,741 INFO L432 NwaCegarLoop]: 485 mSDtfsCounter, 569 mSDsluCounter, 391 mSDsCounter, 0 mSdLazyCounter, 304 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 569 SdHoareTripleChecker+Valid, 876 SdHoareTripleChecker+Invalid, 309 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 304 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-13 23:49:46,742 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [569 Valid, 876 Invalid, 309 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 304 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-13 23:49:46,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13344 states. [2024-11-13 23:49:47,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13344 to 13306. [2024-11-13 23:49:47,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13306 states, 11621 states have (on average 1.4481542035969366) internal successors, (16829), 11598 states have internal predecessors, (16829), 1236 states have call successors, (1236), 392 states have call predecessors, (1236), 448 states have return successors, (1580), 1316 states have call predecessors, (1580), 1236 states have call successors, (1580) [2024-11-13 23:49:47,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13306 states to 13306 states and 19645 transitions. [2024-11-13 23:49:47,643 INFO L78 Accepts]: Start accepts. Automaton has 13306 states and 19645 transitions. Word has length 67 [2024-11-13 23:49:47,644 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 23:49:47,644 INFO L471 AbstractCegarLoop]: Abstraction has 13306 states and 19645 transitions. [2024-11-13 23:49:47,644 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:47,644 INFO L276 IsEmpty]: Start isEmpty. Operand 13306 states and 19645 transitions. [2024-11-13 23:49:47,645 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 23:49:47,646 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 23:49:47,646 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 23:49:47,646 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2024-11-13 23:49:47,646 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 23:49:47,647 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 23:49:47,647 INFO L85 PathProgramCache]: Analyzing trace with hash 788520254, now seen corresponding path program 1 times [2024-11-13 23:49:47,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-13 23:49:47,647 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1908539635] [2024-11-13 23:49:47,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 23:49:47,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 23:49:47,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 23:49:47,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 23:49:47,844 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-13 23:49:47,844 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1908539635] [2024-11-13 23:49:47,844 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1908539635] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 23:49:47,844 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 23:49:47,845 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 23:49:47,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [299236577] [2024-11-13 23:49:47,845 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 23:49:47,846 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-13 23:49:47,846 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-13 23:49:47,847 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 23:49:47,847 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 23:49:47,852 INFO L87 Difference]: Start difference. First operand 13306 states and 19645 transitions. Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:50,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 23:49:50,520 INFO L93 Difference]: Finished difference Result 44871 states and 67472 transitions. [2024-11-13 23:49:50,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 23:49:50,522 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2024-11-13 23:49:50,522 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 23:49:50,721 INFO L225 Difference]: With dead ends: 44871 [2024-11-13 23:49:50,721 INFO L226 Difference]: Without dead ends: 30842 [2024-11-13 23:49:50,794 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-13 23:49:50,795 INFO L432 NwaCegarLoop]: 472 mSDtfsCounter, 1161 mSDsluCounter, 580 mSDsCounter, 0 mSdLazyCounter, 424 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1175 SdHoareTripleChecker+Valid, 1052 SdHoareTripleChecker+Invalid, 634 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 424 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-11-13 23:49:50,796 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [1175 Valid, 1052 Invalid, 634 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 424 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-11-13 23:49:50,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30842 states. [2024-11-13 23:49:52,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30842 to 25984. [2024-11-13 23:49:52,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25984 states, 22699 states have (on average 1.4463632759152385) internal successors, (32831), 22708 states have internal predecessors, (32831), 2388 states have call successors, (2388), 776 states have call predecessors, (2388), 896 states have return successors, (3100), 2500 states have call predecessors, (3100), 2388 states have call successors, (3100) [2024-11-13 23:49:52,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25984 states to 25984 states and 38319 transitions. [2024-11-13 23:49:52,737 INFO L78 Accepts]: Start accepts. Automaton has 25984 states and 38319 transitions. Word has length 67 [2024-11-13 23:49:52,738 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 23:49:52,738 INFO L471 AbstractCegarLoop]: Abstraction has 25984 states and 38319 transitions. [2024-11-13 23:49:52,738 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:52,739 INFO L276 IsEmpty]: Start isEmpty. Operand 25984 states and 38319 transitions. [2024-11-13 23:49:52,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 23:49:52,742 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 23:49:52,742 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 23:49:52,745 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2024-11-13 23:49:52,745 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 23:49:52,745 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 23:49:52,746 INFO L85 PathProgramCache]: Analyzing trace with hash -801874723, now seen corresponding path program 1 times [2024-11-13 23:49:52,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-13 23:49:52,746 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359826248] [2024-11-13 23:49:52,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 23:49:52,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 23:49:52,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 23:49:52,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 23:49:52,955 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-13 23:49:52,955 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359826248] [2024-11-13 23:49:52,955 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359826248] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 23:49:52,955 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 23:49:52,955 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 23:49:52,956 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [720851604] [2024-11-13 23:49:52,956 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 23:49:52,957 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-13 23:49:52,957 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-13 23:49:52,957 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 23:49:52,958 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 23:49:52,958 INFO L87 Difference]: Start difference. First operand 25984 states and 38319 transitions. Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:49:57,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 23:49:57,236 INFO L93 Difference]: Finished difference Result 86905 states and 130606 transitions. [2024-11-13 23:49:57,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 23:49:57,238 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2024-11-13 23:49:57,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 23:49:57,655 INFO L225 Difference]: With dead ends: 86905 [2024-11-13 23:49:57,656 INFO L226 Difference]: Without dead ends: 59510 [2024-11-13 23:49:57,767 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-13 23:49:57,769 INFO L432 NwaCegarLoop]: 472 mSDtfsCounter, 1161 mSDsluCounter, 580 mSDsCounter, 0 mSdLazyCounter, 424 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1175 SdHoareTripleChecker+Valid, 1052 SdHoareTripleChecker+Invalid, 634 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 424 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-11-13 23:49:57,769 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [1175 Valid, 1052 Invalid, 634 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 424 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-11-13 23:49:57,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59510 states. [2024-11-13 23:50:00,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59510 to 51068. [2024-11-13 23:50:00,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51068 states, 44647 states have (on average 1.4437476202208435) internal successors, (64459), 44720 states have internal predecessors, (64459), 4628 states have call successors, (4628), 1544 states have call predecessors, (4628), 1792 states have return successors, (6044), 4804 states have call predecessors, (6044), 4628 states have call successors, (6044) [2024-11-13 23:50:01,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51068 states to 51068 states and 75131 transitions. [2024-11-13 23:50:01,038 INFO L78 Accepts]: Start accepts. Automaton has 51068 states and 75131 transitions. Word has length 67 [2024-11-13 23:50:01,039 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 23:50:01,039 INFO L471 AbstractCegarLoop]: Abstraction has 51068 states and 75131 transitions. [2024-11-13 23:50:01,039 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:50:01,039 INFO L276 IsEmpty]: Start isEmpty. Operand 51068 states and 75131 transitions. [2024-11-13 23:50:01,040 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2024-11-13 23:50:01,040 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 23:50:01,040 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 23:50:01,041 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2024-11-13 23:50:01,041 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 23:50:01,041 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 23:50:01,042 INFO L85 PathProgramCache]: Analyzing trace with hash -1775363682, now seen corresponding path program 1 times [2024-11-13 23:50:01,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-13 23:50:01,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1321130051] [2024-11-13 23:50:01,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 23:50:01,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 23:50:01,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 23:50:01,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 23:50:01,399 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-13 23:50:01,399 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1321130051] [2024-11-13 23:50:01,399 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1321130051] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 23:50:01,400 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 23:50:01,400 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-13 23:50:01,402 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [720546192] [2024-11-13 23:50:01,402 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 23:50:01,403 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-13 23:50:01,403 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-13 23:50:01,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-13 23:50:01,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-13 23:50:01,403 INFO L87 Difference]: Start difference. First operand 51068 states and 75131 transitions. Second operand has 6 states, 6 states have (on average 9.5) internal successors, (57), 6 states have internal predecessors, (57), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:50:07,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 23:50:07,232 INFO L93 Difference]: Finished difference Result 149288 states and 220865 transitions. [2024-11-13 23:50:07,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-13 23:50:07,233 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 9.5) internal successors, (57), 6 states have internal predecessors, (57), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2024-11-13 23:50:07,233 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 23:50:08,026 INFO L225 Difference]: With dead ends: 149288 [2024-11-13 23:50:08,027 INFO L226 Difference]: Without dead ends: 98226 [2024-11-13 23:50:08,188 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2024-11-13 23:50:08,190 INFO L432 NwaCegarLoop]: 238 mSDtfsCounter, 917 mSDsluCounter, 502 mSDsCounter, 0 mSdLazyCounter, 278 mSolverCounterSat, 146 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 924 SdHoareTripleChecker+Valid, 740 SdHoareTripleChecker+Invalid, 424 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 146 IncrementalHoareTripleChecker+Valid, 278 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-13 23:50:08,191 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [924 Valid, 740 Invalid, 424 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [146 Valid, 278 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-13 23:50:08,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98226 states. [2024-11-13 23:50:13,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98226 to 86176. [2024-11-13 23:50:14,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86176 states, 76091 states have (on average 1.4357414148848089) internal successors, (109247), 76236 states have internal predecessors, (109247), 7012 states have call successors, (7012), 2576 states have call predecessors, (7012), 3072 states have return successors, (9844), 7364 states have call predecessors, (9844), 7012 states have call successors, (9844) [2024-11-13 23:50:14,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86176 states to 86176 states and 126103 transitions. [2024-11-13 23:50:14,642 INFO L78 Accepts]: Start accepts. Automaton has 86176 states and 126103 transitions. Word has length 67 [2024-11-13 23:50:14,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 23:50:14,643 INFO L471 AbstractCegarLoop]: Abstraction has 86176 states and 126103 transitions. [2024-11-13 23:50:14,643 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 9.5) internal successors, (57), 6 states have internal predecessors, (57), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-13 23:50:14,643 INFO L276 IsEmpty]: Start isEmpty. Operand 86176 states and 126103 transitions. [2024-11-13 23:50:14,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2024-11-13 23:50:14,644 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 23:50:14,644 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 23:50:14,644 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2024-11-13 23:50:14,644 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 23:50:14,649 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 23:50:14,649 INFO L85 PathProgramCache]: Analyzing trace with hash 1832443502, now seen corresponding path program 1 times [2024-11-13 23:50:14,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-13 23:50:14,649 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77821754] [2024-11-13 23:50:14,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 23:50:14,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 23:50:14,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 23:50:14,702 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 23:50:14,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 23:50:14,909 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2024-11-13 23:50:14,910 INFO L325 BasicCegarLoop]: Counterexample is feasible [2024-11-13 23:50:14,912 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-11-13 23:50:14,914 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2024-11-13 23:50:14,919 INFO L407 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 23:50:15,158 INFO L173 ceAbstractionStarter]: Computing trace abstraction results [2024-11-13 23:50:15,165 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 13.11 11:50:15 BoogieIcfgContainer [2024-11-13 23:50:15,165 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-11-13 23:50:15,167 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 23:50:15,167 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 23:50:15,168 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 23:50:15,169 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 11:49:34" (3/4) ... [2024-11-13 23:50:15,170 INFO L136 WitnessPrinter]: Generating witness for reachability counterexample [2024-11-13 23:50:15,408 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E/witness.graphml [2024-11-13 23:50:15,408 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 23:50:15,409 INFO L158 Benchmark]: Toolchain (without parser) took 44015.73ms. Allocated memory was 142.6MB in the beginning and 7.9GB in the end (delta: 7.8GB). Free memory was 118.5MB in the beginning and 7.0GB in the end (delta: -6.9GB). Peak memory consumption was 850.2MB. Max. memory is 16.1GB. [2024-11-13 23:50:15,410 INFO L158 Benchmark]: CDTParser took 0.50ms. Allocated memory is still 142.6MB. Free memory is still 80.7MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 23:50:15,410 INFO L158 Benchmark]: CACSL2BoogieTranslator took 699.87ms. Allocated memory is still 142.6MB. Free memory was 118.2MB in the beginning and 95.9MB in the end (delta: 22.4MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-13 23:50:15,410 INFO L158 Benchmark]: Boogie Procedure Inliner took 73.54ms. Allocated memory is still 142.6MB. Free memory was 95.9MB in the beginning and 92.1MB in the end (delta: 3.8MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 23:50:15,410 INFO L158 Benchmark]: Boogie Preprocessor took 101.69ms. Allocated memory is still 142.6MB. Free memory was 92.1MB in the beginning and 88.5MB in the end (delta: 3.6MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 23:50:15,411 INFO L158 Benchmark]: RCFGBuilder took 2661.18ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 88.5MB in the beginning and 324.3MB in the end (delta: -235.8MB). Peak memory consumption was 51.5MB. Max. memory is 16.1GB. [2024-11-13 23:50:15,411 INFO L158 Benchmark]: TraceAbstraction took 40226.88ms. Allocated memory was 427.8MB in the beginning and 7.9GB in the end (delta: 7.5GB). Free memory was 323.4MB in the beginning and 7.1GB in the end (delta: -6.7GB). Peak memory consumption was 749.2MB. Max. memory is 16.1GB. [2024-11-13 23:50:15,411 INFO L158 Benchmark]: Witness Printer took 241.36ms. Allocated memory is still 7.9GB. Free memory was 7.1GB in the beginning and 7.0GB in the end (delta: 29.4MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-13 23:50:15,415 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.50ms. Allocated memory is still 142.6MB. Free memory is still 80.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 699.87ms. Allocated memory is still 142.6MB. Free memory was 118.2MB in the beginning and 95.9MB in the end (delta: 22.4MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 73.54ms. Allocated memory is still 142.6MB. Free memory was 95.9MB in the beginning and 92.1MB in the end (delta: 3.8MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 101.69ms. Allocated memory is still 142.6MB. Free memory was 92.1MB in the beginning and 88.5MB in the end (delta: 3.6MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 2661.18ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 88.5MB in the beginning and 324.3MB in the end (delta: -235.8MB). Peak memory consumption was 51.5MB. Max. memory is 16.1GB. * TraceAbstraction took 40226.88ms. Allocated memory was 427.8MB in the beginning and 7.9GB in the end (delta: 7.5GB). Free memory was 323.4MB in the beginning and 7.1GB in the end (delta: -6.7GB). Peak memory consumption was 749.2MB. Max. memory is 16.1GB. * Witness Printer took 241.36ms. Allocated memory is still 7.9GB. Free memory was 7.1GB in the beginning and 7.0GB in the end (delta: 29.4MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int t8_pc = 0; [L34] int t9_pc = 0; [L35] int t10_pc = 0; [L36] int t11_pc = 0; [L37] int t12_pc = 0; [L38] int t13_pc = 0; [L39] int m_st ; [L40] int t1_st ; [L41] int t2_st ; [L42] int t3_st ; [L43] int t4_st ; [L44] int t5_st ; [L45] int t6_st ; [L46] int t7_st ; [L47] int t8_st ; [L48] int t9_st ; [L49] int t10_st ; [L50] int t11_st ; [L51] int t12_st ; [L52] int t13_st ; [L53] int m_i ; [L54] int t1_i ; [L55] int t2_i ; [L56] int t3_i ; [L57] int t4_i ; [L58] int t5_i ; [L59] int t6_i ; [L60] int t7_i ; [L61] int t8_i ; [L62] int t9_i ; [L63] int t10_i ; [L64] int t11_i ; [L65] int t12_i ; [L66] int t13_i ; [L67] int M_E = 2; [L68] int T1_E = 2; [L69] int T2_E = 2; [L70] int T3_E = 2; [L71] int T4_E = 2; [L72] int T5_E = 2; [L73] int T6_E = 2; [L74] int T7_E = 2; [L75] int T8_E = 2; [L76] int T9_E = 2; [L77] int T10_E = 2; [L78] int T11_E = 2; [L79] int T12_E = 2; [L80] int T13_E = 2; [L81] int E_1 = 2; [L82] int E_2 = 2; [L83] int E_3 = 2; [L84] int E_4 = 2; [L85] int E_5 = 2; [L86] int E_6 = 2; [L87] int E_7 = 2; [L88] int E_8 = 2; [L89] int E_9 = 2; [L90] int E_10 = 2; [L91] int E_11 = 2; [L92] int E_12 = 2; [L93] int E_13 = 2; [L1937] int __retres1 ; [L1941] CALL init_model() [L1840] m_i = 1 [L1841] t1_i = 1 [L1842] t2_i = 1 [L1843] t3_i = 1 [L1844] t4_i = 1 [L1845] t5_i = 1 [L1846] t6_i = 1 [L1847] t7_i = 1 [L1848] t8_i = 1 [L1849] t9_i = 1 [L1850] t10_i = 1 [L1851] t11_i = 1 [L1852] t12_i = 1 [L1853] t13_i = 1 [L1941] RET init_model() [L1942] CALL start_simulation() [L1878] int kernel_st ; [L1879] int tmp ; [L1880] int tmp___0 ; [L1884] kernel_st = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1885] FCALL update_channels() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1886] CALL init_threads() [L881] COND TRUE m_i == 1 [L882] m_st = 0 [L886] COND TRUE t1_i == 1 [L887] t1_st = 0 [L891] COND TRUE t2_i == 1 [L892] t2_st = 0 [L896] COND TRUE t3_i == 1 [L897] t3_st = 0 [L901] COND TRUE t4_i == 1 [L902] t4_st = 0 [L906] COND TRUE t5_i == 1 [L907] t5_st = 0 [L911] COND TRUE t6_i == 1 [L912] t6_st = 0 [L916] COND TRUE t7_i == 1 [L917] t7_st = 0 [L921] COND TRUE t8_i == 1 [L922] t8_st = 0 [L926] COND TRUE t9_i == 1 [L927] t9_st = 0 [L931] COND TRUE t10_i == 1 [L932] t10_st = 0 [L936] COND TRUE t11_i == 1 [L937] t11_st = 0 [L941] COND TRUE t12_i == 1 [L942] t12_st = 0 [L946] COND TRUE t13_i == 1 [L947] t13_st = 0 [L1886] RET init_threads() [L1887] CALL fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1258] COND FALSE !(M_E == 0) [L1263] COND FALSE !(T1_E == 0) [L1268] COND FALSE !(T2_E == 0) [L1273] COND FALSE !(T3_E == 0) [L1278] COND FALSE !(T4_E == 0) [L1283] COND FALSE !(T5_E == 0) [L1288] COND FALSE !(T6_E == 0) [L1293] COND FALSE !(T7_E == 0) [L1298] COND FALSE !(T8_E == 0) [L1303] COND FALSE !(T9_E == 0) [L1308] COND FALSE !(T10_E == 0) [L1313] COND FALSE !(T11_E == 0) [L1318] COND FALSE !(T12_E == 0) [L1323] COND FALSE !(T13_E == 0) [L1328] COND FALSE !(E_1 == 0) [L1333] COND FALSE !(E_2 == 0) [L1338] COND FALSE !(E_3 == 0) [L1343] COND FALSE !(E_4 == 0) [L1348] COND FALSE !(E_5 == 0) [L1353] COND FALSE !(E_6 == 0) [L1358] COND FALSE !(E_7 == 0) [L1363] COND FALSE !(E_8 == 0) [L1368] COND FALSE !(E_9 == 0) [L1373] COND FALSE !(E_10 == 0) [L1378] COND FALSE !(E_11 == 0) [L1383] COND FALSE !(E_12 == 0) [L1388] COND FALSE !(E_13 == 0) [L1887] RET fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1888] CALL activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1541] int tmp ; [L1542] int tmp___0 ; [L1543] int tmp___1 ; [L1544] int tmp___2 ; [L1545] int tmp___3 ; [L1546] int tmp___4 ; [L1547] int tmp___5 ; [L1548] int tmp___6 ; [L1549] int tmp___7 ; [L1550] int tmp___8 ; [L1551] int tmp___9 ; [L1552] int tmp___10 ; [L1553] int tmp___11 ; [L1554] int tmp___12 ; [L1558] CALL, EXPR is_master_triggered() [L604] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L607] COND FALSE !(m_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L617] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L619] return (__retres1); [L1558] RET, EXPR is_master_triggered() [L1558] tmp = is_master_triggered() [L1560] COND FALSE !(\read(tmp)) [L1566] CALL, EXPR is_transmit1_triggered() [L623] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L626] COND FALSE !(t1_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L636] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L638] return (__retres1); [L1566] RET, EXPR is_transmit1_triggered() [L1566] tmp___0 = is_transmit1_triggered() [L1568] COND FALSE !(\read(tmp___0)) [L1574] CALL, EXPR is_transmit2_triggered() [L642] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L645] COND FALSE !(t2_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L655] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L657] return (__retres1); [L1574] RET, EXPR is_transmit2_triggered() [L1574] tmp___1 = is_transmit2_triggered() [L1576] COND FALSE !(\read(tmp___1)) [L1582] CALL, EXPR is_transmit3_triggered() [L661] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L664] COND FALSE !(t3_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L674] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L676] return (__retres1); [L1582] RET, EXPR is_transmit3_triggered() [L1582] tmp___2 = is_transmit3_triggered() [L1584] COND FALSE !(\read(tmp___2)) [L1590] CALL, EXPR is_transmit4_triggered() [L680] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L683] COND FALSE !(t4_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L693] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L695] return (__retres1); [L1590] RET, EXPR is_transmit4_triggered() [L1590] tmp___3 = is_transmit4_triggered() [L1592] COND FALSE !(\read(tmp___3)) [L1598] CALL, EXPR is_transmit5_triggered() [L699] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L702] COND FALSE !(t5_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L712] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L714] return (__retres1); [L1598] RET, EXPR is_transmit5_triggered() [L1598] tmp___4 = is_transmit5_triggered() [L1600] COND FALSE !(\read(tmp___4)) [L1606] CALL, EXPR is_transmit6_triggered() [L718] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L721] COND FALSE !(t6_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L731] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L733] return (__retres1); [L1606] RET, EXPR is_transmit6_triggered() [L1606] tmp___5 = is_transmit6_triggered() [L1608] COND FALSE !(\read(tmp___5)) [L1614] CALL, EXPR is_transmit7_triggered() [L737] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L740] COND FALSE !(t7_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L750] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L752] return (__retres1); [L1614] RET, EXPR is_transmit7_triggered() [L1614] tmp___6 = is_transmit7_triggered() [L1616] COND FALSE !(\read(tmp___6)) [L1622] CALL, EXPR is_transmit8_triggered() [L756] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L759] COND FALSE !(t8_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L769] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L771] return (__retres1); [L1622] RET, EXPR is_transmit8_triggered() [L1622] tmp___7 = is_transmit8_triggered() [L1624] COND FALSE !(\read(tmp___7)) [L1630] CALL, EXPR is_transmit9_triggered() [L775] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L778] COND FALSE !(t9_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L788] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L790] return (__retres1); [L1630] RET, EXPR is_transmit9_triggered() [L1630] tmp___8 = is_transmit9_triggered() [L1632] COND FALSE !(\read(tmp___8)) [L1638] CALL, EXPR is_transmit10_triggered() [L794] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L797] COND FALSE !(t10_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L807] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L809] return (__retres1); [L1638] RET, EXPR is_transmit10_triggered() [L1638] tmp___9 = is_transmit10_triggered() [L1640] COND FALSE !(\read(tmp___9)) [L1646] CALL, EXPR is_transmit11_triggered() [L813] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L816] COND FALSE !(t11_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L826] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L828] return (__retres1); [L1646] RET, EXPR is_transmit11_triggered() [L1646] tmp___10 = is_transmit11_triggered() [L1648] COND FALSE !(\read(tmp___10)) [L1654] CALL, EXPR is_transmit12_triggered() [L832] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L835] COND FALSE !(t12_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L845] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L847] return (__retres1); [L1654] RET, EXPR is_transmit12_triggered() [L1654] tmp___11 = is_transmit12_triggered() [L1656] COND FALSE !(\read(tmp___11)) [L1662] CALL, EXPR is_transmit13_triggered() [L851] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L854] COND FALSE !(t13_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L864] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L866] return (__retres1); [L1662] RET, EXPR is_transmit13_triggered() [L1662] tmp___12 = is_transmit13_triggered() [L1664] COND FALSE !(\read(tmp___12)) [L1888] RET activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1889] CALL reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1401] COND FALSE !(M_E == 1) [L1406] COND FALSE !(T1_E == 1) [L1411] COND FALSE !(T2_E == 1) [L1416] COND FALSE !(T3_E == 1) [L1421] COND FALSE !(T4_E == 1) [L1426] COND FALSE !(T5_E == 1) [L1431] COND FALSE !(T6_E == 1) [L1436] COND FALSE !(T7_E == 1) [L1441] COND FALSE !(T8_E == 1) [L1446] COND FALSE !(T9_E == 1) [L1451] COND FALSE !(T10_E == 1) [L1456] COND FALSE !(T11_E == 1) [L1461] COND FALSE !(T12_E == 1) [L1466] COND FALSE !(T13_E == 1) [L1471] COND FALSE !(E_1 == 1) [L1476] COND FALSE !(E_2 == 1) [L1481] COND FALSE !(E_3 == 1) [L1486] COND FALSE !(E_4 == 1) [L1491] COND FALSE !(E_5 == 1) [L1496] COND FALSE !(E_6 == 1) [L1501] COND FALSE !(E_7 == 1) [L1506] COND FALSE !(E_8 == 1) [L1511] COND FALSE !(E_9 == 1) [L1516] COND FALSE !(E_10 == 1) [L1521] COND FALSE !(E_11 == 1) [L1526] COND FALSE !(E_12 == 1) [L1531] COND FALSE !(E_13 == 1) [L1889] RET reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1892] COND TRUE 1 [L1895] kernel_st = 1 [L1896] CALL eval() [L1037] int tmp ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1041] COND TRUE 1 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1044] CALL, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L956] int __retres1 ; [L959] COND TRUE m_st == 0 [L960] __retres1 = 1 [L1032] return (__retres1); [L1044] RET, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1044] tmp = exists_runnable_thread() [L1046] COND TRUE \read(tmp) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1051] COND TRUE m_st == 0 [L1052] int tmp_ndt_1; [L1053] tmp_ndt_1 = __VERIFIER_nondet_int() [L1054] COND FALSE !(\read(tmp_ndt_1)) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1065] COND TRUE t1_st == 0 [L1066] int tmp_ndt_2; [L1067] tmp_ndt_2 = __VERIFIER_nondet_int() [L1068] COND FALSE !(\read(tmp_ndt_2)) [L1074] CALL error() [L21] reach_error() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 7 procedures, 206 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 39.9s, OverallIterations: 10, TraceHistogramMax: 1, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 22.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 8467 SdHoareTripleChecker+Valid, 7.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 8390 mSDsluCounter, 8913 SdHoareTripleChecker+Invalid, 6.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 4853 mSDsCounter, 1220 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 3363 IncrementalHoareTripleChecker+Invalid, 4583 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1220 mSolverCounterUnsat, 4060 mSDtfsCounter, 3363 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 72 GetRequests, 32 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=86176occurred in iteration=9, InterpolantAutomatonStates: 45, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 14.0s AutomataMinimizationTime, 9 MinimizatonAttempts, 27549 StatesRemovedByMinimization, 9 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 2.5s InterpolantComputationTime, 672 NumberOfCodeBlocks, 672 NumberOfCodeBlocksAsserted, 10 NumberOfCheckSat, 594 ConstructedInterpolants, 0 QuantifiedInterpolants, 1570 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 9 InterpolantComputations, 9 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2024-11-13 23:50:15,461 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_60b511b7-c238-4ae5-97fb-3e8ec876835b/bin/utaipan-verify-sOmjnqqW8E/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE