./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.16.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-14 04:00:01,538 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-14 04:00:01,638 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E/config/svcomp-Reach-32bit-Taipan_Default.epf [2024-11-14 04:00:01,647 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-14 04:00:01,651 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-14 04:00:01,689 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-14 04:00:01,690 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-14 04:00:01,690 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-14 04:00:01,690 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-14 04:00:01,690 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-14 04:00:01,690 INFO L153 SettingsManager]: * User list type=DISABLED [2024-11-14 04:00:01,691 INFO L151 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2024-11-14 04:00:01,691 INFO L153 SettingsManager]: * Explicit value domain=true [2024-11-14 04:00:01,691 INFO L153 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2024-11-14 04:00:01,691 INFO L153 SettingsManager]: * Octagon Domain=false [2024-11-14 04:00:01,691 INFO L153 SettingsManager]: * Abstract domain=CompoundDomain [2024-11-14 04:00:01,691 INFO L153 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2024-11-14 04:00:01,691 INFO L153 SettingsManager]: * Use the RCFG-of-the-future interface=true [2024-11-14 04:00:01,691 INFO L153 SettingsManager]: * Interval Domain=false [2024-11-14 04:00:01,692 INFO L151 SettingsManager]: Preferences of Sifa differ from their defaults: [2024-11-14 04:00:01,692 INFO L153 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2024-11-14 04:00:01,692 INFO L153 SettingsManager]: * Simplification Technique=POLY_PAC [2024-11-14 04:00:01,692 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-14 04:00:01,693 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-14 04:00:01,693 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-14 04:00:01,693 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-14 04:00:01,693 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-14 04:00:01,693 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-14 04:00:01,693 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-14 04:00:01,693 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-14 04:00:01,693 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-14 04:00:01,693 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-14 04:00:01,694 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-14 04:00:01,694 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-14 04:00:01,694 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-14 04:00:01,694 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-14 04:00:01,694 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-14 04:00:01,694 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-14 04:00:01,694 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-11-14 04:00:01,694 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-14 04:00:01,694 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-14 04:00:01,695 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-14 04:00:01,695 INFO L153 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2024-11-14 04:00:01,695 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-14 04:00:01,695 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-14 04:00:01,695 INFO L153 SettingsManager]: * Trace refinement exception blacklist=NONE [2024-11-14 04:00:01,695 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-14 04:00:01,695 INFO L153 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 [2024-11-14 04:00:02,050 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-14 04:00:02,060 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-14 04:00:02,063 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-14 04:00:02,065 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-14 04:00:02,065 INFO L274 PluginConnector]: CDTParser initialized [2024-11-14 04:00:02,066 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E/../../sv-benchmarks/c/systemc/transmitter.16.cil.c Unable to find full path for "g++" [2024-11-14 04:00:03,942 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-14 04:00:04,206 INFO L384 CDTParser]: Found 1 translation units. [2024-11-14 04:00:04,210 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/sv-benchmarks/c/systemc/transmitter.16.cil.c [2024-11-14 04:00:04,235 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E/data/f5f61a82b/13318bc5f3684469a5a7b4cd3730dd63/FLAG41dc6eaa2 [2024-11-14 04:00:04,257 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E/data/f5f61a82b/13318bc5f3684469a5a7b4cd3730dd63 [2024-11-14 04:00:04,259 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-14 04:00:04,262 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-14 04:00:04,263 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-14 04:00:04,264 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-14 04:00:04,272 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-14 04:00:04,273 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.11 04:00:04" (1/1) ... [2024-11-14 04:00:04,274 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@67a695d8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:00:04, skipping insertion in model container [2024-11-14 04:00:04,276 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.11 04:00:04" (1/1) ... [2024-11-14 04:00:04,330 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-14 04:00:04,516 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2024-11-14 04:00:04,716 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-14 04:00:04,729 INFO L200 MainTranslator]: Completed pre-run [2024-11-14 04:00:04,740 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2024-11-14 04:00:04,817 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-14 04:00:04,860 INFO L204 MainTranslator]: Completed translation [2024-11-14 04:00:04,861 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:00:04 WrapperNode [2024-11-14 04:00:04,862 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-14 04:00:04,863 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-14 04:00:04,864 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-14 04:00:04,864 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-14 04:00:04,873 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:00:04" (1/1) ... [2024-11-14 04:00:04,889 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:00:04" (1/1) ... [2024-11-14 04:00:04,972 INFO L138 Inliner]: procedures = 56, calls = 71, calls flagged for inlining = 40, calls inlined = 40, statements flattened = 956 [2024-11-14 04:00:04,973 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-14 04:00:04,973 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-14 04:00:04,973 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-14 04:00:04,973 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-14 04:00:04,984 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:00:04" (1/1) ... [2024-11-14 04:00:04,984 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:00:04" (1/1) ... [2024-11-14 04:00:04,988 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:00:04" (1/1) ... [2024-11-14 04:00:04,989 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:00:04" (1/1) ... [2024-11-14 04:00:05,003 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:00:04" (1/1) ... [2024-11-14 04:00:05,017 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:00:04" (1/1) ... [2024-11-14 04:00:05,020 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:00:04" (1/1) ... [2024-11-14 04:00:05,023 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:00:04" (1/1) ... [2024-11-14 04:00:05,028 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-14 04:00:05,029 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-14 04:00:05,029 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-14 04:00:05,029 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-14 04:00:05,030 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:00:04" (1/1) ... [2024-11-14 04:00:05,036 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-11-14 04:00:05,056 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E/z3 [2024-11-14 04:00:05,072 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2024-11-14 04:00:05,075 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2024-11-14 04:00:05,101 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-14 04:00:05,101 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2024-11-14 04:00:05,101 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2024-11-14 04:00:05,101 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2024-11-14 04:00:05,101 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2024-11-14 04:00:05,101 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2024-11-14 04:00:05,102 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2024-11-14 04:00:05,102 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2024-11-14 04:00:05,102 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2024-11-14 04:00:05,102 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2024-11-14 04:00:05,102 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2024-11-14 04:00:05,102 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2024-11-14 04:00:05,102 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2024-11-14 04:00:05,102 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2024-11-14 04:00:05,102 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-14 04:00:05,102 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-14 04:00:05,287 INFO L238 CfgBuilder]: Building ICFG [2024-11-14 04:00:05,289 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-14 04:00:06,571 INFO L? ?]: Removed 109 outVars from TransFormulas that were not future-live. [2024-11-14 04:00:06,572 INFO L287 CfgBuilder]: Performing block encoding [2024-11-14 04:00:07,416 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-14 04:00:07,416 INFO L316 CfgBuilder]: Removed 18 assume(true) statements. [2024-11-14 04:00:07,417 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.11 04:00:07 BoogieIcfgContainer [2024-11-14 04:00:07,417 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-14 04:00:07,420 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-14 04:00:07,420 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-14 04:00:07,424 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-14 04:00:07,425 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 14.11 04:00:04" (1/3) ... [2024-11-14 04:00:07,425 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@cbd3311 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.11 04:00:07, skipping insertion in model container [2024-11-14 04:00:07,425 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.11 04:00:04" (2/3) ... [2024-11-14 04:00:07,426 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@cbd3311 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.11 04:00:07, skipping insertion in model container [2024-11-14 04:00:07,426 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.11 04:00:07" (3/3) ... [2024-11-14 04:00:07,427 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.16.cil.c [2024-11-14 04:00:07,448 INFO L217 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-14 04:00:07,451 INFO L154 ceAbstractionStarter]: Applying trace abstraction to ICFG transmitter.16.cil.c that has 7 procedures, 210 locations, 1 initial locations, 18 loop locations, and 1 error locations. [2024-11-14 04:00:07,533 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-14 04:00:07,550 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@3ec260e7, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-14 04:00:07,551 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-14 04:00:07,558 INFO L276 IsEmpty]: Start isEmpty. Operand has 210 states, 176 states have (on average 1.5113636363636365) internal successors, (266), 178 states have internal predecessors, (266), 26 states have call successors, (26), 6 states have call predecessors, (26), 6 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2024-11-14 04:00:07,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-14 04:00:07,573 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 04:00:07,574 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 04:00:07,574 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 04:00:07,580 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 04:00:07,581 INFO L85 PathProgramCache]: Analyzing trace with hash -1764366358, now seen corresponding path program 1 times [2024-11-14 04:00:07,590 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 04:00:07,591 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797196376] [2024-11-14 04:00:07,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 04:00:07,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 04:00:07,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 04:00:08,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-14 04:00:08,380 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-14 04:00:08,381 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797196376] [2024-11-14 04:00:08,382 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1797196376] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-14 04:00:08,382 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-14 04:00:08,382 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-14 04:00:08,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [119344916] [2024-11-14 04:00:08,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-14 04:00:08,394 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-14 04:00:08,395 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-14 04:00:08,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-14 04:00:08,424 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-14 04:00:08,430 INFO L87 Difference]: Start difference. First operand has 210 states, 176 states have (on average 1.5113636363636365) internal successors, (266), 178 states have internal predecessors, (266), 26 states have call successors, (26), 6 states have call predecessors, (26), 6 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:09,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-14 04:00:09,448 INFO L93 Difference]: Finished difference Result 613 states and 958 transitions. [2024-11-14 04:00:09,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-14 04:00:09,452 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2024-11-14 04:00:09,452 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-14 04:00:09,464 INFO L225 Difference]: With dead ends: 613 [2024-11-14 04:00:09,465 INFO L226 Difference]: Without dead ends: 404 [2024-11-14 04:00:09,472 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-14 04:00:09,476 INFO L432 NwaCegarLoop]: 496 mSDtfsCounter, 551 mSDsluCounter, 402 mSDsCounter, 0 mSdLazyCounter, 306 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 551 SdHoareTripleChecker+Valid, 898 SdHoareTripleChecker+Invalid, 320 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 306 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-11-14 04:00:09,476 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [551 Valid, 898 Invalid, 320 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 306 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-11-14 04:00:09,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 404 states. [2024-11-14 04:00:09,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 404 to 401. [2024-11-14 04:00:09,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 401 states, 341 states have (on average 1.4721407624633431) internal successors, (502), 342 states have internal predecessors, (502), 47 states have call successors, (47), 12 states have call predecessors, (47), 12 states have return successors, (47), 47 states have call predecessors, (47), 47 states have call successors, (47) [2024-11-14 04:00:09,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 401 states to 401 states and 596 transitions. [2024-11-14 04:00:09,605 INFO L78 Accepts]: Start accepts. Automaton has 401 states and 596 transitions. Word has length 70 [2024-11-14 04:00:09,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-14 04:00:09,606 INFO L471 AbstractCegarLoop]: Abstraction has 401 states and 596 transitions. [2024-11-14 04:00:09,606 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:09,607 INFO L276 IsEmpty]: Start isEmpty. Operand 401 states and 596 transitions. [2024-11-14 04:00:09,609 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-14 04:00:09,609 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 04:00:09,610 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 04:00:09,610 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2024-11-14 04:00:09,610 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 04:00:09,611 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 04:00:09,611 INFO L85 PathProgramCache]: Analyzing trace with hash 624116745, now seen corresponding path program 1 times [2024-11-14 04:00:09,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 04:00:09,612 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804986479] [2024-11-14 04:00:09,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 04:00:09,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 04:00:09,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 04:00:10,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-14 04:00:10,149 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-14 04:00:10,149 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804986479] [2024-11-14 04:00:10,149 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1804986479] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-14 04:00:10,150 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-14 04:00:10,150 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-14 04:00:10,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [348673377] [2024-11-14 04:00:10,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-14 04:00:10,152 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-14 04:00:10,153 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-14 04:00:10,153 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-14 04:00:10,154 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-14 04:00:10,154 INFO L87 Difference]: Start difference. First operand 401 states and 596 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:11,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-14 04:00:11,800 INFO L93 Difference]: Finished difference Result 1378 states and 2072 transitions. [2024-11-14 04:00:11,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-14 04:00:11,801 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2024-11-14 04:00:11,802 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-14 04:00:11,812 INFO L225 Difference]: With dead ends: 1378 [2024-11-14 04:00:11,812 INFO L226 Difference]: Without dead ends: 955 [2024-11-14 04:00:11,816 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-14 04:00:11,817 INFO L432 NwaCegarLoop]: 488 mSDtfsCounter, 1185 mSDsluCounter, 877 mSDsCounter, 0 mSdLazyCounter, 485 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1199 SdHoareTripleChecker+Valid, 1365 SdHoareTripleChecker+Invalid, 695 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 485 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2024-11-14 04:00:11,817 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [1199 Valid, 1365 Invalid, 695 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 485 Invalid, 0 Unknown, 0 Unchecked, 1.4s Time] [2024-11-14 04:00:11,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 955 states. [2024-11-14 04:00:11,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 955 to 943. [2024-11-14 04:00:11,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 943 states, 822 states have (on average 1.4610705596107056) internal successors, (1201), 811 states have internal predecessors, (1201), 92 states have call successors, (92), 26 states have call predecessors, (92), 28 states have return successors, (106), 106 states have call predecessors, (106), 92 states have call successors, (106) [2024-11-14 04:00:11,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 943 states to 943 states and 1399 transitions. [2024-11-14 04:00:11,967 INFO L78 Accepts]: Start accepts. Automaton has 943 states and 1399 transitions. Word has length 70 [2024-11-14 04:00:11,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-14 04:00:11,969 INFO L471 AbstractCegarLoop]: Abstraction has 943 states and 1399 transitions. [2024-11-14 04:00:11,969 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:11,969 INFO L276 IsEmpty]: Start isEmpty. Operand 943 states and 1399 transitions. [2024-11-14 04:00:11,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-14 04:00:11,971 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 04:00:11,972 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 04:00:11,972 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-11-14 04:00:11,972 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 04:00:11,973 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 04:00:11,973 INFO L85 PathProgramCache]: Analyzing trace with hash 726917992, now seen corresponding path program 1 times [2024-11-14 04:00:11,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 04:00:11,973 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1422568944] [2024-11-14 04:00:11,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 04:00:11,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 04:00:12,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 04:00:12,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-14 04:00:12,326 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-14 04:00:12,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1422568944] [2024-11-14 04:00:12,326 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1422568944] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-14 04:00:12,326 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-14 04:00:12,326 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-14 04:00:12,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1792131748] [2024-11-14 04:00:12,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-14 04:00:12,329 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-14 04:00:12,330 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-14 04:00:12,330 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-14 04:00:12,331 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-14 04:00:12,331 INFO L87 Difference]: Start difference. First operand 943 states and 1399 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:13,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-14 04:00:13,680 INFO L93 Difference]: Finished difference Result 3323 states and 4994 transitions. [2024-11-14 04:00:13,681 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-14 04:00:13,681 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2024-11-14 04:00:13,682 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-14 04:00:13,699 INFO L225 Difference]: With dead ends: 3323 [2024-11-14 04:00:13,700 INFO L226 Difference]: Without dead ends: 2334 [2024-11-14 04:00:13,708 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-14 04:00:13,715 INFO L432 NwaCegarLoop]: 482 mSDtfsCounter, 1185 mSDsluCounter, 595 mSDsCounter, 0 mSdLazyCounter, 429 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1199 SdHoareTripleChecker+Valid, 1077 SdHoareTripleChecker+Invalid, 639 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 429 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-11-14 04:00:13,715 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [1199 Valid, 1077 Invalid, 639 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 429 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-11-14 04:00:13,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2334 states. [2024-11-14 04:00:13,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2334 to 1806. [2024-11-14 04:00:13,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1806 states, 1577 states have (on average 1.4654407102092581) internal successors, (2311), 1567 states have internal predecessors, (2311), 172 states have call successors, (172), 50 states have call predecessors, (172), 56 states have return successors, (213), 189 states have call predecessors, (213), 172 states have call successors, (213) [2024-11-14 04:00:14,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1806 states to 1806 states and 2696 transitions. [2024-11-14 04:00:14,014 INFO L78 Accepts]: Start accepts. Automaton has 1806 states and 2696 transitions. Word has length 70 [2024-11-14 04:00:14,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-14 04:00:14,017 INFO L471 AbstractCegarLoop]: Abstraction has 1806 states and 2696 transitions. [2024-11-14 04:00:14,017 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:14,018 INFO L276 IsEmpty]: Start isEmpty. Operand 1806 states and 2696 transitions. [2024-11-14 04:00:14,020 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-14 04:00:14,024 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 04:00:14,025 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 04:00:14,025 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2024-11-14 04:00:14,025 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 04:00:14,026 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 04:00:14,026 INFO L85 PathProgramCache]: Analyzing trace with hash -1373923223, now seen corresponding path program 1 times [2024-11-14 04:00:14,026 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 04:00:14,026 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511510161] [2024-11-14 04:00:14,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 04:00:14,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 04:00:14,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 04:00:14,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-14 04:00:14,359 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-14 04:00:14,361 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511510161] [2024-11-14 04:00:14,361 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [511510161] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-14 04:00:14,361 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-14 04:00:14,362 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-14 04:00:14,362 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602758319] [2024-11-14 04:00:14,362 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-14 04:00:14,362 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-14 04:00:14,363 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-14 04:00:14,363 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-14 04:00:14,363 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-14 04:00:14,364 INFO L87 Difference]: Start difference. First operand 1806 states and 2696 transitions. Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:15,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-14 04:00:15,239 INFO L93 Difference]: Finished difference Result 5379 states and 8167 transitions. [2024-11-14 04:00:15,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-14 04:00:15,240 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2024-11-14 04:00:15,240 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-14 04:00:15,275 INFO L225 Difference]: With dead ends: 5379 [2024-11-14 04:00:15,275 INFO L226 Difference]: Without dead ends: 3578 [2024-11-14 04:00:15,286 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-14 04:00:15,287 INFO L432 NwaCegarLoop]: 495 mSDtfsCounter, 566 mSDsluCounter, 401 mSDsCounter, 0 mSdLazyCounter, 308 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 566 SdHoareTripleChecker+Valid, 896 SdHoareTripleChecker+Invalid, 313 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 308 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-14 04:00:15,291 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [566 Valid, 896 Invalid, 313 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 308 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-14 04:00:15,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3578 states. [2024-11-14 04:00:15,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3578 to 3566. [2024-11-14 04:00:15,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3566 states, 3121 states have (on average 1.4578660685677667) internal successors, (4550), 3101 states have internal predecessors, (4550), 332 states have call successors, (332), 100 states have call predecessors, (332), 112 states have return successors, (411), 365 states have call predecessors, (411), 332 states have call successors, (411) [2024-11-14 04:00:15,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3566 states to 3566 states and 5293 transitions. [2024-11-14 04:00:15,664 INFO L78 Accepts]: Start accepts. Automaton has 3566 states and 5293 transitions. Word has length 70 [2024-11-14 04:00:15,664 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-14 04:00:15,664 INFO L471 AbstractCegarLoop]: Abstraction has 3566 states and 5293 transitions. [2024-11-14 04:00:15,665 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:15,665 INFO L276 IsEmpty]: Start isEmpty. Operand 3566 states and 5293 transitions. [2024-11-14 04:00:15,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-14 04:00:15,668 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 04:00:15,668 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 04:00:15,669 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2024-11-14 04:00:15,669 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 04:00:15,670 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 04:00:15,670 INFO L85 PathProgramCache]: Analyzing trace with hash 2047566378, now seen corresponding path program 1 times [2024-11-14 04:00:15,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 04:00:15,670 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738542506] [2024-11-14 04:00:15,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 04:00:15,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 04:00:15,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 04:00:15,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-14 04:00:15,963 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-14 04:00:15,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [738542506] [2024-11-14 04:00:15,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [738542506] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-14 04:00:15,963 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-14 04:00:15,963 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-14 04:00:15,964 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [846225422] [2024-11-14 04:00:15,964 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-14 04:00:15,964 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-14 04:00:15,965 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-14 04:00:15,965 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-14 04:00:15,966 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-14 04:00:15,966 INFO L87 Difference]: Start difference. First operand 3566 states and 5293 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:17,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-14 04:00:17,563 INFO L93 Difference]: Finished difference Result 12330 states and 18602 transitions. [2024-11-14 04:00:17,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-14 04:00:17,564 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2024-11-14 04:00:17,565 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-14 04:00:17,626 INFO L225 Difference]: With dead ends: 12330 [2024-11-14 04:00:17,626 INFO L226 Difference]: Without dead ends: 8577 [2024-11-14 04:00:17,649 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-14 04:00:17,652 INFO L432 NwaCegarLoop]: 482 mSDtfsCounter, 1185 mSDsluCounter, 595 mSDsCounter, 0 mSdLazyCounter, 429 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1199 SdHoareTripleChecker+Valid, 1077 SdHoareTripleChecker+Invalid, 639 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 429 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-11-14 04:00:17,653 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [1199 Valid, 1077 Invalid, 639 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 429 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-11-14 04:00:17,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8577 states. [2024-11-14 04:00:18,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8577 to 6915. [2024-11-14 04:00:18,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6915 states, 6054 states have (on average 1.458374628344896) internal successors, (8829), 6042 states have internal predecessors, (8829), 636 states have call successors, (636), 196 states have call predecessors, (636), 224 states have return successors, (815), 677 states have call predecessors, (815), 636 states have call successors, (815) [2024-11-14 04:00:18,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6915 states to 6915 states and 10280 transitions. [2024-11-14 04:00:18,411 INFO L78 Accepts]: Start accepts. Automaton has 6915 states and 10280 transitions. Word has length 70 [2024-11-14 04:00:18,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-14 04:00:18,412 INFO L471 AbstractCegarLoop]: Abstraction has 6915 states and 10280 transitions. [2024-11-14 04:00:18,413 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:18,413 INFO L276 IsEmpty]: Start isEmpty. Operand 6915 states and 10280 transitions. [2024-11-14 04:00:18,418 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-14 04:00:18,419 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 04:00:18,419 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 04:00:18,419 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2024-11-14 04:00:18,419 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 04:00:18,419 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 04:00:18,420 INFO L85 PathProgramCache]: Analyzing trace with hash 1090637995, now seen corresponding path program 1 times [2024-11-14 04:00:18,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 04:00:18,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1962097484] [2024-11-14 04:00:18,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 04:00:18,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 04:00:18,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 04:00:18,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-14 04:00:18,640 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-14 04:00:18,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1962097484] [2024-11-14 04:00:18,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1962097484] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-14 04:00:18,641 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-14 04:00:18,641 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-14 04:00:18,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2008636205] [2024-11-14 04:00:18,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-14 04:00:18,644 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-14 04:00:18,644 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-14 04:00:18,645 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-14 04:00:18,645 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-14 04:00:18,645 INFO L87 Difference]: Start difference. First operand 6915 states and 10280 transitions. Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:20,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-14 04:00:20,013 INFO L93 Difference]: Finished difference Result 20622 states and 31184 transitions. [2024-11-14 04:00:20,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-14 04:00:20,015 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2024-11-14 04:00:20,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-14 04:00:20,169 INFO L225 Difference]: With dead ends: 20622 [2024-11-14 04:00:20,169 INFO L226 Difference]: Without dead ends: 13712 [2024-11-14 04:00:20,204 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-14 04:00:20,205 INFO L432 NwaCegarLoop]: 495 mSDtfsCounter, 578 mSDsluCounter, 401 mSDsCounter, 0 mSdLazyCounter, 308 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 578 SdHoareTripleChecker+Valid, 896 SdHoareTripleChecker+Invalid, 313 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 308 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-14 04:00:20,206 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [578 Valid, 896 Invalid, 313 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 308 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-14 04:00:20,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13712 states. [2024-11-14 04:00:21,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13712 to 13674. [2024-11-14 04:00:21,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13674 states, 11989 states have (on average 1.4497456001334557) internal successors, (17381), 11966 states have internal predecessors, (17381), 1236 states have call successors, (1236), 392 states have call predecessors, (1236), 448 states have return successors, (1580), 1316 states have call predecessors, (1580), 1236 states have call successors, (1580) [2024-11-14 04:00:21,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13674 states to 13674 states and 20197 transitions. [2024-11-14 04:00:21,503 INFO L78 Accepts]: Start accepts. Automaton has 13674 states and 20197 transitions. Word has length 70 [2024-11-14 04:00:21,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-14 04:00:21,505 INFO L471 AbstractCegarLoop]: Abstraction has 13674 states and 20197 transitions. [2024-11-14 04:00:21,510 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:21,510 INFO L276 IsEmpty]: Start isEmpty. Operand 13674 states and 20197 transitions. [2024-11-14 04:00:21,511 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-14 04:00:21,514 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 04:00:21,515 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 04:00:21,515 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2024-11-14 04:00:21,515 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 04:00:21,515 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 04:00:21,516 INFO L85 PathProgramCache]: Analyzing trace with hash -485919764, now seen corresponding path program 1 times [2024-11-14 04:00:21,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 04:00:21,516 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [907996040] [2024-11-14 04:00:21,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 04:00:21,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 04:00:21,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 04:00:21,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-14 04:00:21,747 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-14 04:00:21,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [907996040] [2024-11-14 04:00:21,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [907996040] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-14 04:00:21,748 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-14 04:00:21,748 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-14 04:00:21,748 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1996576673] [2024-11-14 04:00:21,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-14 04:00:21,749 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-14 04:00:21,750 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-14 04:00:21,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-14 04:00:21,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-14 04:00:21,753 INFO L87 Difference]: Start difference. First operand 13674 states and 20197 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:24,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-14 04:00:24,436 INFO L93 Difference]: Finished difference Result 46215 states and 69488 transitions. [2024-11-14 04:00:24,436 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-14 04:00:24,437 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2024-11-14 04:00:24,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-14 04:00:24,775 INFO L225 Difference]: With dead ends: 46215 [2024-11-14 04:00:24,775 INFO L226 Difference]: Without dead ends: 31818 [2024-11-14 04:00:24,871 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-14 04:00:24,873 INFO L432 NwaCegarLoop]: 482 mSDtfsCounter, 1185 mSDsluCounter, 595 mSDsCounter, 0 mSdLazyCounter, 429 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1199 SdHoareTripleChecker+Valid, 1077 SdHoareTripleChecker+Invalid, 639 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 429 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-11-14 04:00:24,874 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [1199 Valid, 1077 Invalid, 639 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 429 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-11-14 04:00:24,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31818 states. [2024-11-14 04:00:27,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31818 to 26736. [2024-11-14 04:00:27,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26736 states, 23451 states have (on average 1.4480832373885975) internal successors, (33959), 23460 states have internal predecessors, (33959), 2388 states have call successors, (2388), 776 states have call predecessors, (2388), 896 states have return successors, (3100), 2500 states have call predecessors, (3100), 2388 states have call successors, (3100) [2024-11-14 04:00:27,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26736 states to 26736 states and 39447 transitions. [2024-11-14 04:00:27,411 INFO L78 Accepts]: Start accepts. Automaton has 26736 states and 39447 transitions. Word has length 70 [2024-11-14 04:00:27,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-14 04:00:27,412 INFO L471 AbstractCegarLoop]: Abstraction has 26736 states and 39447 transitions. [2024-11-14 04:00:27,412 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:27,413 INFO L276 IsEmpty]: Start isEmpty. Operand 26736 states and 39447 transitions. [2024-11-14 04:00:27,413 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-14 04:00:27,414 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 04:00:27,414 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 04:00:27,416 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2024-11-14 04:00:27,417 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 04:00:27,417 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 04:00:27,418 INFO L85 PathProgramCache]: Analyzing trace with hash 2136529901, now seen corresponding path program 1 times [2024-11-14 04:00:27,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 04:00:27,418 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [174651104] [2024-11-14 04:00:27,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 04:00:27,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 04:00:27,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 04:00:27,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-14 04:00:27,608 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-14 04:00:27,608 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [174651104] [2024-11-14 04:00:27,608 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [174651104] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-14 04:00:27,608 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-14 04:00:27,608 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-14 04:00:27,608 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497679465] [2024-11-14 04:00:27,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-14 04:00:27,610 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-14 04:00:27,610 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-14 04:00:27,610 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-14 04:00:27,611 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-14 04:00:27,611 INFO L87 Difference]: Start difference. First operand 26736 states and 39447 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:31,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-14 04:00:31,503 INFO L93 Difference]: Finished difference Result 89657 states and 134734 transitions. [2024-11-14 04:00:31,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-14 04:00:31,504 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2024-11-14 04:00:31,506 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-14 04:00:31,908 INFO L225 Difference]: With dead ends: 89657 [2024-11-14 04:00:31,908 INFO L226 Difference]: Without dead ends: 61510 [2024-11-14 04:00:32,039 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-14 04:00:32,041 INFO L432 NwaCegarLoop]: 482 mSDtfsCounter, 1185 mSDsluCounter, 595 mSDsCounter, 0 mSdLazyCounter, 429 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1199 SdHoareTripleChecker+Valid, 1077 SdHoareTripleChecker+Invalid, 639 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 429 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-11-14 04:00:32,041 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [1199 Valid, 1077 Invalid, 639 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 429 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-11-14 04:00:32,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61510 states. [2024-11-14 04:00:35,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61510 to 52588. [2024-11-14 04:00:35,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52588 states, 46167 states have (on average 1.4455996707604999) internal successors, (66739), 46240 states have internal predecessors, (66739), 4628 states have call successors, (4628), 1544 states have call predecessors, (4628), 1792 states have return successors, (6044), 4804 states have call predecessors, (6044), 4628 states have call successors, (6044) [2024-11-14 04:00:36,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52588 states to 52588 states and 77411 transitions. [2024-11-14 04:00:36,117 INFO L78 Accepts]: Start accepts. Automaton has 52588 states and 77411 transitions. Word has length 70 [2024-11-14 04:00:36,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-14 04:00:36,118 INFO L471 AbstractCegarLoop]: Abstraction has 52588 states and 77411 transitions. [2024-11-14 04:00:36,118 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:36,118 INFO L276 IsEmpty]: Start isEmpty. Operand 52588 states and 77411 transitions. [2024-11-14 04:00:36,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-14 04:00:36,120 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 04:00:36,120 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 04:00:36,120 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2024-11-14 04:00:36,121 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 04:00:36,121 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 04:00:36,122 INFO L85 PathProgramCache]: Analyzing trace with hash 546134924, now seen corresponding path program 1 times [2024-11-14 04:00:36,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 04:00:36,122 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1924225171] [2024-11-14 04:00:36,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 04:00:36,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 04:00:36,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 04:00:36,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-14 04:00:36,378 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-14 04:00:36,378 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1924225171] [2024-11-14 04:00:36,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1924225171] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-14 04:00:36,379 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-14 04:00:36,379 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-14 04:00:36,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965095004] [2024-11-14 04:00:36,380 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-14 04:00:36,381 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-14 04:00:36,381 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-14 04:00:36,382 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-14 04:00:36,382 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-14 04:00:36,382 INFO L87 Difference]: Start difference. First operand 52588 states and 77411 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:42,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-14 04:00:42,860 INFO L93 Difference]: Finished difference Result 150335 states and 224067 transitions. [2024-11-14 04:00:42,861 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-14 04:00:42,861 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2024-11-14 04:00:42,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-14 04:00:43,595 INFO L225 Difference]: With dead ends: 150335 [2024-11-14 04:00:43,596 INFO L226 Difference]: Without dead ends: 95120 [2024-11-14 04:00:43,811 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-14 04:00:43,813 INFO L432 NwaCegarLoop]: 504 mSDtfsCounter, 1143 mSDsluCounter, 1005 mSDsCounter, 0 mSdLazyCounter, 522 mSolverCounterSat, 125 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1165 SdHoareTripleChecker+Valid, 1509 SdHoareTripleChecker+Invalid, 647 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 125 IncrementalHoareTripleChecker+Valid, 522 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2024-11-14 04:00:43,815 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [1165 Valid, 1509 Invalid, 647 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [125 Valid, 522 Invalid, 0 Unknown, 0 Unchecked, 1.3s Time] [2024-11-14 04:00:43,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95120 states. [2024-11-14 04:00:48,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95120 to 59556. [2024-11-14 04:00:48,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59556 states, 52672 states have (on average 1.441942588092345) internal successors, (75950), 52863 states have internal predecessors, (75950), 4827 states have call successors, (4827), 1680 states have call predecessors, (4827), 2056 states have return successors, (6429), 5013 states have call predecessors, (6429), 4827 states have call successors, (6429) [2024-11-14 04:00:48,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59556 states to 59556 states and 87206 transitions. [2024-11-14 04:00:48,730 INFO L78 Accepts]: Start accepts. Automaton has 59556 states and 87206 transitions. Word has length 70 [2024-11-14 04:00:48,730 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-14 04:00:48,730 INFO L471 AbstractCegarLoop]: Abstraction has 59556 states and 87206 transitions. [2024-11-14 04:00:48,731 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:48,731 INFO L276 IsEmpty]: Start isEmpty. Operand 59556 states and 87206 transitions. [2024-11-14 04:00:48,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2024-11-14 04:00:48,732 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 04:00:48,732 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 04:00:48,733 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2024-11-14 04:00:48,733 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 04:00:48,737 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 04:00:48,737 INFO L85 PathProgramCache]: Analyzing trace with hash 1686486635, now seen corresponding path program 1 times [2024-11-14 04:00:48,737 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 04:00:48,737 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156502169] [2024-11-14 04:00:48,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 04:00:48,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 04:00:48,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-14 04:00:49,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-14 04:00:49,177 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2024-11-14 04:00:49,177 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156502169] [2024-11-14 04:00:49,177 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1156502169] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-14 04:00:49,177 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-14 04:00:49,178 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-14 04:00:49,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1171568303] [2024-11-14 04:00:49,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-14 04:00:49,179 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-14 04:00:49,179 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2024-11-14 04:00:49,180 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-14 04:00:49,181 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-14 04:00:49,181 INFO L87 Difference]: Start difference. First operand 59556 states and 87206 transitions. Second operand has 6 states, 6 states have (on average 10.0) internal successors, (60), 6 states have internal predecessors, (60), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:00:54,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-14 04:00:54,777 INFO L93 Difference]: Finished difference Result 168343 states and 248135 transitions. [2024-11-14 04:00:54,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-14 04:00:54,777 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 10.0) internal successors, (60), 6 states have internal predecessors, (60), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2024-11-14 04:00:54,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-14 04:00:55,660 INFO L225 Difference]: With dead ends: 168343 [2024-11-14 04:00:55,661 INFO L226 Difference]: Without dead ends: 112960 [2024-11-14 04:00:55,861 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2024-11-14 04:00:55,862 INFO L432 NwaCegarLoop]: 246 mSDtfsCounter, 941 mSDsluCounter, 520 mSDsCounter, 0 mSdLazyCounter, 282 mSolverCounterSat, 146 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 948 SdHoareTripleChecker+Valid, 766 SdHoareTripleChecker+Invalid, 428 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 146 IncrementalHoareTripleChecker+Valid, 282 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-11-14 04:00:55,866 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [948 Valid, 766 Invalid, 428 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [146 Valid, 282 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-11-14 04:00:55,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112960 states. [2024-11-14 04:01:01,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112960 to 96552. [2024-11-14 04:01:01,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 96552 states, 85993 states have (on average 1.4364657588408358) internal successors, (123526), 86256 states have internal predecessors, (123526), 7216 states have call successors, (7216), 2718 states have call predecessors, (7216), 3342 states have return successors, (10234), 7578 states have call predecessors, (10234), 7216 states have call successors, (10234) [2024-11-14 04:01:02,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96552 states to 96552 states and 140976 transitions. [2024-11-14 04:01:02,068 INFO L78 Accepts]: Start accepts. Automaton has 96552 states and 140976 transitions. Word has length 70 [2024-11-14 04:01:02,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-14 04:01:02,070 INFO L471 AbstractCegarLoop]: Abstraction has 96552 states and 140976 transitions. [2024-11-14 04:01:02,070 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 10.0) internal successors, (60), 6 states have internal predecessors, (60), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-14 04:01:02,070 INFO L276 IsEmpty]: Start isEmpty. Operand 96552 states and 140976 transitions. [2024-11-14 04:01:02,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2024-11-14 04:01:02,071 INFO L207 NwaCegarLoop]: Found error trace [2024-11-14 04:01:02,071 INFO L215 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 04:01:02,071 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2024-11-14 04:01:02,072 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-14 04:01:02,072 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-14 04:01:02,072 INFO L85 PathProgramCache]: Analyzing trace with hash 70945595, now seen corresponding path program 1 times [2024-11-14 04:01:02,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2024-11-14 04:01:02,073 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671757571] [2024-11-14 04:01:02,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-14 04:01:02,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-14 04:01:02,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-14 04:01:02,123 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-14 04:01:02,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-14 04:01:02,343 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2024-11-14 04:01:02,343 INFO L325 BasicCegarLoop]: Counterexample is feasible [2024-11-14 04:01:02,344 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-11-14 04:01:02,346 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2024-11-14 04:01:02,351 INFO L407 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-14 04:01:02,612 INFO L173 ceAbstractionStarter]: Computing trace abstraction results [2024-11-14 04:01:02,619 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 14.11 04:01:02 BoogieIcfgContainer [2024-11-14 04:01:02,622 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-11-14 04:01:02,623 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-14 04:01:02,623 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-14 04:01:02,623 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-14 04:01:02,624 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.11 04:00:07" (3/4) ... [2024-11-14 04:01:02,625 INFO L136 WitnessPrinter]: Generating witness for reachability counterexample [2024-11-14 04:01:03,150 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E/witness.graphml [2024-11-14 04:01:03,150 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-14 04:01:03,151 INFO L158 Benchmark]: Toolchain (without parser) took 58889.75ms. Allocated memory was 117.4MB in the beginning and 11.3GB in the end (delta: 11.2GB). Free memory was 91.1MB in the beginning and 10.2GB in the end (delta: -10.1GB). Peak memory consumption was 1.6GB. Max. memory is 16.1GB. [2024-11-14 04:01:03,152 INFO L158 Benchmark]: CDTParser took 0.42ms. Allocated memory is still 83.9MB. Free memory is still 41.1MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-14 04:01:03,152 INFO L158 Benchmark]: CACSL2BoogieTranslator took 598.87ms. Allocated memory is still 117.4MB. Free memory was 90.7MB in the beginning and 67.7MB in the end (delta: 22.9MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-14 04:01:03,153 INFO L158 Benchmark]: Boogie Procedure Inliner took 109.89ms. Allocated memory is still 117.4MB. Free memory was 67.7MB in the beginning and 64.0MB in the end (delta: 3.7MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-14 04:01:03,153 INFO L158 Benchmark]: Boogie Preprocessor took 54.85ms. Allocated memory is still 117.4MB. Free memory was 64.0MB in the beginning and 60.3MB in the end (delta: 3.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-14 04:01:03,154 INFO L158 Benchmark]: RCFGBuilder took 2388.43ms. Allocated memory was 117.4MB in the beginning and 167.8MB in the end (delta: 50.3MB). Free memory was 59.9MB in the beginning and 130.9MB in the end (delta: -71.0MB). Peak memory consumption was 40.0MB. Max. memory is 16.1GB. [2024-11-14 04:01:03,155 INFO L158 Benchmark]: TraceAbstraction took 55202.37ms. Allocated memory was 167.8MB in the beginning and 11.3GB in the end (delta: 11.1GB). Free memory was 130.9MB in the beginning and 9.8GB in the end (delta: -9.7GB). Peak memory consumption was 1.5GB. Max. memory is 16.1GB. [2024-11-14 04:01:03,155 INFO L158 Benchmark]: Witness Printer took 527.53ms. Allocated memory is still 11.3GB. Free memory was 9.8GB in the beginning and 10.2GB in the end (delta: -378.0MB). Peak memory consumption was 108.6MB. Max. memory is 16.1GB. [2024-11-14 04:01:03,159 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.42ms. Allocated memory is still 83.9MB. Free memory is still 41.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 598.87ms. Allocated memory is still 117.4MB. Free memory was 90.7MB in the beginning and 67.7MB in the end (delta: 22.9MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 109.89ms. Allocated memory is still 117.4MB. Free memory was 67.7MB in the beginning and 64.0MB in the end (delta: 3.7MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 54.85ms. Allocated memory is still 117.4MB. Free memory was 64.0MB in the beginning and 60.3MB in the end (delta: 3.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 2388.43ms. Allocated memory was 117.4MB in the beginning and 167.8MB in the end (delta: 50.3MB). Free memory was 59.9MB in the beginning and 130.9MB in the end (delta: -71.0MB). Peak memory consumption was 40.0MB. Max. memory is 16.1GB. * TraceAbstraction took 55202.37ms. Allocated memory was 167.8MB in the beginning and 11.3GB in the end (delta: 11.1GB). Free memory was 130.9MB in the beginning and 9.8GB in the end (delta: -9.7GB). Peak memory consumption was 1.5GB. Max. memory is 16.1GB. * Witness Printer took 527.53ms. Allocated memory is still 11.3GB. Free memory was 9.8GB in the beginning and 10.2GB in the end (delta: -378.0MB). Peak memory consumption was 108.6MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int t8_pc = 0; [L34] int t9_pc = 0; [L35] int t10_pc = 0; [L36] int t11_pc = 0; [L37] int t12_pc = 0; [L38] int t13_pc = 0; [L39] int t14_pc = 0; [L40] int m_st ; [L41] int t1_st ; [L42] int t2_st ; [L43] int t3_st ; [L44] int t4_st ; [L45] int t5_st ; [L46] int t6_st ; [L47] int t7_st ; [L48] int t8_st ; [L49] int t9_st ; [L50] int t10_st ; [L51] int t11_st ; [L52] int t12_st ; [L53] int t13_st ; [L54] int t14_st ; [L55] int m_i ; [L56] int t1_i ; [L57] int t2_i ; [L58] int t3_i ; [L59] int t4_i ; [L60] int t5_i ; [L61] int t6_i ; [L62] int t7_i ; [L63] int t8_i ; [L64] int t9_i ; [L65] int t10_i ; [L66] int t11_i ; [L67] int t12_i ; [L68] int t13_i ; [L69] int t14_i ; [L70] int M_E = 2; [L71] int T1_E = 2; [L72] int T2_E = 2; [L73] int T3_E = 2; [L74] int T4_E = 2; [L75] int T5_E = 2; [L76] int T6_E = 2; [L77] int T7_E = 2; [L78] int T8_E = 2; [L79] int T9_E = 2; [L80] int T10_E = 2; [L81] int T11_E = 2; [L82] int T12_E = 2; [L83] int T13_E = 2; [L84] int T14_E = 2; [L85] int E_1 = 2; [L86] int E_2 = 2; [L87] int E_3 = 2; [L88] int E_4 = 2; [L89] int E_5 = 2; [L90] int E_6 = 2; [L91] int E_7 = 2; [L92] int E_8 = 2; [L93] int E_9 = 2; [L94] int E_10 = 2; [L95] int E_11 = 2; [L96] int E_12 = 2; [L97] int E_13 = 2; [L98] int E_14 = 2; [L2062] int __retres1 ; [L2066] CALL init_model() [L1964] m_i = 1 [L1965] t1_i = 1 [L1966] t2_i = 1 [L1967] t3_i = 1 [L1968] t4_i = 1 [L1969] t5_i = 1 [L1970] t6_i = 1 [L1971] t7_i = 1 [L1972] t8_i = 1 [L1973] t9_i = 1 [L1974] t10_i = 1 [L1975] t11_i = 1 [L1976] t12_i = 1 [L1977] t13_i = 1 [L1978] t14_i = 1 [L2066] RET init_model() [L2067] CALL start_simulation() [L2003] int kernel_st ; [L2004] int tmp ; [L2005] int tmp___0 ; [L2009] kernel_st = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2010] FCALL update_channels() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2011] CALL init_threads() [L939] COND TRUE m_i == 1 [L940] m_st = 0 [L944] COND TRUE t1_i == 1 [L945] t1_st = 0 [L949] COND TRUE t2_i == 1 [L950] t2_st = 0 [L954] COND TRUE t3_i == 1 [L955] t3_st = 0 [L959] COND TRUE t4_i == 1 [L960] t4_st = 0 [L964] COND TRUE t5_i == 1 [L965] t5_st = 0 [L969] COND TRUE t6_i == 1 [L970] t6_st = 0 [L974] COND TRUE t7_i == 1 [L975] t7_st = 0 [L979] COND TRUE t8_i == 1 [L980] t8_st = 0 [L984] COND TRUE t9_i == 1 [L985] t9_st = 0 [L989] COND TRUE t10_i == 1 [L990] t10_st = 0 [L994] COND TRUE t11_i == 1 [L995] t11_st = 0 [L999] COND TRUE t12_i == 1 [L1000] t12_st = 0 [L1004] COND TRUE t13_i == 1 [L1005] t13_st = 0 [L1009] COND TRUE t14_i == 1 [L1010] t14_st = 0 [L2011] RET init_threads() [L2012] CALL fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_14)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T14_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1342] COND FALSE !(M_E == 0) [L1347] COND FALSE !(T1_E == 0) [L1352] COND FALSE !(T2_E == 0) [L1357] COND FALSE !(T3_E == 0) [L1362] COND FALSE !(T4_E == 0) [L1367] COND FALSE !(T5_E == 0) [L1372] COND FALSE !(T6_E == 0) [L1377] COND FALSE !(T7_E == 0) [L1382] COND FALSE !(T8_E == 0) [L1387] COND FALSE !(T9_E == 0) [L1392] COND FALSE !(T10_E == 0) [L1397] COND FALSE !(T11_E == 0) [L1402] COND FALSE !(T12_E == 0) [L1407] COND FALSE !(T13_E == 0) [L1412] COND FALSE !(T14_E == 0) [L1417] COND FALSE !(E_1 == 0) [L1422] COND FALSE !(E_2 == 0) [L1427] COND FALSE !(E_3 == 0) [L1432] COND FALSE !(E_4 == 0) [L1437] COND FALSE !(E_5 == 0) [L1442] COND FALSE !(E_6 == 0) [L1447] COND FALSE !(E_7 == 0) [L1452] COND FALSE !(E_8 == 0) [L1457] COND FALSE !(E_9 == 0) [L1462] COND FALSE !(E_10 == 0) [L1467] COND FALSE !(E_11 == 0) [L1472] COND FALSE !(E_12 == 0) [L1477] COND FALSE !(E_13 == 0) [L1482] COND FALSE !(E_14 == 0) [L2012] RET fire_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2013] CALL activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1645] int tmp ; [L1646] int tmp___0 ; [L1647] int tmp___1 ; [L1648] int tmp___2 ; [L1649] int tmp___3 ; [L1650] int tmp___4 ; [L1651] int tmp___5 ; [L1652] int tmp___6 ; [L1653] int tmp___7 ; [L1654] int tmp___8 ; [L1655] int tmp___9 ; [L1656] int tmp___10 ; [L1657] int tmp___11 ; [L1658] int tmp___12 ; [L1659] int tmp___13 ; [L1664] CALL, EXPR is_master_triggered() [L643] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L646] COND FALSE !(m_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L656] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L658] return (__retres1); [L1664] RET, EXPR is_master_triggered() [L1664] tmp = is_master_triggered() [L1666] COND FALSE !(\read(tmp)) [L1672] CALL, EXPR is_transmit1_triggered() [L662] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L665] COND FALSE !(t1_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L675] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L677] return (__retres1); [L1672] RET, EXPR is_transmit1_triggered() [L1672] tmp___0 = is_transmit1_triggered() [L1674] COND FALSE !(\read(tmp___0)) [L1680] CALL, EXPR is_transmit2_triggered() [L681] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L684] COND FALSE !(t2_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L694] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L696] return (__retres1); [L1680] RET, EXPR is_transmit2_triggered() [L1680] tmp___1 = is_transmit2_triggered() [L1682] COND FALSE !(\read(tmp___1)) [L1688] CALL, EXPR is_transmit3_triggered() [L700] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L703] COND FALSE !(t3_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L713] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L715] return (__retres1); [L1688] RET, EXPR is_transmit3_triggered() [L1688] tmp___2 = is_transmit3_triggered() [L1690] COND FALSE !(\read(tmp___2)) [L1696] CALL, EXPR is_transmit4_triggered() [L719] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L722] COND FALSE !(t4_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L732] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L734] return (__retres1); [L1696] RET, EXPR is_transmit4_triggered() [L1696] tmp___3 = is_transmit4_triggered() [L1698] COND FALSE !(\read(tmp___3)) [L1704] CALL, EXPR is_transmit5_triggered() [L738] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L741] COND FALSE !(t5_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L751] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L753] return (__retres1); [L1704] RET, EXPR is_transmit5_triggered() [L1704] tmp___4 = is_transmit5_triggered() [L1706] COND FALSE !(\read(tmp___4)) [L1712] CALL, EXPR is_transmit6_triggered() [L757] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L760] COND FALSE !(t6_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L770] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L772] return (__retres1); [L1712] RET, EXPR is_transmit6_triggered() [L1712] tmp___5 = is_transmit6_triggered() [L1714] COND FALSE !(\read(tmp___5)) [L1720] CALL, EXPR is_transmit7_triggered() [L776] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L779] COND FALSE !(t7_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L789] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L791] return (__retres1); [L1720] RET, EXPR is_transmit7_triggered() [L1720] tmp___6 = is_transmit7_triggered() [L1722] COND FALSE !(\read(tmp___6)) [L1728] CALL, EXPR is_transmit8_triggered() [L795] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L798] COND FALSE !(t8_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L808] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L810] return (__retres1); [L1728] RET, EXPR is_transmit8_triggered() [L1728] tmp___7 = is_transmit8_triggered() [L1730] COND FALSE !(\read(tmp___7)) [L1736] CALL, EXPR is_transmit9_triggered() [L814] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L817] COND FALSE !(t9_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L827] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L829] return (__retres1); [L1736] RET, EXPR is_transmit9_triggered() [L1736] tmp___8 = is_transmit9_triggered() [L1738] COND FALSE !(\read(tmp___8)) [L1744] CALL, EXPR is_transmit10_triggered() [L833] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L836] COND FALSE !(t10_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L846] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L848] return (__retres1); [L1744] RET, EXPR is_transmit10_triggered() [L1744] tmp___9 = is_transmit10_triggered() [L1746] COND FALSE !(\read(tmp___9)) [L1752] CALL, EXPR is_transmit11_triggered() [L852] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L855] COND FALSE !(t11_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L865] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L867] return (__retres1); [L1752] RET, EXPR is_transmit11_triggered() [L1752] tmp___10 = is_transmit11_triggered() [L1754] COND FALSE !(\read(tmp___10)) [L1760] CALL, EXPR is_transmit12_triggered() [L871] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L874] COND FALSE !(t12_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L884] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L886] return (__retres1); [L1760] RET, EXPR is_transmit12_triggered() [L1760] tmp___11 = is_transmit12_triggered() [L1762] COND FALSE !(\read(tmp___11)) [L1768] CALL, EXPR is_transmit13_triggered() [L890] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L893] COND FALSE !(t13_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L903] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L905] return (__retres1); [L1768] RET, EXPR is_transmit13_triggered() [L1768] tmp___12 = is_transmit13_triggered() [L1770] COND FALSE !(\read(tmp___12)) [L1776] CALL, EXPR is_transmit14_triggered() [L909] int __retres1 ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L912] COND FALSE !(t14_pc == 1) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L922] __retres1 = 0 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L924] return (__retres1); [L1776] RET, EXPR is_transmit14_triggered() [L1776] tmp___13 = is_transmit14_triggered() [L1778] COND FALSE !(\read(tmp___13)) [L2013] RET activate_threads() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2014] CALL reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, \old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_14)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T14_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1495] COND FALSE !(M_E == 1) [L1500] COND FALSE !(T1_E == 1) [L1505] COND FALSE !(T2_E == 1) [L1510] COND FALSE !(T3_E == 1) [L1515] COND FALSE !(T4_E == 1) [L1520] COND FALSE !(T5_E == 1) [L1525] COND FALSE !(T6_E == 1) [L1530] COND FALSE !(T7_E == 1) [L1535] COND FALSE !(T8_E == 1) [L1540] COND FALSE !(T9_E == 1) [L1545] COND FALSE !(T10_E == 1) [L1550] COND FALSE !(T11_E == 1) [L1555] COND FALSE !(T12_E == 1) [L1560] COND FALSE !(T13_E == 1) [L1565] COND FALSE !(T14_E == 1) [L1570] COND FALSE !(E_1 == 1) [L1575] COND FALSE !(E_2 == 1) [L1580] COND FALSE !(E_3 == 1) [L1585] COND FALSE !(E_4 == 1) [L1590] COND FALSE !(E_5 == 1) [L1595] COND FALSE !(E_6 == 1) [L1600] COND FALSE !(E_7 == 1) [L1605] COND FALSE !(E_8 == 1) [L1610] COND FALSE !(E_9 == 1) [L1615] COND FALSE !(E_10 == 1) [L1620] COND FALSE !(E_11 == 1) [L1625] COND FALSE !(E_12 == 1) [L1630] COND FALSE !(E_13 == 1) [L1635] COND FALSE !(E_14 == 1) [L2014] RET reset_delta_events() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L2017] COND TRUE 1 [L2020] kernel_st = 1 [L2021] CALL eval() [L1106] int tmp ; VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1110] COND TRUE 1 VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1113] CALL, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1019] int __retres1 ; [L1022] COND TRUE m_st == 0 [L1023] __retres1 = 1 [L1101] return (__retres1); [L1113] RET, EXPR exists_runnable_thread() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1113] tmp = exists_runnable_thread() [L1115] COND TRUE \read(tmp) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1120] COND TRUE m_st == 0 [L1121] int tmp_ndt_1; [L1122] tmp_ndt_1 = __VERIFIER_nondet_int() [L1123] COND FALSE !(\read(tmp_ndt_1)) VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] [L1134] COND TRUE t1_st == 0 [L1135] int tmp_ndt_2; [L1136] tmp_ndt_2 = __VERIFIER_nondet_int() [L1137] COND FALSE !(\read(tmp_ndt_2)) [L1143] CALL error() [L21] reach_error() VAL [E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, T10_E=2, T11_E=2, T12_E=2, T13_E=2, T14_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, T8_E=2, T9_E=2, m_i=1, m_pc=0, m_st=0, t10_i=1, t10_pc=0, t10_st=0, t11_i=1, t11_pc=0, t11_st=0, t12_i=1, t12_pc=0, t12_st=0, t13_i=1, t13_pc=0, t13_st=0, t14_i=1, t14_pc=0, t14_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, t8_i=1, t8_pc=0, t8_st=0, t9_i=1, t9_pc=0, t9_st=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 7 procedures, 210 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 54.8s, OverallIterations: 11, TraceHistogramMax: 1, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.1s, AutomataDifference: 30.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 9803 SdHoareTripleChecker+Valid, 10.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 9704 mSDsluCounter, 10638 SdHoareTripleChecker+Invalid, 8.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 5986 mSDsCounter, 1345 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 3927 IncrementalHoareTripleChecker+Invalid, 5272 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1345 mSolverCounterUnsat, 4652 mSDtfsCounter, 3927 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 81 GetRequests, 36 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=96552occurred in iteration=10, InterpolantAutomatonStates: 51, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 20.5s AutomataMinimizationTime, 10 MinimizatonAttempts, 68231 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.2s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 2.8s InterpolantComputationTime, 772 NumberOfCodeBlocks, 772 NumberOfCodeBlocksAsserted, 11 NumberOfCheckSat, 690 ConstructedInterpolants, 0 QuantifiedInterpolants, 1878 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 10 InterpolantComputations, 10 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2024-11-14 04:01:03,207 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1f02dcc0-01e5-47ef-9779-39a9f7dda2f9/bin/utaipan-verify-sOmjnqqW8E/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE