/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -tc config/AutomizerReach.xml -s config/svcomp-Reach-64bit-Automizer_Default.epf -i ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c -------------------------------------------------------------------------------- This is Ultimate 0.2.1-bitabs-178dd20 [2021-01-06 19:24:06,215 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-01-06 19:24:06,218 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-01-06 19:24:06,253 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-01-06 19:24:06,254 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-01-06 19:24:06,255 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-01-06 19:24:06,257 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-01-06 19:24:06,259 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-01-06 19:24:06,262 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-01-06 19:24:06,263 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-01-06 19:24:06,264 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-01-06 19:24:06,266 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-01-06 19:24:06,267 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-01-06 19:24:06,268 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-01-06 19:24:06,269 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-01-06 19:24:06,272 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-01-06 19:24:06,273 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-01-06 19:24:06,278 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-01-06 19:24:06,281 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-01-06 19:24:06,288 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-01-06 19:24:06,290 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-01-06 19:24:06,295 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-01-06 19:24:06,297 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-01-06 19:24:06,299 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-01-06 19:24:06,316 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-01-06 19:24:06,318 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-01-06 19:24:06,319 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-01-06 19:24:06,324 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-01-06 19:24:06,327 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-01-06 19:24:06,329 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-01-06 19:24:06,329 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-01-06 19:24:06,330 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-01-06 19:24:06,332 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-01-06 19:24:06,334 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-01-06 19:24:06,335 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-01-06 19:24:06,335 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-01-06 19:24:06,336 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-01-06 19:24:06,336 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-01-06 19:24:06,343 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-01-06 19:24:06,345 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-01-06 19:24:06,346 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-01-06 19:24:06,348 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf [2021-01-06 19:24:06,402 INFO L113 SettingsManager]: Loading preferences was successful [2021-01-06 19:24:06,402 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-01-06 19:24:06,404 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-01-06 19:24:06,405 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-01-06 19:24:06,405 INFO L138 SettingsManager]: * Use SBE=true [2021-01-06 19:24:06,405 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-01-06 19:24:06,406 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-01-06 19:24:06,406 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-01-06 19:24:06,406 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-01-06 19:24:06,406 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-01-06 19:24:06,406 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-01-06 19:24:06,407 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-01-06 19:24:06,407 INFO L138 SettingsManager]: * Use constant arrays=true [2021-01-06 19:24:06,407 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-01-06 19:24:06,407 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-01-06 19:24:06,408 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-01-06 19:24:06,408 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2021-01-06 19:24:06,408 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-01-06 19:24:06,408 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-01-06 19:24:06,409 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-01-06 19:24:06,409 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2021-01-06 19:24:06,409 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-01-06 19:24:06,409 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-01-06 19:24:06,409 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-01-06 19:24:06,410 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-01-06 19:24:06,410 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release [2021-01-06 19:24:06,771 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-01-06 19:24:06,800 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-01-06 19:24:06,803 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-01-06 19:24:06,804 INFO L271 PluginConnector]: Initializing CDTParser... [2021-01-06 19:24:06,805 INFO L275 PluginConnector]: CDTParser initialized [2021-01-06 19:24:06,806 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2021-01-06 19:24:06,893 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/data/34428ea0d/2c99d853afcb49479b5e62aa03b01d5a/FLAG73709ed98 [2021-01-06 19:24:07,604 INFO L306 CDTParser]: Found 1 translation units. [2021-01-06 19:24:07,605 INFO L160 CDTParser]: Scanning /storage/repos/ultimate-bitabs/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2021-01-06 19:24:07,622 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/data/34428ea0d/2c99d853afcb49479b5e62aa03b01d5a/FLAG73709ed98 [2021-01-06 19:24:07,905 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/data/34428ea0d/2c99d853afcb49479b5e62aa03b01d5a [2021-01-06 19:24:07,914 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-01-06 19:24:07,918 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-01-06 19:24:07,922 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-01-06 19:24:07,923 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-01-06 19:24:07,927 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-01-06 19:24:07,928 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.01 07:24:07" (1/1) ... [2021-01-06 19:24:07,931 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2bc177de and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:24:07, skipping insertion in model container [2021-01-06 19:24:07,931 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.01 07:24:07" (1/1) ... [2021-01-06 19:24:07,940 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-01-06 19:24:08,004 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-01-06 19:24:08,186 WARN L226 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate-bitabs/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c[335,348] left hand side expression in assignment: lhs: VariableLHS[~q_write_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_read_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_req_up~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~__retres1~0,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~0,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~0,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~1,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~1,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~1,] left hand side expression in assignment: lhs: VariableLHS[~tmp~0,] left hand side expression in assignment: lhs: VariableLHS[~p_dw_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___0~0,] left hand side expression in assignment: lhs: VariableLHS[~c_dr_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_buf_0~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_last_write~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_free~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_req_up~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_dr_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_dr_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~a_t~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~a~0,] left hand side expression in assignment: lhs: VariableLHS[~c_dr_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_dr_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~a_t~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~a~0,] left hand side expression in assignment: lhs: VariableLHS[~a~0,] left hand side expression in assignment: lhs: VariableLHS[~c_last_read~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_free~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_req_up~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_dr_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_dr_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~__retres1~2,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~2,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~2,] left hand side expression in assignment: lhs: VariableLHS[~q_read_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_write_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_read_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_write_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~fast_clk_edge~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~fast_clk_edge~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~slow_clk_edge~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~fast_clk_edge~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~slow_clk_edge~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp~1,] left hand side expression in assignment: lhs: VariableLHS[~p_dw_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___0~1,] left hand side expression in assignment: lhs: VariableLHS[~c_dr_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___1~0,] left hand side expression in assignment: lhs: VariableLHS[~tmp~2,] left hand side expression in assignment: lhs: VariableLHS[~p_dw_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___0~2,] left hand side expression in assignment: lhs: VariableLHS[~c_dr_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp~3,] left hand side expression in assignment: lhs: VariableLHS[~__retres2~0,] left hand side expression in assignment: lhs: VariableLHS[~__retres2~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~tmp~4,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~tmp___0~3,] left hand side expression in assignment: lhs: VariableLHS[~fast_clk_edge~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~slow_clk_edge~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_free~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_write_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_read_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_num_write~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_num_read~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_dr_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_dr_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~__retres1~3,] [2021-01-06 19:24:08,273 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-01-06 19:24:08,299 INFO L203 MainTranslator]: Completed pre-run [2021-01-06 19:24:08,320 WARN L226 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate-bitabs/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c[335,348] left hand side expression in assignment: lhs: VariableLHS[~q_write_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_read_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_req_up~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~__retres1~0,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~0,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~0,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~1,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~1,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~1,] left hand side expression in assignment: lhs: VariableLHS[~tmp~0,] left hand side expression in assignment: lhs: VariableLHS[~p_dw_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___0~0,] left hand side expression in assignment: lhs: VariableLHS[~c_dr_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_buf_0~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_last_write~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_free~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_req_up~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_dr_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_dr_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~a_t~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~a~0,] left hand side expression in assignment: lhs: VariableLHS[~c_dr_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_dr_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~a_t~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~a~0,] left hand side expression in assignment: lhs: VariableLHS[~a~0,] left hand side expression in assignment: lhs: VariableLHS[~c_last_read~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_free~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_req_up~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_dr_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_dr_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~__retres1~2,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~2,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~2,] left hand side expression in assignment: lhs: VariableLHS[~q_read_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_write_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_read_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_write_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~fast_clk_edge~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~fast_clk_edge~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~slow_clk_edge~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~fast_clk_edge~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~slow_clk_edge~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp~1,] left hand side expression in assignment: lhs: VariableLHS[~p_dw_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___0~1,] left hand side expression in assignment: lhs: VariableLHS[~c_dr_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___1~0,] left hand side expression in assignment: lhs: VariableLHS[~tmp~2,] left hand side expression in assignment: lhs: VariableLHS[~p_dw_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___0~2,] left hand side expression in assignment: lhs: VariableLHS[~c_dr_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp~3,] left hand side expression in assignment: lhs: VariableLHS[~__retres2~0,] left hand side expression in assignment: lhs: VariableLHS[~__retres2~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~tmp~4,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~tmp___0~3,] left hand side expression in assignment: lhs: VariableLHS[~fast_clk_edge~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~slow_clk_edge~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_free~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_write_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~q_read_ev~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_num_write~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~p_dw_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_num_read~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_dr_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_dr_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~__retres1~3,] [2021-01-06 19:24:08,404 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-01-06 19:24:08,432 INFO L208 MainTranslator]: Completed translation [2021-01-06 19:24:08,433 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:24:08 WrapperNode [2021-01-06 19:24:08,433 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-01-06 19:24:08,435 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-01-06 19:24:08,435 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-01-06 19:24:08,435 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-01-06 19:24:08,448 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:24:08" (1/1) ... [2021-01-06 19:24:08,460 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:24:08" (1/1) ... [2021-01-06 19:24:08,506 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-01-06 19:24:08,508 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-01-06 19:24:08,508 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-01-06 19:24:08,508 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-01-06 19:24:08,521 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:24:08" (1/1) ... [2021-01-06 19:24:08,521 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:24:08" (1/1) ... [2021-01-06 19:24:08,525 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:24:08" (1/1) ... [2021-01-06 19:24:08,525 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:24:08" (1/1) ... [2021-01-06 19:24:08,534 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:24:08" (1/1) ... [2021-01-06 19:24:08,560 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:24:08" (1/1) ... [2021-01-06 19:24:08,569 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:24:08" (1/1) ... [2021-01-06 19:24:08,582 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-01-06 19:24:08,583 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-01-06 19:24:08,584 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-01-06 19:24:08,584 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-01-06 19:24:08,585 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:24:08" (1/1) ... No working directory specified, using /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-01-06 19:24:08,750 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-01-06 19:24:08,751 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-01-06 19:24:08,752 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-01-06 19:24:08,752 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-01-06 19:24:09,565 INFO L759 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##104: assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 2;~a_t~0 := do_read_c_~a~0; [2021-01-06 19:24:09,566 INFO L759 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##105: assume !(1 == ~q_free~0); [2021-01-06 19:24:09,577 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-01-06 19:24:09,577 INFO L299 CfgBuilder]: Removed 70 assume(true) statements. [2021-01-06 19:24:09,580 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.01 07:24:09 BoogieIcfgContainer [2021-01-06 19:24:09,580 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-01-06 19:24:09,582 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2021-01-06 19:24:09,583 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2021-01-06 19:24:09,586 INFO L275 PluginConnector]: TraceAbstraction initialized [2021-01-06 19:24:09,586 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.01 07:24:07" (1/3) ... [2021-01-06 19:24:09,588 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4f91e070 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.01 07:24:09, skipping insertion in model container [2021-01-06 19:24:09,588 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:24:08" (2/3) ... [2021-01-06 19:24:09,588 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4f91e070 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.01 07:24:09, skipping insertion in model container [2021-01-06 19:24:09,588 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.01 07:24:09" (3/3) ... [2021-01-06 19:24:09,590 INFO L111 eAbstractionObserver]: Analyzing ICFG pc_sfifo_3.cil.c [2021-01-06 19:24:09,597 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2021-01-06 19:24:09,604 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2021-01-06 19:24:09,629 INFO L253 AbstractCegarLoop]: Starting to check reachability of 2 error locations. [2021-01-06 19:24:09,665 INFO L377 AbstractCegarLoop]: Interprodecural is true [2021-01-06 19:24:09,665 INFO L378 AbstractCegarLoop]: Hoare is true [2021-01-06 19:24:09,665 INFO L379 AbstractCegarLoop]: Compute interpolants for FPandBP [2021-01-06 19:24:09,665 INFO L380 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2021-01-06 19:24:09,665 INFO L381 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-01-06 19:24:09,666 INFO L382 AbstractCegarLoop]: Difference is false [2021-01-06 19:24:09,666 INFO L383 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-01-06 19:24:09,666 INFO L387 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2021-01-06 19:24:09,686 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states. [2021-01-06 19:24:09,694 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2021-01-06 19:24:09,694 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:09,695 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:09,696 INFO L429 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:09,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:09,703 INFO L82 PathProgramCache]: Analyzing trace with hash -660120607, now seen corresponding path program 1 times [2021-01-06 19:24:09,714 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:09,715 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1443063810] [2021-01-06 19:24:09,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:09,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:10,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:24:10,054 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1443063810] [2021-01-06 19:24:10,056 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:10,056 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:24:10,058 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366393528] [2021-01-06 19:24:10,065 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:24:10,066 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:10,089 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:24:10,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:10,094 INFO L87 Difference]: Start difference. First operand 131 states. Second operand 3 states. [2021-01-06 19:24:10,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:10,321 INFO L93 Difference]: Finished difference Result 377 states and 602 transitions. [2021-01-06 19:24:10,321 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:24:10,323 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 39 [2021-01-06 19:24:10,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:10,358 INFO L225 Difference]: With dead ends: 377 [2021-01-06 19:24:10,359 INFO L226 Difference]: Without dead ends: 248 [2021-01-06 19:24:10,367 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:10,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248 states. [2021-01-06 19:24:10,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248 to 244. [2021-01-06 19:24:10,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 244 states. [2021-01-06 19:24:10,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 244 states to 244 states and 372 transitions. [2021-01-06 19:24:10,495 INFO L78 Accepts]: Start accepts. Automaton has 244 states and 372 transitions. Word has length 39 [2021-01-06 19:24:10,495 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:10,496 INFO L481 AbstractCegarLoop]: Abstraction has 244 states and 372 transitions. [2021-01-06 19:24:10,496 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:24:10,496 INFO L276 IsEmpty]: Start isEmpty. Operand 244 states and 372 transitions. [2021-01-06 19:24:10,500 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2021-01-06 19:24:10,500 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:10,501 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:10,501 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2021-01-06 19:24:10,502 INFO L429 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:10,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:10,506 INFO L82 PathProgramCache]: Analyzing trace with hash 1873516389, now seen corresponding path program 1 times [2021-01-06 19:24:10,506 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:10,506 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131414331] [2021-01-06 19:24:10,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:10,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:10,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:24:10,660 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [131414331] [2021-01-06 19:24:10,660 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:10,661 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:24:10,662 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1677195145] [2021-01-06 19:24:10,664 INFO L461 AbstractCegarLoop]: Interpolant automaton has 5 states [2021-01-06 19:24:10,664 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:10,665 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-01-06 19:24:10,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:24:10,666 INFO L87 Difference]: Start difference. First operand 244 states and 372 transitions. Second operand 5 states. [2021-01-06 19:24:11,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:11,013 INFO L93 Difference]: Finished difference Result 1043 states and 1573 transitions. [2021-01-06 19:24:11,016 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-01-06 19:24:11,017 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 39 [2021-01-06 19:24:11,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:11,023 INFO L225 Difference]: With dead ends: 1043 [2021-01-06 19:24:11,023 INFO L226 Difference]: Without dead ends: 803 [2021-01-06 19:24:11,026 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-01-06 19:24:11,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 803 states. [2021-01-06 19:24:11,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 803 to 775. [2021-01-06 19:24:11,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 775 states. [2021-01-06 19:24:11,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 775 states to 775 states and 1155 transitions. [2021-01-06 19:24:11,093 INFO L78 Accepts]: Start accepts. Automaton has 775 states and 1155 transitions. Word has length 39 [2021-01-06 19:24:11,094 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:11,094 INFO L481 AbstractCegarLoop]: Abstraction has 775 states and 1155 transitions. [2021-01-06 19:24:11,094 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2021-01-06 19:24:11,094 INFO L276 IsEmpty]: Start isEmpty. Operand 775 states and 1155 transitions. [2021-01-06 19:24:11,095 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2021-01-06 19:24:11,096 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:11,098 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:11,099 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2021-01-06 19:24:11,099 INFO L429 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:11,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:11,101 INFO L82 PathProgramCache]: Analyzing trace with hash 1793155390, now seen corresponding path program 1 times [2021-01-06 19:24:11,101 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:11,101 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974075953] [2021-01-06 19:24:11,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:11,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:11,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:24:11,203 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [974075953] [2021-01-06 19:24:11,204 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:11,204 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-01-06 19:24:11,204 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858737618] [2021-01-06 19:24:11,205 INFO L461 AbstractCegarLoop]: Interpolant automaton has 5 states [2021-01-06 19:24:11,205 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:11,206 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-01-06 19:24:11,206 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:24:11,206 INFO L87 Difference]: Start difference. First operand 775 states and 1155 transitions. Second operand 5 states. [2021-01-06 19:24:11,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:11,369 INFO L93 Difference]: Finished difference Result 2611 states and 3903 transitions. [2021-01-06 19:24:11,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-01-06 19:24:11,370 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 40 [2021-01-06 19:24:11,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:11,382 INFO L225 Difference]: With dead ends: 2611 [2021-01-06 19:24:11,382 INFO L226 Difference]: Without dead ends: 1851 [2021-01-06 19:24:11,387 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-01-06 19:24:11,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1851 states. [2021-01-06 19:24:11,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1851 to 811. [2021-01-06 19:24:11,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 811 states. [2021-01-06 19:24:11,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 811 states to 811 states and 1184 transitions. [2021-01-06 19:24:11,445 INFO L78 Accepts]: Start accepts. Automaton has 811 states and 1184 transitions. Word has length 40 [2021-01-06 19:24:11,446 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:11,446 INFO L481 AbstractCegarLoop]: Abstraction has 811 states and 1184 transitions. [2021-01-06 19:24:11,446 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2021-01-06 19:24:11,446 INFO L276 IsEmpty]: Start isEmpty. Operand 811 states and 1184 transitions. [2021-01-06 19:24:11,447 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2021-01-06 19:24:11,448 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:11,448 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:11,448 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2021-01-06 19:24:11,448 INFO L429 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:11,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:11,449 INFO L82 PathProgramCache]: Analyzing trace with hash 1855195004, now seen corresponding path program 1 times [2021-01-06 19:24:11,450 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:11,450 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934526220] [2021-01-06 19:24:11,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:11,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:11,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:24:11,510 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934526220] [2021-01-06 19:24:11,510 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:11,510 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:24:11,511 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [283688582] [2021-01-06 19:24:11,511 INFO L461 AbstractCegarLoop]: Interpolant automaton has 5 states [2021-01-06 19:24:11,511 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:11,512 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-01-06 19:24:11,513 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:24:11,513 INFO L87 Difference]: Start difference. First operand 811 states and 1184 transitions. Second operand 5 states. [2021-01-06 19:24:11,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:11,804 INFO L93 Difference]: Finished difference Result 2575 states and 3727 transitions. [2021-01-06 19:24:11,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-01-06 19:24:11,805 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 40 [2021-01-06 19:24:11,805 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:11,815 INFO L225 Difference]: With dead ends: 2575 [2021-01-06 19:24:11,815 INFO L226 Difference]: Without dead ends: 1781 [2021-01-06 19:24:11,818 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-01-06 19:24:11,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1781 states. [2021-01-06 19:24:11,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1781 to 1722. [2021-01-06 19:24:11,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1722 states. [2021-01-06 19:24:11,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1722 states to 1722 states and 2452 transitions. [2021-01-06 19:24:11,919 INFO L78 Accepts]: Start accepts. Automaton has 1722 states and 2452 transitions. Word has length 40 [2021-01-06 19:24:11,919 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:11,919 INFO L481 AbstractCegarLoop]: Abstraction has 1722 states and 2452 transitions. [2021-01-06 19:24:11,919 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2021-01-06 19:24:11,919 INFO L276 IsEmpty]: Start isEmpty. Operand 1722 states and 2452 transitions. [2021-01-06 19:24:11,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2021-01-06 19:24:11,921 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:11,922 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:11,922 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2021-01-06 19:24:11,922 INFO L429 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:11,923 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:11,923 INFO L82 PathProgramCache]: Analyzing trace with hash 1105087616, now seen corresponding path program 1 times [2021-01-06 19:24:11,923 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:11,924 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557982346] [2021-01-06 19:24:11,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:11,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:12,006 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2021-01-06 19:24:12,007 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557982346] [2021-01-06 19:24:12,007 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:12,007 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-01-06 19:24:12,008 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038040380] [2021-01-06 19:24:12,008 INFO L461 AbstractCegarLoop]: Interpolant automaton has 5 states [2021-01-06 19:24:12,008 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:12,011 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-01-06 19:24:12,012 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:24:12,012 INFO L87 Difference]: Start difference. First operand 1722 states and 2452 transitions. Second operand 5 states. [2021-01-06 19:24:12,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:12,341 INFO L93 Difference]: Finished difference Result 5626 states and 8070 transitions. [2021-01-06 19:24:12,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-01-06 19:24:12,342 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 53 [2021-01-06 19:24:12,343 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:12,365 INFO L225 Difference]: With dead ends: 5626 [2021-01-06 19:24:12,365 INFO L226 Difference]: Without dead ends: 3926 [2021-01-06 19:24:12,370 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-01-06 19:24:12,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3926 states. [2021-01-06 19:24:12,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3926 to 1830. [2021-01-06 19:24:12,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1830 states. [2021-01-06 19:24:12,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1830 states to 1830 states and 2553 transitions. [2021-01-06 19:24:12,516 INFO L78 Accepts]: Start accepts. Automaton has 1830 states and 2553 transitions. Word has length 53 [2021-01-06 19:24:12,518 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:12,519 INFO L481 AbstractCegarLoop]: Abstraction has 1830 states and 2553 transitions. [2021-01-06 19:24:12,519 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2021-01-06 19:24:12,519 INFO L276 IsEmpty]: Start isEmpty. Operand 1830 states and 2553 transitions. [2021-01-06 19:24:12,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2021-01-06 19:24:12,524 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:12,524 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:12,524 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2021-01-06 19:24:12,525 INFO L429 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:12,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:12,525 INFO L82 PathProgramCache]: Analyzing trace with hash 1379847230, now seen corresponding path program 1 times [2021-01-06 19:24:12,525 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:12,526 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1384926249] [2021-01-06 19:24:12,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:12,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:12,633 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2021-01-06 19:24:12,634 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1384926249] [2021-01-06 19:24:12,634 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:12,634 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:24:12,634 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1671561092] [2021-01-06 19:24:12,635 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:24:12,635 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:12,636 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:24:12,636 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:24:12,636 INFO L87 Difference]: Start difference. First operand 1830 states and 2553 transitions. Second operand 4 states. [2021-01-06 19:24:12,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:12,970 INFO L93 Difference]: Finished difference Result 5113 states and 7076 transitions. [2021-01-06 19:24:12,971 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-01-06 19:24:12,971 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 53 [2021-01-06 19:24:12,971 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:12,989 INFO L225 Difference]: With dead ends: 5113 [2021-01-06 19:24:12,989 INFO L226 Difference]: Without dead ends: 3307 [2021-01-06 19:24:12,993 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:24:12,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3307 states. [2021-01-06 19:24:13,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3307 to 2257. [2021-01-06 19:24:13,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2257 states. [2021-01-06 19:24:13,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2257 states to 2257 states and 3068 transitions. [2021-01-06 19:24:13,201 INFO L78 Accepts]: Start accepts. Automaton has 2257 states and 3068 transitions. Word has length 53 [2021-01-06 19:24:13,201 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:13,201 INFO L481 AbstractCegarLoop]: Abstraction has 2257 states and 3068 transitions. [2021-01-06 19:24:13,201 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:24:13,202 INFO L276 IsEmpty]: Start isEmpty. Operand 2257 states and 3068 transitions. [2021-01-06 19:24:13,202 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2021-01-06 19:24:13,203 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:13,203 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:13,203 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2021-01-06 19:24:13,205 INFO L429 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:13,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:13,209 INFO L82 PathProgramCache]: Analyzing trace with hash 1402479484, now seen corresponding path program 1 times [2021-01-06 19:24:13,209 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:13,210 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [580139278] [2021-01-06 19:24:13,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:13,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:13,312 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2021-01-06 19:24:13,312 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [580139278] [2021-01-06 19:24:13,313 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:13,313 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:24:13,314 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1634487011] [2021-01-06 19:24:13,315 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:24:13,315 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:13,316 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:24:13,316 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:13,316 INFO L87 Difference]: Start difference. First operand 2257 states and 3068 transitions. Second operand 3 states. [2021-01-06 19:24:13,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:13,681 INFO L93 Difference]: Finished difference Result 6563 states and 8862 transitions. [2021-01-06 19:24:13,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:24:13,682 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 53 [2021-01-06 19:24:13,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:13,705 INFO L225 Difference]: With dead ends: 6563 [2021-01-06 19:24:13,705 INFO L226 Difference]: Without dead ends: 4346 [2021-01-06 19:24:13,710 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:13,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4346 states. [2021-01-06 19:24:13,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4346 to 4342. [2021-01-06 19:24:13,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4342 states. [2021-01-06 19:24:14,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4342 states to 4342 states and 5752 transitions. [2021-01-06 19:24:14,006 INFO L78 Accepts]: Start accepts. Automaton has 4342 states and 5752 transitions. Word has length 53 [2021-01-06 19:24:14,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:14,007 INFO L481 AbstractCegarLoop]: Abstraction has 4342 states and 5752 transitions. [2021-01-06 19:24:14,007 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:24:14,007 INFO L276 IsEmpty]: Start isEmpty. Operand 4342 states and 5752 transitions. [2021-01-06 19:24:14,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2021-01-06 19:24:14,009 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:14,009 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:14,009 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2021-01-06 19:24:14,009 INFO L429 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:14,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:14,010 INFO L82 PathProgramCache]: Analyzing trace with hash -1150705430, now seen corresponding path program 1 times [2021-01-06 19:24:14,010 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:14,011 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051465241] [2021-01-06 19:24:14,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:14,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:14,093 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:24:14,094 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1051465241] [2021-01-06 19:24:14,094 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:14,095 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:24:14,095 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [536588418] [2021-01-06 19:24:14,095 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:24:14,096 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:14,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:24:14,096 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:24:14,097 INFO L87 Difference]: Start difference. First operand 4342 states and 5752 transitions. Second operand 4 states. [2021-01-06 19:24:14,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:14,727 INFO L93 Difference]: Finished difference Result 12792 states and 16918 transitions. [2021-01-06 19:24:14,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:24:14,727 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 55 [2021-01-06 19:24:14,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:14,775 INFO L225 Difference]: With dead ends: 12792 [2021-01-06 19:24:14,776 INFO L226 Difference]: Without dead ends: 8525 [2021-01-06 19:24:14,785 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:24:14,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8525 states. [2021-01-06 19:24:15,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8525 to 8521. [2021-01-06 19:24:15,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8521 states. [2021-01-06 19:24:15,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8521 states to 8521 states and 11141 transitions. [2021-01-06 19:24:15,443 INFO L78 Accepts]: Start accepts. Automaton has 8521 states and 11141 transitions. Word has length 55 [2021-01-06 19:24:15,444 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:15,444 INFO L481 AbstractCegarLoop]: Abstraction has 8521 states and 11141 transitions. [2021-01-06 19:24:15,444 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:24:15,444 INFO L276 IsEmpty]: Start isEmpty. Operand 8521 states and 11141 transitions. [2021-01-06 19:24:15,447 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2021-01-06 19:24:15,448 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:15,448 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:15,448 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2021-01-06 19:24:15,448 INFO L429 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:15,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:15,449 INFO L82 PathProgramCache]: Analyzing trace with hash 216468379, now seen corresponding path program 1 times [2021-01-06 19:24:15,449 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:15,450 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334748701] [2021-01-06 19:24:15,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:15,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:15,500 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:24:15,500 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1334748701] [2021-01-06 19:24:15,501 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:15,501 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:24:15,501 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1906073295] [2021-01-06 19:24:15,502 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:24:15,502 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:15,502 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:24:15,503 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:24:15,503 INFO L87 Difference]: Start difference. First operand 8521 states and 11141 transitions. Second operand 4 states. [2021-01-06 19:24:16,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:16,104 INFO L93 Difference]: Finished difference Result 16387 states and 21487 transitions. [2021-01-06 19:24:16,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:24:16,105 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 61 [2021-01-06 19:24:16,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:16,138 INFO L225 Difference]: With dead ends: 16387 [2021-01-06 19:24:16,139 INFO L226 Difference]: Without dead ends: 8336 [2021-01-06 19:24:16,152 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:24:16,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8336 states. [2021-01-06 19:24:16,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8336 to 8324. [2021-01-06 19:24:16,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8324 states. [2021-01-06 19:24:16,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8324 states to 8324 states and 10739 transitions. [2021-01-06 19:24:16,700 INFO L78 Accepts]: Start accepts. Automaton has 8324 states and 10739 transitions. Word has length 61 [2021-01-06 19:24:16,700 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:16,700 INFO L481 AbstractCegarLoop]: Abstraction has 8324 states and 10739 transitions. [2021-01-06 19:24:16,701 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:24:16,701 INFO L276 IsEmpty]: Start isEmpty. Operand 8324 states and 10739 transitions. [2021-01-06 19:24:16,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2021-01-06 19:24:16,706 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:16,707 INFO L422 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:16,707 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2021-01-06 19:24:16,707 INFO L429 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:16,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:16,708 INFO L82 PathProgramCache]: Analyzing trace with hash 918521819, now seen corresponding path program 1 times [2021-01-06 19:24:16,708 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:16,708 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [400913613] [2021-01-06 19:24:16,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:16,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:16,785 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2021-01-06 19:24:16,785 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [400913613] [2021-01-06 19:24:16,785 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:16,786 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2021-01-06 19:24:16,786 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765384071] [2021-01-06 19:24:16,786 INFO L461 AbstractCegarLoop]: Interpolant automaton has 6 states [2021-01-06 19:24:16,787 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:16,790 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-01-06 19:24:16,791 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2021-01-06 19:24:16,791 INFO L87 Difference]: Start difference. First operand 8324 states and 10739 transitions. Second operand 6 states. [2021-01-06 19:24:17,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:17,414 INFO L93 Difference]: Finished difference Result 14098 states and 18169 transitions. [2021-01-06 19:24:17,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-01-06 19:24:17,414 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 96 [2021-01-06 19:24:17,415 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:17,428 INFO L225 Difference]: With dead ends: 14098 [2021-01-06 19:24:17,428 INFO L226 Difference]: Without dead ends: 5883 [2021-01-06 19:24:17,439 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 10 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=60, Invalid=122, Unknown=0, NotChecked=0, Total=182 [2021-01-06 19:24:17,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5883 states. [2021-01-06 19:24:17,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5883 to 5191. [2021-01-06 19:24:17,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5191 states. [2021-01-06 19:24:17,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5191 states to 5191 states and 6694 transitions. [2021-01-06 19:24:17,850 INFO L78 Accepts]: Start accepts. Automaton has 5191 states and 6694 transitions. Word has length 96 [2021-01-06 19:24:17,851 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:17,851 INFO L481 AbstractCegarLoop]: Abstraction has 5191 states and 6694 transitions. [2021-01-06 19:24:17,851 INFO L482 AbstractCegarLoop]: Interpolant automaton has 6 states. [2021-01-06 19:24:17,851 INFO L276 IsEmpty]: Start isEmpty. Operand 5191 states and 6694 transitions. [2021-01-06 19:24:17,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2021-01-06 19:24:17,856 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:17,856 INFO L422 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:17,856 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2021-01-06 19:24:17,857 INFO L429 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:17,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:17,857 INFO L82 PathProgramCache]: Analyzing trace with hash 1430687950, now seen corresponding path program 1 times [2021-01-06 19:24:17,858 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:17,858 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [518449753] [2021-01-06 19:24:17,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:17,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:17,925 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2021-01-06 19:24:17,926 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [518449753] [2021-01-06 19:24:17,926 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:17,926 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:24:17,926 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1637980842] [2021-01-06 19:24:17,927 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:24:17,927 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:17,928 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:24:17,928 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:24:17,928 INFO L87 Difference]: Start difference. First operand 5191 states and 6694 transitions. Second operand 4 states. [2021-01-06 19:24:18,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:18,472 INFO L93 Difference]: Finished difference Result 11504 states and 14819 transitions. [2021-01-06 19:24:18,472 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:24:18,473 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 99 [2021-01-06 19:24:18,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:18,485 INFO L225 Difference]: With dead ends: 11504 [2021-01-06 19:24:18,485 INFO L226 Difference]: Without dead ends: 6164 [2021-01-06 19:24:18,492 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:24:18,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6164 states. [2021-01-06 19:24:18,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6164 to 4506. [2021-01-06 19:24:18,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4506 states. [2021-01-06 19:24:18,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4506 states to 4506 states and 5775 transitions. [2021-01-06 19:24:18,793 INFO L78 Accepts]: Start accepts. Automaton has 4506 states and 5775 transitions. Word has length 99 [2021-01-06 19:24:18,793 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:18,793 INFO L481 AbstractCegarLoop]: Abstraction has 4506 states and 5775 transitions. [2021-01-06 19:24:18,793 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:24:18,794 INFO L276 IsEmpty]: Start isEmpty. Operand 4506 states and 5775 transitions. [2021-01-06 19:24:18,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2021-01-06 19:24:18,796 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:18,797 INFO L422 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:18,797 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2021-01-06 19:24:18,797 INFO L429 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:18,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:18,798 INFO L82 PathProgramCache]: Analyzing trace with hash -661247030, now seen corresponding path program 1 times [2021-01-06 19:24:18,798 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:18,799 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850001537] [2021-01-06 19:24:18,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:18,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:18,888 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2021-01-06 19:24:18,888 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [850001537] [2021-01-06 19:24:18,888 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:18,889 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:24:18,889 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [661627636] [2021-01-06 19:24:18,889 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:24:18,889 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:18,890 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:24:18,890 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:24:18,890 INFO L87 Difference]: Start difference. First operand 4506 states and 5775 transitions. Second operand 4 states. [2021-01-06 19:24:19,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:19,251 INFO L93 Difference]: Finished difference Result 9550 states and 12213 transitions. [2021-01-06 19:24:19,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-01-06 19:24:19,251 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 99 [2021-01-06 19:24:19,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:19,262 INFO L225 Difference]: With dead ends: 9550 [2021-01-06 19:24:19,262 INFO L226 Difference]: Without dead ends: 5324 [2021-01-06 19:24:19,268 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:24:19,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5324 states. [2021-01-06 19:24:19,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5324 to 4502. [2021-01-06 19:24:19,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4502 states. [2021-01-06 19:24:19,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4502 states to 4502 states and 5708 transitions. [2021-01-06 19:24:19,554 INFO L78 Accepts]: Start accepts. Automaton has 4502 states and 5708 transitions. Word has length 99 [2021-01-06 19:24:19,555 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:19,555 INFO L481 AbstractCegarLoop]: Abstraction has 4502 states and 5708 transitions. [2021-01-06 19:24:19,555 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:24:19,555 INFO L276 IsEmpty]: Start isEmpty. Operand 4502 states and 5708 transitions. [2021-01-06 19:24:19,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2021-01-06 19:24:19,558 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:19,558 INFO L422 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:19,558 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2021-01-06 19:24:19,558 INFO L429 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:19,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:19,559 INFO L82 PathProgramCache]: Analyzing trace with hash -1763595376, now seen corresponding path program 1 times [2021-01-06 19:24:19,559 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:19,559 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508741450] [2021-01-06 19:24:19,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:19,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:19,586 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2021-01-06 19:24:19,586 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508741450] [2021-01-06 19:24:19,587 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:19,587 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:24:19,587 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1893331107] [2021-01-06 19:24:19,587 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:24:19,588 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:19,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:24:19,588 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:19,589 INFO L87 Difference]: Start difference. First operand 4502 states and 5708 transitions. Second operand 3 states. [2021-01-06 19:24:19,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:19,807 INFO L93 Difference]: Finished difference Result 8614 states and 10969 transitions. [2021-01-06 19:24:19,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:24:19,807 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 99 [2021-01-06 19:24:19,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:19,817 INFO L225 Difference]: With dead ends: 8614 [2021-01-06 19:24:19,817 INFO L226 Difference]: Without dead ends: 4315 [2021-01-06 19:24:19,823 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:19,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4315 states. [2021-01-06 19:24:20,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4315 to 4315. [2021-01-06 19:24:20,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4315 states. [2021-01-06 19:24:20,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4315 states to 4315 states and 5488 transitions. [2021-01-06 19:24:20,140 INFO L78 Accepts]: Start accepts. Automaton has 4315 states and 5488 transitions. Word has length 99 [2021-01-06 19:24:20,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:20,140 INFO L481 AbstractCegarLoop]: Abstraction has 4315 states and 5488 transitions. [2021-01-06 19:24:20,141 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:24:20,141 INFO L276 IsEmpty]: Start isEmpty. Operand 4315 states and 5488 transitions. [2021-01-06 19:24:20,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2021-01-06 19:24:20,143 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:20,143 INFO L422 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:20,144 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2021-01-06 19:24:20,144 INFO L429 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:20,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:20,144 INFO L82 PathProgramCache]: Analyzing trace with hash -1242360231, now seen corresponding path program 1 times [2021-01-06 19:24:20,145 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:20,145 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347825793] [2021-01-06 19:24:20,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:20,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:20,181 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:24:20,182 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347825793] [2021-01-06 19:24:20,182 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:20,182 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:24:20,182 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1022172038] [2021-01-06 19:24:20,183 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:24:20,183 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:20,184 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:24:20,184 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:20,184 INFO L87 Difference]: Start difference. First operand 4315 states and 5488 transitions. Second operand 3 states. [2021-01-06 19:24:20,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:20,483 INFO L93 Difference]: Finished difference Result 8241 states and 10504 transitions. [2021-01-06 19:24:20,484 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:24:20,484 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 102 [2021-01-06 19:24:20,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:20,492 INFO L225 Difference]: With dead ends: 8241 [2021-01-06 19:24:20,493 INFO L226 Difference]: Without dead ends: 4019 [2021-01-06 19:24:20,499 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:20,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4019 states. [2021-01-06 19:24:20,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4019 to 3964. [2021-01-06 19:24:20,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3964 states. [2021-01-06 19:24:20,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3964 states to 3964 states and 4979 transitions. [2021-01-06 19:24:20,811 INFO L78 Accepts]: Start accepts. Automaton has 3964 states and 4979 transitions. Word has length 102 [2021-01-06 19:24:20,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:20,812 INFO L481 AbstractCegarLoop]: Abstraction has 3964 states and 4979 transitions. [2021-01-06 19:24:20,812 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:24:20,812 INFO L276 IsEmpty]: Start isEmpty. Operand 3964 states and 4979 transitions. [2021-01-06 19:24:20,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2021-01-06 19:24:20,814 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:20,814 INFO L422 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:20,815 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2021-01-06 19:24:20,815 INFO L429 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:20,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:20,815 INFO L82 PathProgramCache]: Analyzing trace with hash -310429394, now seen corresponding path program 1 times [2021-01-06 19:24:20,816 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:20,816 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144816006] [2021-01-06 19:24:20,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:20,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:20,880 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2021-01-06 19:24:20,881 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144816006] [2021-01-06 19:24:20,881 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:20,881 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:24:20,882 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [745677894] [2021-01-06 19:24:20,882 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:24:20,882 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:20,883 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:24:20,883 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:24:20,883 INFO L87 Difference]: Start difference. First operand 3964 states and 4979 transitions. Second operand 4 states. [2021-01-06 19:24:21,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:21,488 INFO L93 Difference]: Finished difference Result 8837 states and 11043 transitions. [2021-01-06 19:24:21,489 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-01-06 19:24:21,489 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 103 [2021-01-06 19:24:21,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:21,501 INFO L225 Difference]: With dead ends: 8837 [2021-01-06 19:24:21,501 INFO L226 Difference]: Without dead ends: 4968 [2021-01-06 19:24:21,508 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:24:21,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4968 states. [2021-01-06 19:24:21,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4968 to 3935. [2021-01-06 19:24:21,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3935 states. [2021-01-06 19:24:21,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3935 states to 3935 states and 4856 transitions. [2021-01-06 19:24:21,912 INFO L78 Accepts]: Start accepts. Automaton has 3935 states and 4856 transitions. Word has length 103 [2021-01-06 19:24:21,913 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:21,913 INFO L481 AbstractCegarLoop]: Abstraction has 3935 states and 4856 transitions. [2021-01-06 19:24:21,913 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:24:21,913 INFO L276 IsEmpty]: Start isEmpty. Operand 3935 states and 4856 transitions. [2021-01-06 19:24:21,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2021-01-06 19:24:21,915 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:21,916 INFO L422 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:21,916 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2021-01-06 19:24:21,916 INFO L429 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:21,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:21,917 INFO L82 PathProgramCache]: Analyzing trace with hash 291943753, now seen corresponding path program 1 times [2021-01-06 19:24:21,917 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:21,917 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1488337565] [2021-01-06 19:24:21,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:21,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:22,015 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2021-01-06 19:24:22,016 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1488337565] [2021-01-06 19:24:22,018 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:22,019 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-06 19:24:22,019 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [593311674] [2021-01-06 19:24:22,019 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:24:22,019 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:22,020 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:24:22,020 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:22,021 INFO L87 Difference]: Start difference. First operand 3935 states and 4856 transitions. Second operand 3 states. [2021-01-06 19:24:22,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:22,448 INFO L93 Difference]: Finished difference Result 9904 states and 12174 transitions. [2021-01-06 19:24:22,449 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:24:22,449 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 119 [2021-01-06 19:24:22,449 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:22,463 INFO L225 Difference]: With dead ends: 9904 [2021-01-06 19:24:22,463 INFO L226 Difference]: Without dead ends: 6064 [2021-01-06 19:24:22,470 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:22,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6064 states. [2021-01-06 19:24:22,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6064 to 6060. [2021-01-06 19:24:22,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6060 states. [2021-01-06 19:24:22,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6060 states to 6060 states and 7390 transitions. [2021-01-06 19:24:22,918 INFO L78 Accepts]: Start accepts. Automaton has 6060 states and 7390 transitions. Word has length 119 [2021-01-06 19:24:22,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:22,918 INFO L481 AbstractCegarLoop]: Abstraction has 6060 states and 7390 transitions. [2021-01-06 19:24:22,918 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:24:22,918 INFO L276 IsEmpty]: Start isEmpty. Operand 6060 states and 7390 transitions. [2021-01-06 19:24:22,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2021-01-06 19:24:22,925 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:22,925 INFO L422 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:22,926 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2021-01-06 19:24:22,926 INFO L429 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:22,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:22,926 INFO L82 PathProgramCache]: Analyzing trace with hash -368834209, now seen corresponding path program 1 times [2021-01-06 19:24:22,927 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:22,927 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [438279695] [2021-01-06 19:24:22,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:22,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:22,984 INFO L134 CoverageAnalysis]: Checked inductivity of 114 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 78 trivial. 0 not checked. [2021-01-06 19:24:22,984 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [438279695] [2021-01-06 19:24:22,984 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:22,985 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:24:22,985 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [294147311] [2021-01-06 19:24:22,985 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:24:22,985 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:22,986 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:24:22,986 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:22,986 INFO L87 Difference]: Start difference. First operand 6060 states and 7390 transitions. Second operand 3 states. [2021-01-06 19:24:23,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:23,452 INFO L93 Difference]: Finished difference Result 12037 states and 14689 transitions. [2021-01-06 19:24:23,453 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:24:23,453 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 179 [2021-01-06 19:24:23,453 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:23,466 INFO L225 Difference]: With dead ends: 12037 [2021-01-06 19:24:23,467 INFO L226 Difference]: Without dead ends: 6060 [2021-01-06 19:24:23,477 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:23,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6060 states. [2021-01-06 19:24:23,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6060 to 5836. [2021-01-06 19:24:23,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5836 states. [2021-01-06 19:24:23,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5836 states to 5836 states and 7047 transitions. [2021-01-06 19:24:23,853 INFO L78 Accepts]: Start accepts. Automaton has 5836 states and 7047 transitions. Word has length 179 [2021-01-06 19:24:23,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:23,853 INFO L481 AbstractCegarLoop]: Abstraction has 5836 states and 7047 transitions. [2021-01-06 19:24:23,853 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:24:23,853 INFO L276 IsEmpty]: Start isEmpty. Operand 5836 states and 7047 transitions. [2021-01-06 19:24:23,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2021-01-06 19:24:23,860 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:23,860 INFO L422 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:23,860 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2021-01-06 19:24:23,861 INFO L429 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:23,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:23,861 INFO L82 PathProgramCache]: Analyzing trace with hash -1199487843, now seen corresponding path program 1 times [2021-01-06 19:24:23,862 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:23,862 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973001521] [2021-01-06 19:24:23,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:23,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:23,955 INFO L134 CoverageAnalysis]: Checked inductivity of 114 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 114 trivial. 0 not checked. [2021-01-06 19:24:23,956 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1973001521] [2021-01-06 19:24:23,956 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:23,956 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:24:23,960 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1529384486] [2021-01-06 19:24:23,962 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:24:23,962 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:23,963 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:24:23,963 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:23,963 INFO L87 Difference]: Start difference. First operand 5836 states and 7047 transitions. Second operand 3 states. [2021-01-06 19:24:24,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:24,429 INFO L93 Difference]: Finished difference Result 11417 states and 13819 transitions. [2021-01-06 19:24:24,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:24:24,430 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 179 [2021-01-06 19:24:24,430 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:24,442 INFO L225 Difference]: With dead ends: 11417 [2021-01-06 19:24:24,442 INFO L226 Difference]: Without dead ends: 5644 [2021-01-06 19:24:24,454 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:24,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5644 states. [2021-01-06 19:24:24,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5644 to 5644. [2021-01-06 19:24:24,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5644 states. [2021-01-06 19:24:24,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5644 states to 5644 states and 6839 transitions. [2021-01-06 19:24:24,851 INFO L78 Accepts]: Start accepts. Automaton has 5644 states and 6839 transitions. Word has length 179 [2021-01-06 19:24:24,851 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:24,851 INFO L481 AbstractCegarLoop]: Abstraction has 5644 states and 6839 transitions. [2021-01-06 19:24:24,851 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:24:24,851 INFO L276 IsEmpty]: Start isEmpty. Operand 5644 states and 6839 transitions. [2021-01-06 19:24:24,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 184 [2021-01-06 19:24:24,858 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:24,858 INFO L422 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:24,858 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2021-01-06 19:24:24,858 INFO L429 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:24,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:24,859 INFO L82 PathProgramCache]: Analyzing trace with hash 1582627211, now seen corresponding path program 1 times [2021-01-06 19:24:24,859 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:24,859 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563483157] [2021-01-06 19:24:24,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:24,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:24,927 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 70 proven. 0 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2021-01-06 19:24:24,928 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1563483157] [2021-01-06 19:24:24,928 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:24,928 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-01-06 19:24:24,928 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1292246416] [2021-01-06 19:24:24,929 INFO L461 AbstractCegarLoop]: Interpolant automaton has 5 states [2021-01-06 19:24:24,929 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:24,930 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-01-06 19:24:24,930 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:24:24,930 INFO L87 Difference]: Start difference. First operand 5644 states and 6839 transitions. Second operand 5 states. [2021-01-06 19:24:25,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:25,419 INFO L93 Difference]: Finished difference Result 12526 states and 15178 transitions. [2021-01-06 19:24:25,419 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:24:25,419 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 183 [2021-01-06 19:24:25,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:25,431 INFO L225 Difference]: With dead ends: 12526 [2021-01-06 19:24:25,431 INFO L226 Difference]: Without dead ends: 6945 [2021-01-06 19:24:25,437 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-01-06 19:24:25,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6945 states. [2021-01-06 19:24:25,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6945 to 5392. [2021-01-06 19:24:25,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5392 states. [2021-01-06 19:24:25,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5392 states to 5392 states and 6469 transitions. [2021-01-06 19:24:25,999 INFO L78 Accepts]: Start accepts. Automaton has 5392 states and 6469 transitions. Word has length 183 [2021-01-06 19:24:25,999 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:25,999 INFO L481 AbstractCegarLoop]: Abstraction has 5392 states and 6469 transitions. [2021-01-06 19:24:26,000 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2021-01-06 19:24:26,000 INFO L276 IsEmpty]: Start isEmpty. Operand 5392 states and 6469 transitions. [2021-01-06 19:24:26,005 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 184 [2021-01-06 19:24:26,006 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:24:26,006 INFO L422 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:24:26,006 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2021-01-06 19:24:26,006 INFO L429 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:24:26,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:24:26,010 INFO L82 PathProgramCache]: Analyzing trace with hash 646872823, now seen corresponding path program 1 times [2021-01-06 19:24:26,010 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:24:26,010 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082433174] [2021-01-06 19:24:26,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:24:26,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:24:26,091 INFO L134 CoverageAnalysis]: Checked inductivity of 116 backedges. 73 proven. 0 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2021-01-06 19:24:26,091 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2082433174] [2021-01-06 19:24:26,091 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:24:26,092 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:24:26,092 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [500134717] [2021-01-06 19:24:26,092 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:24:26,093 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:24:26,093 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:24:26,093 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:26,093 INFO L87 Difference]: Start difference. First operand 5392 states and 6469 transitions. Second operand 3 states. [2021-01-06 19:24:26,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:24:26,362 INFO L93 Difference]: Finished difference Result 7992 states and 9637 transitions. [2021-01-06 19:24:26,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:24:26,363 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 183 [2021-01-06 19:24:26,363 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:24:26,363 INFO L225 Difference]: With dead ends: 7992 [2021-01-06 19:24:26,363 INFO L226 Difference]: Without dead ends: 0 [2021-01-06 19:24:26,370 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:24:26,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2021-01-06 19:24:26,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2021-01-06 19:24:26,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2021-01-06 19:24:26,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2021-01-06 19:24:26,372 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 183 [2021-01-06 19:24:26,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:24:26,372 INFO L481 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2021-01-06 19:24:26,372 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:24:26,372 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2021-01-06 19:24:26,373 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2021-01-06 19:24:26,373 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2021-01-06 19:24:26,375 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 0 states and 0 transitions. [2021-01-06 19:24:26,655 WARN L197 SmtUtils]: Spent 260.00 ms on a formula simplification. DAG size of input: 196 DAG size of output: 117 [2021-01-06 19:24:27,239 WARN L197 SmtUtils]: Spent 568.00 ms on a formula simplification. DAG size of input: 387 DAG size of output: 151 [2021-01-06 19:24:27,591 WARN L197 SmtUtils]: Spent 348.00 ms on a formula simplification. DAG size of input: 210 DAG size of output: 111 [2021-01-06 19:24:28,815 WARN L197 SmtUtils]: Spent 1.21 s on a formula simplification. DAG size of input: 642 DAG size of output: 296 [2021-01-06 19:24:29,701 WARN L197 SmtUtils]: Spent 881.00 ms on a formula simplification. DAG size of input: 632 DAG size of output: 283 [2021-01-06 19:24:30,059 WARN L197 SmtUtils]: Spent 355.00 ms on a formula simplification. DAG size of input: 447 DAG size of output: 172 [2021-01-06 19:24:30,266 WARN L197 SmtUtils]: Spent 204.00 ms on a formula simplification. DAG size of input: 286 DAG size of output: 121 [2021-01-06 19:24:30,474 WARN L197 SmtUtils]: Spent 204.00 ms on a formula simplification. DAG size of input: 263 DAG size of output: 113 [2021-01-06 19:24:30,696 WARN L197 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 288 DAG size of output: 153 [2021-01-06 19:24:30,962 WARN L197 SmtUtils]: Spent 259.00 ms on a formula simplification. DAG size of input: 387 DAG size of output: 151 [2021-01-06 19:24:31,081 WARN L197 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 224 DAG size of output: 99 [2021-01-06 19:24:31,363 WARN L197 SmtUtils]: Spent 275.00 ms on a formula simplification. DAG size of input: 384 DAG size of output: 138 [2021-01-06 19:24:31,465 WARN L197 SmtUtils]: Spent 100.00 ms on a formula simplification. DAG size of input: 204 DAG size of output: 105 [2021-01-06 19:24:31,591 WARN L197 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 233 DAG size of output: 128 [2021-01-06 19:24:31,888 WARN L197 SmtUtils]: Spent 219.00 ms on a formula simplification. DAG size of input: 388 DAG size of output: 152 [2021-01-06 19:24:32,394 WARN L197 SmtUtils]: Spent 477.00 ms on a formula simplification. DAG size of input: 629 DAG size of output: 294 [2021-01-06 19:24:32,560 WARN L197 SmtUtils]: Spent 161.00 ms on a formula simplification. DAG size of input: 284 DAG size of output: 97 [2021-01-06 19:24:33,288 WARN L197 SmtUtils]: Spent 508.00 ms on a formula simplification. DAG size of input: 524 DAG size of output: 231 [2021-01-06 19:24:33,677 WARN L197 SmtUtils]: Spent 385.00 ms on a formula simplification. DAG size of input: 387 DAG size of output: 151 [2021-01-06 19:24:33,817 WARN L197 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 290 DAG size of output: 139 [2021-01-06 19:24:34,103 WARN L197 SmtUtils]: Spent 208.00 ms on a formula simplification. DAG size of input: 407 DAG size of output: 114 [2021-01-06 19:24:34,858 WARN L197 SmtUtils]: Spent 544.00 ms on a formula simplification. DAG size of input: 92 DAG size of output: 52 [2021-01-06 19:24:34,982 WARN L197 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 36 [2021-01-06 19:24:35,660 WARN L197 SmtUtils]: Spent 675.00 ms on a formula simplification. DAG size of input: 133 DAG size of output: 66 [2021-01-06 19:24:36,068 WARN L197 SmtUtils]: Spent 406.00 ms on a formula simplification. DAG size of input: 102 DAG size of output: 60 [2021-01-06 19:24:36,269 WARN L197 SmtUtils]: Spent 199.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 44 [2021-01-06 19:24:37,736 WARN L197 SmtUtils]: Spent 1.46 s on a formula simplification. DAG size of input: 250 DAG size of output: 81 [2021-01-06 19:24:39,157 WARN L197 SmtUtils]: Spent 1.42 s on a formula simplification. DAG size of input: 241 DAG size of output: 81 [2021-01-06 19:24:39,831 WARN L197 SmtUtils]: Spent 671.00 ms on a formula simplification. DAG size of input: 144 DAG size of output: 60 [2021-01-06 19:24:40,454 WARN L197 SmtUtils]: Spent 617.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 59 [2021-01-06 19:24:41,061 WARN L197 SmtUtils]: Spent 604.00 ms on a formula simplification. DAG size of input: 101 DAG size of output: 63 [2021-01-06 19:24:41,589 WARN L197 SmtUtils]: Spent 526.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 55 [2021-01-06 19:24:42,006 WARN L197 SmtUtils]: Spent 415.00 ms on a formula simplification. DAG size of input: 136 DAG size of output: 48 [2021-01-06 19:24:42,183 WARN L197 SmtUtils]: Spent 176.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 42 [2021-01-06 19:24:42,300 WARN L197 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 40 DAG size of output: 32 [2021-01-06 19:24:42,995 WARN L197 SmtUtils]: Spent 691.00 ms on a formula simplification. DAG size of input: 133 DAG size of output: 66 [2021-01-06 19:24:43,746 WARN L197 SmtUtils]: Spent 748.00 ms on a formula simplification. DAG size of input: 88 DAG size of output: 70 [2021-01-06 19:24:43,932 WARN L197 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 42 DAG size of output: 34 [2021-01-06 19:24:44,632 WARN L197 SmtUtils]: Spent 698.00 ms on a formula simplification. DAG size of input: 126 DAG size of output: 63 [2021-01-06 19:24:45,018 WARN L197 SmtUtils]: Spent 383.00 ms on a formula simplification. DAG size of input: 96 DAG size of output: 54 [2021-01-06 19:24:45,566 WARN L197 SmtUtils]: Spent 546.00 ms on a formula simplification. DAG size of input: 115 DAG size of output: 60 [2021-01-06 19:24:45,960 WARN L197 SmtUtils]: Spent 391.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 57 [2021-01-06 19:24:46,771 WARN L197 SmtUtils]: Spent 809.00 ms on a formula simplification. DAG size of input: 134 DAG size of output: 74 [2021-01-06 19:24:46,877 WARN L197 SmtUtils]: Spent 104.00 ms on a formula simplification that was a NOOP. DAG size: 47 [2021-01-06 19:24:48,156 WARN L197 SmtUtils]: Spent 1.28 s on a formula simplification. DAG size of input: 235 DAG size of output: 76 [2021-01-06 19:24:48,735 WARN L197 SmtUtils]: Spent 515.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 57 [2021-01-06 19:24:49,229 WARN L197 SmtUtils]: Spent 493.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 57 [2021-01-06 19:24:49,334 WARN L197 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 40 DAG size of output: 32 [2021-01-06 19:24:49,744 WARN L197 SmtUtils]: Spent 408.00 ms on a formula simplification. DAG size of input: 88 DAG size of output: 61 [2021-01-06 19:24:50,218 WARN L197 SmtUtils]: Spent 472.00 ms on a formula simplification. DAG size of input: 78 DAG size of output: 53 [2021-01-06 19:24:50,379 WARN L197 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 48 DAG size of output: 40 [2021-01-06 19:24:51,537 WARN L197 SmtUtils]: Spent 1.15 s on a formula simplification. DAG size of input: 187 DAG size of output: 79 [2021-01-06 19:24:52,263 WARN L197 SmtUtils]: Spent 724.00 ms on a formula simplification. DAG size of input: 133 DAG size of output: 66 [2021-01-06 19:24:52,661 WARN L197 SmtUtils]: Spent 394.00 ms on a formula simplification. DAG size of input: 125 DAG size of output: 48 [2021-01-06 19:24:53,374 WARN L197 SmtUtils]: Spent 711.00 ms on a formula simplification. DAG size of input: 96 DAG size of output: 65 [2021-01-06 19:24:53,882 WARN L197 SmtUtils]: Spent 506.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 61 [2021-01-06 19:24:54,208 WARN L197 SmtUtils]: Spent 324.00 ms on a formula simplification. DAG size of input: 113 DAG size of output: 47 [2021-01-06 19:24:54,399 WARN L197 SmtUtils]: Spent 189.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 41 [2021-01-06 19:24:54,849 WARN L197 SmtUtils]: Spent 447.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 49 [2021-01-06 19:24:54,855 INFO L189 CegarLoopUtils]: For program point L68-3(lines 68 77) no Hoare annotation was computed. [2021-01-06 19:24:54,855 INFO L189 CegarLoopUtils]: For program point L68-5(lines 68 77) no Hoare annotation was computed. [2021-01-06 19:24:54,856 INFO L189 CegarLoopUtils]: For program point ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION(line 11) no Hoare annotation was computed. [2021-01-06 19:24:54,858 INFO L185 CegarLoopUtils]: At program point L465(lines 449 467) the Hoare annotation is: (let ((.cse5 (= ~t~0 0)) (.cse16 (= ~q_read_ev~0 2)) (.cse14 (not (= ~p_dw_st~0 0))) (.cse17 (= ~q_req_up~0 0)) (.cse15 (not (= ~p_dw_pc~0 1))) (.cse0 (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0))) (.cse1 (= 1 ~c_dr_i~0)) (.cse2 (not (= ~slow_clk_edge~0 1))) (.cse3 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse4 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse6 (= ~p_dw_i~0 1)) (.cse7 (= ~c_dr_pc~0 1)) (.cse13 (not (= ~c_dr_st~0 0))) (.cse8 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse9 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse10 (not (= ~q_write_ev~0 0))) (.cse11 (not (= ~fast_clk_edge~0 1))) (.cse12 (not (= ~q_write_ev~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10 .cse11 .cse12) (and .cse1 .cse2 .cse13 .cse14 .cse10 .cse11 .cse12 .cse6 .cse7) (and .cse0 .cse1 .cse2 .cse14 .cse4 .cse5 .cse10 .cse11 .cse12 .cse6 .cse7) (and .cse0 .cse1 .cse2 .cse4 .cse10 .cse5 .cse11 .cse12 .cse6 .cse15 .cse7) (and .cse0 .cse1 .cse2 .cse13 .cse4 .cse10 .cse11 .cse12 .cse6 .cse15 .cse7) (and (not .cse7) .cse13 .cse16 .cse14 .cse10 .cse17 .cse12 .cse15) (and .cse13 .cse16 .cse14 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse17 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse12 .cse15) (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse6 .cse7 .cse13 .cse8 .cse9 .cse10 .cse11 .cse12))) [2021-01-06 19:24:54,858 INFO L189 CegarLoopUtils]: For program point L69(lines 69 74) no Hoare annotation was computed. [2021-01-06 19:24:54,859 INFO L189 CegarLoopUtils]: For program point L69-1(lines 69 74) no Hoare annotation was computed. [2021-01-06 19:24:54,859 INFO L189 CegarLoopUtils]: For program point L69-2(lines 69 74) no Hoare annotation was computed. [2021-01-06 19:24:54,859 INFO L189 CegarLoopUtils]: For program point L203(line 203) no Hoare annotation was computed. [2021-01-06 19:24:54,859 INFO L189 CegarLoopUtils]: For program point L303-1(lines 302 315) no Hoare annotation was computed. [2021-01-06 19:24:54,859 INFO L185 CegarLoopUtils]: At program point L270-1(lines 303 307) the Hoare annotation is: (let ((.cse1 (= ~q_read_ev~0 2)) (.cse2 (= ~p_dw_st~0 0)) (.cse3 (= ~c_dr_pc~0 ~q_req_up~0)) (.cse4 (= ~q_req_up~0 0)) (.cse0 (= ~c_dr_st~0 0)) (.cse5 (= ~q_req_up~0 ~p_dw_pc~0)) (.cse6 (= ~q_write_ev~0 ~q_read_ev~0))) (or (and (not .cse0) .cse1 (not .cse2) .cse3 .cse4 .cse5 .cse6) (and (= 1 ~c_dr_i~0) .cse1 (= ~q_read_ev~0 ~fast_clk_edge~0) .cse2 (= ~slow_clk_edge~0 ~q_read_ev~0) .cse3 .cse4 (= ~t~0 0) .cse0 .cse5 (= ~p_dw_i~0 1) .cse6))) [2021-01-06 19:24:54,859 INFO L189 CegarLoopUtils]: For program point L303-2(lines 303 307) no Hoare annotation was computed. [2021-01-06 19:24:54,859 INFO L189 CegarLoopUtils]: For program point L303-4(lines 302 315) no Hoare annotation was computed. [2021-01-06 19:24:54,859 INFO L189 CegarLoopUtils]: For program point L502(lines 502 511) no Hoare annotation was computed. [2021-01-06 19:24:54,860 INFO L185 CegarLoopUtils]: At program point L502-1(lines 502 511) the Hoare annotation is: (let ((.cse10 (= ~q_read_ev~0 2)) (.cse11 (= ~q_req_up~0 0)) (.cse3 (not (= ~p_dw_st~0 0))) (.cse2 (not (= ~c_dr_st~0 0))) (.cse14 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse13 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse15 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse0 (= 1 ~c_dr_i~0)) (.cse1 (not (= ~slow_clk_edge~0 1))) (.cse4 (not (= ~q_write_ev~0 0))) (.cse12 (= ~t~0 0)) (.cse5 (not (= ~fast_clk_edge~0 1))) (.cse6 (not (= ~q_write_ev~0 1))) (.cse7 (= ~p_dw_i~0 1)) (.cse9 (not (= ~p_dw_pc~0 1))) (.cse8 (= ~c_dr_pc~0 1))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8) (and .cse0 .cse2 .cse1 .cse4 .cse5 .cse6 .cse7 .cse9 .cse8) (and (not .cse8) .cse2 .cse10 .cse3 .cse4 .cse11 .cse6 .cse9) (and .cse2 .cse10 .cse3 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse11 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse6 .cse9) (and .cse0 .cse1 .cse3 .cse4 .cse12 .cse5 .cse6 .cse7 .cse8) (and .cse0 .cse1 .cse13 .cse14 .cse15 .cse12 .cse4 .cse5 .cse6 .cse7 .cse8) (and .cse0 .cse2 .cse1 .cse14 .cse13 .cse15 .cse4 .cse5 .cse6 .cse7 .cse8) (and .cse0 .cse1 .cse4 .cse12 .cse5 .cse6 .cse7 .cse9 .cse8))) [2021-01-06 19:24:54,860 INFO L189 CegarLoopUtils]: For program point L403(line 403) no Hoare annotation was computed. [2021-01-06 19:24:54,860 INFO L189 CegarLoopUtils]: For program point L141(lines 141 153) no Hoare annotation was computed. [2021-01-06 19:24:54,860 INFO L185 CegarLoopUtils]: At program point L108(lines 86 110) the Hoare annotation is: (let ((.cse4 (= ~c_dr_st~0 0)) (.cse0 (= ~q_read_ev~0 2)) (.cse1 (= ULTIMATE.start_activate_threads_~tmp~1 0)) (.cse8 (= ~p_dw_st~0 0)) (.cse2 (= ~c_dr_pc~0 ~q_req_up~0)) (.cse3 (= ~q_req_up~0 0)) (.cse5 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse6 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0)) (.cse9 (= ~q_req_up~0 ~p_dw_pc~0)) (.cse7 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|))) (or (and (= 1 ~c_dr_i~0) .cse0 (= ~q_read_ev~0 ~fast_clk_edge~0) .cse1 .cse2 .cse3 (= ~t~0 0) .cse4 .cse5 .cse6 .cse7 (= ~p_dw_i~0 1) .cse8 (= ~slow_clk_edge~0 ~q_read_ev~0) .cse9 (= ~q_write_ev~0 ~q_read_ev~0)) (and (not .cse4) .cse0 .cse1 (not .cse8) .cse2 .cse3 .cse5 .cse6 .cse9 .cse7))) [2021-01-06 19:24:54,860 INFO L185 CegarLoopUtils]: At program point L108-1(lines 86 110) the Hoare annotation is: (let ((.cse0 (= 1 ~c_dr_i~0)) (.cse1 (not (= ~slow_clk_edge~0 1))) (.cse10 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse8 (= ~p_dw_i~0 1)) (.cse12 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse13 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse6 (not (= ~fast_clk_edge~0 1))) (.cse7 (not (= ~q_write_ev~0 1))) (.cse9 (= ~c_dr_pc~0 1)) (.cse2 (not (= ~c_dr_st~0 0))) (.cse15 (= ~q_read_ev~0 2)) (.cse16 (= ULTIMATE.start_activate_threads_~tmp~1 0)) (.cse3 (not (= ~p_dw_st~0 0))) (.cse4 (not (= ~q_write_ev~0 0))) (.cse11 (= ~q_req_up~0 0)) (.cse17 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse5 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0)) (.cse18 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse14 (not (= ~p_dw_pc~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9) (and .cse0 .cse1 .cse10 .cse11 .cse5 .cse8 .cse9 .cse2 .cse12 .cse13 .cse4 .cse6 .cse14) (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse11 .cse5 .cse6 .cse8 .cse9) (and .cse2 .cse15 .cse16 .cse3 (= ~c_dr_pc~0 ~q_req_up~0) .cse11 .cse17 .cse5 .cse18 .cse14) (and .cse0 .cse1 .cse10 .cse5 .cse8 .cse9 .cse2 .cse12 .cse13 .cse4 .cse6 .cse7 .cse14) (and (not .cse9) .cse2 .cse15 .cse16 .cse3 .cse4 .cse11 .cse17 .cse5 .cse18 .cse14))) [2021-01-06 19:24:54,861 INFO L185 CegarLoopUtils]: At program point L108-2(lines 86 110) the Hoare annotation is: (let ((.cse13 (= ~p_dw_st~0 0))) (let ((.cse5 (not (= ~fast_clk_edge~0 1))) (.cse12 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse11 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse14 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse4 (= ~t~0 0)) (.cse0 (= 1 ~c_dr_i~0)) (.cse9 (not (= ~slow_clk_edge~0 1))) (.cse3 (not (= ~q_write_ev~0 0))) (.cse7 (= ~p_dw_i~0 1)) (.cse8 (= ~c_dr_pc~0 1)) (.cse1 (not (= ~c_dr_st~0 0))) (.cse15 (= ~q_read_ev~0 2)) (.cse16 (= ULTIMATE.start_activate_threads_~tmp~1 0)) (.cse2 (not .cse13)) (.cse17 (= ~q_req_up~0 0)) (.cse18 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse10 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0)) (.cse19 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse6 (not (= ~q_write_ev~0 1))) (.cse20 (not (= ~p_dw_pc~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8) (and .cse0 .cse9 .cse1 .cse2 .cse3 .cse10 .cse5 .cse6 .cse7 .cse8) (and .cse0 .cse9 .cse1 .cse11 .cse12 .cse13 .cse14 .cse3 .cse10 .cse6 .cse7 .cse8) (and (not .cse8) .cse1 .cse15 .cse16 .cse2 .cse3 .cse17 .cse18 .cse10 .cse19 .cse6 .cse20) (and .cse0 .cse1 .cse13 .cse12 .cse11 .cse14 .cse3 .cse4 .cse6 .cse7 .cse8) (and .cse0 .cse1 .cse3 .cse4 .cse6 .cse7 .cse20 .cse8) (and .cse0 .cse1 .cse9 .cse3 .cse10 .cse6 .cse7 .cse20 .cse8) (and .cse1 .cse15 .cse16 .cse2 (= ~c_dr_pc~0 ~q_req_up~0) .cse17 .cse18 .cse10 .cse19 .cse6 .cse20)))) [2021-01-06 19:24:54,861 INFO L185 CegarLoopUtils]: At program point L109(lines 83 111) the Hoare annotation is: (let ((.cse4 (= ~c_dr_st~0 0)) (.cse0 (= ~q_read_ev~0 2)) (.cse1 (= ULTIMATE.start_activate_threads_~tmp~1 0)) (.cse9 (= ~p_dw_st~0 0)) (.cse2 (= ~c_dr_pc~0 ~q_req_up~0)) (.cse3 (= ~q_req_up~0 0)) (.cse5 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse6 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0)) (.cse10 (= ~q_req_up~0 ~p_dw_pc~0)) (.cse7 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse8 (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0))) (or (and (= 1 ~c_dr_i~0) .cse0 (= ~q_read_ev~0 ~fast_clk_edge~0) .cse1 .cse2 .cse3 (= ~t~0 0) .cse4 .cse5 .cse6 .cse7 .cse8 (= ~p_dw_i~0 1) .cse9 (= ~slow_clk_edge~0 ~q_read_ev~0) .cse10 (= ~q_write_ev~0 ~q_read_ev~0)) (and (not .cse4) .cse0 .cse1 (not .cse9) .cse2 .cse3 .cse5 .cse6 .cse10 .cse7 .cse8))) [2021-01-06 19:24:54,861 INFO L185 CegarLoopUtils]: At program point L109-1(lines 83 111) the Hoare annotation is: (let ((.cse14 (not (= ~q_write_ev~0 1))) (.cse0 (= 1 ~c_dr_i~0)) (.cse1 (not (= ~slow_clk_edge~0 1))) (.cse11 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse9 (= ~p_dw_i~0 1)) (.cse10 (= ~c_dr_pc~0 1)) (.cse12 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse13 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse5 (not (= ~q_write_ev~0 0))) (.cse8 (not (= ~fast_clk_edge~0 1))) (.cse2 (not (= ~c_dr_st~0 0))) (.cse16 (= ~q_read_ev~0 2)) (.cse17 (= ULTIMATE.start_activate_threads_~tmp~1 0)) (.cse3 (not (= ~p_dw_st~0 0))) (.cse4 (= ~q_req_up~0 0)) (.cse18 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse6 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0)) (.cse19 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse7 (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0)) (.cse15 (not (= ~p_dw_pc~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10) (and .cse0 .cse1 .cse11 .cse6 .cse7 .cse9 .cse10 .cse2 .cse12 .cse13 .cse5 .cse8 .cse14 .cse15) (and .cse0 .cse1 .cse2 .cse3 .cse5 .cse6 .cse8 .cse7 .cse14 .cse9 .cse10) (and (not .cse10) .cse2 .cse16 .cse17 .cse3 .cse5 .cse4 .cse18 .cse6 .cse19 .cse7 .cse15) (and .cse0 .cse1 .cse11 .cse4 .cse6 .cse7 .cse9 .cse10 .cse2 .cse12 .cse13 .cse5 .cse8 .cse15) (and .cse2 .cse16 .cse17 .cse3 (= ~c_dr_pc~0 ~q_req_up~0) .cse4 .cse18 .cse6 .cse19 .cse7 .cse15))) [2021-01-06 19:24:54,862 INFO L185 CegarLoopUtils]: At program point L109-2(lines 83 111) the Hoare annotation is: (let ((.cse18 (= ~p_dw_st~0 0))) (let ((.cse13 (= ~q_read_ev~0 2)) (.cse14 (= ULTIMATE.start_activate_threads_~tmp~1 0)) (.cse15 (= ~q_req_up~0 0)) (.cse16 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse17 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse4 (= ~t~0 0)) (.cse12 (not (= ~p_dw_pc~0 1))) (.cse2 (not .cse18)) (.cse5 (not (= ~fast_clk_edge~0 1))) (.cse0 (= 1 ~c_dr_i~0)) (.cse9 (not (= ~slow_clk_edge~0 1))) (.cse20 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse10 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0)) (.cse11 (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0)) (.cse7 (= ~p_dw_i~0 1)) (.cse8 (= ~c_dr_pc~0 1)) (.cse1 (not (= ~c_dr_st~0 0))) (.cse19 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse21 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse3 (not (= ~q_write_ev~0 0))) (.cse6 (not (= ~q_write_ev~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8) (and .cse0 .cse9 .cse1 .cse3 .cse10 .cse11 .cse6 .cse7 .cse12 .cse8) (and .cse13 .cse14 .cse2 .cse15 .cse16 .cse10 .cse17 .cse11 (not .cse8) .cse1 .cse3 .cse6 .cse12) (and .cse0 .cse1 .cse18 .cse19 .cse20 .cse21 .cse3 .cse4 .cse6 .cse7 .cse8) (and .cse1 .cse13 .cse14 .cse2 (= ~c_dr_pc~0 ~q_req_up~0) .cse15 .cse16 .cse10 .cse17 .cse11 .cse6 .cse12) (and .cse0 .cse1 .cse3 .cse4 .cse6 .cse7 .cse12 .cse8) (and .cse0 .cse9 .cse1 .cse2 .cse3 .cse10 .cse5 .cse11 .cse6 .cse7 .cse8) (and .cse0 .cse9 .cse20 .cse10 .cse11 .cse7 .cse8 .cse1 .cse19 .cse18 .cse21 .cse3 .cse6)))) [2021-01-06 19:24:54,862 INFO L189 CegarLoopUtils]: For program point L407(lines 407 411) no Hoare annotation was computed. [2021-01-06 19:24:54,862 INFO L189 CegarLoopUtils]: For program point L407-1(lines 402 442) no Hoare annotation was computed. [2021-01-06 19:24:54,862 INFO L189 CegarLoopUtils]: For program point L341(lines 341 348) no Hoare annotation was computed. [2021-01-06 19:24:54,862 INFO L185 CegarLoopUtils]: At program point L308-1(lines 299 316) the Hoare annotation is: (let ((.cse1 (= ~q_read_ev~0 2)) (.cse2 (= ~p_dw_st~0 0)) (.cse3 (= ~c_dr_pc~0 ~q_req_up~0)) (.cse4 (= ~q_req_up~0 0)) (.cse0 (= ~c_dr_st~0 0)) (.cse5 (= ~q_req_up~0 ~p_dw_pc~0))) (or (and (not .cse0) .cse1 (not .cse2) .cse3 .cse4 .cse5) (and (= 1 ~c_dr_i~0) .cse1 (= ~q_read_ev~0 ~fast_clk_edge~0) .cse2 (= ~slow_clk_edge~0 ~q_read_ev~0) .cse3 .cse4 (= ~t~0 0) .cse0 .cse5 (= ~p_dw_i~0 1) (= ~q_write_ev~0 ~q_read_ev~0)))) [2021-01-06 19:24:54,862 INFO L185 CegarLoopUtils]: At program point L341-2(lines 337 352) the Hoare annotation is: (let ((.cse2 (= ~q_read_ev~0 2)) (.cse5 (= ~q_req_up~0 0)) (.cse9 (= ~t~0 0)) (.cse3 (not (= ~p_dw_st~0 0))) (.cse11 (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0))) (.cse8 (= 1 ~c_dr_i~0)) (.cse16 (not (= ~slow_clk_edge~0 1))) (.cse12 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse13 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse10 (= ~p_dw_i~0 1)) (.cse0 (= ~c_dr_pc~0 1)) (.cse1 (not (= ~c_dr_st~0 0))) (.cse14 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse15 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse4 (not (= ~q_write_ev~0 0))) (.cse6 (not (= ~q_write_ev~0 1))) (.cse7 (not (= ~p_dw_pc~0 1)))) (or (and (not .cse0) .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7) (and .cse1 .cse2 .cse3 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse5 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse6 .cse7) (and .cse8 .cse1 .cse3 .cse4 .cse9 .cse6 .cse10 .cse0) (and .cse11 .cse8 .cse12 .cse13 .cse9 .cse10 .cse0 .cse1 .cse14 .cse15 .cse4 .cse6 .cse7) (and .cse8 .cse16 .cse1 .cse3 .cse4 .cse6 .cse10 .cse0) (and .cse11 .cse8 .cse16 .cse12 .cse13 .cse10 .cse0 .cse1 .cse14 .cse15 .cse4 .cse6 .cse7))) [2021-01-06 19:24:54,863 INFO L185 CegarLoopUtils]: At program point L308-3(lines 299 316) the Hoare annotation is: (let ((.cse6 (not (= ~q_write_ev~0 1))) (.cse0 (= 1 ~c_dr_i~0)) (.cse1 (not (= ~slow_clk_edge~0 1))) (.cse4 (not (= ~q_write_ev~0 0))) (.cse5 (not (= ~fast_clk_edge~0 1))) (.cse7 (= ~p_dw_i~0 1)) (.cse8 (= ~c_dr_pc~0 1)) (.cse2 (not (= ~c_dr_st~0 0))) (.cse9 (= ~q_read_ev~0 2)) (.cse3 (not (= ~p_dw_st~0 0))) (.cse10 (= ~q_req_up~0 0)) (.cse11 (not (= ~p_dw_pc~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8) (and (not .cse8) .cse2 .cse9 .cse3 .cse4 .cse10 .cse6 .cse11) (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse10 .cse5 .cse7 .cse8) (and .cse2 .cse9 .cse3 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse10 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse11))) [2021-01-06 19:24:54,863 INFO L189 CegarLoopUtils]: For program point L11(line 11) no Hoare annotation was computed. [2021-01-06 19:24:54,863 INFO L189 CegarLoopUtils]: For program point L11-1(line 11) no Hoare annotation was computed. [2021-01-06 19:24:54,863 INFO L189 CegarLoopUtils]: For program point L210-1(lines 210 220) no Hoare annotation was computed. [2021-01-06 19:24:54,863 INFO L189 CegarLoopUtils]: For program point L144(lines 144 152) no Hoare annotation was computed. [2021-01-06 19:24:54,863 INFO L185 CegarLoopUtils]: At program point L12-1(lines 190 244) the Hoare annotation is: (let ((.cse16 (= ~p_dw_st~0 0))) (let ((.cse4 (not .cse16)) (.cse3 (= ~q_read_ev~0 2)) (.cse7 (= ~q_req_up~0 0)) (.cse10 (= ~p_dw_pc~0 1)) (.cse0 (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0))) (.cse1 (= 1 ~c_dr_i~0)) (.cse2 (not (= ~slow_clk_edge~0 1))) (.cse5 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse6 (= ~t~0 0)) (.cse8 (= ~p_dw_i~0 1)) (.cse15 (= ~c_dr_pc~0 1)) (.cse9 (not (= ~c_dr_st~0 0))) (.cse11 (not (= ~q_write_ev~0 0))) (.cse12 (not (= ~fast_clk_edge~0 1))) (.cse13 (not (= ~q_write_ev~0 1))) (.cse14 (not (= ULTIMATE.start_eval_~tmp___1~0 0)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10 .cse11 .cse12 .cse13 .cse14) (and .cse0 .cse1 .cse2 .cse4 .cse5 .cse6 .cse8 .cse15 .cse9 .cse11 .cse12 .cse13 .cse14) (and .cse0 .cse1 .cse3 (= ~q_read_ev~0 ~fast_clk_edge~0) (= ULTIMATE.start_activate_threads_~tmp~1 0) .cse5 .cse6 .cse7 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0) (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|) .cse8 .cse9 .cse16 (= ~slow_clk_edge~0 ~q_read_ev~0) (= ~q_req_up~0 ~p_dw_pc~0) (= ~q_write_ev~0 ~q_read_ev~0) .cse14) (and .cse0 .cse1 .cse2 .cse5 .cse6 .cse8 .cse15 .cse9 .cse11 .cse12 .cse13 .cse14 (not .cse10)) (and .cse0 .cse1 .cse2 (= ULTIMATE.start_activate_threads_~tmp~1 1) .cse5 .cse6 .cse8 .cse15 .cse9 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1) (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|) .cse11 .cse12 .cse13 .cse14)))) [2021-01-06 19:24:54,863 INFO L185 CegarLoopUtils]: At program point L145(lines 140 184) the Hoare annotation is: (let ((.cse0 (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0))) (.cse1 (= 1 ~c_dr_i~0)) (.cse2 (not (= ~slow_clk_edge~0 1))) (.cse3 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse4 (not (= ~p_dw_st~0 0))) (.cse5 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse6 (= ~p_dw_i~0 1)) (.cse7 (= ~c_dr_pc~0 1)) (.cse8 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse9 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse10 (= ~p_dw_pc~0 1)) (.cse11 (not (= ~q_write_ev~0 0))) (.cse12 (not (= ~fast_clk_edge~0 1))) (.cse13 (not (= ~q_write_ev~0 1))) (.cse14 (not (= ULTIMATE.start_eval_~tmp___1~0 0)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 (= ~t~0 0) .cse6 .cse7 .cse8 .cse9 .cse10 .cse11 .cse12 .cse13 .cse14) (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 (not (= ~c_dr_st~0 0)) .cse8 .cse9 .cse10 .cse11 .cse12 .cse13 .cse14))) [2021-01-06 19:24:54,863 INFO L185 CegarLoopUtils]: At program point L79(lines 57 81) the Hoare annotation is: (let ((.cse3 (= ~c_dr_st~0 0)) (.cse0 (= ~q_read_ev~0 2)) (.cse5 (= ~p_dw_st~0 0)) (.cse1 (= ~c_dr_pc~0 ~q_req_up~0)) (.cse2 (= ~q_req_up~0 0)) (.cse4 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse6 (= ~q_req_up~0 ~p_dw_pc~0))) (or (and (= 1 ~c_dr_i~0) .cse0 (= ~q_read_ev~0 ~fast_clk_edge~0) .cse1 .cse2 (= ~t~0 0) .cse3 .cse4 (= ~p_dw_i~0 1) .cse5 (= ~slow_clk_edge~0 ~q_read_ev~0) .cse6 (= ~q_write_ev~0 ~q_read_ev~0)) (and (not .cse3) .cse0 (not .cse5) .cse1 .cse2 .cse4 .cse6))) [2021-01-06 19:24:54,864 INFO L185 CegarLoopUtils]: At program point L79-1(lines 57 81) the Hoare annotation is: (let ((.cse3 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse13 (= ~q_read_ev~0 2)) (.cse6 (= ~q_req_up~0 0)) (.cse9 (not (= ~p_dw_pc~0 1))) (.cse0 (= 1 ~c_dr_i~0)) (.cse1 (not (= ~slow_clk_edge~0 1))) (.cse2 (not (= ~c_dr_st~0 0))) (.cse4 (not (= ~p_dw_st~0 0))) (.cse5 (not (= ~q_write_ev~0 0))) (.cse11 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse7 (not (= ~fast_clk_edge~0 1))) (.cse12 (not (= ~q_write_ev~0 1))) (.cse8 (= ~p_dw_i~0 1)) (.cse10 (= ~c_dr_pc~0 1))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10) (and .cse0 .cse1 .cse2 .cse4 .cse5 .cse6 .cse11 .cse7 .cse8 .cse10) (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse7 .cse12 .cse8 .cse9 .cse10) (and (not .cse10) .cse2 .cse13 .cse4 .cse5 .cse6 .cse11 .cse12 .cse9) (and .cse2 .cse13 .cse4 (= ~c_dr_pc~0 ~q_req_up~0) .cse6 .cse11 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse9) (and .cse0 .cse1 .cse2 .cse4 .cse5 .cse11 .cse7 .cse12 .cse8 .cse10))) [2021-01-06 19:24:54,864 INFO L185 CegarLoopUtils]: At program point L79-2(lines 57 81) the Hoare annotation is: (let ((.cse16 (not (= ~fast_clk_edge~0 1))) (.cse13 (not (= ~slow_clk_edge~0 1))) (.cse11 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse10 (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0))) (.cse0 (= 1 ~c_dr_i~0)) (.cse12 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse3 (not (= ~q_write_ev~0 0))) (.cse4 (= ~t~0 0)) (.cse7 (= ~p_dw_i~0 1)) (.cse9 (= ~c_dr_pc~0 1)) (.cse1 (not (= ~c_dr_st~0 0))) (.cse14 (= ~q_read_ev~0 2)) (.cse2 (not (= ~p_dw_st~0 0))) (.cse15 (= ~q_req_up~0 0)) (.cse5 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse6 (not (= ~q_write_ev~0 1))) (.cse8 (not (= ~p_dw_pc~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9) (and (or (and .cse10 .cse0 .cse1 .cse11 .cse12 .cse3 .cse4 .cse6 .cse7 .cse8) (and .cse0 .cse1 .cse11 .cse2 .cse3 .cse4 .cse6 .cse7)) .cse9) (and .cse10 .cse0 .cse13 .cse1 .cse11 .cse12 .cse3 .cse6 .cse7 .cse8 .cse9) (and .cse10 .cse0 .cse13 .cse1 .cse12 .cse3 .cse5 .cse6 .cse7 .cse8 .cse9) (and (not .cse9) .cse1 .cse14 .cse2 .cse3 .cse15 .cse5 .cse6 .cse8) (and .cse0 .cse13 .cse1 .cse2 .cse3 .cse5 .cse6 .cse7 .cse8 .cse9) (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse16 .cse6 .cse7 .cse9) (and .cse0 .cse13 .cse1 .cse2 .cse3 .cse5 .cse16 .cse6 .cse7 .cse9) (and .cse0 .cse13 .cse1 .cse11 .cse2 .cse3 .cse6 .cse7 .cse9) (and .cse10 .cse0 .cse1 .cse12 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9) (and .cse1 .cse14 .cse2 (= ~c_dr_pc~0 ~q_req_up~0) .cse15 .cse5 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse6 .cse8))) [2021-01-06 19:24:54,864 INFO L185 CegarLoopUtils]: At program point L443(lines 396 448) the Hoare annotation is: (let ((.cse4 (= ~c_dr_pc~0 1)) (.cse2 (not (= ~q_write_ev~0 0))) (.cse0 (not (= ~c_dr_st~0 0))) (.cse5 (= ~q_read_ev~0 2)) (.cse1 (not (= ~p_dw_st~0 0))) (.cse6 (= ~q_req_up~0 0)) (.cse3 (not (= ~q_write_ev~0 1))) (.cse7 (not (= ~p_dw_pc~0 1)))) (or (and (= 1 ~c_dr_i~0) (not (= ~slow_clk_edge~0 1)) .cse0 .cse1 .cse2 (not (= ~fast_clk_edge~0 1)) .cse3 (= ~p_dw_i~0 1) .cse4) (and (not .cse4) .cse0 .cse5 .cse1 .cse2 .cse6 .cse3 .cse7) (and .cse0 .cse5 .cse1 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse6 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse3 .cse7))) [2021-01-06 19:24:54,864 INFO L185 CegarLoopUtils]: At program point L80(lines 54 82) the Hoare annotation is: (let ((.cse1 (= ~q_read_ev~0 2)) (.cse3 (= ~c_dr_pc~0 ~q_req_up~0)) (.cse4 (= ~q_req_up~0 0)) (.cse0 (= ~c_dr_st~0 0)) (.cse5 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse7 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse2 (= ~p_dw_st~0 0)) (.cse6 (= ~q_req_up~0 ~p_dw_pc~0))) (or (and (not .cse0) .cse1 (not .cse2) .cse3 .cse4 .cse5 .cse6 .cse7) (and (= 1 ~c_dr_i~0) .cse1 (= ~q_read_ev~0 ~fast_clk_edge~0) .cse3 .cse4 (= ~t~0 0) .cse0 .cse5 .cse7 (= ~p_dw_i~0 1) .cse2 (= ~slow_clk_edge~0 ~q_read_ev~0) .cse6 (= ~q_write_ev~0 ~q_read_ev~0)))) [2021-01-06 19:24:54,864 INFO L185 CegarLoopUtils]: At program point L80-1(lines 54 82) the Hoare annotation is: (let ((.cse0 (= 1 ~c_dr_i~0)) (.cse1 (not (= ~slow_clk_edge~0 1))) (.cse3 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse5 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse8 (not (= ~fast_clk_edge~0 1))) (.cse9 (= ~p_dw_i~0 1)) (.cse11 (= ~c_dr_pc~0 1)) (.cse2 (not (= ~c_dr_st~0 0))) (.cse15 (= ~q_read_ev~0 2)) (.cse4 (not (= ~p_dw_st~0 0))) (.cse6 (not (= ~q_write_ev~0 0))) (.cse7 (= ~q_req_up~0 0)) (.cse12 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse13 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse14 (not (= ~q_write_ev~0 1))) (.cse10 (not (= ~p_dw_pc~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10 .cse11) (and .cse0 .cse1 .cse2 .cse4 .cse7 .cse6 .cse12 .cse13 .cse8 .cse9 .cse11) (and .cse0 .cse1 .cse2 .cse4 .cse6 .cse12 .cse8 .cse13 .cse14 .cse9 .cse11) (and .cse2 .cse15 .cse4 (= ~c_dr_pc~0 ~q_req_up~0) .cse7 .cse12 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) .cse13 (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse10) (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse8 .cse14 .cse9 .cse10 .cse11) (and (not .cse11) .cse2 .cse15 .cse4 .cse6 .cse7 .cse12 .cse13 .cse14 .cse10))) [2021-01-06 19:24:54,865 INFO L185 CegarLoopUtils]: At program point L80-2(lines 54 82) the Hoare annotation is: (let ((.cse4 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse5 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse0 (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0))) (.cse2 (not (= ~slow_clk_edge~0 1))) (.cse6 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse13 (= ~q_read_ev~0 2)) (.cse14 (= ~q_req_up~0 0)) (.cse10 (not (= ~p_dw_pc~0 1))) (.cse1 (= 1 ~c_dr_i~0)) (.cse3 (not (= ~c_dr_st~0 0))) (.cse11 (not (= ~p_dw_st~0 0))) (.cse7 (not (= ~q_write_ev~0 0))) (.cse17 (= ~t~0 0)) (.cse15 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse18 (not (= ~fast_clk_edge~0 1))) (.cse16 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse8 (not (= ~q_write_ev~0 1))) (.cse9 (= ~p_dw_i~0 1)) (.cse12 (= ~c_dr_pc~0 1))) (or (and (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10) (and .cse1 .cse2 .cse3 .cse4 .cse11 .cse5 .cse7 .cse8 .cse9)) .cse12) (and .cse3 .cse13 .cse11 (= ~c_dr_pc~0 ~q_req_up~0) .cse14 .cse15 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) .cse16 (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse8 .cse10) (and .cse1 .cse2 .cse3 .cse11 .cse7 .cse15 .cse16 .cse8 .cse9 .cse10 .cse12) (and (or (and .cse0 .cse1 .cse3 .cse4 .cse5 .cse6 .cse7 .cse17 .cse8 .cse9 .cse10) (and .cse1 .cse3 .cse4 .cse11 .cse5 .cse7 .cse17 .cse8 .cse9)) .cse12) (and .cse0 .cse1 .cse3 .cse6 .cse7 .cse17 .cse15 .cse16 .cse8 .cse9 .cse10 .cse12) (and .cse1 .cse2 .cse3 .cse11 .cse7 .cse15 .cse18 .cse16 .cse8 .cse9 .cse12) (and .cse0 .cse1 .cse2 .cse3 .cse6 .cse7 .cse15 .cse16 .cse8 .cse9 .cse10 .cse12) (and .cse1 .cse3 .cse11 .cse7 .cse17 .cse15 .cse16 .cse8 .cse9 .cse10 .cse12) (and (not .cse12) .cse3 .cse13 .cse11 .cse7 .cse14 .cse15 .cse16 .cse8 .cse10) (and .cse1 .cse3 .cse11 .cse7 .cse17 .cse15 .cse18 .cse16 .cse8 .cse9 .cse12))) [2021-01-06 19:24:54,865 INFO L185 CegarLoopUtils]: At program point L543(lines 527 545) the Hoare annotation is: (and (= 1 ~c_dr_i~0) (= ~q_read_ev~0 2) (= ~q_read_ev~0 ~fast_clk_edge~0) (= ~p_dw_st~0 0) (= ~slow_clk_edge~0 ~q_read_ev~0) (= ~c_dr_pc~0 ~q_req_up~0) (= ~q_req_up~0 0) (= ~t~0 0) (= ~c_dr_st~0 0) (= ~q_req_up~0 ~p_dw_pc~0) (= ~p_dw_i~0 1) (= ~q_write_ev~0 ~q_read_ev~0)) [2021-01-06 19:24:54,865 INFO L189 CegarLoopUtils]: For program point L147(lines 147 151) no Hoare annotation was computed. [2021-01-06 19:24:54,865 INFO L185 CegarLoopUtils]: At program point L412(lines 402 442) the Hoare annotation is: (let ((.cse22 (= ~p_dw_pc~0 1)) (.cse28 (= ~p_dw_st~0 0)) (.cse19 (= ~c_dr_st~0 0))) (let ((.cse12 (= ~q_read_ev~0 ~fast_clk_edge~0)) (.cse14 (= ULTIMATE.start_activate_threads_~tmp___0~1 0)) (.cse13 (= ~c_dr_pc~0 ~q_req_up~0)) (.cse18 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0)) (.cse20 (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0)) (.cse21 (= ~slow_clk_edge~0 ~q_read_ev~0)) (.cse23 (= ~q_write_ev~0 ~q_read_ev~0)) (.cse25 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse26 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse27 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse17 (= ~t~0 0)) (.cse10 (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0))) (.cse0 (= 1 ~c_dr_i~0)) (.cse2 (not (= ~slow_clk_edge~0 1))) (.cse15 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse5 (not (= ~fast_clk_edge~0 1))) (.cse7 (= ~p_dw_i~0 1)) (.cse9 (= ~c_dr_pc~0 1)) (.cse1 (not .cse19)) (.cse11 (= ~q_read_ev~0 2)) (.cse3 (not .cse28)) (.cse4 (not (= ~q_write_ev~0 0))) (.cse16 (= ~q_req_up~0 0)) (.cse6 (not (= ~q_write_ev~0 1))) (.cse8 (not (= ULTIMATE.start_eval_~tmp___1~0 0))) (.cse24 (not .cse22))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9) (and .cse10 .cse0 .cse11 .cse12 .cse3 .cse13 .cse14 .cse15 .cse16 .cse17 .cse18 .cse19 .cse20 .cse7 .cse21 .cse22 .cse23 .cse8) (and .cse1 .cse11 .cse3 .cse13 .cse14 .cse16 .cse18 .cse20 .cse6 .cse24) (and .cse10 .cse0 .cse2 .cse25 .cse15 .cse17 .cse7 .cse9 .cse26 .cse27 .cse4 .cse5 .cse6 .cse8) (and .cse10 .cse0 .cse11 (= ULTIMATE.start_activate_threads_~tmp~1 0) .cse12 .cse14 .cse15 .cse13 .cse17 .cse16 .cse19 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0) .cse18 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|) .cse20 .cse7 .cse28 .cse21 (= ~q_req_up~0 ~p_dw_pc~0) .cse23 .cse8) (and .cse10 .cse0 .cse2 .cse25 .cse15 .cse7 .cse9 .cse1 .cse26 .cse27 .cse4 .cse5 .cse6 .cse8) (and .cse10 .cse0 .cse2 .cse15 .cse17 .cse4 .cse5 .cse6 .cse7 .cse8 .cse24 .cse9) (and .cse10 .cse0 .cse2 .cse3 .cse15 .cse17 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9) (and .cse10 .cse0 .cse2 .cse1 .cse15 .cse4 .cse5 .cse6 .cse7 .cse8 .cse24 .cse9) (and (not .cse9) .cse1 .cse11 .cse3 .cse4 .cse16 .cse6 .cse8 .cse24)))) [2021-01-06 19:24:54,865 INFO L189 CegarLoopUtils]: For program point L379(lines 379 383) no Hoare annotation was computed. [2021-01-06 19:24:54,866 INFO L189 CegarLoopUtils]: For program point L379-2(lines 379 383) no Hoare annotation was computed. [2021-01-06 19:24:54,866 INFO L189 CegarLoopUtils]: For program point L379-3(lines 379 383) no Hoare annotation was computed. [2021-01-06 19:24:54,866 INFO L189 CegarLoopUtils]: For program point L379-5(lines 379 383) no Hoare annotation was computed. [2021-01-06 19:24:54,866 INFO L189 CegarLoopUtils]: For program point L379-6(lines 379 383) no Hoare annotation was computed. [2021-01-06 19:24:54,866 INFO L189 CegarLoopUtils]: For program point L379-8(lines 379 383) no Hoare annotation was computed. [2021-01-06 19:24:54,866 INFO L189 CegarLoopUtils]: For program point L283(lines 283 293) no Hoare annotation was computed. [2021-01-06 19:24:54,866 INFO L189 CegarLoopUtils]: For program point L250(lines 250 256) no Hoare annotation was computed. [2021-01-06 19:24:54,866 INFO L189 CegarLoopUtils]: For program point L283-1(lines 283 293) no Hoare annotation was computed. [2021-01-06 19:24:54,866 INFO L185 CegarLoopUtils]: At program point L250-1(lines 265 269) the Hoare annotation is: (and (= 1 ~c_dr_i~0) (= ~q_read_ev~0 2) (= ~q_read_ev~0 ~fast_clk_edge~0) (= ~p_dw_st~0 0) (= ~slow_clk_edge~0 ~q_read_ev~0) (= ~c_dr_pc~0 ~q_req_up~0) (= ~q_req_up~0 0) (= ~t~0 0) (= ~c_dr_st~0 0) (= ~q_req_up~0 ~p_dw_pc~0) (= ~p_dw_i~0 1) (= ~q_write_ev~0 ~q_read_ev~0)) [2021-01-06 19:24:54,866 INFO L189 CegarLoopUtils]: For program point L283-2(lines 283 293) no Hoare annotation was computed. [2021-01-06 19:24:54,866 INFO L189 CegarLoopUtils]: For program point L250-2(lines 250 256) no Hoare annotation was computed. [2021-01-06 19:24:54,867 INFO L185 CegarLoopUtils]: At program point L250-3(lines 246 260) the Hoare annotation is: (let ((.cse4 (not (= ~q_write_ev~0 0))) (.cse9 (= ~q_read_ev~0 2)) (.cse11 (not (= ~p_dw_pc~0 1))) (.cse0 (= 1 ~c_dr_i~0)) (.cse1 (not (= ~slow_clk_edge~0 1))) (.cse2 (not (= ~c_dr_st~0 0))) (.cse3 (not (= ~p_dw_st~0 0))) (.cse10 (= ~q_req_up~0 0)) (.cse5 (not (= ~fast_clk_edge~0 1))) (.cse6 (not (= ~q_write_ev~0 1))) (.cse7 (= ~p_dw_i~0 1)) (.cse8 (= ~c_dr_pc~0 1))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8) (and (not .cse8) .cse2 .cse9 .cse3 .cse4 .cse10 .cse6 .cse11) (and .cse2 .cse9 .cse3 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse10 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse6 .cse11) (and .cse0 .cse1 .cse2 .cse3 .cse10 .cse5 .cse6 .cse7 .cse8))) [2021-01-06 19:24:54,867 INFO L189 CegarLoopUtils]: For program point L515(lines 515 519) no Hoare annotation was computed. [2021-01-06 19:24:54,867 INFO L189 CegarLoopUtils]: For program point L416(lines 416 423) no Hoare annotation was computed. [2021-01-06 19:24:54,867 INFO L189 CegarLoopUtils]: For program point ULTIMATE.startENTRY(line -1) no Hoare annotation was computed. [2021-01-06 19:24:54,867 INFO L185 CegarLoopUtils]: At program point L483-1(lines 317 520) the Hoare annotation is: (let ((.cse20 (= ~c_dr_st~0 0)) (.cse23 (= ~p_dw_st~0 0))) (let ((.cse5 (= ~t~0 0)) (.cse16 (= ~q_read_ev~0 2)) (.cse14 (not .cse23)) (.cse18 (= ~c_dr_pc~0 ~q_req_up~0)) (.cse19 (= ULTIMATE.start_activate_threads_~tmp___0~1 0)) (.cse17 (= ~q_req_up~0 0)) (.cse21 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0)) (.cse22 (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0)) (.cse15 (not (= ~p_dw_pc~0 1))) (.cse0 (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0))) (.cse1 (= 1 ~c_dr_i~0)) (.cse2 (not (= ~slow_clk_edge~0 1))) (.cse3 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse4 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse6 (= ~p_dw_i~0 1)) (.cse7 (= ~c_dr_pc~0 1)) (.cse13 (not .cse20)) (.cse8 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse9 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse10 (not (= ~q_write_ev~0 0))) (.cse11 (not (= ~fast_clk_edge~0 1))) (.cse12 (not (= ~q_write_ev~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10 .cse11 .cse12) (and .cse1 .cse2 .cse13 .cse14 .cse10 .cse11 .cse12 .cse6 .cse7) (and .cse0 .cse1 .cse2 .cse14 .cse4 .cse5 .cse10 .cse11 .cse12 .cse6 .cse7) (and .cse0 .cse1 .cse2 .cse4 .cse10 .cse5 .cse11 .cse12 .cse6 .cse15 .cse7) (and .cse0 .cse1 .cse2 .cse13 .cse4 .cse10 .cse11 .cse12 .cse6 .cse15 .cse7) (and (not .cse7) .cse13 .cse16 .cse14 .cse10 .cse17 .cse12 .cse15) (and .cse1 .cse16 (= ~q_read_ev~0 ~fast_clk_edge~0) (= ULTIMATE.start_activate_threads_~tmp~1 0) .cse18 .cse19 .cse5 .cse17 .cse20 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0) .cse21 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|) .cse22 .cse6 .cse23 (= ~slow_clk_edge~0 ~q_read_ev~0) (= ~q_req_up~0 ~p_dw_pc~0) (= ~q_write_ev~0 ~q_read_ev~0)) (and .cse13 .cse16 .cse14 .cse18 .cse19 .cse17 .cse21 .cse22 .cse12 .cse15) (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse6 .cse7 .cse13 .cse8 .cse9 .cse10 .cse11 .cse12)))) [2021-01-06 19:24:54,867 INFO L189 CegarLoopUtils]: For program point L87(lines 87 96) no Hoare annotation was computed. [2021-01-06 19:24:54,868 INFO L189 CegarLoopUtils]: For program point L87-2(lines 86 110) no Hoare annotation was computed. [2021-01-06 19:24:54,868 INFO L189 CegarLoopUtils]: For program point L87-3(lines 87 96) no Hoare annotation was computed. [2021-01-06 19:24:54,868 INFO L189 CegarLoopUtils]: For program point L87-5(lines 86 110) no Hoare annotation was computed. [2021-01-06 19:24:54,868 INFO L189 CegarLoopUtils]: For program point L87-6(lines 87 96) no Hoare annotation was computed. [2021-01-06 19:24:54,868 INFO L189 CegarLoopUtils]: For program point L87-8(lines 86 110) no Hoare annotation was computed. [2021-01-06 19:24:54,868 INFO L189 CegarLoopUtils]: For program point L484(line 484) no Hoare annotation was computed. [2021-01-06 19:24:54,868 INFO L189 CegarLoopUtils]: For program point L88(lines 88 93) no Hoare annotation was computed. [2021-01-06 19:24:54,868 INFO L189 CegarLoopUtils]: For program point L88-1(lines 88 93) no Hoare annotation was computed. [2021-01-06 19:24:54,868 INFO L189 CegarLoopUtils]: For program point L88-2(lines 88 93) no Hoare annotation was computed. [2021-01-06 19:24:54,869 INFO L189 CegarLoopUtils]: For program point L287(lines 287 292) no Hoare annotation was computed. [2021-01-06 19:24:54,869 INFO L189 CegarLoopUtils]: For program point L287-1(lines 287 292) no Hoare annotation was computed. [2021-01-06 19:24:54,869 INFO L189 CegarLoopUtils]: For program point L287-2(lines 287 292) no Hoare annotation was computed. [2021-01-06 19:24:54,869 INFO L189 CegarLoopUtils]: For program point L387(lines 387 391) no Hoare annotation was computed. [2021-01-06 19:24:54,869 INFO L185 CegarLoopUtils]: At program point L387-2(lines 321 325) the Hoare annotation is: (let ((.cse1 (= ~q_read_ev~0 2)) (.cse2 (= ULTIMATE.start_activate_threads_~tmp~1 0)) (.cse4 (= ~c_dr_pc~0 ~q_req_up~0)) (.cse5 (= ULTIMATE.start_activate_threads_~tmp___0~1 0)) (.cse6 (= ~q_req_up~0 0)) (.cse0 (= ~c_dr_st~0 0)) (.cse7 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse8 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0)) (.cse10 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse11 (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0)) (.cse3 (= ~p_dw_st~0 0)) (.cse9 (= ~q_req_up~0 ~p_dw_pc~0))) (or (and (not .cse0) .cse1 .cse2 (not .cse3) .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10 .cse11) (and (= 1 ~c_dr_i~0) .cse1 (= ~q_read_ev~0 ~fast_clk_edge~0) .cse2 .cse4 .cse5 .cse6 (= ~t~0 0) .cse0 .cse7 .cse8 .cse10 .cse11 (= ~p_dw_i~0 1) .cse3 (= ~slow_clk_edge~0 ~q_read_ev~0) .cse9 (= ~q_write_ev~0 ~q_read_ev~0)))) [2021-01-06 19:24:54,869 INFO L189 CegarLoopUtils]: For program point L321-1(lines 320 333) no Hoare annotation was computed. [2021-01-06 19:24:54,869 INFO L189 CegarLoopUtils]: For program point L387-3(lines 387 391) no Hoare annotation was computed. [2021-01-06 19:24:54,870 INFO L185 CegarLoopUtils]: At program point L387-5(lines 321 325) the Hoare annotation is: (let ((.cse8 (not (= ~q_write_ev~0 1))) (.cse13 (= ~q_read_ev~0 2)) (.cse14 (= ULTIMATE.start_activate_threads_~tmp~1 0)) (.cse16 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse17 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse12 (not (= ~p_dw_st~0 0))) (.cse0 (= 1 ~c_dr_i~0)) (.cse1 (not (= ~slow_clk_edge~0 1))) (.cse2 (not (= ~c_dr_st~0 0))) (.cse3 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse4 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse5 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse15 (= ~q_req_up~0 0)) (.cse6 (not (= ~q_write_ev~0 0))) (.cse7 (not (= ~fast_clk_edge~0 1))) (.cse9 (= ~p_dw_i~0 1)) (.cse10 (not (= ~p_dw_pc~0 1))) (.cse11 (= ~c_dr_pc~0 1))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10 .cse11) (and .cse0 .cse1 .cse2 .cse12 .cse6 .cse7 .cse8 .cse9 .cse11) (and .cse2 .cse13 .cse14 .cse12 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse15 .cse16 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) .cse17 (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse10) (and (not .cse11) .cse2 .cse13 .cse14 .cse12 .cse6 .cse15 .cse16 .cse17 .cse10) (and .cse0 .cse1 .cse2 .cse12 .cse6 .cse15 .cse7 .cse9 .cse11) (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse15 .cse6 .cse7 .cse9 .cse10 .cse11))) [2021-01-06 19:24:54,870 INFO L189 CegarLoopUtils]: For program point L321-3(lines 320 333) no Hoare annotation was computed. [2021-01-06 19:24:54,870 INFO L189 CegarLoopUtils]: For program point L387-6(lines 387 391) no Hoare annotation was computed. [2021-01-06 19:24:54,870 INFO L185 CegarLoopUtils]: At program point L156-1(lines 140 184) the Hoare annotation is: (let ((.cse3 (not (= ~slow_clk_edge~0 1))) (.cse6 (not (= ~q_write_ev~0 0))) (.cse7 (not (= ~fast_clk_edge~0 1))) (.cse8 (not (= ~q_write_ev~0 1))) (.cse11 (= ~c_dr_pc~0 1)) (.cse0 (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0))) (.cse1 (= 1 ~c_dr_i~0)) (.cse4 (not (= ~p_dw_st~0 0))) (.cse5 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse12 (= ~t~0 0)) (.cse2 (= ~c_dr_st~0 0)) (.cse9 (= ~p_dw_i~0 1)) (.cse10 (not (= ULTIMATE.start_eval_~tmp___1~0 0)))) (or (and .cse0 .cse1 (not .cse2) .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10 .cse11) (and .cse0 .cse1 .cse3 .cse4 .cse5 .cse12 .cse6 .cse7 .cse8 .cse9 .cse10 .cse11) (and .cse0 .cse1 (= ~q_read_ev~0 2) (= ~q_read_ev~0 ~fast_clk_edge~0) .cse4 .cse5 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse12 (= ~q_req_up~0 0) .cse2 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse9 (= ~slow_clk_edge~0 ~q_read_ev~0) (= ~q_write_ev~0 ~q_read_ev~0) .cse10 (not (= ~p_dw_pc~0 1))))) [2021-01-06 19:24:54,870 INFO L185 CegarLoopUtils]: At program point L387-8(lines 357 361) the Hoare annotation is: (let ((.cse3 (= ~p_dw_st~0 0))) (let ((.cse2 (not (= ~slow_clk_edge~0 1))) (.cse4 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse5 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse6 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse12 (not (= ~fast_clk_edge~0 1))) (.cse0 (= 1 ~c_dr_i~0)) (.cse14 (= ~t~0 0)) (.cse9 (= ~p_dw_i~0 1)) (.cse10 (= ~c_dr_pc~0 1)) (.cse1 (not (= ~c_dr_st~0 0))) (.cse15 (= ~q_read_ev~0 2)) (.cse16 (= ULTIMATE.start_activate_threads_~tmp~1 0)) (.cse11 (not .cse3)) (.cse7 (not (= ~q_write_ev~0 0))) (.cse17 (= ~q_req_up~0 0)) (.cse18 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0)) (.cse19 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse8 (not (= ~q_write_ev~0 1))) (.cse13 (not (= ~p_dw_pc~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10) (and .cse0 .cse2 .cse1 .cse11 .cse7 .cse12 .cse8 .cse9 .cse10) (and .cse0 .cse2 .cse1 .cse7 .cse8 .cse9 .cse13 .cse10) (and .cse0 .cse3 .cse4 .cse5 .cse6 .cse7 .cse14 .cse8 .cse9 .cse10) (and .cse15 .cse16 .cse11 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse17 .cse18 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) .cse19 (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse1 .cse8 .cse13) (and .cse0 .cse11 .cse7 .cse14 .cse12 .cse8 .cse9 .cse10) (and .cse0 .cse7 .cse14 .cse8 .cse9 .cse13 .cse10) (and (not .cse10) .cse1 .cse15 .cse16 .cse11 .cse7 .cse17 .cse18 .cse19 .cse8 .cse13)))) [2021-01-06 19:24:54,871 INFO L189 CegarLoopUtils]: For program point ULTIMATE.startEXIT(line -1) no Hoare annotation was computed. [2021-01-06 19:24:54,871 INFO L189 CegarLoopUtils]: For program point L157(line 157) no Hoare annotation was computed. [2021-01-06 19:24:54,871 INFO L189 CegarLoopUtils]: For program point L58(lines 58 67) no Hoare annotation was computed. [2021-01-06 19:24:54,871 INFO L189 CegarLoopUtils]: For program point L58-2(lines 57 81) no Hoare annotation was computed. [2021-01-06 19:24:54,871 INFO L189 CegarLoopUtils]: For program point L58-3(lines 58 67) no Hoare annotation was computed. [2021-01-06 19:24:54,871 INFO L189 CegarLoopUtils]: For program point L58-5(lines 57 81) no Hoare annotation was computed. [2021-01-06 19:24:54,871 INFO L189 CegarLoopUtils]: For program point L58-6(lines 58 67) no Hoare annotation was computed. [2021-01-06 19:24:54,871 INFO L189 CegarLoopUtils]: For program point L58-8(lines 57 81) no Hoare annotation was computed. [2021-01-06 19:24:54,871 INFO L192 CegarLoopUtils]: At program point L521(lines 468 526) the Hoare annotation is: true [2021-01-06 19:24:54,872 INFO L189 CegarLoopUtils]: For program point L191(lines 191 199) no Hoare annotation was computed. [2021-01-06 19:24:54,872 INFO L189 CegarLoopUtils]: For program point L59(lines 59 64) no Hoare annotation was computed. [2021-01-06 19:24:54,872 INFO L189 CegarLoopUtils]: For program point L59-1(lines 59 64) no Hoare annotation was computed. [2021-01-06 19:24:54,872 INFO L189 CegarLoopUtils]: For program point L59-2(lines 59 64) no Hoare annotation was computed. [2021-01-06 19:24:54,872 INFO L192 CegarLoopUtils]: At program point L555(lines 546 557) the Hoare annotation is: true [2021-01-06 19:24:54,872 INFO L189 CegarLoopUtils]: For program point L357-1(lines 356 369) no Hoare annotation was computed. [2021-01-06 19:24:54,872 INFO L189 CegarLoopUtils]: For program point L457(lines 457 462) no Hoare annotation was computed. [2021-01-06 19:24:54,872 INFO L189 CegarLoopUtils]: For program point L226(lines 226 238) no Hoare annotation was computed. [2021-01-06 19:24:54,872 INFO L189 CegarLoopUtils]: For program point ULTIMATE.startFINAL(line -1) no Hoare annotation was computed. [2021-01-06 19:24:54,872 INFO L189 CegarLoopUtils]: For program point L28(lines 28 32) no Hoare annotation was computed. [2021-01-06 19:24:54,872 INFO L189 CegarLoopUtils]: For program point L28-2(lines 27 42) no Hoare annotation was computed. [2021-01-06 19:24:54,873 INFO L189 CegarLoopUtils]: For program point L28-3(lines 28 32) no Hoare annotation was computed. [2021-01-06 19:24:54,873 INFO L189 CegarLoopUtils]: For program point L28-5(lines 27 42) no Hoare annotation was computed. [2021-01-06 19:24:54,873 INFO L189 CegarLoopUtils]: For program point L227(lines 227 233) no Hoare annotation was computed. [2021-01-06 19:24:54,873 INFO L185 CegarLoopUtils]: At program point L326-3(lines 317 334) the Hoare annotation is: (let ((.cse0 (= 1 ~c_dr_i~0)) (.cse1 (not (= ~slow_clk_edge~0 1))) (.cse4 (not (= ~fast_clk_edge~0 1))) (.cse6 (= ~p_dw_i~0 1)) (.cse8 (= ~c_dr_pc~0 1)) (.cse3 (not (= ~q_write_ev~0 0))) (.cse2 (not (= ~c_dr_st~0 0))) (.cse10 (= ~q_read_ev~0 2)) (.cse9 (not (= ~p_dw_st~0 0))) (.cse11 (= ~q_req_up~0 0)) (.cse5 (not (= ~q_write_ev~0 1))) (.cse7 (not (= ~p_dw_pc~0 1)))) (or (and .cse0 .cse1 .cse2 (= ULTIMATE.start_activate_threads_~tmp~1 1) (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1) (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|) .cse3 .cse4 .cse5 .cse6 .cse7 .cse8) (and .cse0 .cse1 .cse2 .cse9 .cse3 .cse4 .cse5 .cse6 .cse8) (and (not .cse8) .cse2 .cse10 .cse9 .cse3 .cse11 .cse5 .cse7) (and .cse2 .cse10 .cse9 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse11 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse5 .cse7))) [2021-01-06 19:24:54,873 INFO L189 CegarLoopUtils]: For program point L194(lines 194 198) no Hoare annotation was computed. [2021-01-06 19:24:54,873 INFO L185 CegarLoopUtils]: At program point L195(lines 190 244) the Hoare annotation is: false [2021-01-06 19:24:54,874 INFO L185 CegarLoopUtils]: At program point L427(lines 402 442) the Hoare annotation is: (let ((.cse24 (= ~p_dw_pc~0 1)) (.cse27 (= ~p_dw_st~0 0)) (.cse21 (= ~c_dr_st~0 0))) (let ((.cse16 (= ~q_read_ev~0 ~fast_clk_edge~0)) (.cse5 (= ~t~0 0)) (.cse23 (= ~slow_clk_edge~0 ~q_read_ev~0)) (.cse25 (= ~q_write_ev~0 ~q_read_ev~0)) (.cse17 (= ~c_dr_pc~0 ~q_req_up~0)) (.cse18 (= ULTIMATE.start_activate_threads_~tmp___0~1 0)) (.cse20 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0)) (.cse22 (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0)) (.cse0 (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0))) (.cse3 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse4 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse8 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse9 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse1 (= 1 ~c_dr_i~0)) (.cse2 (not (= ~slow_clk_edge~0 1))) (.cse11 (not (= ~fast_clk_edge~0 1))) (.cse6 (= ~p_dw_i~0 1)) (.cse7 (= ~c_dr_pc~0 1)) (.cse26 (not .cse21)) (.cse15 (= ~q_read_ev~0 2)) (.cse14 (not .cse27)) (.cse19 (= ~q_req_up~0 0)) (.cse10 (not (= ~q_write_ev~0 0))) (.cse12 (not (= ~q_write_ev~0 1))) (.cse13 (not .cse24))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10 .cse11 .cse12) (and .cse0 .cse1 .cse2 .cse4 .cse10 .cse5 .cse11 .cse12 .cse6 .cse13 .cse7) (and .cse0 .cse1 .cse2 .cse14 .cse4 .cse10 .cse5 .cse11 .cse12 .cse6 .cse7) (and .cse0 .cse1 .cse15 .cse16 .cse14 .cse17 .cse18 .cse4 .cse19 .cse5 .cse20 .cse21 .cse22 .cse6 .cse23 .cse24 .cse25 (not (= ULTIMATE.start_eval_~tmp___1~0 0))) (and .cse0 .cse1 .cse26 .cse2 .cse4 .cse10 .cse11 .cse12 .cse6 .cse13 .cse7) (and .cse1 .cse15 .cse16 (= ULTIMATE.start_activate_threads_~tmp~1 0) .cse17 .cse18 .cse5 .cse19 .cse21 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0) .cse20 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|) .cse22 .cse6 .cse27 .cse23 (= ~q_req_up~0 ~p_dw_pc~0) .cse25) (and .cse26 .cse15 .cse14 .cse17 .cse18 .cse19 .cse20 .cse22 .cse12 .cse13) (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse6 .cse7 .cse26 .cse8 .cse9 .cse10 .cse11 .cse12) (and .cse1 .cse26 .cse2 .cse14 .cse10 .cse11 .cse12 .cse6 .cse7) (and (not .cse7) .cse26 .cse15 .cse14 .cse19 .cse10 .cse12 .cse13)))) [2021-01-06 19:24:54,874 INFO L185 CegarLoopUtils]: At program point L295(lines 282 297) the Hoare annotation is: (let ((.cse23 (= ~p_dw_st~0 0)) (.cse26 (= ~p_dw_pc~0 1)) (.cse22 (= ~c_dr_st~0 0))) (let ((.cse14 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse15 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse16 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse10 (not .cse22)) (.cse1 (not (= ~slow_clk_edge~0 1))) (.cse4 (not (= ~q_write_ev~0 0))) (.cse6 (not (= ~fast_clk_edge~0 1))) (.cse7 (not (= ~q_write_ev~0 1))) (.cse13 (not .cse26)) (.cse9 (= ~c_dr_pc~0 1)) (.cse0 (= 1 ~c_dr_i~0)) (.cse11 (= ~q_read_ev~0 2)) (.cse21 (= ~q_read_ev~0 ~fast_clk_edge~0)) (.cse2 (not .cse23)) (.cse17 (= ~c_dr_pc~0 ~q_req_up~0)) (.cse18 (= ULTIMATE.start_activate_threads_~tmp___0~1 0)) (.cse3 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse12 (= ~q_req_up~0 0)) (.cse5 (= ~t~0 0)) (.cse19 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0)) (.cse20 (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0)) (.cse8 (= ~p_dw_i~0 1)) (.cse24 (= ~slow_clk_edge~0 ~q_read_ev~0)) (.cse25 (= ~q_write_ev~0 ~q_read_ev~0))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9) (and .cse0 .cse1 .cse10 .cse2 .cse4 .cse6 .cse7 .cse8 .cse9) (and (not .cse9) .cse10 .cse11 .cse2 .cse4 .cse12 .cse7 .cse13) (and .cse0 .cse1 .cse10 .cse14 .cse15 .cse16 .cse3 .cse4 .cse6 .cse7 .cse8 .cse9) (and .cse10 .cse11 .cse2 .cse17 .cse18 .cse12 .cse19 .cse20 .cse7 .cse13) (and .cse0 .cse11 .cse21 (= ULTIMATE.start_activate_threads_~tmp~1 0) .cse17 .cse18 .cse3 .cse5 .cse12 .cse22 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0) .cse19 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|) .cse20 .cse8 .cse23 .cse24 (= ~q_req_up~0 ~p_dw_pc~0) .cse25) (and .cse0 .cse1 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse13 .cse9) (and .cse0 .cse1 .cse14 .cse15 .cse16 .cse3 .cse5 .cse4 .cse6 .cse7 .cse8 .cse9) (and .cse0 .cse10 .cse1 .cse3 .cse4 .cse6 .cse7 .cse8 .cse13 .cse9) (and .cse0 .cse11 .cse21 .cse2 .cse17 .cse18 .cse3 .cse12 .cse5 .cse19 .cse22 .cse20 .cse8 .cse24 .cse26 .cse25 (not (= ULTIMATE.start_eval_~tmp___1~0 0)))))) [2021-01-06 19:24:54,874 INFO L185 CegarLoopUtils]: At program point L295-1(lines 282 297) the Hoare annotation is: (let ((.cse9 (= ~q_read_ev~0 2)) (.cse3 (not (= ~p_dw_st~0 0))) (.cse10 (= ~q_req_up~0 0)) (.cse0 (= 1 ~c_dr_i~0)) (.cse1 (not (= ~slow_clk_edge~0 1))) (.cse7 (= ~p_dw_i~0 1)) (.cse8 (= ~c_dr_pc~0 1)) (.cse2 (not (= ~c_dr_st~0 0))) (.cse4 (not (= ~q_write_ev~0 0))) (.cse5 (not (= ~fast_clk_edge~0 1))) (.cse6 (not (= ~q_write_ev~0 1))) (.cse11 (not (= ~p_dw_pc~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8) (and (not .cse8) .cse2 .cse9 .cse3 .cse4 .cse10 .cse6 .cse11) (and .cse2 .cse9 .cse3 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse10 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse6 .cse11) (and .cse0 .cse1 (= ULTIMATE.start_activate_threads_~tmp~1 1) (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0)) .cse7 .cse8 .cse2 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1) (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|) .cse4 .cse5 .cse6 .cse11))) [2021-01-06 19:24:54,875 INFO L185 CegarLoopUtils]: At program point L295-2(lines 282 297) the Hoare annotation is: (let ((.cse14 (= ~q_read_ev~0 2)) (.cse2 (not (= ~p_dw_st~0 0))) (.cse15 (= ~q_req_up~0 0)) (.cse11 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse12 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse13 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse5 (= ~t~0 0)) (.cse0 (= 1 ~c_dr_i~0)) (.cse1 (not (= ~slow_clk_edge~0 1))) (.cse10 (not (= ~c_dr_st~0 0))) (.cse3 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse4 (not (= ~q_write_ev~0 0))) (.cse6 (not (= ~fast_clk_edge~0 1))) (.cse7 (not (= ~q_write_ev~0 1))) (.cse8 (= ~p_dw_i~0 1)) (.cse9 (= ~c_dr_pc~0 1)) (.cse16 (not (= ~p_dw_pc~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9) (and .cse0 .cse1 .cse10 .cse2 .cse4 .cse6 .cse7 .cse8 .cse9) (and .cse0 .cse1 .cse10 .cse11 .cse12 .cse13 .cse3 .cse4 .cse6 .cse7 .cse8 .cse9) (and (not .cse9) .cse10 .cse14 .cse2 .cse4 .cse15 .cse7 .cse16) (and .cse10 .cse14 .cse2 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse15 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse7 .cse16) (and .cse0 .cse1 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse16 .cse9) (and .cse0 .cse1 .cse11 .cse12 .cse13 .cse3 .cse5 .cse4 .cse6 .cse7 .cse8 .cse9) (and .cse0 .cse1 .cse10 .cse3 .cse4 .cse6 .cse7 .cse8 .cse9 .cse16))) [2021-01-06 19:24:54,875 INFO L185 CegarLoopUtils]: At program point L163(lines 140 184) the Hoare annotation is: (let ((.cse0 (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0))) (.cse1 (= 1 ~c_dr_i~0)) (.cse2 (not (= ~slow_clk_edge~0 1))) (.cse3 (not (= ~p_dw_st~0 0))) (.cse4 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse5 (not (= ~q_write_ev~0 0))) (.cse6 (not (= ~fast_clk_edge~0 1))) (.cse7 (not (= ~q_write_ev~0 1))) (.cse8 (= ~p_dw_i~0 1)) (.cse9 (not (= ULTIMATE.start_eval_~tmp___1~0 0))) (.cse10 (= ~c_dr_pc~0 1))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 (= ~t~0 0) .cse5 .cse6 .cse7 .cse8 .cse9 .cse10) (and .cse0 .cse1 .cse2 (not (= ~c_dr_st~0 0)) .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10))) [2021-01-06 19:24:54,875 INFO L189 CegarLoopUtils]: For program point L97-1(lines 97 106) no Hoare annotation was computed. [2021-01-06 19:24:54,875 INFO L189 CegarLoopUtils]: For program point L97-3(lines 97 106) no Hoare annotation was computed. [2021-01-06 19:24:54,875 INFO L189 CegarLoopUtils]: For program point L97-5(lines 97 106) no Hoare annotation was computed. [2021-01-06 19:24:54,876 INFO L185 CegarLoopUtils]: At program point L296(lines 279 298) the Hoare annotation is: (let ((.cse22 (= ~c_dr_st~0 0)) (.cse25 (= ~p_dw_pc~0 1)) (.cse27 (= ~p_dw_st~0 0))) (let ((.cse14 (not .cse27)) (.cse15 (not .cse25)) (.cse2 (not (= ~slow_clk_edge~0 1))) (.cse3 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse7 (= ~c_dr_pc~0 1)) (.cse13 (not .cse22)) (.cse8 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse9 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse10 (not (= ~q_write_ev~0 0))) (.cse11 (not (= ~fast_clk_edge~0 1))) (.cse12 (not (= ~q_write_ev~0 1))) (.cse0 (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0))) (.cse1 (= 1 ~c_dr_i~0)) (.cse16 (= ~q_read_ev~0 2)) (.cse17 (= ~q_read_ev~0 ~fast_clk_edge~0)) (.cse18 (= ~c_dr_pc~0 ~q_req_up~0)) (.cse19 (= ULTIMATE.start_activate_threads_~tmp___0~1 0)) (.cse4 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse20 (= ~q_req_up~0 0)) (.cse5 (= ~t~0 0)) (.cse21 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0)) (.cse23 (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0)) (.cse6 (= ~p_dw_i~0 1)) (.cse24 (= ~slow_clk_edge~0 ~q_read_ev~0)) (.cse26 (= ~q_write_ev~0 ~q_read_ev~0))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10 .cse11 .cse12) (and .cse1 .cse2 .cse13 .cse14 .cse10 .cse11 .cse12 .cse6 .cse7) (and .cse0 .cse1 .cse2 .cse4 .cse10 .cse5 .cse11 .cse12 .cse6 .cse15 .cse7) (and .cse0 .cse1 .cse2 .cse14 .cse4 .cse10 .cse5 .cse11 .cse12 .cse6 .cse7) (and .cse0 .cse1 .cse16 .cse17 .cse14 .cse18 .cse19 .cse4 .cse20 .cse5 .cse21 .cse22 .cse23 .cse6 .cse24 .cse25 .cse26 (not (= ULTIMATE.start_eval_~tmp___1~0 0))) (and .cse0 .cse1 .cse13 .cse2 .cse4 .cse10 .cse11 .cse12 .cse6 .cse15 .cse7) (and (not .cse7) .cse13 .cse16 .cse14 .cse10 .cse20 .cse12 .cse15) (and .cse13 .cse16 .cse14 .cse18 .cse19 .cse20 .cse21 .cse23 .cse12 .cse15) (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse6 .cse7 .cse13 .cse8 .cse9 .cse10 .cse11 .cse12) (and .cse0 .cse1 .cse16 .cse17 (= ULTIMATE.start_activate_threads_~tmp~1 0) .cse18 .cse19 .cse4 .cse20 .cse5 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 0) .cse21 .cse22 (= 0 |ULTIMATE.start_is_do_write_p_triggered_#res|) .cse23 .cse6 .cse27 .cse24 (= ~q_req_up~0 ~p_dw_pc~0) .cse26)))) [2021-01-06 19:24:54,876 INFO L185 CegarLoopUtils]: At program point L296-1(lines 279 298) the Hoare annotation is: (let ((.cse9 (= ~q_read_ev~0 2)) (.cse3 (not (= ~p_dw_st~0 0))) (.cse10 (= ~q_req_up~0 0)) (.cse0 (= 1 ~c_dr_i~0)) (.cse1 (not (= ~slow_clk_edge~0 1))) (.cse7 (= ~p_dw_i~0 1)) (.cse8 (= ~c_dr_pc~0 1)) (.cse2 (not (= ~c_dr_st~0 0))) (.cse4 (not (= ~q_write_ev~0 0))) (.cse5 (not (= ~fast_clk_edge~0 1))) (.cse6 (not (= ~q_write_ev~0 1))) (.cse11 (not (= ~p_dw_pc~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8) (and (not .cse8) .cse2 .cse9 .cse3 .cse4 .cse10 .cse6 .cse11) (and .cse2 .cse9 .cse3 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse10 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse6 .cse11) (and (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0)) .cse0 .cse1 (= ULTIMATE.start_activate_threads_~tmp~1 1) (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0)) .cse7 .cse8 .cse2 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1) (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|) .cse4 .cse5 .cse6 .cse11))) [2021-01-06 19:24:54,876 INFO L185 CegarLoopUtils]: At program point L296-2(lines 279 298) the Hoare annotation is: (let ((.cse5 (= ~t~0 0)) (.cse16 (= ~q_read_ev~0 2)) (.cse14 (not (= ~p_dw_st~0 0))) (.cse17 (= ~q_req_up~0 0)) (.cse15 (not (= ~p_dw_pc~0 1))) (.cse0 (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0))) (.cse1 (= 1 ~c_dr_i~0)) (.cse2 (not (= ~slow_clk_edge~0 1))) (.cse3 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse4 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse6 (= ~p_dw_i~0 1)) (.cse7 (= ~c_dr_pc~0 1)) (.cse13 (not (= ~c_dr_st~0 0))) (.cse8 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse9 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse10 (not (= ~q_write_ev~0 0))) (.cse11 (not (= ~fast_clk_edge~0 1))) (.cse12 (not (= ~q_write_ev~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10 .cse11 .cse12) (and .cse1 .cse2 .cse13 .cse14 .cse10 .cse11 .cse12 .cse6 .cse7) (and .cse0 .cse1 .cse2 .cse14 .cse4 .cse5 .cse10 .cse11 .cse12 .cse6 .cse7) (and .cse0 .cse1 .cse2 .cse4 .cse10 .cse5 .cse11 .cse12 .cse6 .cse15 .cse7) (and .cse0 .cse1 .cse2 .cse13 .cse4 .cse10 .cse11 .cse12 .cse6 .cse15 .cse7) (and (not .cse7) .cse13 .cse16 .cse14 .cse10 .cse17 .cse12 .cse15) (and .cse13 .cse16 .cse14 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse17 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse12 .cse15) (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse6 .cse7 .cse13 .cse8 .cse9 .cse10 .cse11 .cse12))) [2021-01-06 19:24:54,876 INFO L189 CegarLoopUtils]: For program point L98(lines 98 103) no Hoare annotation was computed. [2021-01-06 19:24:54,876 INFO L189 CegarLoopUtils]: For program point L98-1(lines 98 103) no Hoare annotation was computed. [2021-01-06 19:24:54,877 INFO L189 CegarLoopUtils]: For program point L98-2(lines 98 103) no Hoare annotation was computed. [2021-01-06 19:24:54,877 INFO L189 CegarLoopUtils]: For program point L-1(line -1) no Hoare annotation was computed. [2021-01-06 19:24:54,877 INFO L189 CegarLoopUtils]: For program point ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION(line 11) no Hoare annotation was computed. [2021-01-06 19:24:54,877 INFO L189 CegarLoopUtils]: For program point L33-1(lines 33 37) no Hoare annotation was computed. [2021-01-06 19:24:54,877 INFO L189 CegarLoopUtils]: For program point L33-3(lines 33 37) no Hoare annotation was computed. [2021-01-06 19:24:54,877 INFO L189 CegarLoopUtils]: For program point L265-1(lines 264 277) no Hoare annotation was computed. [2021-01-06 19:24:54,877 INFO L185 CegarLoopUtils]: At program point L464(lines 453 466) the Hoare annotation is: (let ((.cse5 (= ~t~0 0)) (.cse16 (= ~q_read_ev~0 2)) (.cse14 (not (= ~p_dw_st~0 0))) (.cse17 (= ~q_req_up~0 0)) (.cse15 (not (= ~p_dw_pc~0 1))) (.cse0 (not (= |ULTIMATE.start_exists_runnable_thread_#res| 0))) (.cse1 (= 1 ~c_dr_i~0)) (.cse2 (not (= ~slow_clk_edge~0 1))) (.cse3 (= ULTIMATE.start_activate_threads_~tmp~1 1)) (.cse4 (not (= ULTIMATE.start_exists_runnable_thread_~__retres1~2 0))) (.cse6 (= ~p_dw_i~0 1)) (.cse7 (= ~c_dr_pc~0 1)) (.cse13 (not (= ~c_dr_st~0 0))) (.cse8 (= ULTIMATE.start_is_do_write_p_triggered_~__retres1~0 1)) (.cse9 (= 1 |ULTIMATE.start_is_do_write_p_triggered_#res|)) (.cse10 (not (= ~q_write_ev~0 0))) (.cse11 (not (= ~fast_clk_edge~0 1))) (.cse12 (not (= ~q_write_ev~0 1)))) (or (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse5 .cse6 .cse7 .cse8 .cse9 .cse10 .cse11 .cse12) (and .cse1 .cse2 .cse13 .cse14 .cse10 .cse11 .cse12 .cse6 .cse7) (and .cse0 .cse1 .cse2 .cse14 .cse4 .cse5 .cse10 .cse11 .cse12 .cse6 .cse7) (and .cse0 .cse1 .cse2 .cse4 .cse10 .cse5 .cse11 .cse12 .cse6 .cse15 .cse7) (and .cse0 .cse1 .cse2 .cse13 .cse4 .cse10 .cse11 .cse12 .cse6 .cse15 .cse7) (and (not .cse7) .cse13 .cse16 .cse14 .cse10 .cse17 .cse12 .cse15) (and .cse13 .cse16 .cse14 (= ~c_dr_pc~0 ~q_req_up~0) (= ULTIMATE.start_activate_threads_~tmp___0~1 0) .cse17 (= ULTIMATE.start_is_do_read_c_triggered_~__retres1~1 0) (= |ULTIMATE.start_is_do_read_c_triggered_#res| 0) .cse12 .cse15) (and .cse0 .cse1 .cse2 .cse3 .cse4 .cse6 .cse7 .cse13 .cse8 .cse9 .cse10 .cse11 .cse12))) [2021-01-06 19:24:54,877 INFO L189 CegarLoopUtils]: For program point L431(lines 431 438) no Hoare annotation was computed. [2021-01-06 19:24:54,878 INFO L189 CegarLoopUtils]: For program point L68-1(lines 68 77) no Hoare annotation was computed. [2021-01-06 19:24:55,011 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 06.01 07:24:55 BoogieIcfgContainer [2021-01-06 19:24:55,011 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2021-01-06 19:24:55,011 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-01-06 19:24:55,012 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-01-06 19:24:55,012 INFO L275 PluginConnector]: Witness Printer initialized [2021-01-06 19:24:55,012 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.01 07:24:09" (3/4) ... [2021-01-06 19:24:55,016 INFO L137 WitnessPrinter]: Generating witness for correct program [2021-01-06 19:24:55,032 INFO L910 BoogieBacktranslator]: Reduced CFG by removing 7 nodes and edges [2021-01-06 19:24:55,033 INFO L910 BoogieBacktranslator]: Reduced CFG by removing 4 nodes and edges [2021-01-06 19:24:55,034 INFO L910 BoogieBacktranslator]: Reduced CFG by removing 1 nodes and edges [2021-01-06 19:24:55,035 INFO L910 BoogieBacktranslator]: Reduced CFG by removing 1 nodes and edges [2021-01-06 19:24:55,066 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && q_req_up == p_dw_pc) && 0 == \result) || (((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && c_dr_pc == q_req_up) && q_req_up == 0) && t == 0) && c_dr_st == 0) && __retres1 == 0) && 0 == \result) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) [2021-01-06 19:24:55,067 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && c_dr_pc == q_req_up) && q_req_up == 0) && t == 0) && c_dr_st == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && q_req_up == p_dw_pc) && 0 == \result) [2021-01-06 19:24:55,067 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && c_dr_pc == q_req_up) && q_req_up == 0) && t == 0) && c_dr_st == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) || ((((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && q_req_up == p_dw_pc) && 0 == \result) && \result == 0) [2021-01-06 19:24:55,067 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && q_req_up == p_dw_pc) && 0 == \result) && \result == 0) || (((((((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && t == 0) && c_dr_st == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) [2021-01-06 19:24:55,067 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && c_dr_pc == q_req_up) && tmp___0 == 0) && t == 0) && q_req_up == 0) && c_dr_st == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev)) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) [2021-01-06 19:24:55,068 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((((((((!(\result == 0) && 1 == c_dr_i) && q_read_ev == 2) && q_read_ev == fast_clk_edge) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && !(__retres1 == 0)) && q_req_up == 0) && t == 0) && __retres1 == 0) && c_dr_st == 0) && \result == 0) && p_dw_i == 1) && slow_clk_edge == q_read_ev) && p_dw_pc == 1) && q_write_ev == q_read_ev) && !(tmp___1 == 0))) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && c_dr_pc == q_req_up) && tmp___0 == 0) && t == 0) && q_req_up == 0) && c_dr_st == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev)) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1))) || ((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && q_req_up == 0) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,068 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,068 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && q_req_up == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) [2021-01-06 19:24:55,068 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(fast_clk_edge == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,069 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && tmp == 1) && __retres1 == 1) && 1 == \result) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && c_dr_pc == q_req_up) && tmp___0 == 0) && !(__retres1 == 0)) && t == 0) && q_req_up == 0) && c_dr_st == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev)) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && __retres1 == 1) && 1 == \result) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && !(__retres1 == 0)) && q_req_up == 0) && t == 0) && __retres1 == 0) && c_dr_st == 0) && \result == 0) && p_dw_i == 1) && slow_clk_edge == q_read_ev) && p_dw_pc == 1) && q_write_ev == q_read_ev) && !(tmp___1 == 0)) [2021-01-06 19:24:55,069 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((((((((!(\result == 0) && 1 == c_dr_i) && q_read_ev == 2) && q_read_ev == fast_clk_edge) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && !(__retres1 == 0)) && q_req_up == 0) && t == 0) && __retres1 == 0) && c_dr_st == 0) && \result == 0) && p_dw_i == 1) && slow_clk_edge == q_read_ev) && p_dw_pc == 1) && q_write_ev == q_read_ev) && !(tmp___1 == 0))) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1))) || (((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && c_dr_pc == q_req_up) && tmp___0 == 0) && !(__retres1 == 0)) && q_req_up == 0) && t == 0) && __retres1 == 0) && __retres1 == 0) && c_dr_st == 0) && 0 == \result) && \result == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) [2021-01-06 19:24:55,069 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && c_dr_pc == 1) || (((((((((((((((((!(\result == 0) && 1 == c_dr_i) && q_read_ev == 2) && q_read_ev == fast_clk_edge) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && !(__retres1 == 0)) && q_req_up == 0) && t == 0) && __retres1 == 0) && c_dr_st == 0) && \result == 0) && p_dw_i == 1) && slow_clk_edge == q_read_ev) && p_dw_pc == 1) && q_write_ev == q_read_ev) && !(tmp___1 == 0))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0))) || ((((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && q_read_ev == 2) && tmp == 0) && q_read_ev == fast_clk_edge) && tmp___0 == 0) && !(__retres1 == 0)) && c_dr_pc == q_req_up) && t == 0) && q_req_up == 0) && c_dr_st == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) && !(tmp___1 == 0))) || (((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0))) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && c_dr_pc == 1)) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(tmp___1 == 0)) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,069 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(fast_clk_edge == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && !(fast_clk_edge == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && \result == 0) && !(p_dw_pc == 1))) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) [2021-01-06 19:24:55,070 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && 1 == \result) && !(q_write_ev == 0)) && q_req_up == 0) && !(fast_clk_edge == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && q_req_up == 0) && !(q_write_ev == 0)) && __retres1 == 0) && 0 == \result) && !(fast_clk_edge == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && 0 == \result) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(p_dw_pc == 1))) || (((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,070 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && c_dr_pc == 1) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && c_dr_pc == 1)) || (((((((((((((((((!(\result == 0) && 1 == c_dr_i) && q_read_ev == 2) && q_read_ev == fast_clk_edge) && !(p_dw_st == 0)) && !(__retres1 == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && t == 0) && q_req_up == 0) && c_dr_st == 0) && __retres1 == 0) && \result == 0) && p_dw_i == 1) && slow_clk_edge == q_read_ev) && q_write_ev == q_read_ev) && !(tmp___1 == 0)) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,070 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && p_dw_pc == 1) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0)) || (((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(p_dw_st == 0)) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && p_dw_pc == 1) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0)) [2021-01-06 19:24:55,070 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && c_dr_pc == 1) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && c_dr_pc == 1) [2021-01-06 19:24:55,071 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && q_req_up == 0) && p_dw_i == 1) && !(c_dr_st == 0)) && p_dw_pc == 1) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0)) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0))) || ((((((((((((((((!(\result == 0) && 1 == c_dr_i) && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && !(__retres1 == 0)) && t == 0) && q_req_up == 0) && __retres1 == 0) && 0 == \result) && p_dw_i == 1) && !(c_dr_st == 0)) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) && !(tmp___1 == 0))) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0)) && !(p_dw_pc == 1))) || ((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0)) [2021-01-06 19:24:55,071 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || ((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && q_req_up == 0) && __retres1 == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(p_dw_pc == 1))) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && !(fast_clk_edge == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && !(p_dw_pc == 1))) || ((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && __retres1 == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,071 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && q_req_up == 0) && !(q_write_ev == 0)) && __retres1 == 0) && \result == 0) && !(fast_clk_edge == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && __retres1 == 0) && \result == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && \result == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(p_dw_pc == 1))) || (((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && q_req_up == 0) && __retres1 == 0) && \result == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(p_dw_pc == 1))) || ((((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,072 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && tmp == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(p_dw_pc == 1))) || (((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && 0 == \result) && !(p_dw_pc == 1))) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(fast_clk_edge == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && tmp == 1) && __retres1 == 1) && 1 == \result) && q_req_up == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1) [2021-01-06 19:24:55,072 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && tmp == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,072 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,072 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,072 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || ((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && __retres1 == 1) && 1 == \result) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && __retres1 == 1) && tmp == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1) [2021-01-06 19:24:55,073 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((1 == c_dr_i && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,073 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: (((((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && tmp == 1) && __retres1 == 1) && 1 == \result) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && __retres1 == 1) && 1 == \result) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,073 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) [2021-01-06 19:24:55,073 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && __retres1 == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(c_dr_st == 0)) && __retres1 == 1) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) || (((((((1 == c_dr_i && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && __retres1 == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && __retres1 == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,073 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && 1 == \result) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && p_dw_i == 1)) && c_dr_pc == 1) || ((((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) || ((((((((1 == c_dr_i && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && 1 == \result) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1)) && c_dr_pc == 1)) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && 0 == \result) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && __retres1 == 0) && !(fast_clk_edge == 1)) && 0 == \result) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) [2021-01-06 19:24:55,074 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) [2021-01-06 19:24:55,074 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) [2021-01-06 19:24:55,074 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && tmp == 1) && __retres1 == 1) && p_dw_st == 0) && 1 == \result) && !(q_write_ev == 0)) && __retres1 == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((1 == c_dr_i && !(c_dr_st == 0)) && p_dw_st == 0) && __retres1 == 1) && tmp == 1) && 1 == \result) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((1 == c_dr_i && !(c_dr_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(q_write_ev == 0)) && __retres1 == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,074 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((((q_read_ev == 2 && tmp == 0) && !(p_dw_st == 0)) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(c_dr_pc == 1)) && !(c_dr_st == 0)) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((1 == c_dr_i && !(c_dr_st == 0)) && p_dw_st == 0) && __retres1 == 1) && tmp == 1) && 1 == \result) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((1 == c_dr_i && !(c_dr_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && \result == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && __retres1 == 0) && \result == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && p_dw_st == 0) && 1 == \result) && !(q_write_ev == 0)) && !(q_write_ev == 1)) [2021-01-06 19:24:55,075 WARN L220 nessWitnessGenerator]: Not writing invariant because ACSL is forbidden: ((((((((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && p_dw_st == 0) && __retres1 == 1) && tmp == 1) && 1 == \result) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((1 == c_dr_i && p_dw_st == 0) && __retres1 == 1) && tmp == 1) && 1 == \result) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((((q_read_ev == 2 && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(c_dr_st == 0)) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((1 == c_dr_i && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((1 == c_dr_i && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) [2021-01-06 19:24:55,127 INFO L141 WitnessManager]: Wrote witness to /storage/repos/svcomp/c/systemc/pc_sfifo_3.cil.c-witness.graphml [2021-01-06 19:24:55,127 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-01-06 19:24:55,131 INFO L168 Benchmark]: Toolchain (without parser) took 47211.46 ms. Allocated memory was 158.3 MB in the beginning and 1.8 GB in the end (delta: 1.7 GB). Free memory was 133.3 MB in the beginning and 1.2 GB in the end (delta: -1.1 GB). Peak memory consumption was 575.2 MB. Max. memory is 8.0 GB. [2021-01-06 19:24:55,131 INFO L168 Benchmark]: CDTParser took 0.27 ms. Allocated memory is still 158.3 MB. Free memory is still 132.0 MB. There was no memory consumed. Max. memory is 8.0 GB. [2021-01-06 19:24:55,131 INFO L168 Benchmark]: CACSL2BoogieTranslator took 511.36 ms. Allocated memory is still 158.3 MB. Free memory was 133.1 MB in the beginning and 118.9 MB in the end (delta: 14.1 MB). Peak memory consumption was 13.6 MB. Max. memory is 8.0 GB. [2021-01-06 19:24:55,132 INFO L168 Benchmark]: Boogie Procedure Inliner took 71.83 ms. Allocated memory is still 158.3 MB. Free memory was 118.7 MB in the beginning and 116.3 MB in the end (delta: 2.4 MB). Peak memory consumption was 3.1 MB. Max. memory is 8.0 GB. [2021-01-06 19:24:55,132 INFO L168 Benchmark]: Boogie Preprocessor took 74.52 ms. Allocated memory is still 158.3 MB. Free memory was 116.3 MB in the beginning and 114.4 MB in the end (delta: 1.9 MB). Peak memory consumption was 1.0 MB. Max. memory is 8.0 GB. [2021-01-06 19:24:55,132 INFO L168 Benchmark]: RCFGBuilder took 997.10 ms. Allocated memory is still 158.3 MB. Free memory was 114.2 MB in the beginning and 107.0 MB in the end (delta: 7.2 MB). Peak memory consumption was 7.9 MB. Max. memory is 8.0 GB. [2021-01-06 19:24:55,133 INFO L168 Benchmark]: TraceAbstraction took 45428.67 ms. Allocated memory was 158.3 MB in the beginning and 1.8 GB in the end (delta: 1.7 GB). Free memory was 106.5 MB in the beginning and 1.2 GB in the end (delta: -1.1 GB). Peak memory consumption was 1.1 GB. Max. memory is 8.0 GB. [2021-01-06 19:24:55,135 INFO L168 Benchmark]: Witness Printer took 115.62 ms. Allocated memory is still 1.8 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 9.4 MB). Peak memory consumption was 9.4 MB. Max. memory is 8.0 GB. [2021-01-06 19:24:55,138 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.27 ms. Allocated memory is still 158.3 MB. Free memory is still 132.0 MB. There was no memory consumed. Max. memory is 8.0 GB. * CACSL2BoogieTranslator took 511.36 ms. Allocated memory is still 158.3 MB. Free memory was 133.1 MB in the beginning and 118.9 MB in the end (delta: 14.1 MB). Peak memory consumption was 13.6 MB. Max. memory is 8.0 GB. * Boogie Procedure Inliner took 71.83 ms. Allocated memory is still 158.3 MB. Free memory was 118.7 MB in the beginning and 116.3 MB in the end (delta: 2.4 MB). Peak memory consumption was 3.1 MB. Max. memory is 8.0 GB. * Boogie Preprocessor took 74.52 ms. Allocated memory is still 158.3 MB. Free memory was 116.3 MB in the beginning and 114.4 MB in the end (delta: 1.9 MB). Peak memory consumption was 1.0 MB. Max. memory is 8.0 GB. * RCFGBuilder took 997.10 ms. Allocated memory is still 158.3 MB. Free memory was 114.2 MB in the beginning and 107.0 MB in the end (delta: 7.2 MB). Peak memory consumption was 7.9 MB. Max. memory is 8.0 GB. * TraceAbstraction took 45428.67 ms. Allocated memory was 158.3 MB in the beginning and 1.8 GB in the end (delta: 1.7 GB). Free memory was 106.5 MB in the beginning and 1.2 GB in the end (delta: -1.1 GB). Peak memory consumption was 1.1 GB. Max. memory is 8.0 GB. * Witness Printer took 115.62 ms. Allocated memory is still 1.8 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 9.4 MB). Peak memory consumption was 9.4 MB. Max. memory is 8.0 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - PositiveResult [Line: 11]: call to reach_error is unreachable For all program executions holds that call to reach_error is unreachable at this location - PositiveResult [Line: 11]: call to reach_error is unreachable For all program executions holds that call to reach_error is unreachable at this location - AllSpecificationsHoldResult: All specifications hold 2 specifications checked. All of them hold - InvariantResult [Line: 54]: Loop Invariant Derived loop invariant: (((((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && 1 == \result) && !(q_write_ev == 0)) && q_req_up == 0) && !(fast_clk_edge == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && q_req_up == 0) && !(q_write_ev == 0)) && __retres1 == 0) && 0 == \result) && !(fast_clk_edge == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && 0 == \result) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(p_dw_pc == 1))) || (((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) - InvariantResult [Line: 54]: Loop Invariant Derived loop invariant: (((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && q_req_up == p_dw_pc) && 0 == \result) || (((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && c_dr_pc == q_req_up) && q_req_up == 0) && t == 0) && c_dr_st == 0) && __retres1 == 0) && 0 == \result) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) - InvariantResult [Line: 279]: Loop Invariant Derived loop invariant: ((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) - InvariantResult [Line: 279]: Loop Invariant Derived loop invariant: ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) - InvariantResult [Line: 321]: Loop Invariant Derived loop invariant: (((((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && q_req_up == p_dw_pc) && 0 == \result) && \result == 0) || (((((((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && t == 0) && c_dr_st == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) - InvariantResult [Line: 546]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 279]: Loop Invariant Derived loop invariant: ((((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((((((((!(\result == 0) && 1 == c_dr_i) && q_read_ev == 2) && q_read_ev == fast_clk_edge) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && !(__retres1 == 0)) && q_req_up == 0) && t == 0) && __retres1 == 0) && c_dr_st == 0) && \result == 0) && p_dw_i == 1) && slow_clk_edge == q_read_ev) && p_dw_pc == 1) && q_write_ev == q_read_ev) && !(tmp___1 == 0))) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1))) || (((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && c_dr_pc == q_req_up) && tmp___0 == 0) && !(__retres1 == 0)) && q_req_up == 0) && t == 0) && __retres1 == 0) && __retres1 == 0) && c_dr_st == 0) && 0 == \result) && \result == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) - InvariantResult [Line: 402]: Loop Invariant Derived loop invariant: ((((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((((((((!(\result == 0) && 1 == c_dr_i) && q_read_ev == 2) && q_read_ev == fast_clk_edge) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && !(__retres1 == 0)) && q_req_up == 0) && t == 0) && __retres1 == 0) && c_dr_st == 0) && \result == 0) && p_dw_i == 1) && slow_clk_edge == q_read_ev) && p_dw_pc == 1) && q_write_ev == q_read_ev) && !(tmp___1 == 0))) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && c_dr_pc == q_req_up) && tmp___0 == 0) && t == 0) && q_req_up == 0) && c_dr_st == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev)) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1))) || ((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && q_req_up == 0) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) - InvariantResult [Line: 502]: Loop Invariant Derived loop invariant: ((((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || ((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && __retres1 == 1) && 1 == \result) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && __retres1 == 1) && tmp == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1) - InvariantResult [Line: 468]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 190]: Loop Invariant Derived loop invariant: (((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && q_req_up == 0) && p_dw_i == 1) && !(c_dr_st == 0)) && p_dw_pc == 1) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0)) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0))) || ((((((((((((((((!(\result == 0) && 1 == c_dr_i) && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && !(__retres1 == 0)) && t == 0) && q_req_up == 0) && __retres1 == 0) && 0 == \result) && p_dw_i == 1) && !(c_dr_st == 0)) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) && !(tmp___1 == 0))) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0)) && !(p_dw_pc == 1))) || ((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0)) - InvariantResult [Line: 83]: Loop Invariant Derived loop invariant: ((((((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((((q_read_ev == 2 && tmp == 0) && !(p_dw_st == 0)) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(c_dr_pc == 1)) && !(c_dr_st == 0)) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((1 == c_dr_i && !(c_dr_st == 0)) && p_dw_st == 0) && __retres1 == 1) && tmp == 1) && 1 == \result) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((1 == c_dr_i && !(c_dr_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && \result == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && __retres1 == 0) && \result == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && p_dw_st == 0) && 1 == \result) && !(q_write_ev == 0)) && !(q_write_ev == 1)) - InvariantResult [Line: 83]: Loop Invariant Derived loop invariant: ((((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && q_req_up == 0) && !(q_write_ev == 0)) && __retres1 == 0) && \result == 0) && !(fast_clk_edge == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && __retres1 == 0) && \result == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && \result == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(p_dw_pc == 1))) || (((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && q_req_up == 0) && __retres1 == 0) && \result == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(p_dw_pc == 1))) || ((((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(p_dw_pc == 1)) - InvariantResult [Line: 246]: Loop Invariant Derived loop invariant: ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && q_req_up == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) - InvariantResult [Line: 303]: Loop Invariant Derived loop invariant: ((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) || (((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && c_dr_pc == q_req_up) && q_req_up == 0) && t == 0) && c_dr_st == 0) && q_req_up == p_dw_pc) && p_dw_i == 1) && q_write_ev == q_read_ev) - InvariantResult [Line: 83]: Loop Invariant Derived loop invariant: ((((((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && c_dr_pc == q_req_up) && q_req_up == 0) && t == 0) && c_dr_st == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) || ((((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && q_req_up == p_dw_pc) && 0 == \result) && \result == 0) - InvariantResult [Line: 190]: Loop Invariant Derived loop invariant: 0 - InvariantResult [Line: 453]: Loop Invariant Derived loop invariant: ((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) - InvariantResult [Line: 54]: Loop Invariant Derived loop invariant: ((((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && 1 == \result) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && p_dw_i == 1)) && c_dr_pc == 1) || ((((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) || ((((((((1 == c_dr_i && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && 1 == \result) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1)) && c_dr_pc == 1)) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && 0 == \result) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && __retres1 == 0) && !(fast_clk_edge == 1)) && 0 == \result) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) - InvariantResult [Line: 265]: Loop Invariant Derived loop invariant: ((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && c_dr_pc == q_req_up) && q_req_up == 0) && t == 0) && c_dr_st == 0) && q_req_up == p_dw_pc) && p_dw_i == 1) && q_write_ev == q_read_ev - InvariantResult [Line: 57]: Loop Invariant Derived loop invariant: ((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && c_dr_pc == q_req_up) && q_req_up == 0) && t == 0) && c_dr_st == 0) && __retres1 == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) || ((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && q_req_up == p_dw_pc) - InvariantResult [Line: 282]: Loop Invariant Derived loop invariant: (((((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && tmp == 1) && __retres1 == 1) && 1 == \result) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && __retres1 == 1) && 1 == \result) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) && !(p_dw_pc == 1)) - InvariantResult [Line: 317]: Loop Invariant Derived loop invariant: (((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && tmp == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) - InvariantResult [Line: 140]: Loop Invariant Derived loop invariant: ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && c_dr_pc == 1) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && c_dr_pc == 1)) || (((((((((((((((((!(\result == 0) && 1 == c_dr_i) && q_read_ev == 2) && q_read_ev == fast_clk_edge) && !(p_dw_st == 0)) && !(__retres1 == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && t == 0) && q_req_up == 0) && c_dr_st == 0) && __retres1 == 0) && \result == 0) && p_dw_i == 1) && slow_clk_edge == q_read_ev) && q_write_ev == q_read_ev) && !(tmp___1 == 0)) && !(p_dw_pc == 1)) - InvariantResult [Line: 282]: Loop Invariant Derived loop invariant: ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) - InvariantResult [Line: 140]: Loop Invariant Derived loop invariant: (((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && p_dw_pc == 1) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0)) || (((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(p_dw_st == 0)) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && p_dw_pc == 1) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0)) - InvariantResult [Line: 317]: Loop Invariant Derived loop invariant: (((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && c_dr_pc == q_req_up) && tmp___0 == 0) && t == 0) && q_req_up == 0) && c_dr_st == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev)) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) - InvariantResult [Line: 282]: Loop Invariant Derived loop invariant: (((((((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && tmp == 1) && __retres1 == 1) && 1 == \result) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && c_dr_pc == q_req_up) && tmp___0 == 0) && !(__retres1 == 0)) && t == 0) && q_req_up == 0) && c_dr_st == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev)) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && __retres1 == 1) && 1 == \result) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && !(__retres1 == 0)) && q_req_up == 0) && t == 0) && __retres1 == 0) && c_dr_st == 0) && \result == 0) && p_dw_i == 1) && slow_clk_edge == q_read_ev) && p_dw_pc == 1) && q_write_ev == q_read_ev) && !(tmp___1 == 0)) - InvariantResult [Line: 527]: Loop Invariant Derived loop invariant: ((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && c_dr_pc == q_req_up) && q_req_up == 0) && t == 0) && c_dr_st == 0) && q_req_up == p_dw_pc) && p_dw_i == 1) && q_write_ev == q_read_ev - InvariantResult [Line: 86]: Loop Invariant Derived loop invariant: ((((((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && tmp == 1) && __retres1 == 1) && p_dw_st == 0) && 1 == \result) && !(q_write_ev == 0)) && __retres1 == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((1 == c_dr_i && !(c_dr_st == 0)) && p_dw_st == 0) && __retres1 == 1) && tmp == 1) && 1 == \result) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((1 == c_dr_i && !(c_dr_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(q_write_ev == 0)) && __retres1 == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) - InvariantResult [Line: 321]: Loop Invariant Derived loop invariant: (((((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && tmp == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(p_dw_pc == 1))) || (((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && 0 == \result) && !(p_dw_pc == 1))) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(fast_clk_edge == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && tmp == 1) && __retres1 == 1) && 1 == \result) && q_req_up == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1) - InvariantResult [Line: 299]: Loop Invariant Derived loop invariant: (((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && q_req_up == p_dw_pc) || (((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && c_dr_pc == q_req_up) && q_req_up == 0) && t == 0) && c_dr_st == 0) && q_req_up == p_dw_pc) && p_dw_i == 1) && q_write_ev == q_read_ev) - InvariantResult [Line: 337]: Loop Invariant Derived loop invariant: (((((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((1 == c_dr_i && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) - InvariantResult [Line: 86]: Loop Invariant Derived loop invariant: (((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || ((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && q_req_up == 0) && __retres1 == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(p_dw_pc == 1))) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && !(fast_clk_edge == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && !(p_dw_pc == 1))) || ((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && tmp == 1) && __retres1 == 0) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && !(p_dw_pc == 1)) - InvariantResult [Line: 86]: Loop Invariant Derived loop invariant: (((((((((((((((1 == c_dr_i && q_read_ev == 2) && q_read_ev == fast_clk_edge) && tmp == 0) && c_dr_pc == q_req_up) && q_req_up == 0) && t == 0) && c_dr_st == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && q_req_up == p_dw_pc) && 0 == \result) - InvariantResult [Line: 402]: Loop Invariant Derived loop invariant: (((((((((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && c_dr_pc == 1) || (((((((((((((((((!(\result == 0) && 1 == c_dr_i) && q_read_ev == 2) && q_read_ev == fast_clk_edge) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && !(__retres1 == 0)) && q_req_up == 0) && t == 0) && __retres1 == 0) && c_dr_st == 0) && \result == 0) && p_dw_i == 1) && slow_clk_edge == q_read_ev) && p_dw_pc == 1) && q_write_ev == q_read_ev) && !(tmp___1 == 0))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0))) || ((((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && q_read_ev == 2) && tmp == 0) && q_read_ev == fast_clk_edge) && tmp___0 == 0) && !(__retres1 == 0)) && c_dr_pc == q_req_up) && t == 0) && q_req_up == 0) && c_dr_st == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && p_dw_i == 1) && p_dw_st == 0) && slow_clk_edge == q_read_ev) && q_req_up == p_dw_pc) && q_write_ev == q_read_ev) && !(tmp___1 == 0))) || (((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && !(tmp___1 == 0))) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && c_dr_pc == 1)) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(tmp___1 == 0)) && !(p_dw_pc == 1)) - InvariantResult [Line: 299]: Loop Invariant Derived loop invariant: ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(fast_clk_edge == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(p_dw_pc == 1)) - InvariantResult [Line: 449]: Loop Invariant Derived loop invariant: ((((((((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && t == 0) && p_dw_i == 1) && c_dr_pc == 1) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && tmp == 1) && !(__retres1 == 0)) && p_dw_i == 1) && c_dr_pc == 1) && !(c_dr_st == 0)) && __retres1 == 1) && 1 == \result) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) - InvariantResult [Line: 57]: Loop Invariant Derived loop invariant: ((((((((((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && __retres1 == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(c_dr_st == 0)) && __retres1 == 1) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) || (((((((1 == c_dr_i && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && __retres1 == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((!(\result == 0) && 1 == c_dr_i) && !(c_dr_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && t == 0) && __retres1 == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) - InvariantResult [Line: 396]: Loop Invariant Derived loop invariant: (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || (((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && \result == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) - InvariantResult [Line: 357]: Loop Invariant Derived loop invariant: ((((((((((((((((1 == c_dr_i && !(c_dr_st == 0)) && !(slow_clk_edge == 1)) && p_dw_st == 0) && __retres1 == 1) && tmp == 1) && 1 == \result) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) || ((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || (((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(q_write_ev == 0)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || (((((((((1 == c_dr_i && p_dw_st == 0) && __retres1 == 1) && tmp == 1) && 1 == \result) && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((((q_read_ev == 2 && tmp == 0) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && tmp___0 == 0) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && 0 == \result) && \result == 0) && !(c_dr_st == 0)) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || (((((((1 == c_dr_i && !(p_dw_st == 0)) && !(q_write_ev == 0)) && t == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((1 == c_dr_i && !(q_write_ev == 0)) && t == 0) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && tmp == 0) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && 0 == \result) && !(q_write_ev == 1)) && !(p_dw_pc == 1)) - InvariantResult [Line: 140]: Loop Invariant Derived loop invariant: (((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && t == 0) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && c_dr_pc == 1) || (((((((((((!(\result == 0) && 1 == c_dr_i) && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(__retres1 == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(tmp___1 == 0)) && c_dr_pc == 1) - InvariantResult [Line: 57]: Loop Invariant Derived loop invariant: ((((((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && !(fast_clk_edge == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && !(fast_clk_edge == 1)) && p_dw_i == 1) && c_dr_pc == 1)) || ((((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && __retres1 == 1) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && !(p_dw_pc == 1)) && c_dr_pc == 1)) || ((((((((!(c_dr_pc == 1) && !(c_dr_st == 0)) && q_read_ev == 2) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && q_req_up == 0) && __retres1 == 0) && !(q_write_ev == 1)) && !(p_dw_pc == 1))) || ((((((((!(c_dr_st == 0) && q_read_ev == 2) && !(p_dw_st == 0)) && c_dr_pc == q_req_up) && q_req_up == 0) && __retres1 == 0) && __retres1 == 0) && \result == 0) && !(p_dw_pc == 1))) || (((((((((1 == c_dr_i && !(slow_clk_edge == 1)) && !(c_dr_st == 0)) && !(p_dw_st == 0)) && !(q_write_ev == 0)) && __retres1 == 0) && !(fast_clk_edge == 1)) && !(q_write_ev == 1)) && p_dw_i == 1) && c_dr_pc == 1) - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 131 locations, 2 error locations. Started 1 CEGAR loops. VerificationResult: SAFE, OverallTime: 16.7s, OverallIterations: 20, TraceHistogramMax: 5, AutomataDifference: 8.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 28.4s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 3891 SDtfs, 6751 SDslu, 5457 SDs, 0 SdLazy, 615 SolverSat, 211 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 117 GetRequests, 54 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=8521occurred in iteration=8, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 5.9s AutomataMinimizationTime, 20 MinimizatonAttempts, 10338 StatesRemovedByMinimization, 17 NontrivialMinimizations, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 43 LocationsWithAnnotation, 43 PreInvPairs, 1302 NumberOfFragments, 8885 HoareAnnotationTreeSize, 43 FomulaSimplifications, 1496534 FormulaSimplificationTreeSizeReduction, 7.9s HoareSimplificationTime, 43 FomulaSimplificationsInter, 134052 FormulaSimplificationTreeSizeReductionInter, 20.5s HoareSimplificationTimeInter, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 0.9s InterpolantComputationTime, 1874 NumberOfCodeBlocks, 1874 NumberOfCodeBlocksAsserted, 20 NumberOfCheckSat, 1854 ConstructedInterpolants, 0 QuantifiedInterpolants, 327104 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 20 InterpolantComputations, 20 PerfectInterpolantSequences, 675/675 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be correct! Received shutdown request...