/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -tc config/AutomizerReach.xml -s config/svcomp-Reach-64bit-Automizer_Default.epf -i ../sv-benchmarks/c/systemc/toy1.cil.c -------------------------------------------------------------------------------- This is Ultimate 0.2.1-bitabs-178dd20 [2021-01-06 19:29:16,728 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-01-06 19:29:16,732 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-01-06 19:29:16,773 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-01-06 19:29:16,774 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-01-06 19:29:16,775 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-01-06 19:29:16,777 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-01-06 19:29:16,780 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-01-06 19:29:16,782 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-01-06 19:29:16,784 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-01-06 19:29:16,785 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-01-06 19:29:16,787 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-01-06 19:29:16,787 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-01-06 19:29:16,789 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-01-06 19:29:16,791 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-01-06 19:29:16,792 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-01-06 19:29:16,794 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-01-06 19:29:16,795 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-01-06 19:29:16,797 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-01-06 19:29:16,800 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-01-06 19:29:16,802 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-01-06 19:29:16,804 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-01-06 19:29:16,805 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-01-06 19:29:16,821 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-01-06 19:29:16,825 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-01-06 19:29:16,825 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-01-06 19:29:16,826 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-01-06 19:29:16,827 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-01-06 19:29:16,828 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-01-06 19:29:16,829 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-01-06 19:29:16,830 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-01-06 19:29:16,831 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-01-06 19:29:16,832 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-01-06 19:29:16,833 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-01-06 19:29:16,834 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-01-06 19:29:16,834 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-01-06 19:29:16,835 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-01-06 19:29:16,836 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-01-06 19:29:16,836 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-01-06 19:29:16,837 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-01-06 19:29:16,838 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-01-06 19:29:16,846 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf [2021-01-06 19:29:16,875 INFO L113 SettingsManager]: Loading preferences was successful [2021-01-06 19:29:16,875 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-01-06 19:29:16,877 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-01-06 19:29:16,877 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-01-06 19:29:16,877 INFO L138 SettingsManager]: * Use SBE=true [2021-01-06 19:29:16,877 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-01-06 19:29:16,878 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-01-06 19:29:16,878 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-01-06 19:29:16,878 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-01-06 19:29:16,878 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-01-06 19:29:16,878 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-01-06 19:29:16,879 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-01-06 19:29:16,879 INFO L138 SettingsManager]: * Use constant arrays=true [2021-01-06 19:29:16,879 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-01-06 19:29:16,879 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-01-06 19:29:16,879 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-01-06 19:29:16,880 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2021-01-06 19:29:16,880 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-01-06 19:29:16,880 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-01-06 19:29:16,880 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-01-06 19:29:16,880 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2021-01-06 19:29:16,881 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-01-06 19:29:16,881 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-01-06 19:29:16,881 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-01-06 19:29:16,881 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-01-06 19:29:16,881 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release [2021-01-06 19:29:17,294 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-01-06 19:29:17,337 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-01-06 19:29:17,340 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-01-06 19:29:17,342 INFO L271 PluginConnector]: Initializing CDTParser... [2021-01-06 19:29:17,343 INFO L275 PluginConnector]: CDTParser initialized [2021-01-06 19:29:17,344 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/toy1.cil.c [2021-01-06 19:29:17,437 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/data/41331c4e9/04dc1241c29448bf8fd238a47c21f4c3/FLAGf7f37d78c [2021-01-06 19:29:18,040 INFO L306 CDTParser]: Found 1 translation units. [2021-01-06 19:29:18,041 INFO L160 CDTParser]: Scanning /storage/repos/ultimate-bitabs/releaseScripts/default/sv-benchmarks/c/systemc/toy1.cil.c [2021-01-06 19:29:18,060 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/data/41331c4e9/04dc1241c29448bf8fd238a47c21f4c3/FLAGf7f37d78c [2021-01-06 19:29:18,373 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/data/41331c4e9/04dc1241c29448bf8fd238a47c21f4c3 [2021-01-06 19:29:18,382 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-01-06 19:29:18,384 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-01-06 19:29:18,386 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-01-06 19:29:18,386 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-01-06 19:29:18,397 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-01-06 19:29:18,398 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.01 07:29:18" (1/1) ... [2021-01-06 19:29:18,399 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2d6da0f8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:29:18, skipping insertion in model container [2021-01-06 19:29:18,401 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.01 07:29:18" (1/1) ... [2021-01-06 19:29:18,410 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-01-06 19:29:18,470 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-01-06 19:29:18,626 WARN L226 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate-bitabs/releaseScripts/default/sv-benchmarks/c/systemc/toy1.cil.c[393,406] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_wl~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t~0,] left hand side expression in assignment: lhs: VariableLHS[~data~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~processed~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_f~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_f~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t_b~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t~0,] left hand side expression in assignment: lhs: VariableLHS[~c1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_t~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_req_up~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~processed~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~d~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_e~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_e~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~r_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp~0,] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___0~0,] left hand side expression in assignment: lhs: VariableLHS[~c1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___1~0,] left hand side expression in assignment: lhs: VariableLHS[~c2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___2~0,] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___3~0,] left hand side expression in assignment: lhs: VariableLHS[~r_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_req_up~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~r_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~r_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_f~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_e~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_wl~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~r_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_e~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_f~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_wl~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_req_up~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~e_f~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_e~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_wl~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~r_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_e~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_f~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_wl~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_wl~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_f~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_e~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~r_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_req_up~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~d~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~__retres1~0,] [2021-01-06 19:29:18,729 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-01-06 19:29:18,741 INFO L203 MainTranslator]: Completed pre-run [2021-01-06 19:29:18,754 WARN L226 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate-bitabs/releaseScripts/default/sv-benchmarks/c/systemc/toy1.cil.c[393,406] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_wl~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t~0,] left hand side expression in assignment: lhs: VariableLHS[~data~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~processed~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_f~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_f~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t_b~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t~0,] left hand side expression in assignment: lhs: VariableLHS[~c1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_t~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_req_up~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~processed~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~d~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_e~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_e~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~r_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp~0,] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___0~0,] left hand side expression in assignment: lhs: VariableLHS[~c1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___1~0,] left hand side expression in assignment: lhs: VariableLHS[~c2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___2~0,] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___3~0,] left hand side expression in assignment: lhs: VariableLHS[~r_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_req_up~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~r_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~r_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_f~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_e~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_wl~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~r_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_e~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_f~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_wl~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_req_up~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~e_f~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_e~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_wl~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~r_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_e~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_f~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_wl~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_wl~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_g~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_f~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~e_e~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wb_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c2_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c1_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~wl_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~r_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c_req_up~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~d~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~c~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~__retres1~0,] [2021-01-06 19:29:18,802 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-01-06 19:29:18,827 INFO L208 MainTranslator]: Completed translation [2021-01-06 19:29:18,828 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:29:18 WrapperNode [2021-01-06 19:29:18,828 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-01-06 19:29:18,830 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-01-06 19:29:18,830 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-01-06 19:29:18,830 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-01-06 19:29:18,839 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:29:18" (1/1) ... [2021-01-06 19:29:18,851 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:29:18" (1/1) ... [2021-01-06 19:29:18,900 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-01-06 19:29:18,901 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-01-06 19:29:18,901 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-01-06 19:29:18,902 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-01-06 19:29:18,911 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:29:18" (1/1) ... [2021-01-06 19:29:18,911 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:29:18" (1/1) ... [2021-01-06 19:29:18,914 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:29:18" (1/1) ... [2021-01-06 19:29:18,915 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:29:18" (1/1) ... [2021-01-06 19:29:18,922 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:29:18" (1/1) ... [2021-01-06 19:29:18,933 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:29:18" (1/1) ... [2021-01-06 19:29:18,936 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:29:18" (1/1) ... [2021-01-06 19:29:18,941 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-01-06 19:29:18,942 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-01-06 19:29:18,943 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-01-06 19:29:18,943 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-01-06 19:29:18,944 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:29:18" (1/1) ... No working directory specified, using /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-01-06 19:29:19,042 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-01-06 19:29:19,042 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-01-06 19:29:19,043 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-01-06 19:29:19,043 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-01-06 19:29:19,718 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-01-06 19:29:19,718 INFO L299 CfgBuilder]: Removed 28 assume(true) statements. [2021-01-06 19:29:19,720 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.01 07:29:19 BoogieIcfgContainer [2021-01-06 19:29:19,721 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-01-06 19:29:19,723 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2021-01-06 19:29:19,723 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2021-01-06 19:29:19,727 INFO L275 PluginConnector]: TraceAbstraction initialized [2021-01-06 19:29:19,728 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.01 07:29:18" (1/3) ... [2021-01-06 19:29:19,729 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@955d34c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.01 07:29:19, skipping insertion in model container [2021-01-06 19:29:19,729 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:29:18" (2/3) ... [2021-01-06 19:29:19,729 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@955d34c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.01 07:29:19, skipping insertion in model container [2021-01-06 19:29:19,730 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.01 07:29:19" (3/3) ... [2021-01-06 19:29:19,731 INFO L111 eAbstractionObserver]: Analyzing ICFG toy1.cil.c [2021-01-06 19:29:19,739 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2021-01-06 19:29:19,745 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2021-01-06 19:29:19,770 INFO L253 AbstractCegarLoop]: Starting to check reachability of 2 error locations. [2021-01-06 19:29:19,806 INFO L377 AbstractCegarLoop]: Interprodecural is true [2021-01-06 19:29:19,806 INFO L378 AbstractCegarLoop]: Hoare is true [2021-01-06 19:29:19,806 INFO L379 AbstractCegarLoop]: Compute interpolants for FPandBP [2021-01-06 19:29:19,807 INFO L380 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2021-01-06 19:29:19,807 INFO L381 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-01-06 19:29:19,807 INFO L382 AbstractCegarLoop]: Difference is false [2021-01-06 19:29:19,807 INFO L383 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-01-06 19:29:19,807 INFO L387 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2021-01-06 19:29:19,834 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states. [2021-01-06 19:29:19,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2021-01-06 19:29:19,845 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:19,847 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:19,847 INFO L429 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:19,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:19,856 INFO L82 PathProgramCache]: Analyzing trace with hash -895778166, now seen corresponding path program 1 times [2021-01-06 19:29:19,869 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:19,870 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [341884424] [2021-01-06 19:29:19,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:20,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:20,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:20,121 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [341884424] [2021-01-06 19:29:20,122 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:20,122 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:20,123 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1553130333] [2021-01-06 19:29:20,129 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:20,129 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:20,145 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:20,146 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:20,149 INFO L87 Difference]: Start difference. First operand 129 states. Second operand 3 states. [2021-01-06 19:29:20,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:20,209 INFO L93 Difference]: Finished difference Result 250 states and 461 transitions. [2021-01-06 19:29:20,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:20,266 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2021-01-06 19:29:20,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:20,292 INFO L225 Difference]: With dead ends: 250 [2021-01-06 19:29:20,293 INFO L226 Difference]: Without dead ends: 125 [2021-01-06 19:29:20,318 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:20,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2021-01-06 19:29:20,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 125. [2021-01-06 19:29:20,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2021-01-06 19:29:20,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 218 transitions. [2021-01-06 19:29:20,389 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 218 transitions. Word has length 36 [2021-01-06 19:29:20,390 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:20,390 INFO L481 AbstractCegarLoop]: Abstraction has 125 states and 218 transitions. [2021-01-06 19:29:20,390 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:20,390 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 218 transitions. [2021-01-06 19:29:20,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2021-01-06 19:29:20,392 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:20,392 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:20,393 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2021-01-06 19:29:20,393 INFO L429 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:20,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:20,394 INFO L82 PathProgramCache]: Analyzing trace with hash -1597378040, now seen corresponding path program 1 times [2021-01-06 19:29:20,394 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:20,395 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [900903258] [2021-01-06 19:29:20,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:20,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:20,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:20,462 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [900903258] [2021-01-06 19:29:20,462 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:20,463 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:29:20,463 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054526286] [2021-01-06 19:29:20,465 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:29:20,465 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:20,466 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:29:20,466 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:29:20,467 INFO L87 Difference]: Start difference. First operand 125 states and 218 transitions. Second operand 4 states. [2021-01-06 19:29:20,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:20,582 INFO L93 Difference]: Finished difference Result 337 states and 586 transitions. [2021-01-06 19:29:20,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-01-06 19:29:20,585 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2021-01-06 19:29:20,586 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:20,590 INFO L225 Difference]: With dead ends: 337 [2021-01-06 19:29:20,590 INFO L226 Difference]: Without dead ends: 215 [2021-01-06 19:29:20,594 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:29:20,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states. [2021-01-06 19:29:20,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 210. [2021-01-06 19:29:20,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 210 states. [2021-01-06 19:29:20,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 366 transitions. [2021-01-06 19:29:20,627 INFO L78 Accepts]: Start accepts. Automaton has 210 states and 366 transitions. Word has length 36 [2021-01-06 19:29:20,627 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:20,627 INFO L481 AbstractCegarLoop]: Abstraction has 210 states and 366 transitions. [2021-01-06 19:29:20,627 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:29:20,628 INFO L276 IsEmpty]: Start isEmpty. Operand 210 states and 366 transitions. [2021-01-06 19:29:20,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2021-01-06 19:29:20,629 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:20,629 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:20,630 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2021-01-06 19:29:20,630 INFO L429 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:20,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:20,631 INFO L82 PathProgramCache]: Analyzing trace with hash -211174646, now seen corresponding path program 1 times [2021-01-06 19:29:20,631 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:20,631 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [739928816] [2021-01-06 19:29:20,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:20,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:20,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:20,699 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [739928816] [2021-01-06 19:29:20,699 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:20,699 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:20,700 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140752708] [2021-01-06 19:29:20,700 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:20,700 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:20,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:20,702 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:20,702 INFO L87 Difference]: Start difference. First operand 210 states and 366 transitions. Second operand 3 states. [2021-01-06 19:29:20,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:20,749 INFO L93 Difference]: Finished difference Result 411 states and 719 transitions. [2021-01-06 19:29:20,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:20,750 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2021-01-06 19:29:20,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:20,752 INFO L225 Difference]: With dead ends: 411 [2021-01-06 19:29:20,752 INFO L226 Difference]: Without dead ends: 210 [2021-01-06 19:29:20,754 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:20,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states. [2021-01-06 19:29:20,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 210. [2021-01-06 19:29:20,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 210 states. [2021-01-06 19:29:20,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 354 transitions. [2021-01-06 19:29:20,778 INFO L78 Accepts]: Start accepts. Automaton has 210 states and 354 transitions. Word has length 36 [2021-01-06 19:29:20,778 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:20,778 INFO L481 AbstractCegarLoop]: Abstraction has 210 states and 354 transitions. [2021-01-06 19:29:20,778 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:20,779 INFO L276 IsEmpty]: Start isEmpty. Operand 210 states and 354 transitions. [2021-01-06 19:29:20,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2021-01-06 19:29:20,780 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:20,780 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:20,781 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2021-01-06 19:29:20,781 INFO L429 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:20,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:20,782 INFO L82 PathProgramCache]: Analyzing trace with hash -1741716090, now seen corresponding path program 1 times [2021-01-06 19:29:20,782 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:20,782 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2146093173] [2021-01-06 19:29:20,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:20,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:20,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:20,833 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2146093173] [2021-01-06 19:29:20,833 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:20,834 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:29:20,834 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1642731344] [2021-01-06 19:29:20,834 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:29:20,834 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:20,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:29:20,836 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:29:20,836 INFO L87 Difference]: Start difference. First operand 210 states and 354 transitions. Second operand 4 states. [2021-01-06 19:29:20,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:20,936 INFO L93 Difference]: Finished difference Result 571 states and 965 transitions. [2021-01-06 19:29:20,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:29:20,937 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2021-01-06 19:29:20,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:20,941 INFO L225 Difference]: With dead ends: 571 [2021-01-06 19:29:20,941 INFO L226 Difference]: Without dead ends: 371 [2021-01-06 19:29:20,943 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:29:20,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 371 states. [2021-01-06 19:29:20,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 371 to 210. [2021-01-06 19:29:20,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 210 states. [2021-01-06 19:29:20,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 351 transitions. [2021-01-06 19:29:20,965 INFO L78 Accepts]: Start accepts. Automaton has 210 states and 351 transitions. Word has length 36 [2021-01-06 19:29:20,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:20,965 INFO L481 AbstractCegarLoop]: Abstraction has 210 states and 351 transitions. [2021-01-06 19:29:20,966 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:29:20,966 INFO L276 IsEmpty]: Start isEmpty. Operand 210 states and 351 transitions. [2021-01-06 19:29:20,967 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2021-01-06 19:29:20,967 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:20,967 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:20,968 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2021-01-06 19:29:20,968 INFO L429 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:20,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:20,969 INFO L82 PathProgramCache]: Analyzing trace with hash 181511944, now seen corresponding path program 1 times [2021-01-06 19:29:20,969 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:20,969 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076653770] [2021-01-06 19:29:20,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:20,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:21,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:21,042 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2076653770] [2021-01-06 19:29:21,042 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:21,043 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:29:21,043 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1323809677] [2021-01-06 19:29:21,043 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:29:21,044 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:21,044 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:29:21,045 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:29:21,046 INFO L87 Difference]: Start difference. First operand 210 states and 351 transitions. Second operand 4 states. [2021-01-06 19:29:21,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:21,158 INFO L93 Difference]: Finished difference Result 574 states and 961 transitions. [2021-01-06 19:29:21,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:29:21,160 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2021-01-06 19:29:21,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:21,163 INFO L225 Difference]: With dead ends: 574 [2021-01-06 19:29:21,164 INFO L226 Difference]: Without dead ends: 375 [2021-01-06 19:29:21,166 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:29:21,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 375 states. [2021-01-06 19:29:21,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 375 to 210. [2021-01-06 19:29:21,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 210 states. [2021-01-06 19:29:21,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 348 transitions. [2021-01-06 19:29:21,201 INFO L78 Accepts]: Start accepts. Automaton has 210 states and 348 transitions. Word has length 36 [2021-01-06 19:29:21,201 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:21,201 INFO L481 AbstractCegarLoop]: Abstraction has 210 states and 348 transitions. [2021-01-06 19:29:21,201 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:29:21,201 INFO L276 IsEmpty]: Start isEmpty. Operand 210 states and 348 transitions. [2021-01-06 19:29:21,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2021-01-06 19:29:21,209 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:21,209 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:21,210 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2021-01-06 19:29:21,210 INFO L429 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:21,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:21,212 INFO L82 PathProgramCache]: Analyzing trace with hash 243551558, now seen corresponding path program 1 times [2021-01-06 19:29:21,212 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:21,212 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798915961] [2021-01-06 19:29:21,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:21,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:21,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:21,293 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [798915961] [2021-01-06 19:29:21,293 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:21,293 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:29:21,294 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1143719316] [2021-01-06 19:29:21,294 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:29:21,294 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:21,295 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:29:21,295 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:29:21,295 INFO L87 Difference]: Start difference. First operand 210 states and 348 transitions. Second operand 4 states. [2021-01-06 19:29:21,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:21,380 INFO L93 Difference]: Finished difference Result 586 states and 972 transitions. [2021-01-06 19:29:21,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:29:21,381 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2021-01-06 19:29:21,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:21,384 INFO L225 Difference]: With dead ends: 586 [2021-01-06 19:29:21,384 INFO L226 Difference]: Without dead ends: 388 [2021-01-06 19:29:21,385 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:29:21,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 388 states. [2021-01-06 19:29:21,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 388 to 216. [2021-01-06 19:29:21,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216 states. [2021-01-06 19:29:21,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216 states to 216 states and 352 transitions. [2021-01-06 19:29:21,403 INFO L78 Accepts]: Start accepts. Automaton has 216 states and 352 transitions. Word has length 36 [2021-01-06 19:29:21,403 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:21,403 INFO L481 AbstractCegarLoop]: Abstraction has 216 states and 352 transitions. [2021-01-06 19:29:21,403 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:29:21,404 INFO L276 IsEmpty]: Start isEmpty. Operand 216 states and 352 transitions. [2021-01-06 19:29:21,404 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2021-01-06 19:29:21,405 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:21,405 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:21,405 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2021-01-06 19:29:21,405 INFO L429 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:21,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:21,406 INFO L82 PathProgramCache]: Analyzing trace with hash 384100168, now seen corresponding path program 1 times [2021-01-06 19:29:21,407 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:21,407 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488447433] [2021-01-06 19:29:21,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:21,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:21,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:21,478 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [488447433] [2021-01-06 19:29:21,479 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:21,480 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:29:21,480 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [850282592] [2021-01-06 19:29:21,481 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:29:21,481 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:21,487 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:29:21,492 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:29:21,492 INFO L87 Difference]: Start difference. First operand 216 states and 352 transitions. Second operand 4 states. [2021-01-06 19:29:21,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:21,610 INFO L93 Difference]: Finished difference Result 737 states and 1201 transitions. [2021-01-06 19:29:21,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:29:21,611 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2021-01-06 19:29:21,611 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:21,615 INFO L225 Difference]: With dead ends: 737 [2021-01-06 19:29:21,616 INFO L226 Difference]: Without dead ends: 534 [2021-01-06 19:29:21,618 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:29:21,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 534 states. [2021-01-06 19:29:21,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 534 to 351. [2021-01-06 19:29:21,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 351 states. [2021-01-06 19:29:21,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 351 states to 351 states and 571 transitions. [2021-01-06 19:29:21,656 INFO L78 Accepts]: Start accepts. Automaton has 351 states and 571 transitions. Word has length 36 [2021-01-06 19:29:21,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:21,657 INFO L481 AbstractCegarLoop]: Abstraction has 351 states and 571 transitions. [2021-01-06 19:29:21,657 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:29:21,657 INFO L276 IsEmpty]: Start isEmpty. Operand 351 states and 571 transitions. [2021-01-06 19:29:21,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2021-01-06 19:29:21,659 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:21,660 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:21,660 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2021-01-06 19:29:21,661 INFO L429 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:21,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:21,661 INFO L82 PathProgramCache]: Analyzing trace with hash 250086662, now seen corresponding path program 1 times [2021-01-06 19:29:21,662 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:21,662 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189298480] [2021-01-06 19:29:21,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:21,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:21,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:21,718 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [189298480] [2021-01-06 19:29:21,718 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:21,718 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:21,718 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [685848445] [2021-01-06 19:29:21,719 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:21,719 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:21,720 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:21,720 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:21,720 INFO L87 Difference]: Start difference. First operand 351 states and 571 transitions. Second operand 3 states. [2021-01-06 19:29:21,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:21,769 INFO L93 Difference]: Finished difference Result 838 states and 1368 transitions. [2021-01-06 19:29:21,774 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:21,774 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2021-01-06 19:29:21,775 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:21,777 INFO L225 Difference]: With dead ends: 838 [2021-01-06 19:29:21,777 INFO L226 Difference]: Without dead ends: 511 [2021-01-06 19:29:21,778 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:21,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 511 states. [2021-01-06 19:29:21,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 511 to 507. [2021-01-06 19:29:21,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 507 states. [2021-01-06 19:29:21,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 507 states to 507 states and 825 transitions. [2021-01-06 19:29:21,810 INFO L78 Accepts]: Start accepts. Automaton has 507 states and 825 transitions. Word has length 36 [2021-01-06 19:29:21,810 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:21,810 INFO L481 AbstractCegarLoop]: Abstraction has 507 states and 825 transitions. [2021-01-06 19:29:21,810 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:21,810 INFO L276 IsEmpty]: Start isEmpty. Operand 507 states and 825 transitions. [2021-01-06 19:29:21,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2021-01-06 19:29:21,811 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:21,811 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:21,812 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2021-01-06 19:29:21,812 INFO L429 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:21,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:21,812 INFO L82 PathProgramCache]: Analyzing trace with hash 1539792002, now seen corresponding path program 1 times [2021-01-06 19:29:21,813 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:21,813 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902938261] [2021-01-06 19:29:21,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:21,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:21,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:21,849 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [902938261] [2021-01-06 19:29:21,850 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:21,850 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:29:21,850 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [331083692] [2021-01-06 19:29:21,850 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:29:21,851 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:21,851 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:29:21,852 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:29:21,852 INFO L87 Difference]: Start difference. First operand 507 states and 825 transitions. Second operand 4 states. [2021-01-06 19:29:21,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:21,966 INFO L93 Difference]: Finished difference Result 1293 states and 2104 transitions. [2021-01-06 19:29:21,966 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-01-06 19:29:21,966 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2021-01-06 19:29:21,967 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:21,971 INFO L225 Difference]: With dead ends: 1293 [2021-01-06 19:29:21,971 INFO L226 Difference]: Without dead ends: 803 [2021-01-06 19:29:21,973 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:29:21,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 803 states. [2021-01-06 19:29:22,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 803 to 507. [2021-01-06 19:29:22,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 507 states. [2021-01-06 19:29:22,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 507 states to 507 states and 817 transitions. [2021-01-06 19:29:22,029 INFO L78 Accepts]: Start accepts. Automaton has 507 states and 817 transitions. Word has length 36 [2021-01-06 19:29:22,029 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:22,029 INFO L481 AbstractCegarLoop]: Abstraction has 507 states and 817 transitions. [2021-01-06 19:29:22,030 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:29:22,030 INFO L276 IsEmpty]: Start isEmpty. Operand 507 states and 817 transitions. [2021-01-06 19:29:22,030 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2021-01-06 19:29:22,030 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:22,031 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:22,031 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2021-01-06 19:29:22,031 INFO L429 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:22,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:22,032 INFO L82 PathProgramCache]: Analyzing trace with hash -48555900, now seen corresponding path program 1 times [2021-01-06 19:29:22,032 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:22,032 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [754604312] [2021-01-06 19:29:22,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:22,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:22,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:22,068 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [754604312] [2021-01-06 19:29:22,068 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:22,068 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:29:22,068 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1214901848] [2021-01-06 19:29:22,069 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:29:22,069 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:22,069 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:29:22,070 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:29:22,070 INFO L87 Difference]: Start difference. First operand 507 states and 817 transitions. Second operand 4 states. [2021-01-06 19:29:22,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:22,196 INFO L93 Difference]: Finished difference Result 1289 states and 2077 transitions. [2021-01-06 19:29:22,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-01-06 19:29:22,197 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2021-01-06 19:29:22,197 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:22,205 INFO L225 Difference]: With dead ends: 1289 [2021-01-06 19:29:22,205 INFO L226 Difference]: Without dead ends: 805 [2021-01-06 19:29:22,206 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:29:22,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 805 states. [2021-01-06 19:29:22,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 805 to 507. [2021-01-06 19:29:22,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 507 states. [2021-01-06 19:29:22,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 507 states to 507 states and 809 transitions. [2021-01-06 19:29:22,292 INFO L78 Accepts]: Start accepts. Automaton has 507 states and 809 transitions. Word has length 36 [2021-01-06 19:29:22,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:22,293 INFO L481 AbstractCegarLoop]: Abstraction has 507 states and 809 transitions. [2021-01-06 19:29:22,293 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:29:22,293 INFO L276 IsEmpty]: Start isEmpty. Operand 507 states and 809 transitions. [2021-01-06 19:29:22,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2021-01-06 19:29:22,294 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:22,294 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:22,296 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2021-01-06 19:29:22,296 INFO L429 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:22,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:22,297 INFO L82 PathProgramCache]: Analyzing trace with hash -1328419578, now seen corresponding path program 1 times [2021-01-06 19:29:22,297 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:22,298 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1020478042] [2021-01-06 19:29:22,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:22,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:22,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:22,351 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1020478042] [2021-01-06 19:29:22,351 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:22,351 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:29:22,351 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [227086201] [2021-01-06 19:29:22,352 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:29:22,352 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:22,353 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:29:22,353 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:29:22,353 INFO L87 Difference]: Start difference. First operand 507 states and 809 transitions. Second operand 4 states. [2021-01-06 19:29:22,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:22,469 INFO L93 Difference]: Finished difference Result 1226 states and 1951 transitions. [2021-01-06 19:29:22,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-01-06 19:29:22,469 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2021-01-06 19:29:22,470 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:22,474 INFO L225 Difference]: With dead ends: 1226 [2021-01-06 19:29:22,475 INFO L226 Difference]: Without dead ends: 736 [2021-01-06 19:29:22,477 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:29:22,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 736 states. [2021-01-06 19:29:22,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 736 to 555. [2021-01-06 19:29:22,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 555 states. [2021-01-06 19:29:22,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 866 transitions. [2021-01-06 19:29:22,524 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 866 transitions. Word has length 36 [2021-01-06 19:29:22,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:22,525 INFO L481 AbstractCegarLoop]: Abstraction has 555 states and 866 transitions. [2021-01-06 19:29:22,525 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:29:22,525 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 866 transitions. [2021-01-06 19:29:22,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2021-01-06 19:29:22,526 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:22,526 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:22,526 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2021-01-06 19:29:22,526 INFO L429 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:22,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:22,527 INFO L82 PathProgramCache]: Analyzing trace with hash -1915225592, now seen corresponding path program 1 times [2021-01-06 19:29:22,527 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:22,528 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37696109] [2021-01-06 19:29:22,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:22,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:22,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:22,603 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37696109] [2021-01-06 19:29:22,604 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:22,604 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:22,604 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1295746224] [2021-01-06 19:29:22,605 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:22,605 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:22,605 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:22,606 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:22,606 INFO L87 Difference]: Start difference. First operand 555 states and 866 transitions. Second operand 3 states. [2021-01-06 19:29:22,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:22,718 INFO L93 Difference]: Finished difference Result 1316 states and 2058 transitions. [2021-01-06 19:29:22,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:22,718 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2021-01-06 19:29:22,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:22,723 INFO L225 Difference]: With dead ends: 1316 [2021-01-06 19:29:22,723 INFO L226 Difference]: Without dead ends: 775 [2021-01-06 19:29:22,724 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:22,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 775 states. [2021-01-06 19:29:22,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 775 to 772. [2021-01-06 19:29:22,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 772 states. [2021-01-06 19:29:22,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 772 states to 772 states and 1190 transitions. [2021-01-06 19:29:22,777 INFO L78 Accepts]: Start accepts. Automaton has 772 states and 1190 transitions. Word has length 36 [2021-01-06 19:29:22,779 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:22,780 INFO L481 AbstractCegarLoop]: Abstraction has 772 states and 1190 transitions. [2021-01-06 19:29:22,780 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:22,780 INFO L276 IsEmpty]: Start isEmpty. Operand 772 states and 1190 transitions. [2021-01-06 19:29:22,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2021-01-06 19:29:22,781 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:22,781 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:22,781 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2021-01-06 19:29:22,782 INFO L429 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:22,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:22,782 INFO L82 PathProgramCache]: Analyzing trace with hash -547155332, now seen corresponding path program 1 times [2021-01-06 19:29:22,783 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:22,783 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699706472] [2021-01-06 19:29:22,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:22,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:22,830 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:22,831 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1699706472] [2021-01-06 19:29:22,831 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:22,831 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:22,831 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1938718405] [2021-01-06 19:29:22,832 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:22,832 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:22,833 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:22,833 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:22,833 INFO L87 Difference]: Start difference. First operand 772 states and 1190 transitions. Second operand 3 states. [2021-01-06 19:29:22,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:22,941 INFO L93 Difference]: Finished difference Result 1906 states and 2978 transitions. [2021-01-06 19:29:22,941 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:22,942 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2021-01-06 19:29:22,942 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:22,949 INFO L225 Difference]: With dead ends: 1906 [2021-01-06 19:29:22,949 INFO L226 Difference]: Without dead ends: 1161 [2021-01-06 19:29:22,956 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:22,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1161 states. [2021-01-06 19:29:23,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1161 to 1157. [2021-01-06 19:29:23,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1157 states. [2021-01-06 19:29:23,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1157 states to 1157 states and 1801 transitions. [2021-01-06 19:29:23,048 INFO L78 Accepts]: Start accepts. Automaton has 1157 states and 1801 transitions. Word has length 46 [2021-01-06 19:29:23,049 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:23,052 INFO L481 AbstractCegarLoop]: Abstraction has 1157 states and 1801 transitions. [2021-01-06 19:29:23,052 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:23,053 INFO L276 IsEmpty]: Start isEmpty. Operand 1157 states and 1801 transitions. [2021-01-06 19:29:23,054 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2021-01-06 19:29:23,061 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:23,061 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:23,062 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2021-01-06 19:29:23,062 INFO L429 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:23,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:23,063 INFO L82 PathProgramCache]: Analyzing trace with hash -299008838, now seen corresponding path program 1 times [2021-01-06 19:29:23,063 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:23,063 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577805913] [2021-01-06 19:29:23,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:23,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:23,110 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2021-01-06 19:29:23,111 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577805913] [2021-01-06 19:29:23,111 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:23,112 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:23,112 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1122948807] [2021-01-06 19:29:23,113 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:23,114 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:23,114 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:23,114 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:23,115 INFO L87 Difference]: Start difference. First operand 1157 states and 1801 transitions. Second operand 3 states. [2021-01-06 19:29:23,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:23,219 INFO L93 Difference]: Finished difference Result 2265 states and 3543 transitions. [2021-01-06 19:29:23,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:23,220 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 46 [2021-01-06 19:29:23,220 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:23,226 INFO L225 Difference]: With dead ends: 2265 [2021-01-06 19:29:23,226 INFO L226 Difference]: Without dead ends: 1135 [2021-01-06 19:29:23,228 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:23,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1135 states. [2021-01-06 19:29:23,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1135 to 1135. [2021-01-06 19:29:23,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1135 states. [2021-01-06 19:29:23,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1135 states to 1135 states and 1774 transitions. [2021-01-06 19:29:23,311 INFO L78 Accepts]: Start accepts. Automaton has 1135 states and 1774 transitions. Word has length 46 [2021-01-06 19:29:23,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:23,311 INFO L481 AbstractCegarLoop]: Abstraction has 1135 states and 1774 transitions. [2021-01-06 19:29:23,311 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:23,311 INFO L276 IsEmpty]: Start isEmpty. Operand 1135 states and 1774 transitions. [2021-01-06 19:29:23,312 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2021-01-06 19:29:23,312 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:23,313 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:23,313 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2021-01-06 19:29:23,313 INFO L429 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:23,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:23,314 INFO L82 PathProgramCache]: Analyzing trace with hash -336670593, now seen corresponding path program 1 times [2021-01-06 19:29:23,314 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:23,314 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [465705843] [2021-01-06 19:29:23,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:23,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:23,344 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:23,345 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [465705843] [2021-01-06 19:29:23,345 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:23,345 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:23,346 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [597550433] [2021-01-06 19:29:23,346 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:23,346 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:23,347 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:23,347 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:23,347 INFO L87 Difference]: Start difference. First operand 1135 states and 1774 transitions. Second operand 3 states. [2021-01-06 19:29:23,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:23,520 INFO L93 Difference]: Finished difference Result 2891 states and 4579 transitions. [2021-01-06 19:29:23,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:23,521 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2021-01-06 19:29:23,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:23,534 INFO L225 Difference]: With dead ends: 2891 [2021-01-06 19:29:23,535 INFO L226 Difference]: Without dead ends: 1783 [2021-01-06 19:29:23,542 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:23,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1783 states. [2021-01-06 19:29:23,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1783 to 1779. [2021-01-06 19:29:23,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1779 states. [2021-01-06 19:29:23,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1779 states to 1779 states and 2808 transitions. [2021-01-06 19:29:23,759 INFO L78 Accepts]: Start accepts. Automaton has 1779 states and 2808 transitions. Word has length 47 [2021-01-06 19:29:23,760 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:23,761 INFO L481 AbstractCegarLoop]: Abstraction has 1779 states and 2808 transitions. [2021-01-06 19:29:23,761 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:23,761 INFO L276 IsEmpty]: Start isEmpty. Operand 1779 states and 2808 transitions. [2021-01-06 19:29:23,762 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2021-01-06 19:29:23,763 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:23,763 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:23,763 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2021-01-06 19:29:23,763 INFO L429 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:23,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:23,764 INFO L82 PathProgramCache]: Analyzing trace with hash 1825522215, now seen corresponding path program 1 times [2021-01-06 19:29:23,764 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:23,765 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [480858848] [2021-01-06 19:29:23,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:23,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:23,831 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:23,832 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [480858848] [2021-01-06 19:29:23,834 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:23,835 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:23,835 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378149652] [2021-01-06 19:29:23,835 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:23,836 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:23,836 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:23,837 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:23,837 INFO L87 Difference]: Start difference. First operand 1779 states and 2808 transitions. Second operand 3 states. [2021-01-06 19:29:24,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:24,097 INFO L93 Difference]: Finished difference Result 4794 states and 7664 transitions. [2021-01-06 19:29:24,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:24,097 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2021-01-06 19:29:24,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:24,115 INFO L225 Difference]: With dead ends: 4794 [2021-01-06 19:29:24,116 INFO L226 Difference]: Without dead ends: 3044 [2021-01-06 19:29:24,120 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:24,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3044 states. [2021-01-06 19:29:24,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3044 to 3040. [2021-01-06 19:29:24,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3040 states. [2021-01-06 19:29:24,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3040 states to 3040 states and 4843 transitions. [2021-01-06 19:29:24,407 INFO L78 Accepts]: Start accepts. Automaton has 3040 states and 4843 transitions. Word has length 48 [2021-01-06 19:29:24,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:24,408 INFO L481 AbstractCegarLoop]: Abstraction has 3040 states and 4843 transitions. [2021-01-06 19:29:24,408 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:24,408 INFO L276 IsEmpty]: Start isEmpty. Operand 3040 states and 4843 transitions. [2021-01-06 19:29:24,410 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2021-01-06 19:29:24,410 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:24,410 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:24,410 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2021-01-06 19:29:24,411 INFO L429 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:24,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:24,411 INFO L82 PathProgramCache]: Analyzing trace with hash 2073668709, now seen corresponding path program 1 times [2021-01-06 19:29:24,411 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:24,412 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1185570144] [2021-01-06 19:29:24,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:24,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:24,448 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2021-01-06 19:29:24,449 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1185570144] [2021-01-06 19:29:24,449 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:24,451 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:24,452 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590230486] [2021-01-06 19:29:24,453 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:24,453 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:24,454 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:24,454 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:24,455 INFO L87 Difference]: Start difference. First operand 3040 states and 4843 transitions. Second operand 3 states. [2021-01-06 19:29:24,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:24,739 INFO L93 Difference]: Finished difference Result 6029 states and 9627 transitions. [2021-01-06 19:29:24,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:24,739 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2021-01-06 19:29:24,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:24,755 INFO L225 Difference]: With dead ends: 6029 [2021-01-06 19:29:24,755 INFO L226 Difference]: Without dead ends: 3018 [2021-01-06 19:29:24,762 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:24,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3018 states. [2021-01-06 19:29:24,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3018 to 3018. [2021-01-06 19:29:24,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3018 states. [2021-01-06 19:29:25,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3018 states to 3018 states and 4817 transitions. [2021-01-06 19:29:25,004 INFO L78 Accepts]: Start accepts. Automaton has 3018 states and 4817 transitions. Word has length 48 [2021-01-06 19:29:25,004 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:25,004 INFO L481 AbstractCegarLoop]: Abstraction has 3018 states and 4817 transitions. [2021-01-06 19:29:25,004 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:25,004 INFO L276 IsEmpty]: Start isEmpty. Operand 3018 states and 4817 transitions. [2021-01-06 19:29:25,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2021-01-06 19:29:25,006 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:25,006 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:25,006 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2021-01-06 19:29:25,006 INFO L429 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:25,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:25,007 INFO L82 PathProgramCache]: Analyzing trace with hash 963117268, now seen corresponding path program 1 times [2021-01-06 19:29:25,007 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:25,008 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450844022] [2021-01-06 19:29:25,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:25,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:25,047 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:25,047 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450844022] [2021-01-06 19:29:25,048 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:25,048 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:29:25,053 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923565230] [2021-01-06 19:29:25,055 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:29:25,055 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:25,056 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:29:25,056 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:29:25,056 INFO L87 Difference]: Start difference. First operand 3018 states and 4817 transitions. Second operand 4 states. [2021-01-06 19:29:25,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:25,554 INFO L93 Difference]: Finished difference Result 7617 states and 12199 transitions. [2021-01-06 19:29:25,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:29:25,555 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 49 [2021-01-06 19:29:25,556 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:25,576 INFO L225 Difference]: With dead ends: 7617 [2021-01-06 19:29:25,576 INFO L226 Difference]: Without dead ends: 3895 [2021-01-06 19:29:25,582 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:29:25,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3895 states. [2021-01-06 19:29:25,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3895 to 3895. [2021-01-06 19:29:25,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3895 states. [2021-01-06 19:29:25,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3895 states to 3895 states and 6183 transitions. [2021-01-06 19:29:25,929 INFO L78 Accepts]: Start accepts. Automaton has 3895 states and 6183 transitions. Word has length 49 [2021-01-06 19:29:25,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:25,929 INFO L481 AbstractCegarLoop]: Abstraction has 3895 states and 6183 transitions. [2021-01-06 19:29:25,929 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:29:25,929 INFO L276 IsEmpty]: Start isEmpty. Operand 3895 states and 6183 transitions. [2021-01-06 19:29:25,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2021-01-06 19:29:25,932 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:25,932 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:25,932 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2021-01-06 19:29:25,932 INFO L429 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:25,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:25,933 INFO L82 PathProgramCache]: Analyzing trace with hash -1671888881, now seen corresponding path program 1 times [2021-01-06 19:29:25,933 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:25,933 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1062797769] [2021-01-06 19:29:25,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:25,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:25,973 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:25,973 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1062797769] [2021-01-06 19:29:25,973 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:25,973 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-01-06 19:29:25,974 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [694057239] [2021-01-06 19:29:25,974 INFO L461 AbstractCegarLoop]: Interpolant automaton has 5 states [2021-01-06 19:29:25,974 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:25,975 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-01-06 19:29:25,975 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:29:25,975 INFO L87 Difference]: Start difference. First operand 3895 states and 6183 transitions. Second operand 5 states. [2021-01-06 19:29:26,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:26,618 INFO L93 Difference]: Finished difference Result 9940 states and 15662 transitions. [2021-01-06 19:29:26,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-01-06 19:29:26,619 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 54 [2021-01-06 19:29:26,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:26,667 INFO L225 Difference]: With dead ends: 9940 [2021-01-06 19:29:26,667 INFO L226 Difference]: Without dead ends: 6068 [2021-01-06 19:29:26,674 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-01-06 19:29:26,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6068 states. [2021-01-06 19:29:27,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6068 to 4554. [2021-01-06 19:29:27,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4554 states. [2021-01-06 19:29:27,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4554 states to 4554 states and 7072 transitions. [2021-01-06 19:29:27,122 INFO L78 Accepts]: Start accepts. Automaton has 4554 states and 7072 transitions. Word has length 54 [2021-01-06 19:29:27,122 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:27,122 INFO L481 AbstractCegarLoop]: Abstraction has 4554 states and 7072 transitions. [2021-01-06 19:29:27,122 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2021-01-06 19:29:27,122 INFO L276 IsEmpty]: Start isEmpty. Operand 4554 states and 7072 transitions. [2021-01-06 19:29:27,126 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2021-01-06 19:29:27,127 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:27,127 INFO L422 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:27,127 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2021-01-06 19:29:27,127 INFO L429 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:27,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:27,128 INFO L82 PathProgramCache]: Analyzing trace with hash -2128152978, now seen corresponding path program 1 times [2021-01-06 19:29:27,128 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:27,128 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1018730531] [2021-01-06 19:29:27,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:27,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:27,187 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:27,189 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1018730531] [2021-01-06 19:29:27,189 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:27,189 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:27,189 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1110128687] [2021-01-06 19:29:27,190 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:27,190 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:27,190 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:27,190 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:27,191 INFO L87 Difference]: Start difference. First operand 4554 states and 7072 transitions. Second operand 3 states. [2021-01-06 19:29:27,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:27,671 INFO L93 Difference]: Finished difference Result 9431 states and 14610 transitions. [2021-01-06 19:29:27,671 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:27,671 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 86 [2021-01-06 19:29:27,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:27,695 INFO L225 Difference]: With dead ends: 9431 [2021-01-06 19:29:27,696 INFO L226 Difference]: Without dead ends: 4906 [2021-01-06 19:29:27,705 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:27,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4906 states. [2021-01-06 19:29:28,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4906 to 4874. [2021-01-06 19:29:28,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4874 states. [2021-01-06 19:29:28,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4874 states to 4874 states and 7321 transitions. [2021-01-06 19:29:28,255 INFO L78 Accepts]: Start accepts. Automaton has 4874 states and 7321 transitions. Word has length 86 [2021-01-06 19:29:28,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:28,255 INFO L481 AbstractCegarLoop]: Abstraction has 4874 states and 7321 transitions. [2021-01-06 19:29:28,255 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:28,255 INFO L276 IsEmpty]: Start isEmpty. Operand 4874 states and 7321 transitions. [2021-01-06 19:29:28,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2021-01-06 19:29:28,260 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:28,261 INFO L422 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:28,261 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2021-01-06 19:29:28,261 INFO L429 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:28,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:28,262 INFO L82 PathProgramCache]: Analyzing trace with hash 1520792899, now seen corresponding path program 1 times [2021-01-06 19:29:28,263 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:28,263 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413307373] [2021-01-06 19:29:28,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:28,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:28,312 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:28,312 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [413307373] [2021-01-06 19:29:28,313 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:28,313 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:28,315 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1648438702] [2021-01-06 19:29:28,316 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:28,316 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:28,316 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:28,317 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:28,317 INFO L87 Difference]: Start difference. First operand 4874 states and 7321 transitions. Second operand 3 states. [2021-01-06 19:29:28,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:28,769 INFO L93 Difference]: Finished difference Result 10229 states and 15320 transitions. [2021-01-06 19:29:28,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:28,769 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 87 [2021-01-06 19:29:28,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:28,783 INFO L225 Difference]: With dead ends: 10229 [2021-01-06 19:29:28,784 INFO L226 Difference]: Without dead ends: 5396 [2021-01-06 19:29:28,793 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:28,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5396 states. [2021-01-06 19:29:29,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5396 to 5348. [2021-01-06 19:29:29,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5348 states. [2021-01-06 19:29:29,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5348 states to 5348 states and 7764 transitions. [2021-01-06 19:29:29,248 INFO L78 Accepts]: Start accepts. Automaton has 5348 states and 7764 transitions. Word has length 87 [2021-01-06 19:29:29,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:29,249 INFO L481 AbstractCegarLoop]: Abstraction has 5348 states and 7764 transitions. [2021-01-06 19:29:29,249 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:29,249 INFO L276 IsEmpty]: Start isEmpty. Operand 5348 states and 7764 transitions. [2021-01-06 19:29:29,254 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2021-01-06 19:29:29,254 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:29,255 INFO L422 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:29,255 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2021-01-06 19:29:29,255 INFO L429 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:29,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:29,256 INFO L82 PathProgramCache]: Analyzing trace with hash -1973365524, now seen corresponding path program 1 times [2021-01-06 19:29:29,256 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:29,256 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1401539540] [2021-01-06 19:29:29,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:29,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:29,292 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:29:29,293 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1401539540] [2021-01-06 19:29:29,293 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:29,293 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:29,293 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [555853440] [2021-01-06 19:29:29,294 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:29,294 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:29,294 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:29,294 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:29,295 INFO L87 Difference]: Start difference. First operand 5348 states and 7764 transitions. Second operand 3 states. [2021-01-06 19:29:29,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:29,905 INFO L93 Difference]: Finished difference Result 11003 states and 15979 transitions. [2021-01-06 19:29:29,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:29,906 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 88 [2021-01-06 19:29:29,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:29,921 INFO L225 Difference]: With dead ends: 11003 [2021-01-06 19:29:29,922 INFO L226 Difference]: Without dead ends: 5716 [2021-01-06 19:29:29,933 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:29,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5716 states. [2021-01-06 19:29:30,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5716 to 5130. [2021-01-06 19:29:30,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5130 states. [2021-01-06 19:29:30,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5130 states to 5130 states and 7126 transitions. [2021-01-06 19:29:30,549 INFO L78 Accepts]: Start accepts. Automaton has 5130 states and 7126 transitions. Word has length 88 [2021-01-06 19:29:30,550 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:30,550 INFO L481 AbstractCegarLoop]: Abstraction has 5130 states and 7126 transitions. [2021-01-06 19:29:30,550 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:30,550 INFO L276 IsEmpty]: Start isEmpty. Operand 5130 states and 7126 transitions. [2021-01-06 19:29:30,556 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2021-01-06 19:29:30,556 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:30,556 INFO L422 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:30,557 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2021-01-06 19:29:30,557 INFO L429 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:30,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:30,558 INFO L82 PathProgramCache]: Analyzing trace with hash 663253701, now seen corresponding path program 1 times [2021-01-06 19:29:30,558 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:30,559 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77008059] [2021-01-06 19:29:30,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:30,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:30,627 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-01-06 19:29:30,628 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [77008059] [2021-01-06 19:29:30,628 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:30,628 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:29:30,630 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988856808] [2021-01-06 19:29:30,630 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:29:30,633 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:30,633 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:29:30,634 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:29:30,634 INFO L87 Difference]: Start difference. First operand 5130 states and 7126 transitions. Second operand 4 states. [2021-01-06 19:29:31,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:31,360 INFO L93 Difference]: Finished difference Result 9554 states and 13184 transitions. [2021-01-06 19:29:31,361 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:29:31,361 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 89 [2021-01-06 19:29:31,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:31,374 INFO L225 Difference]: With dead ends: 9554 [2021-01-06 19:29:31,374 INFO L226 Difference]: Without dead ends: 4875 [2021-01-06 19:29:31,382 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:29:31,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4875 states. [2021-01-06 19:29:31,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4875 to 4759. [2021-01-06 19:29:31,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4759 states. [2021-01-06 19:29:31,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4759 states to 4759 states and 6364 transitions. [2021-01-06 19:29:31,691 INFO L78 Accepts]: Start accepts. Automaton has 4759 states and 6364 transitions. Word has length 89 [2021-01-06 19:29:31,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:31,691 INFO L481 AbstractCegarLoop]: Abstraction has 4759 states and 6364 transitions. [2021-01-06 19:29:31,691 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:29:31,691 INFO L276 IsEmpty]: Start isEmpty. Operand 4759 states and 6364 transitions. [2021-01-06 19:29:31,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2021-01-06 19:29:31,704 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:31,704 INFO L422 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:31,704 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2021-01-06 19:29:31,704 INFO L429 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:31,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:31,705 INFO L82 PathProgramCache]: Analyzing trace with hash 1690650567, now seen corresponding path program 1 times [2021-01-06 19:29:31,705 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:31,705 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [968071578] [2021-01-06 19:29:31,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:31,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:31,752 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2021-01-06 19:29:31,752 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [968071578] [2021-01-06 19:29:31,753 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:31,753 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:31,753 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074427122] [2021-01-06 19:29:31,753 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:31,754 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:31,754 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:31,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:31,755 INFO L87 Difference]: Start difference. First operand 4759 states and 6364 transitions. Second operand 3 states. [2021-01-06 19:29:32,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:32,295 INFO L93 Difference]: Finished difference Result 9073 states and 12125 transitions. [2021-01-06 19:29:32,296 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:32,296 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 116 [2021-01-06 19:29:32,296 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:32,307 INFO L225 Difference]: With dead ends: 9073 [2021-01-06 19:29:32,307 INFO L226 Difference]: Without dead ends: 4705 [2021-01-06 19:29:32,313 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:32,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4705 states. [2021-01-06 19:29:32,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4705 to 4705. [2021-01-06 19:29:32,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4705 states. [2021-01-06 19:29:32,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4705 states to 4705 states and 6258 transitions. [2021-01-06 19:29:32,625 INFO L78 Accepts]: Start accepts. Automaton has 4705 states and 6258 transitions. Word has length 116 [2021-01-06 19:29:32,625 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:32,625 INFO L481 AbstractCegarLoop]: Abstraction has 4705 states and 6258 transitions. [2021-01-06 19:29:32,626 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:32,626 INFO L276 IsEmpty]: Start isEmpty. Operand 4705 states and 6258 transitions. [2021-01-06 19:29:32,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2021-01-06 19:29:32,637 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:32,637 INFO L422 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:32,637 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23 [2021-01-06 19:29:32,637 INFO L429 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:32,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:32,638 INFO L82 PathProgramCache]: Analyzing trace with hash 762576065, now seen corresponding path program 1 times [2021-01-06 19:29:32,639 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:32,639 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877651262] [2021-01-06 19:29:32,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:32,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:32,701 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 43 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2021-01-06 19:29:32,701 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [877651262] [2021-01-06 19:29:32,701 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:32,702 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:29:32,702 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647175116] [2021-01-06 19:29:32,702 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:29:32,702 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:32,703 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:29:32,703 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:29:32,703 INFO L87 Difference]: Start difference. First operand 4705 states and 6258 transitions. Second operand 4 states. [2021-01-06 19:29:33,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:33,070 INFO L93 Difference]: Finished difference Result 8363 states and 11148 transitions. [2021-01-06 19:29:33,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:29:33,071 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 128 [2021-01-06 19:29:33,071 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:33,081 INFO L225 Difference]: With dead ends: 8363 [2021-01-06 19:29:33,081 INFO L226 Difference]: Without dead ends: 4627 [2021-01-06 19:29:33,088 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:29:33,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4627 states. [2021-01-06 19:29:33,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4627 to 4623. [2021-01-06 19:29:33,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4623 states. [2021-01-06 19:29:33,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4623 states to 4623 states and 6037 transitions. [2021-01-06 19:29:33,524 INFO L78 Accepts]: Start accepts. Automaton has 4623 states and 6037 transitions. Word has length 128 [2021-01-06 19:29:33,524 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:33,524 INFO L481 AbstractCegarLoop]: Abstraction has 4623 states and 6037 transitions. [2021-01-06 19:29:33,524 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:29:33,524 INFO L276 IsEmpty]: Start isEmpty. Operand 4623 states and 6037 transitions. [2021-01-06 19:29:33,539 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2021-01-06 19:29:33,539 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:33,539 INFO L422 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:33,539 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24 [2021-01-06 19:29:33,540 INFO L429 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:33,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:33,540 INFO L82 PathProgramCache]: Analyzing trace with hash 843157933, now seen corresponding path program 1 times [2021-01-06 19:29:33,540 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:33,541 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132016918] [2021-01-06 19:29:33,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:33,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:33,591 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2021-01-06 19:29:33,592 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [132016918] [2021-01-06 19:29:33,592 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:33,592 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:33,592 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1263943897] [2021-01-06 19:29:33,593 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:33,593 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:33,594 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:33,594 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:33,594 INFO L87 Difference]: Start difference. First operand 4623 states and 6037 transitions. Second operand 3 states. [2021-01-06 19:29:33,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:33,902 INFO L93 Difference]: Finished difference Result 8859 states and 11562 transitions. [2021-01-06 19:29:33,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:33,902 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 134 [2021-01-06 19:29:33,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:33,912 INFO L225 Difference]: With dead ends: 8859 [2021-01-06 19:29:33,912 INFO L226 Difference]: Without dead ends: 4622 [2021-01-06 19:29:33,920 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:33,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4622 states. [2021-01-06 19:29:34,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4622 to 4582. [2021-01-06 19:29:34,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4582 states. [2021-01-06 19:29:34,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4582 states to 4582 states and 5954 transitions. [2021-01-06 19:29:34,450 INFO L78 Accepts]: Start accepts. Automaton has 4582 states and 5954 transitions. Word has length 134 [2021-01-06 19:29:34,450 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:34,450 INFO L481 AbstractCegarLoop]: Abstraction has 4582 states and 5954 transitions. [2021-01-06 19:29:34,451 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:34,451 INFO L276 IsEmpty]: Start isEmpty. Operand 4582 states and 5954 transitions. [2021-01-06 19:29:34,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2021-01-06 19:29:34,461 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:34,461 INFO L422 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:34,462 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable25 [2021-01-06 19:29:34,462 INFO L429 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:34,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:34,462 INFO L82 PathProgramCache]: Analyzing trace with hash 713131341, now seen corresponding path program 1 times [2021-01-06 19:29:34,463 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:34,463 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459417312] [2021-01-06 19:29:34,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:34,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:34,525 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 36 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2021-01-06 19:29:34,526 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1459417312] [2021-01-06 19:29:34,526 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:34,526 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:34,526 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [453194871] [2021-01-06 19:29:34,527 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:34,527 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:34,527 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:34,528 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:34,528 INFO L87 Difference]: Start difference. First operand 4582 states and 5954 transitions. Second operand 3 states. [2021-01-06 19:29:34,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:34,924 INFO L93 Difference]: Finished difference Result 8798 states and 11423 transitions. [2021-01-06 19:29:34,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:34,924 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 134 [2021-01-06 19:29:34,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:34,934 INFO L225 Difference]: With dead ends: 8798 [2021-01-06 19:29:34,934 INFO L226 Difference]: Without dead ends: 4592 [2021-01-06 19:29:34,941 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:34,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4592 states. [2021-01-06 19:29:35,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4592 to 4552. [2021-01-06 19:29:35,620 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4552 states. [2021-01-06 19:29:35,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4552 states to 4552 states and 5883 transitions. [2021-01-06 19:29:35,631 INFO L78 Accepts]: Start accepts. Automaton has 4552 states and 5883 transitions. Word has length 134 [2021-01-06 19:29:35,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:35,632 INFO L481 AbstractCegarLoop]: Abstraction has 4552 states and 5883 transitions. [2021-01-06 19:29:35,632 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:35,632 INFO L276 IsEmpty]: Start isEmpty. Operand 4552 states and 5883 transitions. [2021-01-06 19:29:35,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2021-01-06 19:29:35,642 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:35,643 INFO L422 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:35,643 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable26 [2021-01-06 19:29:35,643 INFO L429 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:35,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:35,644 INFO L82 PathProgramCache]: Analyzing trace with hash -57826629, now seen corresponding path program 1 times [2021-01-06 19:29:35,645 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:35,645 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [188794153] [2021-01-06 19:29:35,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:35,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:35,722 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-01-06 19:29:35,723 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [188794153] [2021-01-06 19:29:35,723 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:35,724 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:29:35,724 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1492631949] [2021-01-06 19:29:35,724 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:29:35,725 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:35,725 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:29:35,725 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:29:35,726 INFO L87 Difference]: Start difference. First operand 4552 states and 5883 transitions. Second operand 4 states. [2021-01-06 19:29:36,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:36,066 INFO L93 Difference]: Finished difference Result 7397 states and 9599 transitions. [2021-01-06 19:29:36,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:29:36,066 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 137 [2021-01-06 19:29:36,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:36,071 INFO L225 Difference]: With dead ends: 7397 [2021-01-06 19:29:36,071 INFO L226 Difference]: Without dead ends: 3218 [2021-01-06 19:29:36,076 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:29:36,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3218 states. [2021-01-06 19:29:36,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3218 to 3214. [2021-01-06 19:29:36,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3214 states. [2021-01-06 19:29:36,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3214 states to 3214 states and 4065 transitions. [2021-01-06 19:29:36,377 INFO L78 Accepts]: Start accepts. Automaton has 3214 states and 4065 transitions. Word has length 137 [2021-01-06 19:29:36,378 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:36,378 INFO L481 AbstractCegarLoop]: Abstraction has 3214 states and 4065 transitions. [2021-01-06 19:29:36,378 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:29:36,378 INFO L276 IsEmpty]: Start isEmpty. Operand 3214 states and 4065 transitions. [2021-01-06 19:29:36,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2021-01-06 19:29:36,384 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:36,384 INFO L422 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:36,384 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable27 [2021-01-06 19:29:36,385 INFO L429 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:36,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:36,385 INFO L82 PathProgramCache]: Analyzing trace with hash -76782736, now seen corresponding path program 1 times [2021-01-06 19:29:36,386 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:36,386 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1176714793] [2021-01-06 19:29:36,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:36,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:36,491 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 45 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2021-01-06 19:29:36,491 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1176714793] [2021-01-06 19:29:36,491 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:36,492 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:29:36,492 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [565298160] [2021-01-06 19:29:36,492 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:29:36,492 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:36,493 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:29:36,493 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:29:36,493 INFO L87 Difference]: Start difference. First operand 3214 states and 4065 transitions. Second operand 4 states. [2021-01-06 19:29:36,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:36,731 INFO L93 Difference]: Finished difference Result 5216 states and 6609 transitions. [2021-01-06 19:29:36,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:29:36,732 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 137 [2021-01-06 19:29:36,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:36,743 INFO L225 Difference]: With dead ends: 5216 [2021-01-06 19:29:36,743 INFO L226 Difference]: Without dead ends: 2075 [2021-01-06 19:29:36,748 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:29:36,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2075 states. [2021-01-06 19:29:36,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2075 to 2071. [2021-01-06 19:29:36,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2071 states. [2021-01-06 19:29:36,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2071 states to 2071 states and 2543 transitions. [2021-01-06 19:29:36,887 INFO L78 Accepts]: Start accepts. Automaton has 2071 states and 2543 transitions. Word has length 137 [2021-01-06 19:29:36,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:36,887 INFO L481 AbstractCegarLoop]: Abstraction has 2071 states and 2543 transitions. [2021-01-06 19:29:36,887 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:29:36,888 INFO L276 IsEmpty]: Start isEmpty. Operand 2071 states and 2543 transitions. [2021-01-06 19:29:36,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2021-01-06 19:29:36,889 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:36,889 INFO L422 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:36,889 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable28 [2021-01-06 19:29:36,890 INFO L429 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:36,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:36,890 INFO L82 PathProgramCache]: Analyzing trace with hash 373327418, now seen corresponding path program 1 times [2021-01-06 19:29:36,890 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:36,891 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927527633] [2021-01-06 19:29:36,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:36,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:36,950 INFO L134 CoverageAnalysis]: Checked inductivity of 103 backedges. 77 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2021-01-06 19:29:36,951 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [927527633] [2021-01-06 19:29:36,951 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:36,951 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:36,951 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [32801782] [2021-01-06 19:29:36,952 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:36,952 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:36,952 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:36,952 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:36,953 INFO L87 Difference]: Start difference. First operand 2071 states and 2543 transitions. Second operand 3 states. [2021-01-06 19:29:37,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:37,114 INFO L93 Difference]: Finished difference Result 3759 states and 4649 transitions. [2021-01-06 19:29:37,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:37,114 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 176 [2021-01-06 19:29:37,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:37,117 INFO L225 Difference]: With dead ends: 3759 [2021-01-06 19:29:37,117 INFO L226 Difference]: Without dead ends: 2029 [2021-01-06 19:29:37,119 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:37,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2029 states. [2021-01-06 19:29:37,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2029 to 1941. [2021-01-06 19:29:37,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1941 states. [2021-01-06 19:29:37,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1941 states to 1941 states and 2345 transitions. [2021-01-06 19:29:37,249 INFO L78 Accepts]: Start accepts. Automaton has 1941 states and 2345 transitions. Word has length 176 [2021-01-06 19:29:37,249 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:37,249 INFO L481 AbstractCegarLoop]: Abstraction has 1941 states and 2345 transitions. [2021-01-06 19:29:37,250 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:37,250 INFO L276 IsEmpty]: Start isEmpty. Operand 1941 states and 2345 transitions. [2021-01-06 19:29:37,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2021-01-06 19:29:37,251 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:37,251 INFO L422 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:37,251 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29 [2021-01-06 19:29:37,252 INFO L429 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:37,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:37,252 INFO L82 PathProgramCache]: Analyzing trace with hash 1072981429, now seen corresponding path program 1 times [2021-01-06 19:29:37,252 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:37,253 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1180208652] [2021-01-06 19:29:37,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:37,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:37,315 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2021-01-06 19:29:37,316 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1180208652] [2021-01-06 19:29:37,316 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:37,316 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:37,316 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2031231437] [2021-01-06 19:29:37,317 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:37,317 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:37,317 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:37,318 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:37,318 INFO L87 Difference]: Start difference. First operand 1941 states and 2345 transitions. Second operand 3 states. [2021-01-06 19:29:37,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:37,549 INFO L93 Difference]: Finished difference Result 4180 states and 5086 transitions. [2021-01-06 19:29:37,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:37,550 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 182 [2021-01-06 19:29:37,550 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:37,553 INFO L225 Difference]: With dead ends: 4180 [2021-01-06 19:29:37,553 INFO L226 Difference]: Without dead ends: 2576 [2021-01-06 19:29:37,555 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:37,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2576 states. [2021-01-06 19:29:37,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2576 to 2219. [2021-01-06 19:29:37,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2219 states. [2021-01-06 19:29:37,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2219 states to 2219 states and 2645 transitions. [2021-01-06 19:29:37,690 INFO L78 Accepts]: Start accepts. Automaton has 2219 states and 2645 transitions. Word has length 182 [2021-01-06 19:29:37,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:37,691 INFO L481 AbstractCegarLoop]: Abstraction has 2219 states and 2645 transitions. [2021-01-06 19:29:37,691 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:37,691 INFO L276 IsEmpty]: Start isEmpty. Operand 2219 states and 2645 transitions. [2021-01-06 19:29:37,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2021-01-06 19:29:37,692 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:37,693 INFO L422 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:37,693 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30 [2021-01-06 19:29:37,693 INFO L429 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:37,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:37,694 INFO L82 PathProgramCache]: Analyzing trace with hash 1005799718, now seen corresponding path program 1 times [2021-01-06 19:29:37,694 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:37,694 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782345947] [2021-01-06 19:29:37,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:37,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:37,761 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 79 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2021-01-06 19:29:37,761 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782345947] [2021-01-06 19:29:37,762 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:37,762 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:37,762 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425721298] [2021-01-06 19:29:37,762 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:37,762 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:37,763 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:37,763 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:37,763 INFO L87 Difference]: Start difference. First operand 2219 states and 2645 transitions. Second operand 3 states. [2021-01-06 19:29:37,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:37,936 INFO L93 Difference]: Finished difference Result 3766 states and 4524 transitions. [2021-01-06 19:29:37,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:37,937 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 185 [2021-01-06 19:29:37,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:37,939 INFO L225 Difference]: With dead ends: 3766 [2021-01-06 19:29:37,939 INFO L226 Difference]: Without dead ends: 1882 [2021-01-06 19:29:37,940 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:37,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1882 states. [2021-01-06 19:29:38,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1882 to 1803. [2021-01-06 19:29:38,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1803 states. [2021-01-06 19:29:38,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1803 states to 1803 states and 2119 transitions. [2021-01-06 19:29:38,088 INFO L78 Accepts]: Start accepts. Automaton has 1803 states and 2119 transitions. Word has length 185 [2021-01-06 19:29:38,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:38,088 INFO L481 AbstractCegarLoop]: Abstraction has 1803 states and 2119 transitions. [2021-01-06 19:29:38,088 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:38,088 INFO L276 IsEmpty]: Start isEmpty. Operand 1803 states and 2119 transitions. [2021-01-06 19:29:38,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2021-01-06 19:29:38,089 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:38,090 INFO L422 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:38,090 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable31 [2021-01-06 19:29:38,090 INFO L429 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:38,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:38,091 INFO L82 PathProgramCache]: Analyzing trace with hash -1330592792, now seen corresponding path program 1 times [2021-01-06 19:29:38,091 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:38,091 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1918190484] [2021-01-06 19:29:38,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:38,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:38,159 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 107 trivial. 0 not checked. [2021-01-06 19:29:38,160 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1918190484] [2021-01-06 19:29:38,160 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:29:38,160 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:29:38,160 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1796264978] [2021-01-06 19:29:38,161 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:29:38,161 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:38,161 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:29:38,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:38,162 INFO L87 Difference]: Start difference. First operand 1803 states and 2119 transitions. Second operand 3 states. [2021-01-06 19:29:38,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:38,404 INFO L93 Difference]: Finished difference Result 1817 states and 2136 transitions. [2021-01-06 19:29:38,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:29:38,404 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 185 [2021-01-06 19:29:38,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:38,407 INFO L225 Difference]: With dead ends: 1817 [2021-01-06 19:29:38,407 INFO L226 Difference]: Without dead ends: 1815 [2021-01-06 19:29:38,410 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:29:38,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1815 states. [2021-01-06 19:29:38,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1815 to 1807. [2021-01-06 19:29:38,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1807 states. [2021-01-06 19:29:38,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1807 states to 1807 states and 2123 transitions. [2021-01-06 19:29:38,635 INFO L78 Accepts]: Start accepts. Automaton has 1807 states and 2123 transitions. Word has length 185 [2021-01-06 19:29:38,636 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:38,636 INFO L481 AbstractCegarLoop]: Abstraction has 1807 states and 2123 transitions. [2021-01-06 19:29:38,636 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:29:38,636 INFO L276 IsEmpty]: Start isEmpty. Operand 1807 states and 2123 transitions. [2021-01-06 19:29:38,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2021-01-06 19:29:38,638 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:38,639 INFO L422 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:38,639 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable32 [2021-01-06 19:29:38,639 INFO L429 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:38,639 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:38,640 INFO L82 PathProgramCache]: Analyzing trace with hash -1330591190, now seen corresponding path program 1 times [2021-01-06 19:29:38,640 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:38,643 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572522079] [2021-01-06 19:29:38,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:38,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:39,039 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 0 proven. 96 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2021-01-06 19:29:39,040 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [572522079] [2021-01-06 19:29:39,040 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1908641117] [2021-01-06 19:29:39,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-01-06 19:29:39,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:29:39,207 INFO L263 TraceCheckSpWp]: Trace formula consists of 528 conjuncts, 20 conjunts are in the unsatisfiable core [2021-01-06 19:29:39,239 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-01-06 19:29:39,767 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 81 proven. 15 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2021-01-06 19:29:39,768 INFO L219 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-01-06 19:29:39,768 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10] total 19 [2021-01-06 19:29:39,768 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [772698653] [2021-01-06 19:29:39,769 INFO L461 AbstractCegarLoop]: Interpolant automaton has 19 states [2021-01-06 19:29:39,769 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:29:39,770 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-01-06 19:29:39,770 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=299, Unknown=0, NotChecked=0, Total=342 [2021-01-06 19:29:39,770 INFO L87 Difference]: Start difference. First operand 1807 states and 2123 transitions. Second operand 19 states. [2021-01-06 19:29:41,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:29:41,305 INFO L93 Difference]: Finished difference Result 5673 states and 6674 transitions. [2021-01-06 19:29:41,305 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2021-01-06 19:29:41,306 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 185 [2021-01-06 19:29:41,306 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:29:41,318 INFO L225 Difference]: With dead ends: 5673 [2021-01-06 19:29:41,318 INFO L226 Difference]: Without dead ends: 4128 [2021-01-06 19:29:41,322 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 228 GetRequests, 189 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 244 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=223, Invalid=1417, Unknown=0, NotChecked=0, Total=1640 [2021-01-06 19:29:41,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4128 states. [2021-01-06 19:29:41,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4128 to 2487. [2021-01-06 19:29:41,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2487 states. [2021-01-06 19:29:41,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2487 states to 2487 states and 2916 transitions. [2021-01-06 19:29:41,635 INFO L78 Accepts]: Start accepts. Automaton has 2487 states and 2916 transitions. Word has length 185 [2021-01-06 19:29:41,636 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:29:41,636 INFO L481 AbstractCegarLoop]: Abstraction has 2487 states and 2916 transitions. [2021-01-06 19:29:41,636 INFO L482 AbstractCegarLoop]: Interpolant automaton has 19 states. [2021-01-06 19:29:41,636 INFO L276 IsEmpty]: Start isEmpty. Operand 2487 states and 2916 transitions. [2021-01-06 19:29:41,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2021-01-06 19:29:41,639 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:29:41,640 INFO L422 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:29:41,855 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable33 [2021-01-06 19:29:41,856 INFO L429 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr1ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:29:41,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:29:41,857 INFO L82 PathProgramCache]: Analyzing trace with hash 1701344696, now seen corresponding path program 1 times [2021-01-06 19:29:41,858 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:29:41,858 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126878100] [2021-01-06 19:29:41,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:29:41,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-01-06 19:29:41,890 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-01-06 19:29:41,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-01-06 19:29:41,917 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-01-06 19:29:42,020 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-01-06 19:29:42,020 INFO L523 BasicCegarLoop]: Counterexample might be feasible [2021-01-06 19:29:42,021 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable34 [2021-01-06 19:29:42,350 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 06.01 07:29:42 BoogieIcfgContainer [2021-01-06 19:29:42,351 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2021-01-06 19:29:42,351 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-01-06 19:29:42,351 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-01-06 19:29:42,351 INFO L275 PluginConnector]: Witness Printer initialized [2021-01-06 19:29:42,352 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.01 07:29:19" (3/4) ... [2021-01-06 19:29:42,354 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2021-01-06 19:29:42,644 INFO L141 WitnessManager]: Wrote witness to /storage/repos/svcomp/c/systemc/toy1.cil.c-witness.graphml [2021-01-06 19:29:42,644 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-01-06 19:29:42,646 INFO L168 Benchmark]: Toolchain (without parser) took 24261.11 ms. Allocated memory was 161.5 MB in the beginning and 1.8 GB in the end (delta: 1.6 GB). Free memory was 136.6 MB in the beginning and 1.7 GB in the end (delta: -1.5 GB). Peak memory consumption was 67.6 MB. Max. memory is 8.0 GB. [2021-01-06 19:29:42,647 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 161.5 MB. Free memory is still 134.5 MB. There was no memory consumed. Max. memory is 8.0 GB. [2021-01-06 19:29:42,648 INFO L168 Benchmark]: CACSL2BoogieTranslator took 442.54 ms. Allocated memory is still 161.5 MB. Free memory was 136.6 MB in the beginning and 122.0 MB in the end (delta: 14.7 MB). Peak memory consumption was 14.7 MB. Max. memory is 8.0 GB. [2021-01-06 19:29:42,648 INFO L168 Benchmark]: Boogie Procedure Inliner took 70.76 ms. Allocated memory is still 161.5 MB. Free memory was 122.0 MB in the beginning and 119.9 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 8.0 GB. [2021-01-06 19:29:42,648 INFO L168 Benchmark]: Boogie Preprocessor took 40.33 ms. Allocated memory is still 161.5 MB. Free memory was 119.9 MB in the beginning and 117.8 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 8.0 GB. [2021-01-06 19:29:42,649 INFO L168 Benchmark]: RCFGBuilder took 778.50 ms. Allocated memory is still 161.5 MB. Free memory was 117.8 MB in the beginning and 75.8 MB in the end (delta: 42.0 MB). Peak memory consumption was 41.9 MB. Max. memory is 8.0 GB. [2021-01-06 19:29:42,649 INFO L168 Benchmark]: TraceAbstraction took 22627.82 ms. Allocated memory was 161.5 MB in the beginning and 1.8 GB in the end (delta: 1.6 GB). Free memory was 75.7 MB in the beginning and 1.7 GB in the end (delta: -1.6 GB). Peak memory consumption was 1.0 GB. Max. memory is 8.0 GB. [2021-01-06 19:29:42,650 INFO L168 Benchmark]: Witness Printer took 292.78 ms. Allocated memory is still 1.8 GB. Free memory was 1.7 GB in the beginning and 1.7 GB in the end (delta: 37.2 MB). Peak memory consumption was 36.7 MB. Max. memory is 8.0 GB. [2021-01-06 19:29:42,652 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 161.5 MB. Free memory is still 134.5 MB. There was no memory consumed. Max. memory is 8.0 GB. * CACSL2BoogieTranslator took 442.54 ms. Allocated memory is still 161.5 MB. Free memory was 136.6 MB in the beginning and 122.0 MB in the end (delta: 14.7 MB). Peak memory consumption was 14.7 MB. Max. memory is 8.0 GB. * Boogie Procedure Inliner took 70.76 ms. Allocated memory is still 161.5 MB. Free memory was 122.0 MB in the beginning and 119.9 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 8.0 GB. * Boogie Preprocessor took 40.33 ms. Allocated memory is still 161.5 MB. Free memory was 119.9 MB in the beginning and 117.8 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 8.0 GB. * RCFGBuilder took 778.50 ms. Allocated memory is still 161.5 MB. Free memory was 117.8 MB in the beginning and 75.8 MB in the end (delta: 42.0 MB). Peak memory consumption was 41.9 MB. Max. memory is 8.0 GB. * TraceAbstraction took 22627.82 ms. Allocated memory was 161.5 MB in the beginning and 1.8 GB in the end (delta: 1.6 GB). Free memory was 75.7 MB in the beginning and 1.7 GB in the end (delta: -1.6 GB). Peak memory consumption was 1.0 GB. Max. memory is 8.0 GB. * Witness Printer took 292.78 ms. Allocated memory is still 1.8 GB. Free memory was 1.7 GB in the beginning and 1.7 GB in the end (delta: 37.2 MB). Peak memory consumption was 36.7 MB. Max. memory is 8.0 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 15]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L20] int c ; [L21] int c_t ; [L22] int c_req_up ; [L23] int p_in ; [L24] int p_out ; [L25] int wl_st ; [L26] int c1_st ; [L27] int c2_st ; [L28] int wb_st ; [L29] int r_st ; [L30] int wl_i ; [L31] int c1_i ; [L32] int c2_i ; [L33] int wb_i ; [L34] int r_i ; [L35] int wl_pc ; [L36] int c1_pc ; [L37] int c2_pc ; [L38] int wb_pc ; [L39] int e_e ; [L40] int e_f ; [L41] int e_g ; [L42] int e_c ; [L43] int e_p_in ; [L44] int e_wl ; [L50] int d ; [L51] int data ; [L52] int processed ; [L53] static int t_b ; VAL [c=0, c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L693] int __retres1 ; [L697] e_wl = 2 [L698] e_c = e_wl [L699] e_g = e_c [L700] e_f = e_g [L701] e_e = e_f [L702] wl_pc = 0 [L703] c1_pc = 0 [L704] c2_pc = 0 [L705] wb_pc = 0 [L706] wb_i = 1 [L707] c2_i = wb_i [L708] c1_i = c2_i [L709] wl_i = c1_i [L710] r_i = 0 [L711] c_req_up = 0 [L712] d = 0 [L713] c = 0 [L404] int kernel_st ; [L407] kernel_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L408] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L419] COND TRUE (int )wl_i == 1 [L420] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L424] COND TRUE (int )c1_i == 1 [L425] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L429] COND TRUE (int )c2_i == 1 [L430] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L434] COND TRUE (int )wb_i == 1 [L435] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L439] COND FALSE !((int )r_i == 1) [L442] r_st = 2 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L444] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L449] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L454] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L459] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L464] COND FALSE !((int )e_wl == 0) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L469] COND FALSE !((int )wl_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L477] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L487] COND FALSE !((int )c1_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L496] COND FALSE !((int )c2_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L505] COND FALSE !((int )wb_pc == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L514] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L519] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L524] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L529] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L534] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L539] COND FALSE !((int )e_wl == 1) VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L545] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L548] kernel_st = 1 [L290] int tmp ; [L291] int tmp___0 ; [L292] int tmp___1 ; [L293] int tmp___2 ; [L294] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L298] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L300] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L321] COND TRUE (int )wl_st == 0 [L323] tmp = __VERIFIER_nondet_int() [L325] COND TRUE \read(tmp) [L327] wl_st = 1 [L55] int t ; VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L58] COND TRUE (int )wl_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=1] [L72] wl_st = 2 [L73] wl_pc = 1 [L74] e_wl = 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L336] COND TRUE (int )c1_st == 0 [L338] tmp___0 = __VERIFIER_nondet_int() [L340] COND TRUE \read(tmp___0) [L342] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L141] COND TRUE (int )c1_pc == 0 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L152] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=0, c1_st=1, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L154] c1_st = 2 [L155] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L351] COND TRUE (int )c2_st == 0 [L353] tmp___1 = __VERIFIER_nondet_int() [L355] COND TRUE \read(tmp___1) [L357] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L186] COND TRUE (int )c2_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L197] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=0, c2_st=1, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L199] c2_st = 2 [L200] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=1, wl_st=2] [L366] COND TRUE (int )wb_st == 0 [L368] tmp___2 = __VERIFIER_nondet_int() [L370] COND TRUE \read(tmp___2) [L372] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L231] COND TRUE (int )wb_pc == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L242] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=1, wl_i=1, wl_pc=1, wl_st=2] [L244] wb_st = 2 [L245] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L381] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L298] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L300] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L303] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L306] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L309] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L312] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L551] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L552] COND FALSE !((int )c_req_up == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L563] kernel_st = 3 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L564] COND FALSE !((int )e_f == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L569] COND FALSE !((int )e_g == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L574] COND FALSE !((int )e_e == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L579] COND FALSE !((int )e_c == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L584] COND TRUE (int )e_wl == 0 [L585] e_wl = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L589] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=2] [L590] COND TRUE (int )e_wl == 1 [L591] wl_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L607] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L608] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L616] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L617] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L625] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L626] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L634] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L639] COND FALSE !((int )e_e == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L644] COND FALSE !((int )e_f == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L649] COND FALSE !((int )e_g == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L654] COND FALSE !((int )e_c == 1) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=1, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L659] COND TRUE (int )e_wl == 1 [L660] e_wl = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L664] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L545] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L548] kernel_st = 1 [L290] int tmp ; [L291] int tmp___0 ; [L292] int tmp___1 ; [L293] int tmp___2 ; [L294] int tmp___3 ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L298] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L300] COND TRUE (int )wl_st == 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=0] [L321] COND TRUE (int )wl_st == 0 [L323] tmp = __VERIFIER_nondet_int() [L325] COND TRUE \read(tmp) [L327] wl_st = 1 [L55] int t ; VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L58] COND FALSE !((int )wl_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L61] COND FALSE !((int )wl_pc == 2) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L64] COND TRUE (int )wl_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L79] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L81] t = d [L82] data = d [L83] processed = 0 [L84] e_f = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L85] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L86] COND TRUE (int )e_f == 1 [L87] c1_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L94] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L95] COND TRUE (int )e_f == 1 [L96] c2_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=1, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=1, wl_st=1] [L103] e_f = 2 [L104] wl_st = 2 [L105] wl_pc = 2 [L106] t_b = t VAL [c=0, c1_i=1, c1_pc=1, c1_st=0, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L336] COND TRUE (int )c1_st == 0 [L338] tmp___0 = __VERIFIER_nondet_int() [L340] COND TRUE \read(tmp___0) [L342] c1_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L141] COND FALSE !((int )c1_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L144] COND TRUE (int )c1_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L159] COND TRUE ! processed [L160] data += 1 [L161] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L162] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L163] COND TRUE (int )e_g == 1 [L164] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L171] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L152] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=1, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L154] c1_st = 2 [L155] c1_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=0, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L351] COND TRUE (int )c2_st == 0 [L353] tmp___1 = __VERIFIER_nondet_int() [L355] COND TRUE \read(tmp___1) [L357] c2_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L186] COND FALSE !((int )c2_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L189] COND TRUE (int )c2_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=1, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L204] COND TRUE ! processed [L205] data += 1 [L206] e_g = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L207] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L208] COND TRUE (int )e_g == 1 [L209] wb_st = 0 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=1, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L216] e_g = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L197] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=1, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L199] c2_st = 2 [L200] c2_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=0, wl_i=1, wl_pc=2, wl_st=2] [L366] COND TRUE (int )wb_st == 0 [L368] tmp___2 = __VERIFIER_nondet_int() [L370] COND TRUE \read(tmp___2) [L372] wb_st = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L231] COND FALSE !((int )wb_pc == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L234] COND TRUE (int )wb_pc == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=0, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L249] c_t = data [L250] c_req_up = 1 [L251] processed = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L242] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=1, wl_i=1, wl_pc=2, wl_st=2] [L244] wb_st = 2 [L245] wb_pc = 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L381] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND TRUE 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L300] COND FALSE !((int )wl_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L303] COND FALSE !((int )c1_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L306] COND FALSE !((int )c2_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L309] COND FALSE !((int )wb_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L312] COND FALSE !((int )r_st == 0) VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L551] kernel_st = 2 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L552] COND TRUE (int )c_req_up == 1 VAL [c=0, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L553] COND TRUE c != c_t [L554] c = c_t [L555] e_c = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=1, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L559] c_req_up = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L563] kernel_st = 3 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L564] COND FALSE !((int )e_f == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L569] COND FALSE !((int )e_g == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L574] COND FALSE !((int )e_e == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=0, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L579] COND TRUE (int )e_c == 0 [L580] e_c = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L584] COND FALSE !((int )e_wl == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L589] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L597] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L598] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L607] COND TRUE (int )c1_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L608] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L616] COND TRUE (int )c2_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L617] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L625] COND TRUE (int )wb_pc == 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L626] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L634] COND TRUE (int )e_c == 1 [L635] r_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L639] COND FALSE !((int )e_e == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L644] COND FALSE !((int )e_f == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L649] COND FALSE !((int )e_g == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=1, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L654] COND TRUE (int )e_c == 1 [L655] e_c = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L659] COND FALSE !((int )e_wl == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L664] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L667] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L670] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L673] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L676] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L545] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L548] kernel_st = 1 [L290] int tmp ; [L291] int tmp___0 ; [L292] int tmp___1 ; [L293] int tmp___2 ; [L294] int tmp___3 ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L298] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L300] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L303] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L306] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L309] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L312] COND TRUE (int )r_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L321] COND FALSE !((int )wl_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L336] COND FALSE !((int )c1_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L351] COND FALSE !((int )c2_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L366] COND FALSE !((int )wb_st == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=0, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L381] COND TRUE (int )r_st == 0 [L383] tmp___3 = __VERIFIER_nondet_int() [L385] COND TRUE \read(tmp___3) [L387] r_st = 1 [L263] d = c [L264] e_e = 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L265] COND FALSE !((int )wl_pc == 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L273] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=2] [L274] COND TRUE (int )e_e == 1 [L275] wl_st = 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=1, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=1, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L283] e_e = 2 [L284] r_st = 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L298] COND TRUE 1 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L300] COND TRUE (int )wl_st == 0 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=0] [L321] COND TRUE (int )wl_st == 0 [L323] tmp = __VERIFIER_nondet_int() [L325] COND TRUE \read(tmp) [L327] wl_st = 1 [L55] int t ; VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L58] COND FALSE !((int )wl_pc == 0) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L61] COND TRUE (int )wl_pc == 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L110] t = t_b VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L111] COND FALSE !(d == t + 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L114] COND TRUE d == t + 2 VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L122] COND FALSE !(d == t + 1) VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] [L15] reach_error() VAL [c=2, c1_i=1, c1_pc=1, c1_st=2, c2_i=1, c2_pc=1, c2_st=2, c_req_up=0, c_t=2, d=2, data=2, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=1, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=1, wb_st=2, wl_i=1, wl_pc=2, wl_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 129 locations, 2 error locations. Started 1 CEGAR loops. VerificationResult: UNSAFE, OverallTime: 22.2s, OverallIterations: 35, TraceHistogramMax: 6, AutomataDifference: 10.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 7212 SDtfs, 9836 SDslu, 8474 SDs, 0 SdLazy, 1107 SolverSat, 265 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 371 GetRequests, 269 SyntacticMatches, 0 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 245 ImplicationChecksByTransitivity, 1.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=5348occurred in iteration=21, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 7.4s AutomataMinimizationTime, 34 MinimizatonAttempts, 6041 StatesRemovedByMinimization, 28 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 1.8s InterpolantComputationTime, 3190 NumberOfCodeBlocks, 3190 NumberOfCodeBlocksAsserted, 36 NumberOfCheckSat, 2969 ConstructedInterpolants, 0 QuantifiedInterpolants, 737591 SizeOfPredicates, 6 NumberOfNonLiveVariables, 528 ConjunctsInSsa, 20 ConjunctsInUnsatCore, 35 InterpolantComputations, 33 PerfectInterpolantSequences, 914/1025 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...