/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -tc config/AutomizerReach.xml -s config/svcomp-Reach-64bit-Automizer_Default.epf -i ../sv-benchmarks/c/systemc/transmitter.04.cil.c -------------------------------------------------------------------------------- This is Ultimate 0.2.1-bitabs-178dd20 [2021-01-06 19:30:05,464 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-01-06 19:30:05,467 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-01-06 19:30:05,505 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-01-06 19:30:05,505 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-01-06 19:30:05,507 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-01-06 19:30:05,509 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-01-06 19:30:05,512 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-01-06 19:30:05,514 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-01-06 19:30:05,516 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-01-06 19:30:05,517 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-01-06 19:30:05,519 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-01-06 19:30:05,519 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-01-06 19:30:05,521 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-01-06 19:30:05,525 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-01-06 19:30:05,526 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-01-06 19:30:05,527 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-01-06 19:30:05,532 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-01-06 19:30:05,535 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-01-06 19:30:05,538 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-01-06 19:30:05,544 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-01-06 19:30:05,549 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-01-06 19:30:05,551 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-01-06 19:30:05,554 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-01-06 19:30:05,573 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-01-06 19:30:05,576 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-01-06 19:30:05,576 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-01-06 19:30:05,578 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-01-06 19:30:05,583 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-01-06 19:30:05,584 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-01-06 19:30:05,585 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-01-06 19:30:05,586 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-01-06 19:30:05,587 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-01-06 19:30:05,588 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-01-06 19:30:05,589 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-01-06 19:30:05,589 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-01-06 19:30:05,590 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-01-06 19:30:05,591 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-01-06 19:30:05,591 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-01-06 19:30:05,592 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-01-06 19:30:05,593 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-01-06 19:30:05,594 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf [2021-01-06 19:30:05,625 INFO L113 SettingsManager]: Loading preferences was successful [2021-01-06 19:30:05,626 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-01-06 19:30:05,627 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-01-06 19:30:05,628 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-01-06 19:30:05,628 INFO L138 SettingsManager]: * Use SBE=true [2021-01-06 19:30:05,628 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-01-06 19:30:05,629 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-01-06 19:30:05,629 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-01-06 19:30:05,629 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-01-06 19:30:05,630 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-01-06 19:30:05,630 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-01-06 19:30:05,630 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-01-06 19:30:05,630 INFO L138 SettingsManager]: * Use constant arrays=true [2021-01-06 19:30:05,631 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-01-06 19:30:05,631 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-01-06 19:30:05,631 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-01-06 19:30:05,632 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2021-01-06 19:30:05,632 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-01-06 19:30:05,632 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-01-06 19:30:05,633 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-01-06 19:30:05,633 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2021-01-06 19:30:05,633 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-01-06 19:30:05,633 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-01-06 19:30:05,634 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-01-06 19:30:05,634 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-01-06 19:30:05,634 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release [2021-01-06 19:30:06,016 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-01-06 19:30:06,055 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-01-06 19:30:06,059 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-01-06 19:30:06,061 INFO L271 PluginConnector]: Initializing CDTParser... [2021-01-06 19:30:06,061 INFO L275 PluginConnector]: CDTParser initialized [2021-01-06 19:30:06,063 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.04.cil.c [2021-01-06 19:30:06,164 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/data/7bccf9003/0a020920eb654baab41110b5efe2bf48/FLAG9f034e4ed [2021-01-06 19:30:06,927 INFO L306 CDTParser]: Found 1 translation units. [2021-01-06 19:30:06,931 INFO L160 CDTParser]: Scanning /storage/repos/ultimate-bitabs/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.04.cil.c [2021-01-06 19:30:06,953 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/data/7bccf9003/0a020920eb654baab41110b5efe2bf48/FLAG9f034e4ed [2021-01-06 19:30:07,224 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/data/7bccf9003/0a020920eb654baab41110b5efe2bf48 [2021-01-06 19:30:07,227 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-01-06 19:30:07,230 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-01-06 19:30:07,234 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-01-06 19:30:07,235 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-01-06 19:30:07,240 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-01-06 19:30:07,241 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.01 07:30:07" (1/1) ... [2021-01-06 19:30:07,242 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6b5bd893 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:30:07, skipping insertion in model container [2021-01-06 19:30:07,242 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.01 07:30:07" (1/1) ... [2021-01-06 19:30:07,252 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-01-06 19:30:07,291 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-01-06 19:30:07,483 WARN L226 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate-bitabs/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.04.cil.c[401,414] left hand side expression in assignment: lhs: VariableLHS[~E_1~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_1~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~m_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~m_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t1_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_2~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_2~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t2_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_3~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_3~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t3_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t3_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_4~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_4~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t4_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t4_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~__retres1~0,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~0,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~1,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~1,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~2,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~2,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~3,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~3,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~4,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~4,] left hand side expression in assignment: lhs: VariableLHS[~m_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~m_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t3_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t3_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t4_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t4_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~__retres1~5,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~5,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~5,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~5,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~5,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~5,] left hand side expression in assignment: lhs: VariableLHS[~tmp~0,] left hand side expression in assignment: lhs: VariableLHS[~tmp_ndt_1~0,] left hand side expression in assignment: lhs: VariableLHS[~m_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp_ndt_2~0,] left hand side expression in assignment: lhs: VariableLHS[~t1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp_ndt_3~0,] left hand side expression in assignment: lhs: VariableLHS[~t2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp_ndt_4~0,] left hand side expression in assignment: lhs: VariableLHS[~t3_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp_ndt_5~0,] left hand side expression in assignment: lhs: VariableLHS[~t4_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~M_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T1_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T2_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T3_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T4_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_1~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_2~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_3~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_4~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~M_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T1_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T2_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T3_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T4_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_1~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_2~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_3~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_4~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp~1,] left hand side expression in assignment: lhs: VariableLHS[~m_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___0~0,] left hand side expression in assignment: lhs: VariableLHS[~t1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___1~0,] left hand side expression in assignment: lhs: VariableLHS[~t2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___2~0,] left hand side expression in assignment: lhs: VariableLHS[~t3_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___3~0,] left hand side expression in assignment: lhs: VariableLHS[~t4_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~M_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~M_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T1_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T2_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T3_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T4_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_1~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_2~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_3~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_4~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~m_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t1_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t2_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t3_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t4_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp~2,] left hand side expression in assignment: lhs: VariableLHS[~__retres2~0,] left hand side expression in assignment: lhs: VariableLHS[~__retres2~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~tmp~3,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~tmp___0~1,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~6,] [2021-01-06 19:30:07,612 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-01-06 19:30:07,630 INFO L203 MainTranslator]: Completed pre-run [2021-01-06 19:30:07,648 WARN L226 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate-bitabs/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.04.cil.c[401,414] left hand side expression in assignment: lhs: VariableLHS[~E_1~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_1~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~m_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~m_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t1_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_2~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_2~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t2_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_3~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_3~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t3_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t3_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_4~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_4~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t4_pc~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t4_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~__retres1~0,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~0,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~1,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~1,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~2,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~2,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~3,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~3,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~4,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~4,] left hand side expression in assignment: lhs: VariableLHS[~m_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~m_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t3_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t3_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t4_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t4_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~__retres1~5,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~5,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~5,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~5,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~5,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~5,] left hand side expression in assignment: lhs: VariableLHS[~tmp~0,] left hand side expression in assignment: lhs: VariableLHS[~tmp_ndt_1~0,] left hand side expression in assignment: lhs: VariableLHS[~m_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp_ndt_2~0,] left hand side expression in assignment: lhs: VariableLHS[~t1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp_ndt_3~0,] left hand side expression in assignment: lhs: VariableLHS[~t2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp_ndt_4~0,] left hand side expression in assignment: lhs: VariableLHS[~t3_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp_ndt_5~0,] left hand side expression in assignment: lhs: VariableLHS[~t4_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~M_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T1_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T2_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T3_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T4_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_1~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_2~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_3~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_4~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~M_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T1_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T2_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T3_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T4_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_1~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_2~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_3~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_4~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp~1,] left hand side expression in assignment: lhs: VariableLHS[~m_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___0~0,] left hand side expression in assignment: lhs: VariableLHS[~t1_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___1~0,] left hand side expression in assignment: lhs: VariableLHS[~t2_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___2~0,] left hand side expression in assignment: lhs: VariableLHS[~t3_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp___3~0,] left hand side expression in assignment: lhs: VariableLHS[~t4_st~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~M_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~M_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T1_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T2_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T3_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~T4_E~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_1~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_2~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_3~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~E_4~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~m_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t1_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t2_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t3_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~t4_i~0,GLOBAL] left hand side expression in assignment: lhs: VariableLHS[~tmp~2,] left hand side expression in assignment: lhs: VariableLHS[~__retres2~0,] left hand side expression in assignment: lhs: VariableLHS[~__retres2~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~tmp~3,] left hand side expression in assignment: lhs: VariableLHS[~kernel_st~0,] left hand side expression in assignment: lhs: VariableLHS[~tmp___0~1,] left hand side expression in assignment: lhs: VariableLHS[~__retres1~6,] [2021-01-06 19:30:07,722 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-01-06 19:30:07,755 INFO L208 MainTranslator]: Completed translation [2021-01-06 19:30:07,756 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:30:07 WrapperNode [2021-01-06 19:30:07,756 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-01-06 19:30:07,758 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-01-06 19:30:07,758 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-01-06 19:30:07,758 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-01-06 19:30:07,770 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:30:07" (1/1) ... [2021-01-06 19:30:07,783 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:30:07" (1/1) ... [2021-01-06 19:30:07,852 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-01-06 19:30:07,853 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-01-06 19:30:07,854 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-01-06 19:30:07,854 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-01-06 19:30:07,865 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:30:07" (1/1) ... [2021-01-06 19:30:07,865 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:30:07" (1/1) ... [2021-01-06 19:30:07,870 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:30:07" (1/1) ... [2021-01-06 19:30:07,871 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:30:07" (1/1) ... [2021-01-06 19:30:07,888 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:30:07" (1/1) ... [2021-01-06 19:30:07,906 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:30:07" (1/1) ... [2021-01-06 19:30:07,912 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:30:07" (1/1) ... [2021-01-06 19:30:07,919 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-01-06 19:30:07,921 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-01-06 19:30:07,921 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-01-06 19:30:07,921 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-01-06 19:30:07,922 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:30:07" (1/1) ... No working directory specified, using /storage/repos/ultimate-bitabs/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-01-06 19:30:08,051 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-01-06 19:30:08,052 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-01-06 19:30:08,052 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-01-06 19:30:08,052 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-01-06 19:30:09,630 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-01-06 19:30:09,630 INFO L299 CfgBuilder]: Removed 148 assume(true) statements. [2021-01-06 19:30:09,633 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.01 07:30:09 BoogieIcfgContainer [2021-01-06 19:30:09,634 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-01-06 19:30:09,638 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2021-01-06 19:30:09,638 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2021-01-06 19:30:09,649 INFO L275 PluginConnector]: TraceAbstraction initialized [2021-01-06 19:30:09,649 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.01 07:30:07" (1/3) ... [2021-01-06 19:30:09,650 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@26a10acb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.01 07:30:09, skipping insertion in model container [2021-01-06 19:30:09,650 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.01 07:30:07" (2/3) ... [2021-01-06 19:30:09,654 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@26a10acb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.01 07:30:09, skipping insertion in model container [2021-01-06 19:30:09,654 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.01 07:30:09" (3/3) ... [2021-01-06 19:30:09,660 INFO L111 eAbstractionObserver]: Analyzing ICFG transmitter.04.cil.c [2021-01-06 19:30:09,669 INFO L153 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2021-01-06 19:30:09,676 INFO L165 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2021-01-06 19:30:09,737 INFO L253 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2021-01-06 19:30:09,792 INFO L377 AbstractCegarLoop]: Interprodecural is true [2021-01-06 19:30:09,793 INFO L378 AbstractCegarLoop]: Hoare is true [2021-01-06 19:30:09,793 INFO L379 AbstractCegarLoop]: Compute interpolants for FPandBP [2021-01-06 19:30:09,793 INFO L380 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2021-01-06 19:30:09,793 INFO L381 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-01-06 19:30:09,793 INFO L382 AbstractCegarLoop]: Difference is false [2021-01-06 19:30:09,793 INFO L383 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-01-06 19:30:09,794 INFO L387 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2021-01-06 19:30:09,824 INFO L276 IsEmpty]: Start isEmpty. Operand 374 states. [2021-01-06 19:30:09,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:09,836 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:09,840 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:09,841 INFO L429 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:09,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:09,848 INFO L82 PathProgramCache]: Analyzing trace with hash -1653942868, now seen corresponding path program 1 times [2021-01-06 19:30:09,859 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:09,860 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [801116850] [2021-01-06 19:30:09,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:09,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:10,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:10,093 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [801116850] [2021-01-06 19:30:10,093 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:10,094 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:30:10,095 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1326840605] [2021-01-06 19:30:10,100 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:10,100 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:10,116 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:10,117 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:10,120 INFO L87 Difference]: Start difference. First operand 374 states. Second operand 3 states. [2021-01-06 19:30:10,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:10,236 INFO L93 Difference]: Finished difference Result 743 states and 1159 transitions. [2021-01-06 19:30:10,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:10,238 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2021-01-06 19:30:10,239 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:10,272 INFO L225 Difference]: With dead ends: 743 [2021-01-06 19:30:10,273 INFO L226 Difference]: Without dead ends: 370 [2021-01-06 19:30:10,287 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:10,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 370 states. [2021-01-06 19:30:10,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 370 to 370. [2021-01-06 19:30:10,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 370 states. [2021-01-06 19:30:10,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 370 states to 370 states and 561 transitions. [2021-01-06 19:30:10,367 INFO L78 Accepts]: Start accepts. Automaton has 370 states and 561 transitions. Word has length 73 [2021-01-06 19:30:10,367 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:10,367 INFO L481 AbstractCegarLoop]: Abstraction has 370 states and 561 transitions. [2021-01-06 19:30:10,368 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:10,368 INFO L276 IsEmpty]: Start isEmpty. Operand 370 states and 561 transitions. [2021-01-06 19:30:10,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:10,374 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:10,374 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:10,374 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2021-01-06 19:30:10,375 INFO L429 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:10,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:10,375 INFO L82 PathProgramCache]: Analyzing trace with hash -1161316694, now seen corresponding path program 1 times [2021-01-06 19:30:10,376 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:10,378 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [6622761] [2021-01-06 19:30:10,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:10,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:10,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:10,490 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [6622761] [2021-01-06 19:30:10,490 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:10,490 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-06 19:30:10,491 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [958479807] [2021-01-06 19:30:10,492 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:10,493 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:10,494 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:10,494 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:10,494 INFO L87 Difference]: Start difference. First operand 370 states and 561 transitions. Second operand 3 states. [2021-01-06 19:30:10,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:10,643 INFO L93 Difference]: Finished difference Result 1004 states and 1519 transitions. [2021-01-06 19:30:10,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:10,644 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2021-01-06 19:30:10,645 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:10,649 INFO L225 Difference]: With dead ends: 1004 [2021-01-06 19:30:10,649 INFO L226 Difference]: Without dead ends: 643 [2021-01-06 19:30:10,652 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:10,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 643 states. [2021-01-06 19:30:10,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 643 to 641. [2021-01-06 19:30:10,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2021-01-06 19:30:10,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 961 transitions. [2021-01-06 19:30:10,722 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 961 transitions. Word has length 73 [2021-01-06 19:30:10,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:10,723 INFO L481 AbstractCegarLoop]: Abstraction has 641 states and 961 transitions. [2021-01-06 19:30:10,723 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:10,723 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 961 transitions. [2021-01-06 19:30:10,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:10,728 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:10,728 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:10,728 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2021-01-06 19:30:10,729 INFO L429 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:10,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:10,733 INFO L82 PathProgramCache]: Analyzing trace with hash 1509510378, now seen corresponding path program 1 times [2021-01-06 19:30:10,733 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:10,733 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779391316] [2021-01-06 19:30:10,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:10,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:10,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:10,805 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1779391316] [2021-01-06 19:30:10,805 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:10,806 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-06 19:30:10,806 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206418202] [2021-01-06 19:30:10,806 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:10,807 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:10,807 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:10,808 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:10,808 INFO L87 Difference]: Start difference. First operand 641 states and 961 transitions. Second operand 3 states. [2021-01-06 19:30:10,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:10,899 INFO L93 Difference]: Finished difference Result 1272 states and 1907 transitions. [2021-01-06 19:30:10,900 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:10,900 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2021-01-06 19:30:10,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:10,904 INFO L225 Difference]: With dead ends: 1272 [2021-01-06 19:30:10,904 INFO L226 Difference]: Without dead ends: 641 [2021-01-06 19:30:10,906 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:10,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2021-01-06 19:30:10,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2021-01-06 19:30:10,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2021-01-06 19:30:10,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 953 transitions. [2021-01-06 19:30:10,940 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 953 transitions. Word has length 73 [2021-01-06 19:30:10,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:10,941 INFO L481 AbstractCegarLoop]: Abstraction has 641 states and 953 transitions. [2021-01-06 19:30:10,941 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:10,941 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 953 transitions. [2021-01-06 19:30:10,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:10,944 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:10,944 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:10,944 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2021-01-06 19:30:10,945 INFO L429 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:10,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:10,945 INFO L82 PathProgramCache]: Analyzing trace with hash 1595666090, now seen corresponding path program 1 times [2021-01-06 19:30:10,946 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:10,946 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [331247955] [2021-01-06 19:30:10,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:10,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:11,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:11,015 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [331247955] [2021-01-06 19:30:11,016 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:11,016 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-06 19:30:11,016 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1284542239] [2021-01-06 19:30:11,017 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:11,017 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:11,018 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:11,018 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:11,018 INFO L87 Difference]: Start difference. First operand 641 states and 953 transitions. Second operand 3 states. [2021-01-06 19:30:11,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:11,076 INFO L93 Difference]: Finished difference Result 1271 states and 1890 transitions. [2021-01-06 19:30:11,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:11,077 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2021-01-06 19:30:11,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:11,081 INFO L225 Difference]: With dead ends: 1271 [2021-01-06 19:30:11,082 INFO L226 Difference]: Without dead ends: 641 [2021-01-06 19:30:11,083 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:11,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2021-01-06 19:30:11,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2021-01-06 19:30:11,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2021-01-06 19:30:11,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 945 transitions. [2021-01-06 19:30:11,114 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 945 transitions. Word has length 73 [2021-01-06 19:30:11,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:11,114 INFO L481 AbstractCegarLoop]: Abstraction has 641 states and 945 transitions. [2021-01-06 19:30:11,114 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:11,114 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 945 transitions. [2021-01-06 19:30:11,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:11,116 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:11,116 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:11,116 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2021-01-06 19:30:11,117 INFO L429 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:11,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:11,117 INFO L82 PathProgramCache]: Analyzing trace with hash 1178269484, now seen corresponding path program 1 times [2021-01-06 19:30:11,118 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:11,118 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837930219] [2021-01-06 19:30:11,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:11,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:11,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:11,176 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1837930219] [2021-01-06 19:30:11,176 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:11,176 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-06 19:30:11,177 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [670470668] [2021-01-06 19:30:11,177 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:11,177 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:11,178 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:11,178 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:11,179 INFO L87 Difference]: Start difference. First operand 641 states and 945 transitions. Second operand 3 states. [2021-01-06 19:30:11,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:11,235 INFO L93 Difference]: Finished difference Result 1270 states and 1873 transitions. [2021-01-06 19:30:11,235 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:11,236 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2021-01-06 19:30:11,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:11,240 INFO L225 Difference]: With dead ends: 1270 [2021-01-06 19:30:11,240 INFO L226 Difference]: Without dead ends: 641 [2021-01-06 19:30:11,241 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:11,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2021-01-06 19:30:11,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2021-01-06 19:30:11,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2021-01-06 19:30:11,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 937 transitions. [2021-01-06 19:30:11,271 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 937 transitions. Word has length 73 [2021-01-06 19:30:11,271 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:11,271 INFO L481 AbstractCegarLoop]: Abstraction has 641 states and 937 transitions. [2021-01-06 19:30:11,271 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:11,271 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 937 transitions. [2021-01-06 19:30:11,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:11,272 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:11,272 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:11,273 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2021-01-06 19:30:11,273 INFO L429 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:11,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:11,274 INFO L82 PathProgramCache]: Analyzing trace with hash 52103404, now seen corresponding path program 1 times [2021-01-06 19:30:11,274 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:11,274 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791050176] [2021-01-06 19:30:11,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:11,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:11,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:11,331 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1791050176] [2021-01-06 19:30:11,331 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:11,331 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-06 19:30:11,332 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451366369] [2021-01-06 19:30:11,332 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:11,332 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:11,333 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:11,333 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:11,333 INFO L87 Difference]: Start difference. First operand 641 states and 937 transitions. Second operand 3 states. [2021-01-06 19:30:11,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:11,439 INFO L93 Difference]: Finished difference Result 1268 states and 1854 transitions. [2021-01-06 19:30:11,440 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:11,440 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2021-01-06 19:30:11,440 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:11,444 INFO L225 Difference]: With dead ends: 1268 [2021-01-06 19:30:11,444 INFO L226 Difference]: Without dead ends: 641 [2021-01-06 19:30:11,445 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:11,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2021-01-06 19:30:11,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2021-01-06 19:30:11,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2021-01-06 19:30:11,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 919 transitions. [2021-01-06 19:30:11,475 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 919 transitions. Word has length 73 [2021-01-06 19:30:11,475 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:11,475 INFO L481 AbstractCegarLoop]: Abstraction has 641 states and 919 transitions. [2021-01-06 19:30:11,475 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:11,475 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 919 transitions. [2021-01-06 19:30:11,476 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:11,476 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:11,476 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:11,477 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2021-01-06 19:30:11,477 INFO L429 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:11,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:11,478 INFO L82 PathProgramCache]: Analyzing trace with hash 2144832493, now seen corresponding path program 1 times [2021-01-06 19:30:11,478 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:11,478 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1072618689] [2021-01-06 19:30:11,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:11,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:11,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:11,524 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1072618689] [2021-01-06 19:30:11,525 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:11,525 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-06 19:30:11,525 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1994743826] [2021-01-06 19:30:11,525 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:11,526 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:11,526 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:11,526 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:11,527 INFO L87 Difference]: Start difference. First operand 641 states and 919 transitions. Second operand 3 states. [2021-01-06 19:30:11,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:11,617 INFO L93 Difference]: Finished difference Result 1267 states and 1817 transitions. [2021-01-06 19:30:11,618 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:11,618 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2021-01-06 19:30:11,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:11,622 INFO L225 Difference]: With dead ends: 1267 [2021-01-06 19:30:11,622 INFO L226 Difference]: Without dead ends: 641 [2021-01-06 19:30:11,624 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:11,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2021-01-06 19:30:11,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2021-01-06 19:30:11,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2021-01-06 19:30:11,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 901 transitions. [2021-01-06 19:30:11,655 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 901 transitions. Word has length 73 [2021-01-06 19:30:11,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:11,656 INFO L481 AbstractCegarLoop]: Abstraction has 641 states and 901 transitions. [2021-01-06 19:30:11,656 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:11,656 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 901 transitions. [2021-01-06 19:30:11,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:11,657 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:11,657 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:11,658 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2021-01-06 19:30:11,658 INFO L429 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:11,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:11,659 INFO L82 PathProgramCache]: Analyzing trace with hash 1887883821, now seen corresponding path program 1 times [2021-01-06 19:30:11,659 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:11,659 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604324499] [2021-01-06 19:30:11,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:11,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:11,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:11,703 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604324499] [2021-01-06 19:30:11,703 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:11,703 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-06 19:30:11,704 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2081177496] [2021-01-06 19:30:11,704 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:11,704 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:11,705 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:11,705 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:11,705 INFO L87 Difference]: Start difference. First operand 641 states and 901 transitions. Second operand 3 states. [2021-01-06 19:30:11,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:11,793 INFO L93 Difference]: Finished difference Result 1266 states and 1780 transitions. [2021-01-06 19:30:11,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:11,795 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2021-01-06 19:30:11,795 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:11,798 INFO L225 Difference]: With dead ends: 1266 [2021-01-06 19:30:11,799 INFO L226 Difference]: Without dead ends: 641 [2021-01-06 19:30:11,800 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:11,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2021-01-06 19:30:11,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2021-01-06 19:30:11,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2021-01-06 19:30:11,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 883 transitions. [2021-01-06 19:30:11,834 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 883 transitions. Word has length 73 [2021-01-06 19:30:11,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:11,834 INFO L481 AbstractCegarLoop]: Abstraction has 641 states and 883 transitions. [2021-01-06 19:30:11,834 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:11,834 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 883 transitions. [2021-01-06 19:30:11,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:11,835 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:11,836 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:11,836 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2021-01-06 19:30:11,836 INFO L429 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:11,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:11,837 INFO L82 PathProgramCache]: Analyzing trace with hash 1757929134, now seen corresponding path program 1 times [2021-01-06 19:30:11,837 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:11,837 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549629290] [2021-01-06 19:30:11,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:11,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:11,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:11,880 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549629290] [2021-01-06 19:30:11,881 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:11,881 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-06 19:30:11,881 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [897233621] [2021-01-06 19:30:11,882 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:11,882 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:11,882 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:11,883 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:11,883 INFO L87 Difference]: Start difference. First operand 641 states and 883 transitions. Second operand 3 states. [2021-01-06 19:30:11,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:11,991 INFO L93 Difference]: Finished difference Result 1265 states and 1743 transitions. [2021-01-06 19:30:11,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:11,992 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2021-01-06 19:30:11,993 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:11,996 INFO L225 Difference]: With dead ends: 1265 [2021-01-06 19:30:11,996 INFO L226 Difference]: Without dead ends: 641 [2021-01-06 19:30:11,998 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:11,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states. [2021-01-06 19:30:12,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 641. [2021-01-06 19:30:12,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 641 states. [2021-01-06 19:30:12,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 641 states to 641 states and 865 transitions. [2021-01-06 19:30:12,031 INFO L78 Accepts]: Start accepts. Automaton has 641 states and 865 transitions. Word has length 73 [2021-01-06 19:30:12,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:12,031 INFO L481 AbstractCegarLoop]: Abstraction has 641 states and 865 transitions. [2021-01-06 19:30:12,031 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:12,031 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 865 transitions. [2021-01-06 19:30:12,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:12,032 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:12,033 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:12,033 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2021-01-06 19:30:12,033 INFO L429 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:12,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:12,034 INFO L82 PathProgramCache]: Analyzing trace with hash 1024701678, now seen corresponding path program 1 times [2021-01-06 19:30:12,034 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:12,035 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588013627] [2021-01-06 19:30:12,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:12,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:12,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:12,124 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1588013627] [2021-01-06 19:30:12,124 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:12,124 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-01-06 19:30:12,125 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1151261826] [2021-01-06 19:30:12,125 INFO L461 AbstractCegarLoop]: Interpolant automaton has 5 states [2021-01-06 19:30:12,125 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:12,126 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-01-06 19:30:12,126 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:30:12,126 INFO L87 Difference]: Start difference. First operand 641 states and 865 transitions. Second operand 5 states. [2021-01-06 19:30:12,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:12,372 INFO L93 Difference]: Finished difference Result 1647 states and 2245 transitions. [2021-01-06 19:30:12,373 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-01-06 19:30:12,373 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2021-01-06 19:30:12,373 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:12,378 INFO L225 Difference]: With dead ends: 1647 [2021-01-06 19:30:12,379 INFO L226 Difference]: Without dead ends: 1037 [2021-01-06 19:30:12,381 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-01-06 19:30:12,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1037 states. [2021-01-06 19:30:12,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1037 to 647. [2021-01-06 19:30:12,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 647 states. [2021-01-06 19:30:12,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 647 states to 647 states and 861 transitions. [2021-01-06 19:30:12,425 INFO L78 Accepts]: Start accepts. Automaton has 647 states and 861 transitions. Word has length 73 [2021-01-06 19:30:12,425 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:12,426 INFO L481 AbstractCegarLoop]: Abstraction has 647 states and 861 transitions. [2021-01-06 19:30:12,426 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2021-01-06 19:30:12,426 INFO L276 IsEmpty]: Start isEmpty. Operand 647 states and 861 transitions. [2021-01-06 19:30:12,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:12,427 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:12,427 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:12,427 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2021-01-06 19:30:12,427 INFO L429 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:12,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:12,428 INFO L82 PathProgramCache]: Analyzing trace with hash 1918188016, now seen corresponding path program 1 times [2021-01-06 19:30:12,428 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:12,429 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [270342683] [2021-01-06 19:30:12,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:12,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:12,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:12,499 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [270342683] [2021-01-06 19:30:12,499 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:12,499 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-01-06 19:30:12,500 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [829619552] [2021-01-06 19:30:12,500 INFO L461 AbstractCegarLoop]: Interpolant automaton has 5 states [2021-01-06 19:30:12,500 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:12,502 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-01-06 19:30:12,503 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:30:12,503 INFO L87 Difference]: Start difference. First operand 647 states and 861 transitions. Second operand 5 states. [2021-01-06 19:30:12,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:12,764 INFO L93 Difference]: Finished difference Result 1700 states and 2283 transitions. [2021-01-06 19:30:12,764 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-01-06 19:30:12,765 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2021-01-06 19:30:12,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:12,771 INFO L225 Difference]: With dead ends: 1700 [2021-01-06 19:30:12,771 INFO L226 Difference]: Without dead ends: 1091 [2021-01-06 19:30:12,774 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-01-06 19:30:12,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1091 states. [2021-01-06 19:30:12,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1091 to 653. [2021-01-06 19:30:12,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 653 states. [2021-01-06 19:30:12,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 653 states to 653 states and 857 transitions. [2021-01-06 19:30:12,824 INFO L78 Accepts]: Start accepts. Automaton has 653 states and 857 transitions. Word has length 73 [2021-01-06 19:30:12,826 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:12,826 INFO L481 AbstractCegarLoop]: Abstraction has 653 states and 857 transitions. [2021-01-06 19:30:12,826 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2021-01-06 19:30:12,826 INFO L276 IsEmpty]: Start isEmpty. Operand 653 states and 857 transitions. [2021-01-06 19:30:12,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:12,827 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:12,827 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:12,828 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2021-01-06 19:30:12,828 INFO L429 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:12,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:12,828 INFO L82 PathProgramCache]: Analyzing trace with hash 72820850, now seen corresponding path program 1 times [2021-01-06 19:30:12,829 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:12,829 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834360066] [2021-01-06 19:30:12,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:12,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:12,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:12,904 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [834360066] [2021-01-06 19:30:12,904 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:12,905 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-01-06 19:30:12,905 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [167861082] [2021-01-06 19:30:12,906 INFO L461 AbstractCegarLoop]: Interpolant automaton has 5 states [2021-01-06 19:30:12,906 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:12,907 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-01-06 19:30:12,907 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:30:12,907 INFO L87 Difference]: Start difference. First operand 653 states and 857 transitions. Second operand 5 states. [2021-01-06 19:30:13,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:13,218 INFO L93 Difference]: Finished difference Result 1753 states and 2321 transitions. [2021-01-06 19:30:13,219 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-01-06 19:30:13,219 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2021-01-06 19:30:13,220 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:13,225 INFO L225 Difference]: With dead ends: 1753 [2021-01-06 19:30:13,226 INFO L226 Difference]: Without dead ends: 1145 [2021-01-06 19:30:13,228 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-01-06 19:30:13,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1145 states. [2021-01-06 19:30:13,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1145 to 659. [2021-01-06 19:30:13,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 659 states. [2021-01-06 19:30:13,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 659 states to 659 states and 853 transitions. [2021-01-06 19:30:13,307 INFO L78 Accepts]: Start accepts. Automaton has 659 states and 853 transitions. Word has length 73 [2021-01-06 19:30:13,307 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:13,308 INFO L481 AbstractCegarLoop]: Abstraction has 659 states and 853 transitions. [2021-01-06 19:30:13,308 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2021-01-06 19:30:13,308 INFO L276 IsEmpty]: Start isEmpty. Operand 659 states and 853 transitions. [2021-01-06 19:30:13,310 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:13,310 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:13,311 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:13,311 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2021-01-06 19:30:13,311 INFO L429 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:13,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:13,312 INFO L82 PathProgramCache]: Analyzing trace with hash 434292, now seen corresponding path program 1 times [2021-01-06 19:30:13,312 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:13,312 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1538690276] [2021-01-06 19:30:13,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:13,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:13,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:13,383 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1538690276] [2021-01-06 19:30:13,383 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:13,383 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-01-06 19:30:13,384 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [168725975] [2021-01-06 19:30:13,384 INFO L461 AbstractCegarLoop]: Interpolant automaton has 5 states [2021-01-06 19:30:13,384 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:13,385 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-01-06 19:30:13,385 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:30:13,385 INFO L87 Difference]: Start difference. First operand 659 states and 853 transitions. Second operand 5 states. [2021-01-06 19:30:13,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:13,661 INFO L93 Difference]: Finished difference Result 1806 states and 2359 transitions. [2021-01-06 19:30:13,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-01-06 19:30:13,662 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 73 [2021-01-06 19:30:13,664 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:13,670 INFO L225 Difference]: With dead ends: 1806 [2021-01-06 19:30:13,670 INFO L226 Difference]: Without dead ends: 1199 [2021-01-06 19:30:13,676 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-01-06 19:30:13,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1199 states. [2021-01-06 19:30:13,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1199 to 665. [2021-01-06 19:30:13,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2021-01-06 19:30:13,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 849 transitions. [2021-01-06 19:30:13,741 INFO L78 Accepts]: Start accepts. Automaton has 665 states and 849 transitions. Word has length 73 [2021-01-06 19:30:13,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:13,742 INFO L481 AbstractCegarLoop]: Abstraction has 665 states and 849 transitions. [2021-01-06 19:30:13,742 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2021-01-06 19:30:13,743 INFO L276 IsEmpty]: Start isEmpty. Operand 665 states and 849 transitions. [2021-01-06 19:30:13,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:13,744 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:13,744 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:13,745 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2021-01-06 19:30:13,745 INFO L429 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:13,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:13,745 INFO L82 PathProgramCache]: Analyzing trace with hash 1923662326, now seen corresponding path program 1 times [2021-01-06 19:30:13,746 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:13,746 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1302283422] [2021-01-06 19:30:13,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:13,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:13,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:13,825 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1302283422] [2021-01-06 19:30:13,825 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:13,825 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-06 19:30:13,826 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672612362] [2021-01-06 19:30:13,826 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:13,826 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:13,827 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:13,827 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:13,827 INFO L87 Difference]: Start difference. First operand 665 states and 849 transitions. Second operand 3 states. [2021-01-06 19:30:13,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:13,897 INFO L93 Difference]: Finished difference Result 1317 states and 1680 transitions. [2021-01-06 19:30:13,897 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:13,898 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2021-01-06 19:30:13,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:13,901 INFO L225 Difference]: With dead ends: 1317 [2021-01-06 19:30:13,901 INFO L226 Difference]: Without dead ends: 665 [2021-01-06 19:30:13,903 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:13,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 665 states. [2021-01-06 19:30:13,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 665 to 665. [2021-01-06 19:30:13,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2021-01-06 19:30:13,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 841 transitions. [2021-01-06 19:30:13,954 INFO L78 Accepts]: Start accepts. Automaton has 665 states and 841 transitions. Word has length 73 [2021-01-06 19:30:13,954 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:13,955 INFO L481 AbstractCegarLoop]: Abstraction has 665 states and 841 transitions. [2021-01-06 19:30:13,955 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:13,955 INFO L276 IsEmpty]: Start isEmpty. Operand 665 states and 841 transitions. [2021-01-06 19:30:13,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-01-06 19:30:13,956 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:13,956 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:13,956 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2021-01-06 19:30:13,956 INFO L429 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:13,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:13,957 INFO L82 PathProgramCache]: Analyzing trace with hash 2142517044, now seen corresponding path program 1 times [2021-01-06 19:30:13,957 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:13,957 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729114064] [2021-01-06 19:30:13,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:13,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:14,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:14,000 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [729114064] [2021-01-06 19:30:14,000 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:14,001 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:30:14,001 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1331581442] [2021-01-06 19:30:14,001 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:14,001 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:14,002 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:14,002 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:14,002 INFO L87 Difference]: Start difference. First operand 665 states and 841 transitions. Second operand 3 states. [2021-01-06 19:30:14,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:14,161 INFO L93 Difference]: Finished difference Result 1884 states and 2366 transitions. [2021-01-06 19:30:14,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:14,162 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2021-01-06 19:30:14,162 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:14,168 INFO L225 Difference]: With dead ends: 1884 [2021-01-06 19:30:14,168 INFO L226 Difference]: Without dead ends: 1280 [2021-01-06 19:30:14,170 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:14,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1280 states. [2021-01-06 19:30:14,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1280 to 1210. [2021-01-06 19:30:14,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1210 states. [2021-01-06 19:30:14,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1210 states to 1210 states and 1507 transitions. [2021-01-06 19:30:14,279 INFO L78 Accepts]: Start accepts. Automaton has 1210 states and 1507 transitions. Word has length 73 [2021-01-06 19:30:14,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:14,280 INFO L481 AbstractCegarLoop]: Abstraction has 1210 states and 1507 transitions. [2021-01-06 19:30:14,280 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:14,280 INFO L276 IsEmpty]: Start isEmpty. Operand 1210 states and 1507 transitions. [2021-01-06 19:30:14,281 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2021-01-06 19:30:14,281 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:14,281 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:14,282 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2021-01-06 19:30:14,282 INFO L429 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:14,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:14,282 INFO L82 PathProgramCache]: Analyzing trace with hash 1551395071, now seen corresponding path program 1 times [2021-01-06 19:30:14,283 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:14,283 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [363114277] [2021-01-06 19:30:14,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:14,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:14,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:14,334 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [363114277] [2021-01-06 19:30:14,336 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:14,336 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:30:14,337 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069874860] [2021-01-06 19:30:14,337 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:14,337 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:14,338 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:14,338 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:14,338 INFO L87 Difference]: Start difference. First operand 1210 states and 1507 transitions. Second operand 3 states. [2021-01-06 19:30:14,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:14,572 INFO L93 Difference]: Finished difference Result 3200 states and 3989 transitions. [2021-01-06 19:30:14,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:14,573 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 74 [2021-01-06 19:30:14,574 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:14,588 INFO L225 Difference]: With dead ends: 3200 [2021-01-06 19:30:14,588 INFO L226 Difference]: Without dead ends: 2108 [2021-01-06 19:30:14,592 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:14,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2108 states. [2021-01-06 19:30:14,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2108 to 2106. [2021-01-06 19:30:14,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2106 states. [2021-01-06 19:30:14,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2106 states to 2106 states and 2608 transitions. [2021-01-06 19:30:14,845 INFO L78 Accepts]: Start accepts. Automaton has 2106 states and 2608 transitions. Word has length 74 [2021-01-06 19:30:14,845 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:14,846 INFO L481 AbstractCegarLoop]: Abstraction has 2106 states and 2608 transitions. [2021-01-06 19:30:14,846 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:14,846 INFO L276 IsEmpty]: Start isEmpty. Operand 2106 states and 2608 transitions. [2021-01-06 19:30:14,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2021-01-06 19:30:14,847 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:14,847 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:14,848 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2021-01-06 19:30:14,848 INFO L429 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:14,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:14,848 INFO L82 PathProgramCache]: Analyzing trace with hash 1640750073, now seen corresponding path program 1 times [2021-01-06 19:30:14,849 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:14,849 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715103495] [2021-01-06 19:30:14,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:14,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:14,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:14,909 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [715103495] [2021-01-06 19:30:14,909 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:14,911 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:30:14,911 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062384411] [2021-01-06 19:30:14,912 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:14,912 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:14,912 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:14,913 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:14,913 INFO L87 Difference]: Start difference. First operand 2106 states and 2608 transitions. Second operand 3 states. [2021-01-06 19:30:15,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:15,312 INFO L93 Difference]: Finished difference Result 5828 states and 7208 transitions. [2021-01-06 19:30:15,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:15,313 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 75 [2021-01-06 19:30:15,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:15,332 INFO L225 Difference]: With dead ends: 5828 [2021-01-06 19:30:15,332 INFO L226 Difference]: Without dead ends: 3840 [2021-01-06 19:30:15,336 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:15,342 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3840 states. [2021-01-06 19:30:15,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3840 to 3838. [2021-01-06 19:30:15,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3838 states. [2021-01-06 19:30:15,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3838 states to 3838 states and 4722 transitions. [2021-01-06 19:30:15,645 INFO L78 Accepts]: Start accepts. Automaton has 3838 states and 4722 transitions. Word has length 75 [2021-01-06 19:30:15,645 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:15,645 INFO L481 AbstractCegarLoop]: Abstraction has 3838 states and 4722 transitions. [2021-01-06 19:30:15,645 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:15,645 INFO L276 IsEmpty]: Start isEmpty. Operand 3838 states and 4722 transitions. [2021-01-06 19:30:15,647 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2021-01-06 19:30:15,647 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:15,647 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:15,648 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2021-01-06 19:30:15,648 INFO L429 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:15,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:15,648 INFO L82 PathProgramCache]: Analyzing trace with hash -745759433, now seen corresponding path program 1 times [2021-01-06 19:30:15,649 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:15,649 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1427434712] [2021-01-06 19:30:15,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:15,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:15,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:15,674 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1427434712] [2021-01-06 19:30:15,674 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:15,675 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:30:15,680 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674579983] [2021-01-06 19:30:15,682 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:15,683 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:15,683 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:15,684 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:15,684 INFO L87 Difference]: Start difference. First operand 3838 states and 4722 transitions. Second operand 3 states. [2021-01-06 19:30:16,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:16,022 INFO L93 Difference]: Finished difference Result 7448 states and 9181 transitions. [2021-01-06 19:30:16,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:16,023 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 75 [2021-01-06 19:30:16,024 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:16,041 INFO L225 Difference]: With dead ends: 7448 [2021-01-06 19:30:16,041 INFO L226 Difference]: Without dead ends: 3728 [2021-01-06 19:30:16,047 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:16,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3728 states. [2021-01-06 19:30:16,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3728 to 3728. [2021-01-06 19:30:16,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3728 states. [2021-01-06 19:30:16,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3728 states to 3728 states and 4594 transitions. [2021-01-06 19:30:16,413 INFO L78 Accepts]: Start accepts. Automaton has 3728 states and 4594 transitions. Word has length 75 [2021-01-06 19:30:16,413 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:16,413 INFO L481 AbstractCegarLoop]: Abstraction has 3728 states and 4594 transitions. [2021-01-06 19:30:16,414 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:16,414 INFO L276 IsEmpty]: Start isEmpty. Operand 3728 states and 4594 transitions. [2021-01-06 19:30:16,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2021-01-06 19:30:16,415 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:16,415 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:16,415 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2021-01-06 19:30:16,416 INFO L429 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:16,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:16,416 INFO L82 PathProgramCache]: Analyzing trace with hash 1207843117, now seen corresponding path program 1 times [2021-01-06 19:30:16,416 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:16,418 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1413649467] [2021-01-06 19:30:16,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:16,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:16,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:16,477 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1413649467] [2021-01-06 19:30:16,477 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:16,477 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:30:16,478 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429399294] [2021-01-06 19:30:16,479 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:16,480 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:16,480 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:16,480 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:16,480 INFO L87 Difference]: Start difference. First operand 3728 states and 4594 transitions. Second operand 3 states. [2021-01-06 19:30:17,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:17,113 INFO L93 Difference]: Finished difference Result 10346 states and 12734 transitions. [2021-01-06 19:30:17,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:17,114 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2021-01-06 19:30:17,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:17,147 INFO L225 Difference]: With dead ends: 10346 [2021-01-06 19:30:17,147 INFO L226 Difference]: Without dead ends: 6736 [2021-01-06 19:30:17,155 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:17,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6736 states. [2021-01-06 19:30:17,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6736 to 6734. [2021-01-06 19:30:17,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6734 states. [2021-01-06 19:30:17,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6734 states to 6734 states and 8252 transitions. [2021-01-06 19:30:17,713 INFO L78 Accepts]: Start accepts. Automaton has 6734 states and 8252 transitions. Word has length 76 [2021-01-06 19:30:17,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:17,713 INFO L481 AbstractCegarLoop]: Abstraction has 6734 states and 8252 transitions. [2021-01-06 19:30:17,714 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:17,714 INFO L276 IsEmpty]: Start isEmpty. Operand 6734 states and 8252 transitions. [2021-01-06 19:30:17,716 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2021-01-06 19:30:17,716 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:17,716 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:17,716 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2021-01-06 19:30:17,716 INFO L429 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:17,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:17,717 INFO L82 PathProgramCache]: Analyzing trace with hash -1178666389, now seen corresponding path program 1 times [2021-01-06 19:30:17,717 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:17,717 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982127306] [2021-01-06 19:30:17,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:17,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:17,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:17,753 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982127306] [2021-01-06 19:30:17,753 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:17,753 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:30:17,754 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1294134675] [2021-01-06 19:30:17,754 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:17,754 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:17,755 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:17,755 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:17,755 INFO L87 Difference]: Start difference. First operand 6734 states and 8252 transitions. Second operand 3 states. [2021-01-06 19:30:18,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:18,276 INFO L93 Difference]: Finished difference Result 13242 states and 16247 transitions. [2021-01-06 19:30:18,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:18,276 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 76 [2021-01-06 19:30:18,277 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:18,314 INFO L225 Difference]: With dead ends: 13242 [2021-01-06 19:30:18,314 INFO L226 Difference]: Without dead ends: 6626 [2021-01-06 19:30:18,326 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:18,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6626 states. [2021-01-06 19:30:18,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6626 to 6626. [2021-01-06 19:30:18,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6626 states. [2021-01-06 19:30:18,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6626 states to 6626 states and 8128 transitions. [2021-01-06 19:30:18,847 INFO L78 Accepts]: Start accepts. Automaton has 6626 states and 8128 transitions. Word has length 76 [2021-01-06 19:30:18,849 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:18,849 INFO L481 AbstractCegarLoop]: Abstraction has 6626 states and 8128 transitions. [2021-01-06 19:30:18,849 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:18,850 INFO L276 IsEmpty]: Start isEmpty. Operand 6626 states and 8128 transitions. [2021-01-06 19:30:18,904 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2021-01-06 19:30:18,905 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:18,905 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:18,905 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2021-01-06 19:30:18,906 INFO L429 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:18,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:18,906 INFO L82 PathProgramCache]: Analyzing trace with hash 1123498955, now seen corresponding path program 1 times [2021-01-06 19:30:18,906 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:18,907 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907092471] [2021-01-06 19:30:18,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:18,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:18,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:18,972 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1907092471] [2021-01-06 19:30:18,973 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:18,973 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-06 19:30:18,973 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96247992] [2021-01-06 19:30:18,974 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:18,974 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:18,975 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:18,975 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:18,975 INFO L87 Difference]: Start difference. First operand 6626 states and 8128 transitions. Second operand 3 states. [2021-01-06 19:30:20,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:20,160 INFO L93 Difference]: Finished difference Result 19474 states and 23887 transitions. [2021-01-06 19:30:20,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:20,161 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 77 [2021-01-06 19:30:20,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:20,192 INFO L225 Difference]: With dead ends: 19474 [2021-01-06 19:30:20,192 INFO L226 Difference]: Without dead ends: 12938 [2021-01-06 19:30:20,202 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:20,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12938 states. [2021-01-06 19:30:20,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12938 to 12874. [2021-01-06 19:30:20,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12874 states. [2021-01-06 19:30:21,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12874 states to 12874 states and 15654 transitions. [2021-01-06 19:30:21,011 INFO L78 Accepts]: Start accepts. Automaton has 12874 states and 15654 transitions. Word has length 77 [2021-01-06 19:30:21,011 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:21,011 INFO L481 AbstractCegarLoop]: Abstraction has 12874 states and 15654 transitions. [2021-01-06 19:30:21,011 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:21,011 INFO L276 IsEmpty]: Start isEmpty. Operand 12874 states and 15654 transitions. [2021-01-06 19:30:21,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2021-01-06 19:30:21,017 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:21,017 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:21,018 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2021-01-06 19:30:21,018 INFO L429 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:21,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:21,018 INFO L82 PathProgramCache]: Analyzing trace with hash -494915717, now seen corresponding path program 1 times [2021-01-06 19:30:21,018 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:21,019 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40598045] [2021-01-06 19:30:21,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:21,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:21,080 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:21,081 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40598045] [2021-01-06 19:30:21,081 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:21,081 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:30:21,081 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2006418328] [2021-01-06 19:30:21,081 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:30:21,082 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:21,082 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:30:21,082 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:30:21,082 INFO L87 Difference]: Start difference. First operand 12874 states and 15654 transitions. Second operand 4 states. [2021-01-06 19:30:22,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:22,682 INFO L93 Difference]: Finished difference Result 38268 states and 46465 transitions. [2021-01-06 19:30:22,683 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:30:22,684 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 96 [2021-01-06 19:30:22,684 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:22,730 INFO L225 Difference]: With dead ends: 38268 [2021-01-06 19:30:22,731 INFO L226 Difference]: Without dead ends: 19220 [2021-01-06 19:30:22,759 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:30:22,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19220 states. [2021-01-06 19:30:23,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19220 to 19220. [2021-01-06 19:30:23,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19220 states. [2021-01-06 19:30:23,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19220 states to 19220 states and 23314 transitions. [2021-01-06 19:30:23,994 INFO L78 Accepts]: Start accepts. Automaton has 19220 states and 23314 transitions. Word has length 96 [2021-01-06 19:30:23,994 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:23,994 INFO L481 AbstractCegarLoop]: Abstraction has 19220 states and 23314 transitions. [2021-01-06 19:30:23,995 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:30:23,995 INFO L276 IsEmpty]: Start isEmpty. Operand 19220 states and 23314 transitions. [2021-01-06 19:30:24,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2021-01-06 19:30:24,009 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:24,009 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:24,009 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2021-01-06 19:30:24,010 INFO L429 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:24,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:24,010 INFO L82 PathProgramCache]: Analyzing trace with hash -2108229190, now seen corresponding path program 1 times [2021-01-06 19:30:24,010 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:24,011 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [441881489] [2021-01-06 19:30:24,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:24,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:24,081 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-01-06 19:30:24,081 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [441881489] [2021-01-06 19:30:24,081 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:24,082 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-06 19:30:24,083 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1771255055] [2021-01-06 19:30:24,083 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:24,086 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:24,087 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:24,087 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:24,087 INFO L87 Difference]: Start difference. First operand 19220 states and 23314 transitions. Second operand 3 states. [2021-01-06 19:30:25,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:25,499 INFO L93 Difference]: Finished difference Result 44030 states and 53355 transitions. [2021-01-06 19:30:25,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:25,500 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 131 [2021-01-06 19:30:25,500 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:25,549 INFO L225 Difference]: With dead ends: 44030 [2021-01-06 19:30:25,549 INFO L226 Difference]: Without dead ends: 24886 [2021-01-06 19:30:25,575 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:25,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24886 states. [2021-01-06 19:30:27,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24886 to 24790. [2021-01-06 19:30:27,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24790 states. [2021-01-06 19:30:27,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24790 states to 24790 states and 29902 transitions. [2021-01-06 19:30:27,169 INFO L78 Accepts]: Start accepts. Automaton has 24790 states and 29902 transitions. Word has length 131 [2021-01-06 19:30:27,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:27,170 INFO L481 AbstractCegarLoop]: Abstraction has 24790 states and 29902 transitions. [2021-01-06 19:30:27,170 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:27,170 INFO L276 IsEmpty]: Start isEmpty. Operand 24790 states and 29902 transitions. [2021-01-06 19:30:27,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2021-01-06 19:30:27,189 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:27,190 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:27,190 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2021-01-06 19:30:27,190 INFO L429 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:27,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:27,191 INFO L82 PathProgramCache]: Analyzing trace with hash -307341713, now seen corresponding path program 1 times [2021-01-06 19:30:27,191 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:27,191 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702149408] [2021-01-06 19:30:27,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:27,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:27,268 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:27,268 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702149408] [2021-01-06 19:30:27,269 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:27,269 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:30:27,269 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1434186951] [2021-01-06 19:30:27,270 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:30:27,270 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:27,270 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:30:27,271 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:30:27,271 INFO L87 Difference]: Start difference. First operand 24790 states and 29902 transitions. Second operand 4 states. [2021-01-06 19:30:29,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:29,070 INFO L93 Difference]: Finished difference Result 43896 states and 53090 transitions. [2021-01-06 19:30:29,071 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:30:29,071 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 134 [2021-01-06 19:30:29,071 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:29,099 INFO L225 Difference]: With dead ends: 43896 [2021-01-06 19:30:29,100 INFO L226 Difference]: Without dead ends: 24792 [2021-01-06 19:30:29,112 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:30:29,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24792 states. [2021-01-06 19:30:30,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24792 to 24790. [2021-01-06 19:30:30,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24790 states. [2021-01-06 19:30:30,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24790 states to 24790 states and 29836 transitions. [2021-01-06 19:30:30,769 INFO L78 Accepts]: Start accepts. Automaton has 24790 states and 29836 transitions. Word has length 134 [2021-01-06 19:30:30,769 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:30,769 INFO L481 AbstractCegarLoop]: Abstraction has 24790 states and 29836 transitions. [2021-01-06 19:30:30,769 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:30:30,769 INFO L276 IsEmpty]: Start isEmpty. Operand 24790 states and 29836 transitions. [2021-01-06 19:30:30,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 170 [2021-01-06 19:30:30,787 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:30,787 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:30,787 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23 [2021-01-06 19:30:30,787 INFO L429 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:30,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:30,788 INFO L82 PathProgramCache]: Analyzing trace with hash 1829407028, now seen corresponding path program 1 times [2021-01-06 19:30:30,788 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:30,788 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [438745292] [2021-01-06 19:30:30,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:30,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:30,895 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-01-06 19:30:30,895 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [438745292] [2021-01-06 19:30:30,895 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:30,896 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-06 19:30:30,896 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1544084049] [2021-01-06 19:30:30,896 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:30,897 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:30,897 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:30,897 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:30,897 INFO L87 Difference]: Start difference. First operand 24790 states and 29836 transitions. Second operand 3 states. [2021-01-06 19:30:32,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:32,788 INFO L93 Difference]: Finished difference Result 54548 states and 65551 transitions. [2021-01-06 19:30:32,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:32,789 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 169 [2021-01-06 19:30:32,789 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:32,823 INFO L225 Difference]: With dead ends: 54548 [2021-01-06 19:30:32,823 INFO L226 Difference]: Without dead ends: 29820 [2021-01-06 19:30:32,844 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:32,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29820 states. [2021-01-06 19:30:34,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29820 to 29692. [2021-01-06 19:30:34,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29692 states. [2021-01-06 19:30:34,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29692 states to 29692 states and 35544 transitions. [2021-01-06 19:30:34,681 INFO L78 Accepts]: Start accepts. Automaton has 29692 states and 35544 transitions. Word has length 169 [2021-01-06 19:30:34,681 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:34,681 INFO L481 AbstractCegarLoop]: Abstraction has 29692 states and 35544 transitions. [2021-01-06 19:30:34,681 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:34,681 INFO L276 IsEmpty]: Start isEmpty. Operand 29692 states and 35544 transitions. [2021-01-06 19:30:34,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2021-01-06 19:30:34,702 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:34,702 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:34,702 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24 [2021-01-06 19:30:34,702 INFO L429 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:34,703 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:34,703 INFO L82 PathProgramCache]: Analyzing trace with hash -1186786501, now seen corresponding path program 1 times [2021-01-06 19:30:34,703 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:34,703 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609734973] [2021-01-06 19:30:34,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:34,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:34,781 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 23 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:34,781 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1609734973] [2021-01-06 19:30:34,782 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:34,782 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:30:34,782 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1483512097] [2021-01-06 19:30:34,782 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:30:34,783 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:34,783 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:30:34,783 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:30:34,784 INFO L87 Difference]: Start difference. First operand 29692 states and 35544 transitions. Second operand 4 states. [2021-01-06 19:30:36,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:36,781 INFO L93 Difference]: Finished difference Result 54370 states and 65258 transitions. [2021-01-06 19:30:36,782 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:30:36,782 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 172 [2021-01-06 19:30:36,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:36,815 INFO L225 Difference]: With dead ends: 54370 [2021-01-06 19:30:36,815 INFO L226 Difference]: Without dead ends: 29694 [2021-01-06 19:30:36,839 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:30:36,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29694 states. [2021-01-06 19:30:38,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29694 to 29692. [2021-01-06 19:30:38,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29692 states. [2021-01-06 19:30:38,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29692 states to 29692 states and 35432 transitions. [2021-01-06 19:30:38,618 INFO L78 Accepts]: Start accepts. Automaton has 29692 states and 35432 transitions. Word has length 172 [2021-01-06 19:30:38,618 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:38,618 INFO L481 AbstractCegarLoop]: Abstraction has 29692 states and 35432 transitions. [2021-01-06 19:30:38,618 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:30:38,618 INFO L276 IsEmpty]: Start isEmpty. Operand 29692 states and 35432 transitions. [2021-01-06 19:30:38,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 208 [2021-01-06 19:30:38,634 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:38,634 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:38,634 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable25 [2021-01-06 19:30:38,634 INFO L429 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:38,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:38,636 INFO L82 PathProgramCache]: Analyzing trace with hash 559094458, now seen corresponding path program 1 times [2021-01-06 19:30:38,636 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:38,636 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [592136947] [2021-01-06 19:30:38,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:38,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:38,892 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2021-01-06 19:30:38,892 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [592136947] [2021-01-06 19:30:38,892 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:38,892 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-01-06 19:30:38,892 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653511059] [2021-01-06 19:30:38,893 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:38,893 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:38,894 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:38,894 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:38,894 INFO L87 Difference]: Start difference. First operand 29692 states and 35432 transitions. Second operand 3 states. [2021-01-06 19:30:40,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:40,926 INFO L93 Difference]: Finished difference Result 63734 states and 75903 transitions. [2021-01-06 19:30:40,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:40,927 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 207 [2021-01-06 19:30:40,927 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:40,964 INFO L225 Difference]: With dead ends: 63734 [2021-01-06 19:30:40,965 INFO L226 Difference]: Without dead ends: 34090 [2021-01-06 19:30:40,995 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:41,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34090 states. [2021-01-06 19:30:42,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34090 to 33930. [2021-01-06 19:30:42,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33930 states. [2021-01-06 19:30:42,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33930 states to 33930 states and 40268 transitions. [2021-01-06 19:30:42,875 INFO L78 Accepts]: Start accepts. Automaton has 33930 states and 40268 transitions. Word has length 207 [2021-01-06 19:30:42,876 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:42,876 INFO L481 AbstractCegarLoop]: Abstraction has 33930 states and 40268 transitions. [2021-01-06 19:30:42,876 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:30:42,876 INFO L276 IsEmpty]: Start isEmpty. Operand 33930 states and 40268 transitions. [2021-01-06 19:30:42,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 211 [2021-01-06 19:30:42,899 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:42,900 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:42,900 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable26 [2021-01-06 19:30:42,900 INFO L429 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:42,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:42,900 INFO L82 PathProgramCache]: Analyzing trace with hash -1688974701, now seen corresponding path program 1 times [2021-01-06 19:30:42,900 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:42,901 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757373782] [2021-01-06 19:30:42,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:42,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:43,154 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:43,154 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [757373782] [2021-01-06 19:30:43,155 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:43,155 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-01-06 19:30:43,155 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [400378507] [2021-01-06 19:30:43,155 INFO L461 AbstractCegarLoop]: Interpolant automaton has 4 states [2021-01-06 19:30:43,156 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:43,156 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-01-06 19:30:43,156 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-01-06 19:30:43,157 INFO L87 Difference]: Start difference. First operand 33930 states and 40268 transitions. Second operand 4 states. [2021-01-06 19:30:45,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:45,399 INFO L93 Difference]: Finished difference Result 63512 states and 75582 transitions. [2021-01-06 19:30:45,399 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-01-06 19:30:45,399 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 210 [2021-01-06 19:30:45,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:45,433 INFO L225 Difference]: With dead ends: 63512 [2021-01-06 19:30:45,433 INFO L226 Difference]: Without dead ends: 33932 [2021-01-06 19:30:45,446 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:30:45,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33932 states. [2021-01-06 19:30:47,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33932 to 33930. [2021-01-06 19:30:47,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33930 states. [2021-01-06 19:30:47,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33930 states to 33930 states and 40068 transitions. [2021-01-06 19:30:47,474 INFO L78 Accepts]: Start accepts. Automaton has 33930 states and 40068 transitions. Word has length 210 [2021-01-06 19:30:47,474 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:47,474 INFO L481 AbstractCegarLoop]: Abstraction has 33930 states and 40068 transitions. [2021-01-06 19:30:47,474 INFO L482 AbstractCegarLoop]: Interpolant automaton has 4 states. [2021-01-06 19:30:47,474 INFO L276 IsEmpty]: Start isEmpty. Operand 33930 states and 40068 transitions. [2021-01-06 19:30:47,495 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 246 [2021-01-06 19:30:47,495 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:47,496 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:47,496 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable27 [2021-01-06 19:30:47,496 INFO L429 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:47,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:47,496 INFO L82 PathProgramCache]: Analyzing trace with hash 346344481, now seen corresponding path program 1 times [2021-01-06 19:30:47,497 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:47,497 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1626347735] [2021-01-06 19:30:47,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:47,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:47,638 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2021-01-06 19:30:47,638 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1626347735] [2021-01-06 19:30:47,638 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:47,638 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-01-06 19:30:47,639 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1398122872] [2021-01-06 19:30:47,639 INFO L461 AbstractCegarLoop]: Interpolant automaton has 5 states [2021-01-06 19:30:47,639 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:47,640 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-01-06 19:30:47,640 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-01-06 19:30:47,640 INFO L87 Difference]: Start difference. First operand 33930 states and 40068 transitions. Second operand 5 states. [2021-01-06 19:30:52,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:52,385 INFO L93 Difference]: Finished difference Result 107911 states and 126916 transitions. [2021-01-06 19:30:52,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-01-06 19:30:52,386 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 245 [2021-01-06 19:30:52,386 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:52,463 INFO L225 Difference]: With dead ends: 107911 [2021-01-06 19:30:52,463 INFO L226 Difference]: Without dead ends: 74058 [2021-01-06 19:30:52,491 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2021-01-06 19:30:52,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74058 states. [2021-01-06 19:30:55,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74058 to 34938. [2021-01-06 19:30:55,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34938 states. [2021-01-06 19:30:55,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34938 states to 34938 states and 40834 transitions. [2021-01-06 19:30:55,170 INFO L78 Accepts]: Start accepts. Automaton has 34938 states and 40834 transitions. Word has length 245 [2021-01-06 19:30:55,171 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:30:55,171 INFO L481 AbstractCegarLoop]: Abstraction has 34938 states and 40834 transitions. [2021-01-06 19:30:55,171 INFO L482 AbstractCegarLoop]: Interpolant automaton has 5 states. [2021-01-06 19:30:55,171 INFO L276 IsEmpty]: Start isEmpty. Operand 34938 states and 40834 transitions. [2021-01-06 19:30:55,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 246 [2021-01-06 19:30:55,194 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:30:55,194 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:30:55,194 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable28 [2021-01-06 19:30:55,195 INFO L429 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:30:55,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:30:55,195 INFO L82 PathProgramCache]: Analyzing trace with hash 378842785, now seen corresponding path program 1 times [2021-01-06 19:30:55,195 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:30:55,195 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [273055314] [2021-01-06 19:30:55,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:30:55,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:30:55,281 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:30:55,281 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [273055314] [2021-01-06 19:30:55,282 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:30:55,282 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:30:55,282 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1277894740] [2021-01-06 19:30:55,282 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:30:55,282 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:30:55,283 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:30:55,283 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:55,283 INFO L87 Difference]: Start difference. First operand 34938 states and 40834 transitions. Second operand 3 states. [2021-01-06 19:30:57,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:30:57,846 INFO L93 Difference]: Finished difference Result 62586 states and 73359 transitions. [2021-01-06 19:30:57,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:30:57,847 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 245 [2021-01-06 19:30:57,847 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:30:57,884 INFO L225 Difference]: With dead ends: 62586 [2021-01-06 19:30:57,884 INFO L226 Difference]: Without dead ends: 35002 [2021-01-06 19:30:57,901 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:30:57,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35002 states. [2021-01-06 19:31:00,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35002 to 34938. [2021-01-06 19:31:00,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34938 states. [2021-01-06 19:31:00,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34938 states to 34938 states and 40242 transitions. [2021-01-06 19:31:00,327 INFO L78 Accepts]: Start accepts. Automaton has 34938 states and 40242 transitions. Word has length 245 [2021-01-06 19:31:00,327 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:31:00,327 INFO L481 AbstractCegarLoop]: Abstraction has 34938 states and 40242 transitions. [2021-01-06 19:31:00,327 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:31:00,327 INFO L276 IsEmpty]: Start isEmpty. Operand 34938 states and 40242 transitions. [2021-01-06 19:31:00,347 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 249 [2021-01-06 19:31:00,348 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:31:00,348 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:31:00,348 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29 [2021-01-06 19:31:00,348 INFO L429 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:31:00,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:31:00,349 INFO L82 PathProgramCache]: Analyzing trace with hash -1600094544, now seen corresponding path program 1 times [2021-01-06 19:31:00,349 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:31:00,349 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [605305038] [2021-01-06 19:31:00,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:31:00,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:31:00,440 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:31:00,440 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [605305038] [2021-01-06 19:31:00,440 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:31:00,441 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:31:00,441 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [569381901] [2021-01-06 19:31:00,441 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:31:00,441 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:31:00,442 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:31:00,442 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:31:00,442 INFO L87 Difference]: Start difference. First operand 34938 states and 40242 transitions. Second operand 3 states. [2021-01-06 19:31:02,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:31:02,736 INFO L93 Difference]: Finished difference Result 59358 states and 68559 transitions. [2021-01-06 19:31:02,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:31:02,736 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 248 [2021-01-06 19:31:02,737 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:31:02,773 INFO L225 Difference]: With dead ends: 59358 [2021-01-06 19:31:02,773 INFO L226 Difference]: Without dead ends: 35002 [2021-01-06 19:31:02,792 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:31:02,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35002 states. [2021-01-06 19:31:05,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35002 to 34938. [2021-01-06 19:31:05,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34938 states. [2021-01-06 19:31:05,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34938 states to 34938 states and 39738 transitions. [2021-01-06 19:31:05,310 INFO L78 Accepts]: Start accepts. Automaton has 34938 states and 39738 transitions. Word has length 248 [2021-01-06 19:31:05,310 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:31:05,310 INFO L481 AbstractCegarLoop]: Abstraction has 34938 states and 39738 transitions. [2021-01-06 19:31:05,310 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:31:05,310 INFO L276 IsEmpty]: Start isEmpty. Operand 34938 states and 39738 transitions. [2021-01-06 19:31:05,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 252 [2021-01-06 19:31:05,331 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:31:05,331 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:31:05,332 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30 [2021-01-06 19:31:05,332 INFO L429 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:31:05,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:31:05,332 INFO L82 PathProgramCache]: Analyzing trace with hash 333289526, now seen corresponding path program 1 times [2021-01-06 19:31:05,333 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:31:05,333 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236527952] [2021-01-06 19:31:05,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:31:05,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:31:05,420 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:31:05,421 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1236527952] [2021-01-06 19:31:05,421 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:31:05,421 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:31:05,421 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1699251197] [2021-01-06 19:31:05,422 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:31:05,422 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:31:05,422 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:31:05,423 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:31:05,423 INFO L87 Difference]: Start difference. First operand 34938 states and 39738 transitions. Second operand 3 states. [2021-01-06 19:31:07,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:31:07,788 INFO L93 Difference]: Finished difference Result 55714 states and 63535 transitions. [2021-01-06 19:31:07,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:31:07,789 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 251 [2021-01-06 19:31:07,789 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:31:07,834 INFO L225 Difference]: With dead ends: 55714 [2021-01-06 19:31:07,834 INFO L226 Difference]: Without dead ends: 34938 [2021-01-06 19:31:07,855 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:31:07,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34938 states. [2021-01-06 19:31:10,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34938 to 34876. [2021-01-06 19:31:10,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34876 states. [2021-01-06 19:31:10,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34876 states to 34876 states and 39268 transitions. [2021-01-06 19:31:10,172 INFO L78 Accepts]: Start accepts. Automaton has 34876 states and 39268 transitions. Word has length 251 [2021-01-06 19:31:10,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:31:10,172 INFO L481 AbstractCegarLoop]: Abstraction has 34876 states and 39268 transitions. [2021-01-06 19:31:10,172 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:31:10,172 INFO L276 IsEmpty]: Start isEmpty. Operand 34876 states and 39268 transitions. [2021-01-06 19:31:10,187 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2021-01-06 19:31:10,187 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:31:10,188 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:31:10,188 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable31 [2021-01-06 19:31:10,188 INFO L429 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:31:10,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:31:10,189 INFO L82 PathProgramCache]: Analyzing trace with hash 391416485, now seen corresponding path program 1 times [2021-01-06 19:31:10,189 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:31:10,189 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772582695] [2021-01-06 19:31:10,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:31:10,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:31:10,273 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2021-01-06 19:31:10,273 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1772582695] [2021-01-06 19:31:10,274 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:31:10,274 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:31:10,274 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953448159] [2021-01-06 19:31:10,274 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:31:10,275 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:31:10,275 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:31:10,275 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:31:10,275 INFO L87 Difference]: Start difference. First operand 34876 states and 39268 transitions. Second operand 3 states. [2021-01-06 19:31:12,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:31:12,343 INFO L93 Difference]: Finished difference Result 62718 states and 70171 transitions. [2021-01-06 19:31:12,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:31:12,344 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 254 [2021-01-06 19:31:12,344 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:31:12,369 INFO L225 Difference]: With dead ends: 62718 [2021-01-06 19:31:12,369 INFO L226 Difference]: Without dead ends: 16774 [2021-01-06 19:31:12,395 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:31:12,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16774 states. [2021-01-06 19:31:13,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16774 to 16254. [2021-01-06 19:31:13,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16254 states. [2021-01-06 19:31:13,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16254 states to 16254 states and 17696 transitions. [2021-01-06 19:31:13,572 INFO L78 Accepts]: Start accepts. Automaton has 16254 states and 17696 transitions. Word has length 254 [2021-01-06 19:31:13,573 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:31:13,573 INFO L481 AbstractCegarLoop]: Abstraction has 16254 states and 17696 transitions. [2021-01-06 19:31:13,573 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:31:13,573 INFO L276 IsEmpty]: Start isEmpty. Operand 16254 states and 17696 transitions. [2021-01-06 19:31:13,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 258 [2021-01-06 19:31:13,585 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:31:13,586 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:31:13,586 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable32 [2021-01-06 19:31:13,586 INFO L429 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:31:13,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:31:13,586 INFO L82 PathProgramCache]: Analyzing trace with hash -1392087481, now seen corresponding path program 1 times [2021-01-06 19:31:13,587 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:31:13,587 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1087697084] [2021-01-06 19:31:13,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:31:13,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-01-06 19:31:13,686 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-01-06 19:31:13,687 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1087697084] [2021-01-06 19:31:13,687 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-01-06 19:31:13,687 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-01-06 19:31:13,687 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [590443177] [2021-01-06 19:31:13,688 INFO L461 AbstractCegarLoop]: Interpolant automaton has 3 states [2021-01-06 19:31:13,688 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-01-06 19:31:13,688 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-01-06 19:31:13,688 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:31:13,689 INFO L87 Difference]: Start difference. First operand 16254 states and 17696 transitions. Second operand 3 states. [2021-01-06 19:31:14,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-01-06 19:31:14,880 INFO L93 Difference]: Finished difference Result 28760 states and 31355 transitions. [2021-01-06 19:31:14,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-01-06 19:31:14,881 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 257 [2021-01-06 19:31:14,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-01-06 19:31:14,898 INFO L225 Difference]: With dead ends: 28760 [2021-01-06 19:31:14,898 INFO L226 Difference]: Without dead ends: 16254 [2021-01-06 19:31:14,908 INFO L677 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-01-06 19:31:14,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16254 states. [2021-01-06 19:31:16,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16254 to 16254. [2021-01-06 19:31:16,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16254 states. [2021-01-06 19:31:16,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16254 states to 16254 states and 17530 transitions. [2021-01-06 19:31:16,053 INFO L78 Accepts]: Start accepts. Automaton has 16254 states and 17530 transitions. Word has length 257 [2021-01-06 19:31:16,054 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-01-06 19:31:16,054 INFO L481 AbstractCegarLoop]: Abstraction has 16254 states and 17530 transitions. [2021-01-06 19:31:16,054 INFO L482 AbstractCegarLoop]: Interpolant automaton has 3 states. [2021-01-06 19:31:16,054 INFO L276 IsEmpty]: Start isEmpty. Operand 16254 states and 17530 transitions. [2021-01-06 19:31:16,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 261 [2021-01-06 19:31:16,067 INFO L414 BasicCegarLoop]: Found error trace [2021-01-06 19:31:16,067 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-01-06 19:31:16,067 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable33 [2021-01-06 19:31:16,067 INFO L429 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2021-01-06 19:31:16,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-01-06 19:31:16,068 INFO L82 PathProgramCache]: Analyzing trace with hash 1978087514, now seen corresponding path program 1 times [2021-01-06 19:31:16,068 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-01-06 19:31:16,068 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600212852] [2021-01-06 19:31:16,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-01-06 19:31:16,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-01-06 19:31:16,112 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-01-06 19:31:16,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-01-06 19:31:16,154 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-01-06 19:31:16,331 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-01-06 19:31:16,331 INFO L523 BasicCegarLoop]: Counterexample might be feasible [2021-01-06 19:31:16,332 WARN L518 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable34 [2021-01-06 19:31:16,683 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 06.01 07:31:16 BoogieIcfgContainer [2021-01-06 19:31:16,683 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2021-01-06 19:31:16,684 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-01-06 19:31:16,684 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-01-06 19:31:16,684 INFO L275 PluginConnector]: Witness Printer initialized [2021-01-06 19:31:16,685 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.01 07:30:09" (3/4) ... [2021-01-06 19:31:16,687 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2021-01-06 19:31:16,986 INFO L141 WitnessManager]: Wrote witness to /storage/repos/svcomp/c/systemc/transmitter.04.cil.c-witness.graphml [2021-01-06 19:31:16,987 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-01-06 19:31:16,989 INFO L168 Benchmark]: Toolchain (without parser) took 69758.77 ms. Allocated memory was 151.0 MB in the beginning and 7.2 GB in the end (delta: 7.0 GB). Free memory was 126.7 MB in the beginning and 5.0 GB in the end (delta: -4.8 GB). Peak memory consumption was 2.2 GB. Max. memory is 8.0 GB. [2021-01-06 19:31:16,990 INFO L168 Benchmark]: CDTParser took 0.27 ms. Allocated memory is still 151.0 MB. Free memory was 125.1 MB in the beginning and 125.0 MB in the end (delta: 83.4 kB). There was no memory consumed. Max. memory is 8.0 GB. [2021-01-06 19:31:16,990 INFO L168 Benchmark]: CACSL2BoogieTranslator took 522.68 ms. Allocated memory is still 151.0 MB. Free memory was 126.4 MB in the beginning and 110.8 MB in the end (delta: 15.6 MB). Peak memory consumption was 15.7 MB. Max. memory is 8.0 GB. [2021-01-06 19:31:16,991 INFO L168 Benchmark]: Boogie Procedure Inliner took 94.98 ms. Allocated memory is still 151.0 MB. Free memory was 110.8 MB in the beginning and 106.7 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 8.0 GB. [2021-01-06 19:31:16,991 INFO L168 Benchmark]: Boogie Preprocessor took 66.33 ms. Allocated memory is still 151.0 MB. Free memory was 106.5 MB in the beginning and 103.0 MB in the end (delta: 3.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 8.0 GB. [2021-01-06 19:31:16,992 INFO L168 Benchmark]: RCFGBuilder took 1712.92 ms. Allocated memory is still 151.0 MB. Free memory was 102.9 MB in the beginning and 50.0 MB in the end (delta: 52.9 MB). Peak memory consumption was 53.9 MB. Max. memory is 8.0 GB. [2021-01-06 19:31:16,992 INFO L168 Benchmark]: TraceAbstraction took 67045.71 ms. Allocated memory was 151.0 MB in the beginning and 7.2 GB in the end (delta: 7.0 GB). Free memory was 49.5 MB in the beginning and 5.0 GB in the end (delta: -5.0 GB). Peak memory consumption was 2.0 GB. Max. memory is 8.0 GB. [2021-01-06 19:31:16,993 INFO L168 Benchmark]: Witness Printer took 302.73 ms. Allocated memory is still 7.2 GB. Free memory was 5.0 GB in the beginning and 5.0 GB in the end (delta: 47.2 MB). Peak memory consumption was 47.2 MB. Max. memory is 8.0 GB. [2021-01-06 19:31:16,995 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.27 ms. Allocated memory is still 151.0 MB. Free memory was 125.1 MB in the beginning and 125.0 MB in the end (delta: 83.4 kB). There was no memory consumed. Max. memory is 8.0 GB. * CACSL2BoogieTranslator took 522.68 ms. Allocated memory is still 151.0 MB. Free memory was 126.4 MB in the beginning and 110.8 MB in the end (delta: 15.6 MB). Peak memory consumption was 15.7 MB. Max. memory is 8.0 GB. * Boogie Procedure Inliner took 94.98 ms. Allocated memory is still 151.0 MB. Free memory was 110.8 MB in the beginning and 106.7 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 8.0 GB. * Boogie Preprocessor took 66.33 ms. Allocated memory is still 151.0 MB. Free memory was 106.5 MB in the beginning and 103.0 MB in the end (delta: 3.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 8.0 GB. * RCFGBuilder took 1712.92 ms. Allocated memory is still 151.0 MB. Free memory was 102.9 MB in the beginning and 50.0 MB in the end (delta: 52.9 MB). Peak memory consumption was 53.9 MB. Max. memory is 8.0 GB. * TraceAbstraction took 67045.71 ms. Allocated memory was 151.0 MB in the beginning and 7.2 GB in the end (delta: 7.0 GB). Free memory was 49.5 MB in the beginning and 5.0 GB in the end (delta: -5.0 GB). Peak memory consumption was 2.0 GB. Max. memory is 8.0 GB. * Witness Printer took 302.73 ms. Allocated memory is still 7.2 GB. Free memory was 5.0 GB in the beginning and 5.0 GB in the end (delta: 47.2 MB). Peak memory consumption was 47.2 MB. Max. memory is 8.0 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 13]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L17] int m_pc = 0; [L18] int t1_pc = 0; [L19] int t2_pc = 0; [L20] int t3_pc = 0; [L21] int t4_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int m_i ; [L28] int t1_i ; [L29] int t2_i ; [L30] int t3_i ; [L31] int t4_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L39] int E_3 = 2; [L40] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0, T3_E=2, t3_i=0, t3_pc=0, t3_st=0, T4_E=2, t4_i=0, t4_pc=0, t4_st=0] [L813] int __retres1 ; [L725] m_i = 1 [L726] t1_i = 1 [L727] t2_i = 1 [L728] t3_i = 1 [L729] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L754] int kernel_st ; [L755] int tmp ; [L756] int tmp___0 ; [L760] kernel_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L333] COND TRUE m_i == 1 [L334] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L338] COND TRUE t1_i == 1 [L339] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L343] COND TRUE t2_i == 1 [L344] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L348] COND TRUE t3_i == 1 [L349] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L353] COND TRUE t4_i == 1 [L354] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L494] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L499] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L504] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L509] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L514] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L519] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L524] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L529] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L534] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L597] int tmp ; [L598] int tmp___0 ; [L599] int tmp___1 ; [L600] int tmp___2 ; [L601] int tmp___3 ; [L227] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L230] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L240] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L242] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L605] tmp = is_master_triggered() [L607] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L246] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L249] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L259] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L261] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L613] tmp___0 = is_transmit1_triggered() [L615] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L265] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L268] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L278] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L280] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L621] tmp___1 = is_transmit2_triggered() [L623] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L284] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L287] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L297] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L299] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L629] tmp___2 = is_transmit3_triggered() [L631] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L303] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L306] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L316] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L318] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L637] tmp___3 = is_transmit4_triggered() [L639] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L547] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L552] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L557] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L562] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L567] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L572] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L577] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L582] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L587] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L768] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L771] kernel_st = 1 [L399] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L403] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L363] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L366] COND TRUE m_st == 0 [L367] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L394] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L406] tmp = exists_runnable_thread() [L408] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L413] COND TRUE m_st == 0 [L414] int tmp_ndt_1; [L415] tmp_ndt_1 = __VERIFIER_nondet_int() [L416] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L427] COND TRUE t1_st == 0 [L428] int tmp_ndt_2; [L429] tmp_ndt_2 = __VERIFIER_nondet_int() [L430] COND TRUE \read(tmp_ndt_2) [L432] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L92] COND TRUE t1_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L103] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L105] t1_pc = 1 [L106] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L441] COND TRUE t2_st == 0 [L442] int tmp_ndt_3; [L443] tmp_ndt_3 = __VERIFIER_nondet_int() [L444] COND TRUE \read(tmp_ndt_3) [L446] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L127] COND TRUE t2_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L138] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L140] t2_pc = 1 [L141] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L455] COND TRUE t3_st == 0 [L456] int tmp_ndt_4; [L457] tmp_ndt_4 = __VERIFIER_nondet_int() [L458] COND TRUE \read(tmp_ndt_4) [L460] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L162] COND TRUE t3_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L173] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=0, t3_st=1, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L175] t3_pc = 1 [L176] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=0] [L469] COND TRUE t4_st == 0 [L470] int tmp_ndt_5; [L471] tmp_ndt_5 = __VERIFIER_nondet_int() [L472] COND TRUE \read(tmp_ndt_5) [L474] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L197] COND TRUE t4_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L208] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=0, t4_st=1] [L210] t4_pc = 1 [L211] t4_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L403] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L363] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L366] COND TRUE m_st == 0 [L367] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L394] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L406] tmp = exists_runnable_thread() [L408] COND TRUE \read(tmp) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L413] COND TRUE m_st == 0 [L414] int tmp_ndt_1; [L415] tmp_ndt_1 = __VERIFIER_nondet_int() [L416] COND TRUE \read(tmp_ndt_1) [L418] m_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L51] COND TRUE m_pc == 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L62] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L65] E_1 = 1 [L597] int tmp ; [L598] int tmp___0 ; [L599] int tmp___1 ; [L600] int tmp___2 ; [L601] int tmp___3 ; [L227] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L230] COND FALSE !(m_pc == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L242] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L605] tmp = is_master_triggered() [L607] COND FALSE !(\read(tmp)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L246] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L249] COND TRUE t1_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L250] COND TRUE E_1 == 1 [L251] __retres1 = 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L261] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L613] tmp___0 = is_transmit1_triggered() [L615] COND TRUE \read(tmp___0) [L616] t1_st = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L265] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L268] COND TRUE t2_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L269] COND FALSE !(E_2 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L280] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L621] tmp___1 = is_transmit2_triggered() [L623] COND FALSE !(\read(tmp___1)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L284] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L287] COND TRUE t3_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L288] COND FALSE !(E_3 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L299] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L629] tmp___2 = is_transmit3_triggered() [L631] COND FALSE !(\read(tmp___2)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L303] int __retres1 ; VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L306] COND TRUE t4_pc == 1 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L307] COND FALSE !(E_4 == 1) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] __retres1 = 0 VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L318] return (__retres1); VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L637] tmp___3 = is_transmit4_triggered() [L639] COND FALSE !(\read(tmp___3)) VAL [E_1=1, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L67] E_1 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L70] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L72] m_pc = 1 [L73] m_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L427] COND TRUE t1_st == 0 [L428] int tmp_ndt_2; [L429] tmp_ndt_2 = __VERIFIER_nondet_int() [L430] COND TRUE \read(tmp_ndt_2) [L432] t1_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L92] COND FALSE !(t1_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L95] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L111] E_2 = 1 [L597] int tmp ; [L598] int tmp___0 ; [L599] int tmp___1 ; [L600] int tmp___2 ; [L601] int tmp___3 ; [L227] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L230] COND TRUE m_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L231] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L242] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L605] tmp = is_master_triggered() [L607] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L246] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L249] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L250] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L261] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L613] tmp___0 = is_transmit1_triggered() [L615] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L265] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L268] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L269] COND TRUE E_2 == 1 [L270] __retres1 = 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L280] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L621] tmp___1 = is_transmit2_triggered() [L623] COND TRUE \read(tmp___1) [L624] t2_st = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L284] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L287] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L288] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L299] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L629] tmp___2 = is_transmit3_triggered() [L631] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L303] int __retres1 ; VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L306] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L307] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] __retres1 = 0 VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L318] return (__retres1); VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L637] tmp___3 = is_transmit4_triggered() [L639] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=1, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L113] E_2 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L103] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L105] t1_pc = 1 [L106] t1_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L441] COND TRUE t2_st == 0 [L442] int tmp_ndt_3; [L443] tmp_ndt_3 = __VERIFIER_nondet_int() [L444] COND TRUE \read(tmp_ndt_3) [L446] t2_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L127] COND FALSE !(t2_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L130] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L146] E_3 = 1 [L597] int tmp ; [L598] int tmp___0 ; [L599] int tmp___1 ; [L600] int tmp___2 ; [L601] int tmp___3 ; [L227] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L230] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L231] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L242] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L605] tmp = is_master_triggered() [L607] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L246] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L249] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L250] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L261] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L613] tmp___0 = is_transmit1_triggered() [L615] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L265] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L268] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L269] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L280] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L621] tmp___1 = is_transmit2_triggered() [L623] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L284] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L287] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L288] COND TRUE E_3 == 1 [L289] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L299] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L629] tmp___2 = is_transmit3_triggered() [L631] COND TRUE \read(tmp___2) [L632] t3_st = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L303] int __retres1 ; VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L306] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L307] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L316] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L318] return (__retres1); VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L637] tmp___3 = is_transmit4_triggered() [L639] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=1, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L148] E_3 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L138] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L140] t2_pc = 1 [L141] t2_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=0, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L455] COND TRUE t3_st == 0 [L456] int tmp_ndt_4; [L457] tmp_ndt_4 = __VERIFIER_nondet_int() [L458] COND TRUE \read(tmp_ndt_4) [L460] t3_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L162] COND FALSE !(t3_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L165] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L181] E_4 = 1 [L597] int tmp ; [L598] int tmp___0 ; [L599] int tmp___1 ; [L600] int tmp___2 ; [L601] int tmp___3 ; [L227] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L230] COND TRUE m_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L231] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L240] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L242] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L605] tmp = is_master_triggered() [L607] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L246] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L249] COND TRUE t1_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L250] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L259] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L261] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L613] tmp___0 = is_transmit1_triggered() [L615] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L265] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L268] COND TRUE t2_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L269] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L278] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L280] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L621] tmp___1 = is_transmit2_triggered() [L623] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L284] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L287] COND TRUE t3_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L288] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L297] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L299] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L629] tmp___2 = is_transmit3_triggered() [L631] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L303] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L306] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L307] COND TRUE E_4 == 1 [L308] __retres1 = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L318] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=2] [L637] tmp___3 = is_transmit4_triggered() [L639] COND TRUE \read(tmp___3) [L640] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L183] E_4 = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L173] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=1, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L175] t3_pc = 1 [L176] t3_st = 2 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=0] [L469] COND TRUE t4_st == 0 [L470] int tmp_ndt_5; [L471] tmp_ndt_5 = __VERIFIER_nondet_int() [L472] COND TRUE \read(tmp_ndt_5) [L474] t4_st = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L197] COND FALSE !(t4_pc == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L200] COND TRUE t4_pc == 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] [L13] reach_error() VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, T3_E=2, t3_i=1, t3_pc=1, t3_st=2, T4_E=2, t4_i=1, t4_pc=1, t4_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 374 locations, 1 error locations. Started 1 CEGAR loops. VerificationResult: UNSAFE, OverallTime: 66.5s, OverallIterations: 35, TraceHistogramMax: 2, AutomataDifference: 34.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 18908 SDtfs, 19453 SDslu, 13432 SDs, 0 SdLazy, 800 SolverSat, 339 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 123 GetRequests, 61 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=34938occurred in iteration=29, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 27.8s AutomataMinimizationTime, 34 MinimizatonAttempts, 42210 StatesRemovedByMinimization, 21 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 1.2s InterpolantComputationTime, 4427 NumberOfCodeBlocks, 4427 NumberOfCodeBlocksAsserted, 35 NumberOfCheckSat, 4133 ConstructedInterpolants, 0 QuantifiedInterpolants, 984805 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 34 InterpolantComputations, 34 PerfectInterpolantSequences, 302/302 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...